drivers/video/nvidia/nv_type.h

   1 #ifndef __NV_TYPE_H__
   2 #define __NV_TYPE_H__
   3
   4 #include <linux/fb.h>
   5 #include <linux/types.h>
   6 #include <linux/i2c.h>
   7 #include <linux/i2c-algo-bit.h>
   8 #include <linux/mutex.h>
   9 #include <video/vga.h>
  10
  11 #define NV_ARCH_04  0x04
  12 #define NV_ARCH_10  0x10
  13 #define NV_ARCH_20  0x20
  14 #define NV_ARCH_30  0x30
  15 #define NV_ARCH_40  0x40
  16
  17 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
  18 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
  19 #define SetBF(mask,value) ((value) << (0?mask))
  20 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
  21 #define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
  22 #define SetBit(n) (1<<(n))
  23 #define Set8Bits(value) ((value)&0xff)
  24
  25 #define V_DBLSCAN  1
  26
  27 typedef struct {
  28         int bitsPerPixel;
  29         int depth;
  30         int displayWidth;
  31         int weight;
  32 } NVFBLayout;
  33
  34 #define NUM_SEQ_REGS            0x05
  35 #define NUM_CRT_REGS            0x41
  36 #define NUM_GRC_REGS            0x09
  37 #define NUM_ATC_REGS            0x15
  38
  39 struct nvidia_par;
  40
  41 struct nvidia_i2c_chan {
  42         struct nvidia_par *par;
  43         unsigned long ddc_base;
  44         struct i2c_adapter adapter;
  45         struct i2c_algo_bit_data algo;
  46 };
  47
  48 typedef struct _riva_hw_state {
  49         u8 attr[NUM_ATC_REGS];
  50         u8 crtc[NUM_CRT_REGS];
  51         u8 gra[NUM_GRC_REGS];
  52         u8 seq[NUM_SEQ_REGS];
  53         u8 misc_output;
  54         u32 bpp;
  55         u32 width;
  56         u32 height;
  57         u32 interlace;
  58         u32 repaint0;
  59         u32 repaint1;
  60         u32 screen;
  61         u32 scale;
  62         u32 dither;
  63         u32 extra;
  64         u32 fifo;
  65         u32 pixel;
  66         u32 horiz;
  67         u32 arbitration0;
  68         u32 arbitration1;
  69         u32 pll;
  70         u32 pllB;
  71         u32 vpll;
  72         u32 vpll2;
  73         u32 vpllB;
  74         u32 vpll2B;
  75         u32 pllsel;
  76         u32 general;
  77         u32 crtcOwner;
  78         u32 head;
  79         u32 head2;
  80         u32 config;
  81         u32 cursorConfig;
  82         u32 cursor0;
  83         u32 cursor1;
  84         u32 cursor2;
  85         u32 timingH;
  86         u32 timingV;
  87         u32 displayV;
  88         u32 crtcSync;
  89         u32 control;
  90 } RIVA_HW_STATE;
  91
  92 struct riva_regs {
  93         RIVA_HW_STATE ext;
  94 };
  95
  96 struct nvidia_par {
  97         RIVA_HW_STATE SavedReg;
  98         RIVA_HW_STATE ModeReg;
  99         RIVA_HW_STATE initial_state;
 100         RIVA_HW_STATE *CurrentState;
 101         struct vgastate vgastate;
 102         struct mutex open_lock;
 103         u32 pseudo_palette[16];
 104         struct pci_dev *pci_dev;
 105         u32 Architecture;
 106         u32 CursorStart;
 107         int Chipset;
 108         unsigned long FbAddress;
 109         u8 __iomem *FbStart;
 110         u32 FbMapSize;
 111         u32 FbUsableSize;
 112         u32 ScratchBufferSize;
 113         u32 ScratchBufferStart;
 114         int FpScale;
 115         u32 MinVClockFreqKHz;
 116         u32 MaxVClockFreqKHz;
 117         u32 CrystalFreqKHz;
 118         u32 RamAmountKBytes;
 119         u32 IOBase;
 120         NVFBLayout CurrentLayout;
 121         int cursor_reset;
 122         int lockup;
 123         int videoKey;
 124         int FlatPanel;
 125         int FPDither;
 126         int Television;
 127         int CRTCnumber;
 128         int alphaCursor;
 129         int twoHeads;
 130         int twoStagePLL;
 131         int fpScaler;
 132         int fpWidth;
 133         int fpHeight;
 134         int PanelTweak;
 135         int paneltweak;
 136         int LVDS;
 137         int pm_state;
 138         int reverse_i2c;
 139         u32 crtcSync_read;
 140         u32 fpSyncs;
 141         u32 dmaPut;
 142         u32 dmaCurrent;
 143         u32 dmaFree;
 144         u32 dmaMax;
 145         u32 __iomem *dmaBase;
 146         u32 currentRop;
 147         int WaitVSyncPossible;
 148         int BlendingPossible;
 149         u32 paletteEnabled;
 150         u32 forceCRTC;
 151         u32 open_count;
 152         u8 DDCBase;
 153 #ifdef CONFIG_MTRR
 154         struct {
 155                 int vram;
 156                 int vram_valid;
 157         } mtrr;
 158 #endif
 159         struct nvidia_i2c_chan chan[3];
 160
 161         volatile u32 __iomem *REGS;
 162         volatile u32 __iomem *PCRTC0;
 163         volatile u32 __iomem *PCRTC;
 164         volatile u32 __iomem *PRAMDAC0;
 165         volatile u32 __iomem *PFB;
 166         volatile u32 __iomem *PFIFO;
 167         volatile u32 __iomem *PGRAPH;
 168         volatile u32 __iomem *PEXTDEV;
 169         volatile u32 __iomem *PTIMER;
 170         volatile u32 __iomem *PMC;
 171         volatile u32 __iomem *PRAMIN;
 172         volatile u32 __iomem *FIFO;
 173         volatile u32 __iomem *CURSOR;
 174         volatile u8 __iomem *PCIO0;
 175         volatile u8 __iomem *PCIO;
 176         volatile u8 __iomem *PVIO;
 177         volatile u8 __iomem *PDIO0;
 178         volatile u8 __iomem *PDIO;
 179         volatile u32 __iomem *PRAMDAC;
 180 };
 181
 182 #endif                          /* __NV_TYPE_H__ */