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mtd: nand_base: always initialise oob_poi before writing OOB data
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mtd / nand / nand_base.c
blob408e1d0abfd1dbe9cdaf8c22dc27bbbfb7b9d829
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <linux/io.h>
50 #include <linux/mtd/partitions.h>
51
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61 };
62
63 static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69 };
70
71 static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80 };
81
82 static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94 };
95
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102 /*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106 DEFINE_LED_TRIGGER(nand_led_trigger);
107
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110 {
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
123 __func__);
124 ret = -EINVAL;
125 }
126
127 /* Do not allow past end of device */
128 if (ofs + len > mtd->size) {
129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
130 __func__);
131 ret = -EINVAL;
132 }
133
134 return ret;
135 }
136
137 /**
138 * nand_release_device - [GENERIC] release chip
139 * @mtd: MTD device structure
140 *
141 * Deselect, release chip lock and wake up anyone waiting on the device.
142 */
143 static void nand_release_device(struct mtd_info *mtd)
144 {
145 struct nand_chip *chip = mtd->priv;
146
147 /* De-select the NAND device */
148 chip->select_chip(mtd, -1);
149
150 /* Release the controller and the chip */
151 spin_lock(&chip->controller->lock);
152 chip->controller->active = NULL;
153 chip->state = FL_READY;
154 wake_up(&chip->controller->wq);
155 spin_unlock(&chip->controller->lock);
156 }
157
158 /**
159 * nand_read_byte - [DEFAULT] read one byte from the chip
160 * @mtd: MTD device structure
161 *
162 * Default read function for 8bit buswith.
163 */
164 static uint8_t nand_read_byte(struct mtd_info *mtd)
165 {
166 struct nand_chip *chip = mtd->priv;
167 return readb(chip->IO_ADDR_R);
168 }
169
170 /**
171 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
172 * @mtd: MTD device structure
173 *
174 * Default read function for 16bit buswith with endianess conversion.
175 */
176 static uint8_t nand_read_byte16(struct mtd_info *mtd)
177 {
178 struct nand_chip *chip = mtd->priv;
179 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
180 }
181
182 /**
183 * nand_read_word - [DEFAULT] read one word from the chip
184 * @mtd: MTD device structure
185 *
186 * Default read function for 16bit buswith without endianess conversion.
187 */
188 static u16 nand_read_word(struct mtd_info *mtd)
189 {
190 struct nand_chip *chip = mtd->priv;
191 return readw(chip->IO_ADDR_R);
192 }
193
194 /**
195 * nand_select_chip - [DEFAULT] control CE line
196 * @mtd: MTD device structure
197 * @chipnr: chipnumber to select, -1 for deselect
198 *
199 * Default select function for 1 chip devices.
200 */
201 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
202 {
203 struct nand_chip *chip = mtd->priv;
204
205 switch (chipnr) {
206 case -1:
207 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
208 break;
209 case 0:
210 break;
211
212 default:
213 BUG();
214 }
215 }
216
217 /**
218 * nand_write_buf - [DEFAULT] write buffer to chip
219 * @mtd: MTD device structure
220 * @buf: data buffer
221 * @len: number of bytes to write
222 *
223 * Default write function for 8bit buswith.
224 */
225 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
226 {
227 int i;
228 struct nand_chip *chip = mtd->priv;
229
230 for (i = 0; i < len; i++)
231 writeb(buf[i], chip->IO_ADDR_W);
232 }
233
234 /**
235 * nand_read_buf - [DEFAULT] read chip data into buffer
236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
239 *
240 * Default read function for 8bit buswith.
241 */
242 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
243 {
244 int i;
245 struct nand_chip *chip = mtd->priv;
246
247 for (i = 0; i < len; i++)
248 buf[i] = readb(chip->IO_ADDR_R);
249 }
250
251 /**
252 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
253 * @mtd: MTD device structure
254 * @buf: buffer containing the data to compare
255 * @len: number of bytes to compare
256 *
257 * Default verify function for 8bit buswith.
258 */
259 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 {
261 int i;
262 struct nand_chip *chip = mtd->priv;
263
264 for (i = 0; i < len; i++)
265 if (buf[i] != readb(chip->IO_ADDR_R))
266 return -EFAULT;
267 return 0;
268 }
269
270 /**
271 * nand_write_buf16 - [DEFAULT] write buffer to chip
272 * @mtd: MTD device structure
273 * @buf: data buffer
274 * @len: number of bytes to write
275 *
276 * Default write function for 16bit buswith.
277 */
278 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
279 {
280 int i;
281 struct nand_chip *chip = mtd->priv;
282 u16 *p = (u16 *) buf;
283 len >>= 1;
284
285 for (i = 0; i < len; i++)
286 writew(p[i], chip->IO_ADDR_W);
287
288 }
289
290 /**
291 * nand_read_buf16 - [DEFAULT] read chip data into buffer
292 * @mtd: MTD device structure
293 * @buf: buffer to store date
294 * @len: number of bytes to read
295 *
296 * Default read function for 16bit buswith.
297 */
298 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
299 {
300 int i;
301 struct nand_chip *chip = mtd->priv;
302 u16 *p = (u16 *) buf;
303 len >>= 1;
304
305 for (i = 0; i < len; i++)
306 p[i] = readw(chip->IO_ADDR_R);
307 }
308
309 /**
310 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
311 * @mtd: MTD device structure
312 * @buf: buffer containing the data to compare
313 * @len: number of bytes to compare
314 *
315 * Default verify function for 16bit buswith.
316 */
317 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
318 {
319 int i;
320 struct nand_chip *chip = mtd->priv;
321 u16 *p = (u16 *) buf;
322 len >>= 1;
323
324 for (i = 0; i < len; i++)
325 if (p[i] != readw(chip->IO_ADDR_R))
326 return -EFAULT;
327
328 return 0;
329 }
330
331 /**
332 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
333 * @mtd: MTD device structure
334 * @ofs: offset from device start
335 * @getchip: 0, if the chip is already selected
336 *
337 * Check, if the block is bad.
338 */
339 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340 {
341 int page, chipnr, res = 0;
342 struct nand_chip *chip = mtd->priv;
343 u16 bad;
344
345 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
346 ofs += mtd->erasesize - mtd->writesize;
347
348 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
349
350 if (getchip) {
351 chipnr = (int)(ofs >> chip->chip_shift);
352
353 nand_get_device(chip, mtd, FL_READING);
354
355 /* Select the NAND device */
356 chip->select_chip(mtd, chipnr);
357 }
358
359 if (chip->options & NAND_BUSWIDTH_16) {
360 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
361 page);
362 bad = cpu_to_le16(chip->read_word(mtd));
363 if (chip->badblockpos & 0x1)
364 bad >>= 8;
365 else
366 bad &= 0xFF;
367 } else {
368 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
369 bad = chip->read_byte(mtd);
370 }
371
372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376
377 if (getchip)
378 nand_release_device(mtd);
379
380 return res;
381 }
382
383 /**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
387 *
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver.
390 */
391 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
392 {
393 struct nand_chip *chip = mtd->priv;
394 uint8_t buf[2] = { 0, 0 };
395 int block, ret, i = 0;
396
397 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
398 ofs += mtd->erasesize - mtd->writesize;
399
400 /* Get block number */
401 block = (int)(ofs >> chip->bbt_erase_shift);
402 if (chip->bbt)
403 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
404
405 /* Do we have a flash based bad block table? */
406 if (chip->bbt_options & NAND_BBT_USE_FLASH)
407 ret = nand_update_bbt(mtd, ofs);
408 else {
409 nand_get_device(chip, mtd, FL_WRITING);
410
411 /*
412 * Write to first two pages if necessary. If we write to more
413 * than one location, the first error encountered quits the
414 * procedure. We write two bytes per location, so we dont have
415 * to mess with 16 bit access.
416 */
417 do {
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
422
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
424
425 i++;
426 ofs += mtd->writesize;
427 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
428 i < 2);
429
430 nand_release_device(mtd);
431 }
432 if (!ret)
433 mtd->ecc_stats.badblocks++;
434
435 return ret;
436 }
437
438 /**
439 * nand_check_wp - [GENERIC] check if the chip is write protected
440 * @mtd: MTD device structure
441 *
442 * Check, if the device is write protected. The function expects, that the
443 * device is already selected.
444 */
445 static int nand_check_wp(struct mtd_info *mtd)
446 {
447 struct nand_chip *chip = mtd->priv;
448
449 /* Broken xD cards report WP despite being writable */
450 if (chip->options & NAND_BROKEN_XD)
451 return 0;
452
453 /* Check the WP bit */
454 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
455 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
456 }
457
458 /**
459 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
460 * @mtd: MTD device structure
461 * @ofs: offset from device start
462 * @getchip: 0, if the chip is already selected
463 * @allowbbt: 1, if its allowed to access the bbt area
464 *
465 * Check, if the block is bad. Either by reading the bad block table or
466 * calling of the scan function.
467 */
468 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
469 int allowbbt)
470 {
471 struct nand_chip *chip = mtd->priv;
472
473 if (!chip->bbt)
474 return chip->block_bad(mtd, ofs, getchip);
475
476 /* Return info from the table */
477 return nand_isbad_bbt(mtd, ofs, allowbbt);
478 }
479
480 /**
481 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
482 * @mtd: MTD device structure
483 * @timeo: Timeout
484 *
485 * Helper function for nand_wait_ready used when needing to wait in interrupt
486 * context.
487 */
488 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
489 {
490 struct nand_chip *chip = mtd->priv;
491 int i;
492
493 /* Wait for the device to get ready */
494 for (i = 0; i < timeo; i++) {
495 if (chip->dev_ready(mtd))
496 break;
497 touch_softlockup_watchdog();
498 mdelay(1);
499 }
500 }
501
502 /* Wait for the ready pin, after a command. The timeout is catched later */
503 void nand_wait_ready(struct mtd_info *mtd)
504 {
505 struct nand_chip *chip = mtd->priv;
506 unsigned long timeo = jiffies + 2;
507
508 /* 400ms timeout */
509 if (in_interrupt() || oops_in_progress)
510 return panic_nand_wait_ready(mtd, 400);
511
512 led_trigger_event(nand_led_trigger, LED_FULL);
513 /* Wait until command is processed or timeout occures */
514 do {
515 if (chip->dev_ready(mtd))
516 break;
517 touch_softlockup_watchdog();
518 } while (time_before(jiffies, timeo));
519 led_trigger_event(nand_led_trigger, LED_OFF);
520 }
521 EXPORT_SYMBOL_GPL(nand_wait_ready);
522
523 /**
524 * nand_command - [DEFAULT] Send command to NAND device
525 * @mtd: MTD device structure
526 * @command: the command to be sent
527 * @column: the column address for this command, -1 if none
528 * @page_addr: the page address for this command, -1 if none
529 *
530 * Send command to NAND device. This function is used for small page devices
531 * (256/512 Bytes per page).
532 */
533 static void nand_command(struct mtd_info *mtd, unsigned int command,
534 int column, int page_addr)
535 {
536 register struct nand_chip *chip = mtd->priv;
537 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
538
539 /* Write out the command to the device */
540 if (command == NAND_CMD_SEQIN) {
541 int readcmd;
542
543 if (column >= mtd->writesize) {
544 /* OOB area */
545 column -= mtd->writesize;
546 readcmd = NAND_CMD_READOOB;
547 } else if (column < 256) {
548 /* First 256 bytes --> READ0 */
549 readcmd = NAND_CMD_READ0;
550 } else {
551 column -= 256;
552 readcmd = NAND_CMD_READ1;
553 }
554 chip->cmd_ctrl(mtd, readcmd, ctrl);
555 ctrl &= ~NAND_CTRL_CHANGE;
556 }
557 chip->cmd_ctrl(mtd, command, ctrl);
558
559 /* Address cycle, when necessary */
560 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
561 /* Serially input address */
562 if (column != -1) {
563 /* Adjust columns for 16 bit buswidth */
564 if (chip->options & NAND_BUSWIDTH_16)
565 column >>= 1;
566 chip->cmd_ctrl(mtd, column, ctrl);
567 ctrl &= ~NAND_CTRL_CHANGE;
568 }
569 if (page_addr != -1) {
570 chip->cmd_ctrl(mtd, page_addr, ctrl);
571 ctrl &= ~NAND_CTRL_CHANGE;
572 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
573 /* One more address cycle for devices > 32MiB */
574 if (chip->chipsize > (32 << 20))
575 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
576 }
577 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
578
579 /*
580 * Program and erase have their own busy handlers status and sequential
581 * in needs no delay
582 */
583 switch (command) {
584
585 case NAND_CMD_PAGEPROG:
586 case NAND_CMD_ERASE1:
587 case NAND_CMD_ERASE2:
588 case NAND_CMD_SEQIN:
589 case NAND_CMD_STATUS:
590 return;
591
592 case NAND_CMD_RESET:
593 if (chip->dev_ready)
594 break;
595 udelay(chip->chip_delay);
596 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
597 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
598 chip->cmd_ctrl(mtd,
599 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
600 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
601 ;
602 return;
603
604 /* This applies to read commands */
605 default:
606 /*
607 * If we don't have access to the busy pin, we apply the given
608 * command delay
609 */
610 if (!chip->dev_ready) {
611 udelay(chip->chip_delay);
612 return;
613 }
614 }
615 /*
616 * Apply this short delay always to ensure that we do wait tWB in
617 * any case on any machine.
618 */
619 ndelay(100);
620
621 nand_wait_ready(mtd);
622 }
623
624 /**
625 * nand_command_lp - [DEFAULT] Send command to NAND large page device
626 * @mtd: MTD device structure
627 * @command: the command to be sent
628 * @column: the column address for this command, -1 if none
629 * @page_addr: the page address for this command, -1 if none
630 *
631 * Send command to NAND device. This is the version for the new large page
632 * devices We dont have the separate regions as we have in the small page
633 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
634 */
635 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
636 int column, int page_addr)
637 {
638 register struct nand_chip *chip = mtd->priv;
639
640 /* Emulate NAND_CMD_READOOB */
641 if (command == NAND_CMD_READOOB) {
642 column += mtd->writesize;
643 command = NAND_CMD_READ0;
644 }
645
646 /* Command latch cycle */
647 chip->cmd_ctrl(mtd, command & 0xff,
648 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
649
650 if (column != -1 || page_addr != -1) {
651 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
652
653 /* Serially input address */
654 if (column != -1) {
655 /* Adjust columns for 16 bit buswidth */
656 if (chip->options & NAND_BUSWIDTH_16)
657 column >>= 1;
658 chip->cmd_ctrl(mtd, column, ctrl);
659 ctrl &= ~NAND_CTRL_CHANGE;
660 chip->cmd_ctrl(mtd, column >> 8, ctrl);
661 }
662 if (page_addr != -1) {
663 chip->cmd_ctrl(mtd, page_addr, ctrl);
664 chip->cmd_ctrl(mtd, page_addr >> 8,
665 NAND_NCE | NAND_ALE);
666 /* One more address cycle for devices > 128MiB */
667 if (chip->chipsize > (128 << 20))
668 chip->cmd_ctrl(mtd, page_addr >> 16,
669 NAND_NCE | NAND_ALE);
670 }
671 }
672 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
673
674 /*
675 * Program and erase have their own busy handlers status, sequential
676 * in, and deplete1 need no delay.
677 */
678 switch (command) {
679
680 case NAND_CMD_CACHEDPROG:
681 case NAND_CMD_PAGEPROG:
682 case NAND_CMD_ERASE1:
683 case NAND_CMD_ERASE2:
684 case NAND_CMD_SEQIN:
685 case NAND_CMD_RNDIN:
686 case NAND_CMD_STATUS:
687 case NAND_CMD_DEPLETE1:
688 return;
689
690 case NAND_CMD_STATUS_ERROR:
691 case NAND_CMD_STATUS_ERROR0:
692 case NAND_CMD_STATUS_ERROR1:
693 case NAND_CMD_STATUS_ERROR2:
694 case NAND_CMD_STATUS_ERROR3:
695 /* Read error status commands require only a short delay */
696 udelay(chip->chip_delay);
697 return;
698
699 case NAND_CMD_RESET:
700 if (chip->dev_ready)
701 break;
702 udelay(chip->chip_delay);
703 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
704 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
705 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
706 NAND_NCE | NAND_CTRL_CHANGE);
707 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
708 ;
709 return;
710
711 case NAND_CMD_RNDOUT:
712 /* No ready / busy check necessary */
713 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 return;
718
719 case NAND_CMD_READ0:
720 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
721 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
722 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
723 NAND_NCE | NAND_CTRL_CHANGE);
724
725 /* This applies to read commands */
726 default:
727 /*
728 * If we don't have access to the busy pin, we apply the given
729 * command delay.
730 */
731 if (!chip->dev_ready) {
732 udelay(chip->chip_delay);
733 return;
734 }
735 }
736
737 /*
738 * Apply this short delay always to ensure that we do wait tWB in
739 * any case on any machine.
740 */
741 ndelay(100);
742
743 nand_wait_ready(mtd);
744 }
745
746 /**
747 * panic_nand_get_device - [GENERIC] Get chip for selected access
748 * @chip: the nand chip descriptor
749 * @mtd: MTD device structure
750 * @new_state: the state which is requested
751 *
752 * Used when in panic, no locks are taken.
753 */
754 static void panic_nand_get_device(struct nand_chip *chip,
755 struct mtd_info *mtd, int new_state)
756 {
757 /* Hardware controller shared among independend devices */
758 chip->controller->active = chip;
759 chip->state = new_state;
760 }
761
762 /**
763 * nand_get_device - [GENERIC] Get chip for selected access
764 * @chip: the nand chip descriptor
765 * @mtd: MTD device structure
766 * @new_state: the state which is requested
767 *
768 * Get the device and lock it for exclusive access
769 */
770 static int
771 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
772 {
773 spinlock_t *lock = &chip->controller->lock;
774 wait_queue_head_t *wq = &chip->controller->wq;
775 DECLARE_WAITQUEUE(wait, current);
776 retry:
777 spin_lock(lock);
778
779 /* Hardware controller shared among independent devices */
780 if (!chip->controller->active)
781 chip->controller->active = chip;
782
783 if (chip->controller->active == chip && chip->state == FL_READY) {
784 chip->state = new_state;
785 spin_unlock(lock);
786 return 0;
787 }
788 if (new_state == FL_PM_SUSPENDED) {
789 if (chip->controller->active->state == FL_PM_SUSPENDED) {
790 chip->state = FL_PM_SUSPENDED;
791 spin_unlock(lock);
792 return 0;
793 }
794 }
795 set_current_state(TASK_UNINTERRUPTIBLE);
796 add_wait_queue(wq, &wait);
797 spin_unlock(lock);
798 schedule();
799 remove_wait_queue(wq, &wait);
800 goto retry;
801 }
802
803 /**
804 * panic_nand_wait - [GENERIC] wait until the command is done
805 * @mtd: MTD device structure
806 * @chip: NAND chip structure
807 * @timeo: timeout
808 *
809 * Wait for command done. This is a helper function for nand_wait used when
810 * we are in interrupt context. May happen when in panic and trying to write
811 * an oops through mtdoops.
812 */
813 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
814 unsigned long timeo)
815 {
816 int i;
817 for (i = 0; i < timeo; i++) {
818 if (chip->dev_ready) {
819 if (chip->dev_ready(mtd))
820 break;
821 } else {
822 if (chip->read_byte(mtd) & NAND_STATUS_READY)
823 break;
824 }
825 mdelay(1);
826 }
827 }
828
829 /**
830 * nand_wait - [DEFAULT] wait until the command is done
831 * @mtd: MTD device structure
832 * @chip: NAND chip structure
833 *
834 * Wait for command done. This applies to erase and program only. Erase can
835 * take up to 400ms and program up to 20ms according to general NAND and
836 * SmartMedia specs.
837 */
838 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
839 {
840
841 unsigned long timeo = jiffies;
842 int status, state = chip->state;
843
844 if (state == FL_ERASING)
845 timeo += (HZ * 400) / 1000;
846 else
847 timeo += (HZ * 20) / 1000;
848
849 led_trigger_event(nand_led_trigger, LED_FULL);
850
851 /*
852 * Apply this short delay always to ensure that we do wait tWB in any
853 * case on any machine.
854 */
855 ndelay(100);
856
857 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
858 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
859 else
860 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
861
862 if (in_interrupt() || oops_in_progress)
863 panic_nand_wait(mtd, chip, timeo);
864 else {
865 while (time_before(jiffies, timeo)) {
866 if (chip->dev_ready) {
867 if (chip->dev_ready(mtd))
868 break;
869 } else {
870 if (chip->read_byte(mtd) & NAND_STATUS_READY)
871 break;
872 }
873 cond_resched();
874 }
875 }
876 led_trigger_event(nand_led_trigger, LED_OFF);
877
878 status = (int)chip->read_byte(mtd);
879 return status;
880 }
881
882 /**
883 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
884 * @mtd: mtd info
885 * @ofs: offset to start unlock from
886 * @len: length to unlock
887 * @invert: when = 0, unlock the range of blocks within the lower and
888 * upper boundary address
889 * when = 1, unlock the range of blocks outside the boundaries
890 * of the lower and upper boundary address
891 *
892 * Returs unlock status.
893 */
894 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
895 uint64_t len, int invert)
896 {
897 int ret = 0;
898 int status, page;
899 struct nand_chip *chip = mtd->priv;
900
901 /* Submit address of first page to unlock */
902 page = ofs >> chip->page_shift;
903 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
904
905 /* Submit address of last page to unlock */
906 page = (ofs + len) >> chip->page_shift;
907 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
908 (page | invert) & chip->pagemask);
909
910 /* Call wait ready function */
911 status = chip->waitfunc(mtd, chip);
912 /* See if device thinks it succeeded */
913 if (status & 0x01) {
914 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
915 __func__, status);
916 ret = -EIO;
917 }
918
919 return ret;
920 }
921
922 /**
923 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
924 * @mtd: mtd info
925 * @ofs: offset to start unlock from
926 * @len: length to unlock
927 *
928 * Returns unlock status.
929 */
930 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
931 {
932 int ret = 0;
933 int chipnr;
934 struct nand_chip *chip = mtd->priv;
935
936 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
937 __func__, (unsigned long long)ofs, len);
938
939 if (check_offs_len(mtd, ofs, len))
940 ret = -EINVAL;
941
942 /* Align to last block address if size addresses end of the device */
943 if (ofs + len == mtd->size)
944 len -= mtd->erasesize;
945
946 nand_get_device(chip, mtd, FL_UNLOCKING);
947
948 /* Shift to get chip number */
949 chipnr = ofs >> chip->chip_shift;
950
951 chip->select_chip(mtd, chipnr);
952
953 /* Check, if it is write protected */
954 if (nand_check_wp(mtd)) {
955 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
956 __func__);
957 ret = -EIO;
958 goto out;
959 }
960
961 ret = __nand_unlock(mtd, ofs, len, 0);
962
963 out:
964 nand_release_device(mtd);
965
966 return ret;
967 }
968 EXPORT_SYMBOL(nand_unlock);
969
970 /**
971 * nand_lock - [REPLACEABLE] locks all blocks present in the device
972 * @mtd: mtd info
973 * @ofs: offset to start unlock from
974 * @len: length to unlock
975 *
976 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
977 * have this feature, but it allows only to lock all blocks, not for specified
978 * range for block. Implementing 'lock' feature by making use of 'unlock', for
979 * now.
980 *
981 * Returns lock status.
982 */
983 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
984 {
985 int ret = 0;
986 int chipnr, status, page;
987 struct nand_chip *chip = mtd->priv;
988
989 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
990 __func__, (unsigned long long)ofs, len);
991
992 if (check_offs_len(mtd, ofs, len))
993 ret = -EINVAL;
994
995 nand_get_device(chip, mtd, FL_LOCKING);
996
997 /* Shift to get chip number */
998 chipnr = ofs >> chip->chip_shift;
999
1000 chip->select_chip(mtd, chipnr);
1001
1002 /* Check, if it is write protected */
1003 if (nand_check_wp(mtd)) {
1004 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1005 __func__);
1006 status = MTD_ERASE_FAILED;
1007 ret = -EIO;
1008 goto out;
1009 }
1010
1011 /* Submit address of first page to lock */
1012 page = ofs >> chip->page_shift;
1013 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1014
1015 /* Call wait ready function */
1016 status = chip->waitfunc(mtd, chip);
1017 /* See if device thinks it succeeded */
1018 if (status & 0x01) {
1019 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1020 __func__, status);
1021 ret = -EIO;
1022 goto out;
1023 }
1024
1025 ret = __nand_unlock(mtd, ofs, len, 0x1);
1026
1027 out:
1028 nand_release_device(mtd);
1029
1030 return ret;
1031 }
1032 EXPORT_SYMBOL(nand_lock);
1033
1034 /**
1035 * nand_read_page_raw - [Intern] read raw page data without ecc
1036 * @mtd: mtd info structure
1037 * @chip: nand chip info structure
1038 * @buf: buffer to store read data
1039 * @page: page number to read
1040 *
1041 * Not for syndrome calculating ecc controllers, which use a special oob
1042 * layout.
1043 */
1044 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1045 uint8_t *buf, int page)
1046 {
1047 chip->read_buf(mtd, buf, mtd->writesize);
1048 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1049 return 0;
1050 }
1051
1052 /**
1053 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1054 * @mtd: mtd info structure
1055 * @chip: nand chip info structure
1056 * @buf: buffer to store read data
1057 * @page: page number to read
1058 *
1059 * We need a special oob layout and handling even when OOB isn't used.
1060 */
1061 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1062 struct nand_chip *chip,
1063 uint8_t *buf, int page)
1064 {
1065 int eccsize = chip->ecc.size;
1066 int eccbytes = chip->ecc.bytes;
1067 uint8_t *oob = chip->oob_poi;
1068 int steps, size;
1069
1070 for (steps = chip->ecc.steps; steps > 0; steps--) {
1071 chip->read_buf(mtd, buf, eccsize);
1072 buf += eccsize;
1073
1074 if (chip->ecc.prepad) {
1075 chip->read_buf(mtd, oob, chip->ecc.prepad);
1076 oob += chip->ecc.prepad;
1077 }
1078
1079 chip->read_buf(mtd, oob, eccbytes);
1080 oob += eccbytes;
1081
1082 if (chip->ecc.postpad) {
1083 chip->read_buf(mtd, oob, chip->ecc.postpad);
1084 oob += chip->ecc.postpad;
1085 }
1086 }
1087
1088 size = mtd->oobsize - (oob - chip->oob_poi);
1089 if (size)
1090 chip->read_buf(mtd, oob, size);
1091
1092 return 0;
1093 }
1094
1095 /**
1096 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1097 * @mtd: mtd info structure
1098 * @chip: nand chip info structure
1099 * @buf: buffer to store read data
1100 * @page: page number to read
1101 */
1102 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1103 uint8_t *buf, int page)
1104 {
1105 int i, eccsize = chip->ecc.size;
1106 int eccbytes = chip->ecc.bytes;
1107 int eccsteps = chip->ecc.steps;
1108 uint8_t *p = buf;
1109 uint8_t *ecc_calc = chip->buffers->ecccalc;
1110 uint8_t *ecc_code = chip->buffers->ecccode;
1111 uint32_t *eccpos = chip->ecc.layout->eccpos;
1112
1113 chip->ecc.read_page_raw(mtd, chip, buf, page);
1114
1115 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1116 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1117
1118 for (i = 0; i < chip->ecc.total; i++)
1119 ecc_code[i] = chip->oob_poi[eccpos[i]];
1120
1121 eccsteps = chip->ecc.steps;
1122 p = buf;
1123
1124 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1125 int stat;
1126
1127 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1128 if (stat < 0)
1129 mtd->ecc_stats.failed++;
1130 else
1131 mtd->ecc_stats.corrected += stat;
1132 }
1133 return 0;
1134 }
1135
1136 /**
1137 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1138 * @mtd: mtd info structure
1139 * @chip: nand chip info structure
1140 * @data_offs: offset of requested data within the page
1141 * @readlen: data length
1142 * @bufpoi: buffer to store read data
1143 */
1144 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1145 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1146 {
1147 int start_step, end_step, num_steps;
1148 uint32_t *eccpos = chip->ecc.layout->eccpos;
1149 uint8_t *p;
1150 int data_col_addr, i, gaps = 0;
1151 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1152 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1153 int index = 0;
1154
1155 /* Column address wihin the page aligned to ECC size (256bytes) */
1156 start_step = data_offs / chip->ecc.size;
1157 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1158 num_steps = end_step - start_step + 1;
1159
1160 /* Data size aligned to ECC ecc.size */
1161 datafrag_len = num_steps * chip->ecc.size;
1162 eccfrag_len = num_steps * chip->ecc.bytes;
1163
1164 data_col_addr = start_step * chip->ecc.size;
1165 /* If we read not a page aligned data */
1166 if (data_col_addr != 0)
1167 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1168
1169 p = bufpoi + data_col_addr;
1170 chip->read_buf(mtd, p, datafrag_len);
1171
1172 /* Calculate ECC */
1173 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1174 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1175
1176 /*
1177 * The performance is faster if we position offsets according to
1178 * ecc.pos. Let's make sure that there are no gaps in ecc positions.
1179 */
1180 for (i = 0; i < eccfrag_len - 1; i++) {
1181 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1182 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1183 gaps = 1;
1184 break;
1185 }
1186 }
1187 if (gaps) {
1188 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1189 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1190 } else {
1191 /*
1192 * Send the command to read the particular ecc bytes take care
1193 * about buswidth alignment in read_buf.
1194 */
1195 index = start_step * chip->ecc.bytes;
1196
1197 aligned_pos = eccpos[index] & ~(busw - 1);
1198 aligned_len = eccfrag_len;
1199 if (eccpos[index] & (busw - 1))
1200 aligned_len++;
1201 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1202 aligned_len++;
1203
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1205 mtd->writesize + aligned_pos, -1);
1206 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1207 }
1208
1209 for (i = 0; i < eccfrag_len; i++)
1210 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1211
1212 p = bufpoi + data_col_addr;
1213 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1214 int stat;
1215
1216 stat = chip->ecc.correct(mtd, p,
1217 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1218 if (stat < 0)
1219 mtd->ecc_stats.failed++;
1220 else
1221 mtd->ecc_stats.corrected += stat;
1222 }
1223 return 0;
1224 }
1225
1226 /**
1227 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1228 * @mtd: mtd info structure
1229 * @chip: nand chip info structure
1230 * @buf: buffer to store read data
1231 * @page: page number to read
1232 *
1233 * Not for syndrome calculating ecc controllers which need a special oob
1234 * layout.
1235 */
1236 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1237 uint8_t *buf, int page)
1238 {
1239 int i, eccsize = chip->ecc.size;
1240 int eccbytes = chip->ecc.bytes;
1241 int eccsteps = chip->ecc.steps;
1242 uint8_t *p = buf;
1243 uint8_t *ecc_calc = chip->buffers->ecccalc;
1244 uint8_t *ecc_code = chip->buffers->ecccode;
1245 uint32_t *eccpos = chip->ecc.layout->eccpos;
1246
1247 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1249 chip->read_buf(mtd, p, eccsize);
1250 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1251 }
1252 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1253
1254 for (i = 0; i < chip->ecc.total; i++)
1255 ecc_code[i] = chip->oob_poi[eccpos[i]];
1256
1257 eccsteps = chip->ecc.steps;
1258 p = buf;
1259
1260 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1261 int stat;
1262
1263 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1264 if (stat < 0)
1265 mtd->ecc_stats.failed++;
1266 else
1267 mtd->ecc_stats.corrected += stat;
1268 }
1269 return 0;
1270 }
1271
1272 /**
1273 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1274 * @mtd: mtd info structure
1275 * @chip: nand chip info structure
1276 * @buf: buffer to store read data
1277 * @page: page number to read
1278 *
1279 * Hardware ECC for large page chips, require OOB to be read first. For this
1280 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283 * the data area, by overwriting the NAND manufacturer bad block markings.
1284 */
1285 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1286 struct nand_chip *chip, uint8_t *buf, int page)
1287 {
1288 int i, eccsize = chip->ecc.size;
1289 int eccbytes = chip->ecc.bytes;
1290 int eccsteps = chip->ecc.steps;
1291 uint8_t *p = buf;
1292 uint8_t *ecc_code = chip->buffers->ecccode;
1293 uint32_t *eccpos = chip->ecc.layout->eccpos;
1294 uint8_t *ecc_calc = chip->buffers->ecccalc;
1295
1296 /* Read the OOB area first */
1297 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1298 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1299 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1300
1301 for (i = 0; i < chip->ecc.total; i++)
1302 ecc_code[i] = chip->oob_poi[eccpos[i]];
1303
1304 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305 int stat;
1306
1307 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1308 chip->read_buf(mtd, p, eccsize);
1309 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1310
1311 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1312 if (stat < 0)
1313 mtd->ecc_stats.failed++;
1314 else
1315 mtd->ecc_stats.corrected += stat;
1316 }
1317 return 0;
1318 }
1319
1320 /**
1321 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1322 * @mtd: mtd info structure
1323 * @chip: nand chip info structure
1324 * @buf: buffer to store read data
1325 * @page: page number to read
1326 *
1327 * The hw generator calculates the error syndrome automatically. Therefore we
1328 * need a special oob layout and handling.
1329 */
1330 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1331 uint8_t *buf, int page)
1332 {
1333 int i, eccsize = chip->ecc.size;
1334 int eccbytes = chip->ecc.bytes;
1335 int eccsteps = chip->ecc.steps;
1336 uint8_t *p = buf;
1337 uint8_t *oob = chip->oob_poi;
1338
1339 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340 int stat;
1341
1342 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1343 chip->read_buf(mtd, p, eccsize);
1344
1345 if (chip->ecc.prepad) {
1346 chip->read_buf(mtd, oob, chip->ecc.prepad);
1347 oob += chip->ecc.prepad;
1348 }
1349
1350 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1351 chip->read_buf(mtd, oob, eccbytes);
1352 stat = chip->ecc.correct(mtd, p, oob, NULL);
1353
1354 if (stat < 0)
1355 mtd->ecc_stats.failed++;
1356 else
1357 mtd->ecc_stats.corrected += stat;
1358
1359 oob += eccbytes;
1360
1361 if (chip->ecc.postpad) {
1362 chip->read_buf(mtd, oob, chip->ecc.postpad);
1363 oob += chip->ecc.postpad;
1364 }
1365 }
1366
1367 /* Calculate remaining oob bytes */
1368 i = mtd->oobsize - (oob - chip->oob_poi);
1369 if (i)
1370 chip->read_buf(mtd, oob, i);
1371
1372 return 0;
1373 }
1374
1375 /**
1376 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1377 * @chip: nand chip structure
1378 * @oob: oob destination address
1379 * @ops: oob ops structure
1380 * @len: size of oob to transfer
1381 */
1382 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1383 struct mtd_oob_ops *ops, size_t len)
1384 {
1385 switch (ops->mode) {
1386
1387 case MTD_OOB_PLACE:
1388 case MTD_OOB_RAW:
1389 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1390 return oob + len;
1391
1392 case MTD_OOB_AUTO: {
1393 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1394 uint32_t boffs = 0, roffs = ops->ooboffs;
1395 size_t bytes = 0;
1396
1397 for (; free->length && len; free++, len -= bytes) {
1398 /* Read request not from offset 0? */
1399 if (unlikely(roffs)) {
1400 if (roffs >= free->length) {
1401 roffs -= free->length;
1402 continue;
1403 }
1404 boffs = free->offset + roffs;
1405 bytes = min_t(size_t, len,
1406 (free->length - roffs));
1407 roffs = 0;
1408 } else {
1409 bytes = min_t(size_t, len, free->length);
1410 boffs = free->offset;
1411 }
1412 memcpy(oob, chip->oob_poi + boffs, bytes);
1413 oob += bytes;
1414 }
1415 return oob;
1416 }
1417 default:
1418 BUG();
1419 }
1420 return NULL;
1421 }
1422
1423 /**
1424 * nand_do_read_ops - [Internal] Read data with ECC
1425 * @mtd: MTD device structure
1426 * @from: offset to read from
1427 * @ops: oob ops structure
1428 *
1429 * Internal function. Called with chip held.
1430 */
1431 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1432 struct mtd_oob_ops *ops)
1433 {
1434 int chipnr, page, realpage, col, bytes, aligned;
1435 struct nand_chip *chip = mtd->priv;
1436 struct mtd_ecc_stats stats;
1437 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1438 int sndcmd = 1;
1439 int ret = 0;
1440 uint32_t readlen = ops->len;
1441 uint32_t oobreadlen = ops->ooblen;
1442 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1443 mtd->oobavail : mtd->oobsize;
1444
1445 uint8_t *bufpoi, *oob, *buf;
1446
1447 stats = mtd->ecc_stats;
1448
1449 chipnr = (int)(from >> chip->chip_shift);
1450 chip->select_chip(mtd, chipnr);
1451
1452 realpage = (int)(from >> chip->page_shift);
1453 page = realpage & chip->pagemask;
1454
1455 col = (int)(from & (mtd->writesize - 1));
1456
1457 buf = ops->datbuf;
1458 oob = ops->oobbuf;
1459
1460 while (1) {
1461 bytes = min(mtd->writesize - col, readlen);
1462 aligned = (bytes == mtd->writesize);
1463
1464 /* Is the current page in the buffer? */
1465 if (realpage != chip->pagebuf || oob) {
1466 bufpoi = aligned ? buf : chip->buffers->databuf;
1467
1468 if (likely(sndcmd)) {
1469 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1470 sndcmd = 0;
1471 }
1472
1473 /* Now read the page into the buffer */
1474 if (unlikely(ops->mode == MTD_OOB_RAW))
1475 ret = chip->ecc.read_page_raw(mtd, chip,
1476 bufpoi, page);
1477 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1478 ret = chip->ecc.read_subpage(mtd, chip,
1479 col, bytes, bufpoi);
1480 else
1481 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1482 page);
1483 if (ret < 0)
1484 break;
1485
1486 /* Transfer not aligned data */
1487 if (!aligned) {
1488 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1489 !(mtd->ecc_stats.failed - stats.failed))
1490 chip->pagebuf = realpage;
1491 memcpy(buf, chip->buffers->databuf + col, bytes);
1492 }
1493
1494 buf += bytes;
1495
1496 if (unlikely(oob)) {
1497
1498 int toread = min(oobreadlen, max_oobsize);
1499
1500 if (toread) {
1501 oob = nand_transfer_oob(chip,
1502 oob, ops, toread);
1503 oobreadlen -= toread;
1504 }
1505 }
1506
1507 if (!(chip->options & NAND_NO_READRDY)) {
1508 /*
1509 * Apply delay or wait for ready/busy pin. Do
1510 * this before the AUTOINCR check, so no
1511 * problems arise if a chip which does auto
1512 * increment is marked as NOAUTOINCR by the
1513 * board driver.
1514 */
1515 if (!chip->dev_ready)
1516 udelay(chip->chip_delay);
1517 else
1518 nand_wait_ready(mtd);
1519 }
1520 } else {
1521 memcpy(buf, chip->buffers->databuf + col, bytes);
1522 buf += bytes;
1523 }
1524
1525 readlen -= bytes;
1526
1527 if (!readlen)
1528 break;
1529
1530 /* For subsequent reads align to page boundary */
1531 col = 0;
1532 /* Increment page address */
1533 realpage++;
1534
1535 page = realpage & chip->pagemask;
1536 /* Check, if we cross a chip boundary */
1537 if (!page) {
1538 chipnr++;
1539 chip->select_chip(mtd, -1);
1540 chip->select_chip(mtd, chipnr);
1541 }
1542
1543 /*
1544 * Check, if the chip supports auto page increment or if we
1545 * have hit a block boundary.
1546 */
1547 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1548 sndcmd = 1;
1549 }
1550
1551 ops->retlen = ops->len - (size_t) readlen;
1552 if (oob)
1553 ops->oobretlen = ops->ooblen - oobreadlen;
1554
1555 if (ret)
1556 return ret;
1557
1558 if (mtd->ecc_stats.failed - stats.failed)
1559 return -EBADMSG;
1560
1561 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1562 }
1563
1564 /**
1565 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1566 * @mtd: MTD device structure
1567 * @from: offset to read from
1568 * @len: number of bytes to read
1569 * @retlen: pointer to variable to store the number of read bytes
1570 * @buf: the databuffer to put data
1571 *
1572 * Get hold of the chip and call nand_do_read.
1573 */
1574 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1575 size_t *retlen, uint8_t *buf)
1576 {
1577 struct nand_chip *chip = mtd->priv;
1578 int ret;
1579
1580 /* Do not allow reads past end of device */
1581 if ((from + len) > mtd->size)
1582 return -EINVAL;
1583 if (!len)
1584 return 0;
1585
1586 nand_get_device(chip, mtd, FL_READING);
1587
1588 chip->ops.len = len;
1589 chip->ops.datbuf = buf;
1590 chip->ops.oobbuf = NULL;
1591
1592 ret = nand_do_read_ops(mtd, from, &chip->ops);
1593
1594 *retlen = chip->ops.retlen;
1595
1596 nand_release_device(mtd);
1597
1598 return ret;
1599 }
1600
1601 /**
1602 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1603 * @mtd: mtd info structure
1604 * @chip: nand chip info structure
1605 * @page: page number to read
1606 * @sndcmd: flag whether to issue read command or not
1607 */
1608 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1609 int page, int sndcmd)
1610 {
1611 if (sndcmd) {
1612 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1613 sndcmd = 0;
1614 }
1615 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1616 return sndcmd;
1617 }
1618
1619 /**
1620 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1621 * with syndromes
1622 * @mtd: mtd info structure
1623 * @chip: nand chip info structure
1624 * @page: page number to read
1625 * @sndcmd: flag whether to issue read command or not
1626 */
1627 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1628 int page, int sndcmd)
1629 {
1630 uint8_t *buf = chip->oob_poi;
1631 int length = mtd->oobsize;
1632 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1633 int eccsize = chip->ecc.size;
1634 uint8_t *bufpoi = buf;
1635 int i, toread, sndrnd = 0, pos;
1636
1637 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1638 for (i = 0; i < chip->ecc.steps; i++) {
1639 if (sndrnd) {
1640 pos = eccsize + i * (eccsize + chunk);
1641 if (mtd->writesize > 512)
1642 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1643 else
1644 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1645 } else
1646 sndrnd = 1;
1647 toread = min_t(int, length, chunk);
1648 chip->read_buf(mtd, bufpoi, toread);
1649 bufpoi += toread;
1650 length -= toread;
1651 }
1652 if (length > 0)
1653 chip->read_buf(mtd, bufpoi, length);
1654
1655 return 1;
1656 }
1657
1658 /**
1659 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1660 * @mtd: mtd info structure
1661 * @chip: nand chip info structure
1662 * @page: page number to write
1663 */
1664 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1665 int page)
1666 {
1667 int status = 0;
1668 const uint8_t *buf = chip->oob_poi;
1669 int length = mtd->oobsize;
1670
1671 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1672 chip->write_buf(mtd, buf, length);
1673 /* Send command to program the OOB data */
1674 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1675
1676 status = chip->waitfunc(mtd, chip);
1677
1678 return status & NAND_STATUS_FAIL ? -EIO : 0;
1679 }
1680
1681 /**
1682 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1683 * with syndrome - only for large page flash
1684 * @mtd: mtd info structure
1685 * @chip: nand chip info structure
1686 * @page: page number to write
1687 */
1688 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1689 struct nand_chip *chip, int page)
1690 {
1691 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1692 int eccsize = chip->ecc.size, length = mtd->oobsize;
1693 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1694 const uint8_t *bufpoi = chip->oob_poi;
1695
1696 /*
1697 * data-ecc-data-ecc ... ecc-oob
1698 * or
1699 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1700 */
1701 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1702 pos = steps * (eccsize + chunk);
1703 steps = 0;
1704 } else
1705 pos = eccsize;
1706
1707 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1708 for (i = 0; i < steps; i++) {
1709 if (sndcmd) {
1710 if (mtd->writesize <= 512) {
1711 uint32_t fill = 0xFFFFFFFF;
1712
1713 len = eccsize;
1714 while (len > 0) {
1715 int num = min_t(int, len, 4);
1716 chip->write_buf(mtd, (uint8_t *)&fill,
1717 num);
1718 len -= num;
1719 }
1720 } else {
1721 pos = eccsize + i * (eccsize + chunk);
1722 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1723 }
1724 } else
1725 sndcmd = 1;
1726 len = min_t(int, length, chunk);
1727 chip->write_buf(mtd, bufpoi, len);
1728 bufpoi += len;
1729 length -= len;
1730 }
1731 if (length > 0)
1732 chip->write_buf(mtd, bufpoi, length);
1733
1734 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1735 status = chip->waitfunc(mtd, chip);
1736
1737 return status & NAND_STATUS_FAIL ? -EIO : 0;
1738 }
1739
1740 /**
1741 * nand_do_read_oob - [Intern] NAND read out-of-band
1742 * @mtd: MTD device structure
1743 * @from: offset to read from
1744 * @ops: oob operations description structure
1745 *
1746 * NAND read out-of-band data from the spare area.
1747 */
1748 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1749 struct mtd_oob_ops *ops)
1750 {
1751 int page, realpage, chipnr, sndcmd = 1;
1752 struct nand_chip *chip = mtd->priv;
1753 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1754 int readlen = ops->ooblen;
1755 int len;
1756 uint8_t *buf = ops->oobbuf;
1757
1758 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1759 __func__, (unsigned long long)from, readlen);
1760
1761 if (ops->mode == MTD_OOB_AUTO)
1762 len = chip->ecc.layout->oobavail;
1763 else
1764 len = mtd->oobsize;
1765
1766 if (unlikely(ops->ooboffs >= len)) {
1767 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1768 "outside oob\n", __func__);
1769 return -EINVAL;
1770 }
1771
1772 /* Do not allow reads past end of device */
1773 if (unlikely(from >= mtd->size ||
1774 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1775 (from >> chip->page_shift)) * len)) {
1776 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1777 "of device\n", __func__);
1778 return -EINVAL;
1779 }
1780
1781 chipnr = (int)(from >> chip->chip_shift);
1782 chip->select_chip(mtd, chipnr);
1783
1784 /* Shift to get page */
1785 realpage = (int)(from >> chip->page_shift);
1786 page = realpage & chip->pagemask;
1787
1788 while (1) {
1789 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1790
1791 len = min(len, readlen);
1792 buf = nand_transfer_oob(chip, buf, ops, len);
1793
1794 if (!(chip->options & NAND_NO_READRDY)) {
1795 /*
1796 * Apply delay or wait for ready/busy pin. Do this
1797 * before the AUTOINCR check, so no problems arise if a
1798 * chip which does auto increment is marked as
1799 * NOAUTOINCR by the board driver.
1800 */
1801 if (!chip->dev_ready)
1802 udelay(chip->chip_delay);
1803 else
1804 nand_wait_ready(mtd);
1805 }
1806
1807 readlen -= len;
1808 if (!readlen)
1809 break;
1810
1811 /* Increment page address */
1812 realpage++;
1813
1814 page = realpage & chip->pagemask;
1815 /* Check, if we cross a chip boundary */
1816 if (!page) {
1817 chipnr++;
1818 chip->select_chip(mtd, -1);
1819 chip->select_chip(mtd, chipnr);
1820 }
1821
1822 /*
1823 * Check, if the chip supports auto page increment or if we
1824 * have hit a block boundary.
1825 */
1826 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1827 sndcmd = 1;
1828 }
1829
1830 ops->oobretlen = ops->ooblen;
1831 return 0;
1832 }
1833
1834 /**
1835 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1836 * @mtd: MTD device structure
1837 * @from: offset to read from
1838 * @ops: oob operation description structure
1839 *
1840 * NAND read data and/or out-of-band data.
1841 */
1842 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1843 struct mtd_oob_ops *ops)
1844 {
1845 struct nand_chip *chip = mtd->priv;
1846 int ret = -ENOTSUPP;
1847
1848 ops->retlen = 0;
1849
1850 /* Do not allow reads past end of device */
1851 if (ops->datbuf && (from + ops->len) > mtd->size) {
1852 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1853 "beyond end of device\n", __func__);
1854 return -EINVAL;
1855 }
1856
1857 nand_get_device(chip, mtd, FL_READING);
1858
1859 switch (ops->mode) {
1860 case MTD_OOB_PLACE:
1861 case MTD_OOB_AUTO:
1862 case MTD_OOB_RAW:
1863 break;
1864
1865 default:
1866 goto out;
1867 }
1868
1869 if (!ops->datbuf)
1870 ret = nand_do_read_oob(mtd, from, ops);
1871 else
1872 ret = nand_do_read_ops(mtd, from, ops);
1873
1874 out:
1875 nand_release_device(mtd);
1876 return ret;
1877 }
1878
1879
1880 /**
1881 * nand_write_page_raw - [Intern] raw page write function
1882 * @mtd: mtd info structure
1883 * @chip: nand chip info structure
1884 * @buf: data buffer
1885 *
1886 * Not for syndrome calculating ecc controllers, which use a special oob
1887 * layout.
1888 */
1889 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1890 const uint8_t *buf)
1891 {
1892 chip->write_buf(mtd, buf, mtd->writesize);
1893 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1894 }
1895
1896 /**
1897 * nand_write_page_raw_syndrome - [Intern] raw page write function
1898 * @mtd: mtd info structure
1899 * @chip: nand chip info structure
1900 * @buf: data buffer
1901 *
1902 * We need a special oob layout and handling even when ECC isn't checked.
1903 */
1904 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1905 struct nand_chip *chip,
1906 const uint8_t *buf)
1907 {
1908 int eccsize = chip->ecc.size;
1909 int eccbytes = chip->ecc.bytes;
1910 uint8_t *oob = chip->oob_poi;
1911 int steps, size;
1912
1913 for (steps = chip->ecc.steps; steps > 0; steps--) {
1914 chip->write_buf(mtd, buf, eccsize);
1915 buf += eccsize;
1916
1917 if (chip->ecc.prepad) {
1918 chip->write_buf(mtd, oob, chip->ecc.prepad);
1919 oob += chip->ecc.prepad;
1920 }
1921
1922 chip->read_buf(mtd, oob, eccbytes);
1923 oob += eccbytes;
1924
1925 if (chip->ecc.postpad) {
1926 chip->write_buf(mtd, oob, chip->ecc.postpad);
1927 oob += chip->ecc.postpad;
1928 }
1929 }
1930
1931 size = mtd->oobsize - (oob - chip->oob_poi);
1932 if (size)
1933 chip->write_buf(mtd, oob, size);
1934 }
1935 /**
1936 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1937 * @mtd: mtd info structure
1938 * @chip: nand chip info structure
1939 * @buf: data buffer
1940 */
1941 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1942 const uint8_t *buf)
1943 {
1944 int i, eccsize = chip->ecc.size;
1945 int eccbytes = chip->ecc.bytes;
1946 int eccsteps = chip->ecc.steps;
1947 uint8_t *ecc_calc = chip->buffers->ecccalc;
1948 const uint8_t *p = buf;
1949 uint32_t *eccpos = chip->ecc.layout->eccpos;
1950
1951 /* Software ecc calculation */
1952 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1953 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1954
1955 for (i = 0; i < chip->ecc.total; i++)
1956 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1957
1958 chip->ecc.write_page_raw(mtd, chip, buf);
1959 }
1960
1961 /**
1962 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1963 * @mtd: mtd info structure
1964 * @chip: nand chip info structure
1965 * @buf: data buffer
1966 */
1967 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1968 const uint8_t *buf)
1969 {
1970 int i, eccsize = chip->ecc.size;
1971 int eccbytes = chip->ecc.bytes;
1972 int eccsteps = chip->ecc.steps;
1973 uint8_t *ecc_calc = chip->buffers->ecccalc;
1974 const uint8_t *p = buf;
1975 uint32_t *eccpos = chip->ecc.layout->eccpos;
1976
1977 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1978 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1979 chip->write_buf(mtd, p, eccsize);
1980 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1981 }
1982
1983 for (i = 0; i < chip->ecc.total; i++)
1984 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1985
1986 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1987 }
1988
1989 /**
1990 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1991 * @mtd: mtd info structure
1992 * @chip: nand chip info structure
1993 * @buf: data buffer
1994 *
1995 * The hw generator calculates the error syndrome automatically. Therefore we
1996 * need a special oob layout and handling.
1997 */
1998 static void nand_write_page_syndrome(struct mtd_info *mtd,
1999 struct nand_chip *chip, const uint8_t *buf)
2000 {
2001 int i, eccsize = chip->ecc.size;
2002 int eccbytes = chip->ecc.bytes;
2003 int eccsteps = chip->ecc.steps;
2004 const uint8_t *p = buf;
2005 uint8_t *oob = chip->oob_poi;
2006
2007 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2008
2009 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2010 chip->write_buf(mtd, p, eccsize);
2011
2012 if (chip->ecc.prepad) {
2013 chip->write_buf(mtd, oob, chip->ecc.prepad);
2014 oob += chip->ecc.prepad;
2015 }
2016
2017 chip->ecc.calculate(mtd, p, oob);
2018 chip->write_buf(mtd, oob, eccbytes);
2019 oob += eccbytes;
2020
2021 if (chip->ecc.postpad) {
2022 chip->write_buf(mtd, oob, chip->ecc.postpad);
2023 oob += chip->ecc.postpad;
2024 }
2025 }
2026
2027 /* Calculate remaining oob bytes */
2028 i = mtd->oobsize - (oob - chip->oob_poi);
2029 if (i)
2030 chip->write_buf(mtd, oob, i);
2031 }
2032
2033 /**
2034 * nand_write_page - [REPLACEABLE] write one page
2035 * @mtd: MTD device structure
2036 * @chip: NAND chip descriptor
2037 * @buf: the data to write
2038 * @page: page number to write
2039 * @cached: cached programming
2040 * @raw: use _raw version of write_page
2041 */
2042 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2043 const uint8_t *buf, int page, int cached, int raw)
2044 {
2045 int status;
2046
2047 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2048
2049 if (unlikely(raw))
2050 chip->ecc.write_page_raw(mtd, chip, buf);
2051 else
2052 chip->ecc.write_page(mtd, chip, buf);
2053
2054 /*
2055 * Cached progamming disabled for now, Not sure if its worth the
2056 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2057 */
2058 cached = 0;
2059
2060 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2061
2062 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2063 status = chip->waitfunc(mtd, chip);
2064 /*
2065 * See if operation failed and additional status checks are
2066 * available.
2067 */
2068 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2069 status = chip->errstat(mtd, chip, FL_WRITING, status,
2070 page);
2071
2072 if (status & NAND_STATUS_FAIL)
2073 return -EIO;
2074 } else {
2075 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2076 status = chip->waitfunc(mtd, chip);
2077 }
2078
2079 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2080 /* Send command to read back the data */
2081 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2082
2083 if (chip->verify_buf(mtd, buf, mtd->writesize))
2084 return -EIO;
2085 #endif
2086 return 0;
2087 }
2088
2089 /**
2090 * nand_fill_oob - [Internal] Transfer client buffer to oob
2091 * @mtd: MTD device structure
2092 * @oob: oob data buffer
2093 * @len: oob data write length
2094 * @ops: oob ops structure
2095 */
2096 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2097 struct mtd_oob_ops *ops)
2098 {
2099 struct nand_chip *chip = mtd->priv;
2100
2101 /*
2102 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2103 * data from a previous OOB read.
2104 */
2105 memset(chip->oob_poi, 0xff, mtd->oobsize);
2106
2107 switch (ops->mode) {
2108
2109 case MTD_OOB_PLACE:
2110 case MTD_OOB_RAW:
2111 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2112 return oob + len;
2113
2114 case MTD_OOB_AUTO: {
2115 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2116 uint32_t boffs = 0, woffs = ops->ooboffs;
2117 size_t bytes = 0;
2118
2119 for (; free->length && len; free++, len -= bytes) {
2120 /* Write request not from offset 0? */
2121 if (unlikely(woffs)) {
2122 if (woffs >= free->length) {
2123 woffs -= free->length;
2124 continue;
2125 }
2126 boffs = free->offset + woffs;
2127 bytes = min_t(size_t, len,
2128 (free->length - woffs));
2129 woffs = 0;
2130 } else {
2131 bytes = min_t(size_t, len, free->length);
2132 boffs = free->offset;
2133 }
2134 memcpy(chip->oob_poi + boffs, oob, bytes);
2135 oob += bytes;
2136 }
2137 return oob;
2138 }
2139 default:
2140 BUG();
2141 }
2142 return NULL;
2143 }
2144
2145 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2146
2147 /**
2148 * nand_do_write_ops - [Internal] NAND write with ECC
2149 * @mtd: MTD device structure
2150 * @to: offset to write to
2151 * @ops: oob operations description structure
2152 *
2153 * NAND write with ECC.
2154 */
2155 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2156 struct mtd_oob_ops *ops)
2157 {
2158 int chipnr, realpage, page, blockmask, column;
2159 struct nand_chip *chip = mtd->priv;
2160 uint32_t writelen = ops->len;
2161
2162 uint32_t oobwritelen = ops->ooblen;
2163 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2164 mtd->oobavail : mtd->oobsize;
2165
2166 uint8_t *oob = ops->oobbuf;
2167 uint8_t *buf = ops->datbuf;
2168 int ret, subpage;
2169
2170 ops->retlen = 0;
2171 if (!writelen)
2172 return 0;
2173
2174 /* Reject writes, which are not page aligned */
2175 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2176 printk(KERN_NOTICE "%s: Attempt to write not "
2177 "page aligned data\n", __func__);
2178 return -EINVAL;
2179 }
2180
2181 column = to & (mtd->writesize - 1);
2182 subpage = column || (writelen & (mtd->writesize - 1));
2183
2184 if (subpage && oob)
2185 return -EINVAL;
2186
2187 chipnr = (int)(to >> chip->chip_shift);
2188 chip->select_chip(mtd, chipnr);
2189
2190 /* Check, if it is write protected */
2191 if (nand_check_wp(mtd))
2192 return -EIO;
2193
2194 realpage = (int)(to >> chip->page_shift);
2195 page = realpage & chip->pagemask;
2196 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2197
2198 /* Invalidate the page cache, when we write to the cached page */
2199 if (to <= (chip->pagebuf << chip->page_shift) &&
2200 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2201 chip->pagebuf = -1;
2202
2203 /* Don't allow multipage oob writes with offset */
2204 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2205 return -EINVAL;
2206
2207 while (1) {
2208 int bytes = mtd->writesize;
2209 int cached = writelen > bytes && page != blockmask;
2210 uint8_t *wbuf = buf;
2211
2212 /* Partial page write? */
2213 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2214 cached = 0;
2215 bytes = min_t(int, bytes - column, (int) writelen);
2216 chip->pagebuf = -1;
2217 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2218 memcpy(&chip->buffers->databuf[column], buf, bytes);
2219 wbuf = chip->buffers->databuf;
2220 }
2221
2222 if (unlikely(oob)) {
2223 size_t len = min(oobwritelen, oobmaxlen);
2224 oob = nand_fill_oob(mtd, oob, len, ops);
2225 oobwritelen -= len;
2226 } else {
2227 /* We still need to erase leftover OOB data */
2228 memset(chip->oob_poi, 0xff, mtd->oobsize);
2229 }
2230
2231 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2232 (ops->mode == MTD_OOB_RAW));
2233 if (ret)
2234 break;
2235
2236 writelen -= bytes;
2237 if (!writelen)
2238 break;
2239
2240 column = 0;
2241 buf += bytes;
2242 realpage++;
2243
2244 page = realpage & chip->pagemask;
2245 /* Check, if we cross a chip boundary */
2246 if (!page) {
2247 chipnr++;
2248 chip->select_chip(mtd, -1);
2249 chip->select_chip(mtd, chipnr);
2250 }
2251 }
2252
2253 ops->retlen = ops->len - writelen;
2254 if (unlikely(oob))
2255 ops->oobretlen = ops->ooblen;
2256 return ret;
2257 }
2258
2259 /**
2260 * panic_nand_write - [MTD Interface] NAND write with ECC
2261 * @mtd: MTD device structure
2262 * @to: offset to write to
2263 * @len: number of bytes to write
2264 * @retlen: pointer to variable to store the number of written bytes
2265 * @buf: the data to write
2266 *
2267 * NAND write with ECC. Used when performing writes in interrupt context, this
2268 * may for example be called by mtdoops when writing an oops while in panic.
2269 */
2270 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2271 size_t *retlen, const uint8_t *buf)
2272 {
2273 struct nand_chip *chip = mtd->priv;
2274 int ret;
2275
2276 /* Do not allow reads past end of device */
2277 if ((to + len) > mtd->size)
2278 return -EINVAL;
2279 if (!len)
2280 return 0;
2281
2282 /* Wait for the device to get ready */
2283 panic_nand_wait(mtd, chip, 400);
2284
2285 /* Grab the device */
2286 panic_nand_get_device(chip, mtd, FL_WRITING);
2287
2288 chip->ops.len = len;
2289 chip->ops.datbuf = (uint8_t *)buf;
2290 chip->ops.oobbuf = NULL;
2291
2292 ret = nand_do_write_ops(mtd, to, &chip->ops);
2293
2294 *retlen = chip->ops.retlen;
2295 return ret;
2296 }
2297
2298 /**
2299 * nand_write - [MTD Interface] NAND write with ECC
2300 * @mtd: MTD device structure
2301 * @to: offset to write to
2302 * @len: number of bytes to write
2303 * @retlen: pointer to variable to store the number of written bytes
2304 * @buf: the data to write
2305 *
2306 * NAND write with ECC.
2307 */
2308 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2309 size_t *retlen, const uint8_t *buf)
2310 {
2311 struct nand_chip *chip = mtd->priv;
2312 int ret;
2313
2314 /* Do not allow reads past end of device */
2315 if ((to + len) > mtd->size)
2316 return -EINVAL;
2317 if (!len)
2318 return 0;
2319
2320 nand_get_device(chip, mtd, FL_WRITING);
2321
2322 chip->ops.len = len;
2323 chip->ops.datbuf = (uint8_t *)buf;
2324 chip->ops.oobbuf = NULL;
2325
2326 ret = nand_do_write_ops(mtd, to, &chip->ops);
2327
2328 *retlen = chip->ops.retlen;
2329
2330 nand_release_device(mtd);
2331
2332 return ret;
2333 }
2334
2335 /**
2336 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2337 * @mtd: MTD device structure
2338 * @to: offset to write to
2339 * @ops: oob operation description structure
2340 *
2341 * NAND write out-of-band.
2342 */
2343 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2344 struct mtd_oob_ops *ops)
2345 {
2346 int chipnr, page, status, len;
2347 struct nand_chip *chip = mtd->priv;
2348
2349 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2350 __func__, (unsigned int)to, (int)ops->ooblen);
2351
2352 if (ops->mode == MTD_OOB_AUTO)
2353 len = chip->ecc.layout->oobavail;
2354 else
2355 len = mtd->oobsize;
2356
2357 /* Do not allow write past end of page */
2358 if ((ops->ooboffs + ops->ooblen) > len) {
2359 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2360 "past end of page\n", __func__);
2361 return -EINVAL;
2362 }
2363
2364 if (unlikely(ops->ooboffs >= len)) {
2365 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2366 "write outside oob\n", __func__);
2367 return -EINVAL;
2368 }
2369
2370 /* Do not allow write past end of device */
2371 if (unlikely(to >= mtd->size ||
2372 ops->ooboffs + ops->ooblen >
2373 ((mtd->size >> chip->page_shift) -
2374 (to >> chip->page_shift)) * len)) {
2375 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2376 "end of device\n", __func__);
2377 return -EINVAL;
2378 }
2379
2380 chipnr = (int)(to >> chip->chip_shift);
2381 chip->select_chip(mtd, chipnr);
2382
2383 /* Shift to get page */
2384 page = (int)(to >> chip->page_shift);
2385
2386 /*
2387 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2388 * of my DiskOnChip 2000 test units) will clear the whole data page too
2389 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2390 * it in the doc2000 driver in August 1999. dwmw2.
2391 */
2392 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2393
2394 /* Check, if it is write protected */
2395 if (nand_check_wp(mtd))
2396 return -EROFS;
2397
2398 /* Invalidate the page cache, if we write to the cached page */
2399 if (page == chip->pagebuf)
2400 chip->pagebuf = -1;
2401
2402 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2403 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2404
2405 if (status)
2406 return status;
2407
2408 ops->oobretlen = ops->ooblen;
2409
2410 return 0;
2411 }
2412
2413 /**
2414 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2415 * @mtd: MTD device structure
2416 * @to: offset to write to
2417 * @ops: oob operation description structure
2418 */
2419 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2420 struct mtd_oob_ops *ops)
2421 {
2422 struct nand_chip *chip = mtd->priv;
2423 int ret = -ENOTSUPP;
2424
2425 ops->retlen = 0;
2426
2427 /* Do not allow writes past end of device */
2428 if (ops->datbuf && (to + ops->len) > mtd->size) {
2429 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2430 "end of device\n", __func__);
2431 return -EINVAL;
2432 }
2433
2434 nand_get_device(chip, mtd, FL_WRITING);
2435
2436 switch (ops->mode) {
2437 case MTD_OOB_PLACE:
2438 case MTD_OOB_AUTO:
2439 case MTD_OOB_RAW:
2440 break;
2441
2442 default:
2443 goto out;
2444 }
2445
2446 if (!ops->datbuf)
2447 ret = nand_do_write_oob(mtd, to, ops);
2448 else
2449 ret = nand_do_write_ops(mtd, to, ops);
2450
2451 out:
2452 nand_release_device(mtd);
2453 return ret;
2454 }
2455
2456 /**
2457 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2458 * @mtd: MTD device structure
2459 * @page: the page address of the block which will be erased
2460 *
2461 * Standard erase command for NAND chips.
2462 */
2463 static void single_erase_cmd(struct mtd_info *mtd, int page)
2464 {
2465 struct nand_chip *chip = mtd->priv;
2466 /* Send commands to erase a block */
2467 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2469 }
2470
2471 /**
2472 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2473 * @mtd: MTD device structure
2474 * @page: the page address of the block which will be erased
2475 *
2476 * AND multi block erase command function. Erase 4 consecutive blocks.
2477 */
2478 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2479 {
2480 struct nand_chip *chip = mtd->priv;
2481 /* Send commands to erase a block */
2482 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2486 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2487 }
2488
2489 /**
2490 * nand_erase - [MTD Interface] erase block(s)
2491 * @mtd: MTD device structure
2492 * @instr: erase instruction
2493 *
2494 * Erase one ore more blocks.
2495 */
2496 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2497 {
2498 return nand_erase_nand(mtd, instr, 0);
2499 }
2500
2501 #define BBT_PAGE_MASK 0xffffff3f
2502 /**
2503 * nand_erase_nand - [Internal] erase block(s)
2504 * @mtd: MTD device structure
2505 * @instr: erase instruction
2506 * @allowbbt: allow erasing the bbt area
2507 *
2508 * Erase one ore more blocks.
2509 */
2510 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2511 int allowbbt)
2512 {
2513 int page, status, pages_per_block, ret, chipnr;
2514 struct nand_chip *chip = mtd->priv;
2515 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2516 unsigned int bbt_masked_page = 0xffffffff;
2517 loff_t len;
2518
2519 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2520 __func__, (unsigned long long)instr->addr,
2521 (unsigned long long)instr->len);
2522
2523 if (check_offs_len(mtd, instr->addr, instr->len))
2524 return -EINVAL;
2525
2526 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2527
2528 /* Grab the lock and see if the device is available */
2529 nand_get_device(chip, mtd, FL_ERASING);
2530
2531 /* Shift to get first page */
2532 page = (int)(instr->addr >> chip->page_shift);
2533 chipnr = (int)(instr->addr >> chip->chip_shift);
2534
2535 /* Calculate pages in each block */
2536 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2537
2538 /* Select the NAND device */
2539 chip->select_chip(mtd, chipnr);
2540
2541 /* Check, if it is write protected */
2542 if (nand_check_wp(mtd)) {
2543 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2544 __func__);
2545 instr->state = MTD_ERASE_FAILED;
2546 goto erase_exit;
2547 }
2548
2549 /*
2550 * If BBT requires refresh, set the BBT page mask to see if the BBT
2551 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2552 * can not be matched. This is also done when the bbt is actually
2553 * erased to avoid recusrsive updates.
2554 */
2555 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2556 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2557
2558 /* Loop through the pages */
2559 len = instr->len;
2560
2561 instr->state = MTD_ERASING;
2562
2563 while (len) {
2564 /* Heck if we have a bad block, we do not erase bad blocks! */
2565 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2566 chip->page_shift, 0, allowbbt)) {
2567 printk(KERN_WARNING "%s: attempt to erase a bad block "
2568 "at page 0x%08x\n", __func__, page);
2569 instr->state = MTD_ERASE_FAILED;
2570 goto erase_exit;
2571 }
2572
2573 /*
2574 * Invalidate the page cache, if we erase the block which
2575 * contains the current cached page.
2576 */
2577 if (page <= chip->pagebuf && chip->pagebuf <
2578 (page + pages_per_block))
2579 chip->pagebuf = -1;
2580
2581 chip->erase_cmd(mtd, page & chip->pagemask);
2582
2583 status = chip->waitfunc(mtd, chip);
2584
2585 /*
2586 * See if operation failed and additional status checks are
2587 * available
2588 */
2589 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2590 status = chip->errstat(mtd, chip, FL_ERASING,
2591 status, page);
2592
2593 /* See if block erase succeeded */
2594 if (status & NAND_STATUS_FAIL) {
2595 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2596 "page 0x%08x\n", __func__, page);
2597 instr->state = MTD_ERASE_FAILED;
2598 instr->fail_addr =
2599 ((loff_t)page << chip->page_shift);
2600 goto erase_exit;
2601 }
2602
2603 /*
2604 * If BBT requires refresh, set the BBT rewrite flag to the
2605 * page being erased.
2606 */
2607 if (bbt_masked_page != 0xffffffff &&
2608 (page & BBT_PAGE_MASK) == bbt_masked_page)
2609 rewrite_bbt[chipnr] =
2610 ((loff_t)page << chip->page_shift);
2611
2612 /* Increment page address and decrement length */
2613 len -= (1 << chip->phys_erase_shift);
2614 page += pages_per_block;
2615
2616 /* Check, if we cross a chip boundary */
2617 if (len && !(page & chip->pagemask)) {
2618 chipnr++;
2619 chip->select_chip(mtd, -1);
2620 chip->select_chip(mtd, chipnr);
2621
2622 /*
2623 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2624 * page mask to see if this BBT should be rewritten.
2625 */
2626 if (bbt_masked_page != 0xffffffff &&
2627 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2628 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2629 BBT_PAGE_MASK;
2630 }
2631 }
2632 instr->state = MTD_ERASE_DONE;
2633
2634 erase_exit:
2635
2636 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2637
2638 /* Deselect and wake up anyone waiting on the device */
2639 nand_release_device(mtd);
2640
2641 /* Do call back function */
2642 if (!ret)
2643 mtd_erase_callback(instr);
2644
2645 /*
2646 * If BBT requires refresh and erase was successful, rewrite any
2647 * selected bad block tables.
2648 */
2649 if (bbt_masked_page == 0xffffffff || ret)
2650 return ret;
2651
2652 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2653 if (!rewrite_bbt[chipnr])
2654 continue;
2655 /* Update the BBT for chip */
2656 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2657 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2658 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2659 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2660 }
2661
2662 /* Return more or less happy */
2663 return ret;
2664 }
2665
2666 /**
2667 * nand_sync - [MTD Interface] sync
2668 * @mtd: MTD device structure
2669 *
2670 * Sync is actually a wait for chip ready function.
2671 */
2672 static void nand_sync(struct mtd_info *mtd)
2673 {
2674 struct nand_chip *chip = mtd->priv;
2675
2676 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2677
2678 /* Grab the lock and see if the device is available */
2679 nand_get_device(chip, mtd, FL_SYNCING);
2680 /* Release it and go back */
2681 nand_release_device(mtd);
2682 }
2683
2684 /**
2685 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2686 * @mtd: MTD device structure
2687 * @offs: offset relative to mtd start
2688 */
2689 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2690 {
2691 /* Check for invalid offset */
2692 if (offs > mtd->size)
2693 return -EINVAL;
2694
2695 return nand_block_checkbad(mtd, offs, 1, 0);
2696 }
2697
2698 /**
2699 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2700 * @mtd: MTD device structure
2701 * @ofs: offset relative to mtd start
2702 */
2703 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2704 {
2705 struct nand_chip *chip = mtd->priv;
2706 int ret;
2707
2708 ret = nand_block_isbad(mtd, ofs);
2709 if (ret) {
2710 /* If it was bad already, return success and do nothing */
2711 if (ret > 0)
2712 return 0;
2713 return ret;
2714 }
2715
2716 return chip->block_markbad(mtd, ofs);
2717 }
2718
2719 /**
2720 * nand_suspend - [MTD Interface] Suspend the NAND flash
2721 * @mtd: MTD device structure
2722 */
2723 static int nand_suspend(struct mtd_info *mtd)
2724 {
2725 struct nand_chip *chip = mtd->priv;
2726
2727 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2728 }
2729
2730 /**
2731 * nand_resume - [MTD Interface] Resume the NAND flash
2732 * @mtd: MTD device structure
2733 */
2734 static void nand_resume(struct mtd_info *mtd)
2735 {
2736 struct nand_chip *chip = mtd->priv;
2737
2738 if (chip->state == FL_PM_SUSPENDED)
2739 nand_release_device(mtd);
2740 else
2741 printk(KERN_ERR "%s called for a chip which is not "
2742 "in suspended state\n", __func__);
2743 }
2744
2745 /* Set default functions */
2746 static void nand_set_defaults(struct nand_chip *chip, int busw)
2747 {
2748 /* check for proper chip_delay setup, set 20us if not */
2749 if (!chip->chip_delay)
2750 chip->chip_delay = 20;
2751
2752 /* check, if a user supplied command function given */
2753 if (chip->cmdfunc == NULL)
2754 chip->cmdfunc = nand_command;
2755
2756 /* check, if a user supplied wait function given */
2757 if (chip->waitfunc == NULL)
2758 chip->waitfunc = nand_wait;
2759
2760 if (!chip->select_chip)
2761 chip->select_chip = nand_select_chip;
2762 if (!chip->read_byte)
2763 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2764 if (!chip->read_word)
2765 chip->read_word = nand_read_word;
2766 if (!chip->block_bad)
2767 chip->block_bad = nand_block_bad;
2768 if (!chip->block_markbad)
2769 chip->block_markbad = nand_default_block_markbad;
2770 if (!chip->write_buf)
2771 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2772 if (!chip->read_buf)
2773 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2774 if (!chip->verify_buf)
2775 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2776 if (!chip->scan_bbt)
2777 chip->scan_bbt = nand_default_bbt;
2778
2779 if (!chip->controller) {
2780 chip->controller = &chip->hwcontrol;
2781 spin_lock_init(&chip->controller->lock);
2782 init_waitqueue_head(&chip->controller->wq);
2783 }
2784
2785 }
2786
2787 /* Sanitize ONFI strings so we can safely print them */
2788 static void sanitize_string(uint8_t *s, size_t len)
2789 {
2790 ssize_t i;
2791
2792 /* Null terminate */
2793 s[len - 1] = 0;
2794
2795 /* Remove non printable chars */
2796 for (i = 0; i < len - 1; i++) {
2797 if (s[i] < ' ' || s[i] > 127)
2798 s[i] = '?';
2799 }
2800
2801 /* Remove trailing spaces */
2802 strim(s);
2803 }
2804
2805 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2806 {
2807 int i;
2808 while (len--) {
2809 crc ^= *p++ << 8;
2810 for (i = 0; i < 8; i++)
2811 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2812 }
2813
2814 return crc;
2815 }
2816
2817 /*
2818 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2819 */
2820 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2821 int busw)
2822 {
2823 struct nand_onfi_params *p = &chip->onfi_params;
2824 int i;
2825 int val;
2826
2827 /* Try ONFI for unknow chip or LP */
2828 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2829 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2830 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2831 return 0;
2832
2833 printk(KERN_INFO "ONFI flash detected\n");
2834 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2835 for (i = 0; i < 3; i++) {
2836 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2837 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2838 le16_to_cpu(p->crc)) {
2839 printk(KERN_INFO "ONFI param page %d valid\n", i);
2840 break;
2841 }
2842 }
2843
2844 if (i == 3)
2845 return 0;
2846
2847 /* Check version */
2848 val = le16_to_cpu(p->revision);
2849 if (val & (1 << 5))
2850 chip->onfi_version = 23;
2851 else if (val & (1 << 4))
2852 chip->onfi_version = 22;
2853 else if (val & (1 << 3))
2854 chip->onfi_version = 21;
2855 else if (val & (1 << 2))
2856 chip->onfi_version = 20;
2857 else if (val & (1 << 1))
2858 chip->onfi_version = 10;
2859 else
2860 chip->onfi_version = 0;
2861
2862 if (!chip->onfi_version) {
2863 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2864 __func__, val);
2865 return 0;
2866 }
2867
2868 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2869 sanitize_string(p->model, sizeof(p->model));
2870 if (!mtd->name)
2871 mtd->name = p->model;
2872 mtd->writesize = le32_to_cpu(p->byte_per_page);
2873 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2874 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2875 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2876 busw = 0;
2877 if (le16_to_cpu(p->features) & 1)
2878 busw = NAND_BUSWIDTH_16;
2879
2880 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2881 chip->options |= (NAND_NO_READRDY |
2882 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2883
2884 return 1;
2885 }
2886
2887 /*
2888 * Get the flash and manufacturer id and lookup if the type is supported.
2889 */
2890 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2891 struct nand_chip *chip,
2892 int busw,
2893 int *maf_id, int *dev_id,
2894 struct nand_flash_dev *type)
2895 {
2896 int i, maf_idx;
2897 u8 id_data[8];
2898 int ret;
2899
2900 /* Select the device */
2901 chip->select_chip(mtd, 0);
2902
2903 /*
2904 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2905 * after power-up.
2906 */
2907 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2908
2909 /* Send the command for reading device ID */
2910 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2911
2912 /* Read manufacturer and device IDs */
2913 *maf_id = chip->read_byte(mtd);
2914 *dev_id = chip->read_byte(mtd);
2915
2916 /*
2917 * Try again to make sure, as some systems the bus-hold or other
2918 * interface concerns can cause random data which looks like a
2919 * possibly credible NAND flash to appear. If the two results do
2920 * not match, ignore the device completely.
2921 */
2922
2923 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2924
2925 for (i = 0; i < 2; i++)
2926 id_data[i] = chip->read_byte(mtd);
2927
2928 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2929 printk(KERN_INFO "%s: second ID read did not match "
2930 "%02x,%02x against %02x,%02x\n", __func__,
2931 *maf_id, *dev_id, id_data[0], id_data[1]);
2932 return ERR_PTR(-ENODEV);
2933 }
2934
2935 if (!type)
2936 type = nand_flash_ids;
2937
2938 for (; type->name != NULL; type++)
2939 if (*dev_id == type->id)
2940 break;
2941
2942 chip->onfi_version = 0;
2943 if (!type->name || !type->pagesize) {
2944 /* Check is chip is ONFI compliant */
2945 ret = nand_flash_detect_onfi(mtd, chip, busw);
2946 if (ret)
2947 goto ident_done;
2948 }
2949
2950 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2951
2952 /* Read entire ID string */
2953
2954 for (i = 0; i < 8; i++)
2955 id_data[i] = chip->read_byte(mtd);
2956
2957 if (!type->name)
2958 return ERR_PTR(-ENODEV);
2959
2960 if (!mtd->name)
2961 mtd->name = type->name;
2962
2963 chip->chipsize = (uint64_t)type->chipsize << 20;
2964
2965 if (!type->pagesize && chip->init_size) {
2966 /* Set the pagesize, oobsize, erasesize by the driver */
2967 busw = chip->init_size(mtd, chip, id_data);
2968 } else if (!type->pagesize) {
2969 int extid;
2970 /* The 3rd id byte holds MLC / multichip data */
2971 chip->cellinfo = id_data[2];
2972 /* The 4th id byte is the important one */
2973 extid = id_data[3];
2974
2975 /*
2976 * Field definitions are in the following datasheets:
2977 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2978 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2979 *
2980 * Check for wraparound + Samsung ID + nonzero 6th byte
2981 * to decide what to do.
2982 */
2983 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2984 id_data[0] == NAND_MFR_SAMSUNG &&
2985 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2986 id_data[5] != 0x00) {
2987 /* Calc pagesize */
2988 mtd->writesize = 2048 << (extid & 0x03);
2989 extid >>= 2;
2990 /* Calc oobsize */
2991 switch (extid & 0x03) {
2992 case 1:
2993 mtd->oobsize = 128;
2994 break;
2995 case 2:
2996 mtd->oobsize = 218;
2997 break;
2998 case 3:
2999 mtd->oobsize = 400;
3000 break;
3001 default:
3002 mtd->oobsize = 436;
3003 break;
3004 }
3005 extid >>= 2;
3006 /* Calc blocksize */
3007 mtd->erasesize = (128 * 1024) <<
3008 (((extid >> 1) & 0x04) | (extid & 0x03));
3009 busw = 0;
3010 } else {
3011 /* Calc pagesize */
3012 mtd->writesize = 1024 << (extid & 0x03);
3013 extid >>= 2;
3014 /* Calc oobsize */
3015 mtd->oobsize = (8 << (extid & 0x01)) *
3016 (mtd->writesize >> 9);
3017 extid >>= 2;
3018 /* Calc blocksize. Blocksize is multiples of 64KiB */
3019 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3020 extid >>= 2;
3021 /* Get buswidth information */
3022 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3023 }
3024 } else {
3025 /*
3026 * Old devices have chip data hardcoded in the device id table.
3027 */
3028 mtd->erasesize = type->erasesize;
3029 mtd->writesize = type->pagesize;
3030 mtd->oobsize = mtd->writesize / 32;
3031 busw = type->options & NAND_BUSWIDTH_16;
3032
3033 /*
3034 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3035 * some Spansion chips have erasesize that conflicts with size
3036 * listed in nand_ids table.
3037 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3038 */
3039 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3040 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3041 id_data[7] == 0x00 && mtd->writesize == 512) {
3042 mtd->erasesize = 128 * 1024;
3043 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3044 }
3045 }
3046 /* Get chip options, preserve non chip based options */
3047 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3048 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3049
3050 /*
3051 * Check if chip is not a Samsung device. Do not clear the
3052 * options for chips which do not have an extended id.
3053 */
3054 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3055 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3056 ident_done:
3057
3058 /*
3059 * Set chip as a default. Board drivers can override it, if necessary.
3060 */
3061 chip->options |= NAND_NO_AUTOINCR;
3062
3063 /* Try to identify manufacturer */
3064 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3065 if (nand_manuf_ids[maf_idx].id == *maf_id)
3066 break;
3067 }
3068
3069 /*
3070 * Check, if buswidth is correct. Hardware drivers should set
3071 * chip correct!
3072 */
3073 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3074 printk(KERN_INFO "NAND device: Manufacturer ID:"
3075 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3076 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3077 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3078 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3079 busw ? 16 : 8);
3080 return ERR_PTR(-EINVAL);
3081 }
3082
3083 /* Calculate the address shift from the page size */
3084 chip->page_shift = ffs(mtd->writesize) - 1;
3085 /* Convert chipsize to number of pages per chip -1 */
3086 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3087
3088 chip->bbt_erase_shift = chip->phys_erase_shift =
3089 ffs(mtd->erasesize) - 1;
3090 if (chip->chipsize & 0xffffffff)
3091 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3092 else {
3093 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3094 chip->chip_shift += 32 - 1;
3095 }
3096
3097 chip->badblockbits = 8;
3098
3099 /* Set the bad block position */
3100 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3101 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3102 else
3103 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3104
3105 /*
3106 * Bad block marker is stored in the last page of each block
3107 * on Samsung and Hynix MLC devices; stored in first two pages
3108 * of each block on Micron devices with 2KiB pages and on
3109 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3110 * only the first page.
3111 */
3112 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3113 (*maf_id == NAND_MFR_SAMSUNG ||
3114 *maf_id == NAND_MFR_HYNIX))
3115 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3116 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3117 (*maf_id == NAND_MFR_SAMSUNG ||
3118 *maf_id == NAND_MFR_HYNIX ||
3119 *maf_id == NAND_MFR_TOSHIBA ||
3120 *maf_id == NAND_MFR_AMD)) ||
3121 (mtd->writesize == 2048 &&
3122 *maf_id == NAND_MFR_MICRON))
3123 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3124
3125 /* Check for AND chips with 4 page planes */
3126 if (chip->options & NAND_4PAGE_ARRAY)
3127 chip->erase_cmd = multi_erase_cmd;
3128 else
3129 chip->erase_cmd = single_erase_cmd;
3130
3131 /* Do not replace user supplied command function! */
3132 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3133 chip->cmdfunc = nand_command_lp;
3134
3135 printk(KERN_INFO "NAND device: Manufacturer ID:"
3136 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3137 nand_manuf_ids[maf_idx].name,
3138 chip->onfi_version ? chip->onfi_params.model : type->name);
3139
3140 return type;
3141 }
3142
3143 /**
3144 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3145 * @mtd: MTD device structure
3146 * @maxchips: number of chips to scan for
3147 * @table: alternative NAND ID table
3148 *
3149 * This is the first phase of the normal nand_scan() function. It reads the
3150 * flash ID and sets up MTD fields accordingly.
3151 *
3152 * The mtd->owner field must be set to the module of the caller.
3153 */
3154 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3155 struct nand_flash_dev *table)
3156 {
3157 int i, busw, nand_maf_id, nand_dev_id;
3158 struct nand_chip *chip = mtd->priv;
3159 struct nand_flash_dev *type;
3160
3161 /* Get buswidth to select the correct functions */
3162 busw = chip->options & NAND_BUSWIDTH_16;
3163 /* Set the default functions */
3164 nand_set_defaults(chip, busw);
3165
3166 /* Read the flash type */
3167 type = nand_get_flash_type(mtd, chip, busw,
3168 &nand_maf_id, &nand_dev_id, table);
3169
3170 if (IS_ERR(type)) {
3171 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3172 printk(KERN_WARNING "No NAND device found.\n");
3173 chip->select_chip(mtd, -1);
3174 return PTR_ERR(type);
3175 }
3176
3177 /* Check for a chip array */
3178 for (i = 1; i < maxchips; i++) {
3179 chip->select_chip(mtd, i);
3180 /* See comment in nand_get_flash_type for reset */
3181 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3182 /* Send the command for reading device ID */
3183 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3184 /* Read manufacturer and device IDs */
3185 if (nand_maf_id != chip->read_byte(mtd) ||
3186 nand_dev_id != chip->read_byte(mtd))
3187 break;
3188 }
3189 if (i > 1)
3190 printk(KERN_INFO "%d NAND chips detected\n", i);
3191
3192 /* Store the number of chips and calc total size for mtd */
3193 chip->numchips = i;
3194 mtd->size = i * chip->chipsize;
3195
3196 return 0;
3197 }
3198 EXPORT_SYMBOL(nand_scan_ident);
3199
3200
3201 /**
3202 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3203 * @mtd: MTD device structure
3204 *
3205 * This is the second phase of the normal nand_scan() function. It fills out
3206 * all the uninitialized function pointers with the defaults and scans for a
3207 * bad block table if appropriate.
3208 */
3209 int nand_scan_tail(struct mtd_info *mtd)
3210 {
3211 int i;
3212 struct nand_chip *chip = mtd->priv;
3213
3214 if (!(chip->options & NAND_OWN_BUFFERS))
3215 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3216 if (!chip->buffers)
3217 return -ENOMEM;
3218
3219 /* Set the internal oob buffer location, just after the page data */
3220 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3221
3222 /*
3223 * If no default placement scheme is given, select an appropriate one.
3224 */
3225 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3226 switch (mtd->oobsize) {
3227 case 8:
3228 chip->ecc.layout = &nand_oob_8;
3229 break;
3230 case 16:
3231 chip->ecc.layout = &nand_oob_16;
3232 break;
3233 case 64:
3234 chip->ecc.layout = &nand_oob_64;
3235 break;
3236 case 128:
3237 chip->ecc.layout = &nand_oob_128;
3238 break;
3239 default:
3240 printk(KERN_WARNING "No oob scheme defined for "
3241 "oobsize %d\n", mtd->oobsize);
3242 BUG();
3243 }
3244 }
3245
3246 if (!chip->write_page)
3247 chip->write_page = nand_write_page;
3248
3249 /*
3250 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3251 * selected and we have 256 byte pagesize fallback to software ECC
3252 */
3253
3254 switch (chip->ecc.mode) {
3255 case NAND_ECC_HW_OOB_FIRST:
3256 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3257 if (!chip->ecc.calculate || !chip->ecc.correct ||
3258 !chip->ecc.hwctl) {
3259 printk(KERN_WARNING "No ECC functions supplied; "
3260 "Hardware ECC not possible\n");
3261 BUG();
3262 }
3263 if (!chip->ecc.read_page)
3264 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3265
3266 case NAND_ECC_HW:
3267 /* Use standard hwecc read page function? */
3268 if (!chip->ecc.read_page)
3269 chip->ecc.read_page = nand_read_page_hwecc;
3270 if (!chip->ecc.write_page)
3271 chip->ecc.write_page = nand_write_page_hwecc;
3272 if (!chip->ecc.read_page_raw)
3273 chip->ecc.read_page_raw = nand_read_page_raw;
3274 if (!chip->ecc.write_page_raw)
3275 chip->ecc.write_page_raw = nand_write_page_raw;
3276 if (!chip->ecc.read_oob)
3277 chip->ecc.read_oob = nand_read_oob_std;
3278 if (!chip->ecc.write_oob)
3279 chip->ecc.write_oob = nand_write_oob_std;
3280
3281 case NAND_ECC_HW_SYNDROME:
3282 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3283 !chip->ecc.hwctl) &&
3284 (!chip->ecc.read_page ||
3285 chip->ecc.read_page == nand_read_page_hwecc ||
3286 !chip->ecc.write_page ||
3287 chip->ecc.write_page == nand_write_page_hwecc)) {
3288 printk(KERN_WARNING "No ECC functions supplied; "
3289 "Hardware ECC not possible\n");
3290 BUG();
3291 }
3292 /* Use standard syndrome read/write page function? */
3293 if (!chip->ecc.read_page)
3294 chip->ecc.read_page = nand_read_page_syndrome;
3295 if (!chip->ecc.write_page)
3296 chip->ecc.write_page = nand_write_page_syndrome;
3297 if (!chip->ecc.read_page_raw)
3298 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3299 if (!chip->ecc.write_page_raw)
3300 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3301 if (!chip->ecc.read_oob)
3302 chip->ecc.read_oob = nand_read_oob_syndrome;
3303 if (!chip->ecc.write_oob)
3304 chip->ecc.write_oob = nand_write_oob_syndrome;
3305
3306 if (mtd->writesize >= chip->ecc.size)
3307 break;
3308 printk(KERN_WARNING "%d byte HW ECC not possible on "
3309 "%d byte page size, fallback to SW ECC\n",
3310 chip->ecc.size, mtd->writesize);
3311 chip->ecc.mode = NAND_ECC_SOFT;
3312
3313 case NAND_ECC_SOFT:
3314 chip->ecc.calculate = nand_calculate_ecc;
3315 chip->ecc.correct = nand_correct_data;
3316 chip->ecc.read_page = nand_read_page_swecc;
3317 chip->ecc.read_subpage = nand_read_subpage;
3318 chip->ecc.write_page = nand_write_page_swecc;
3319 chip->ecc.read_page_raw = nand_read_page_raw;
3320 chip->ecc.write_page_raw = nand_write_page_raw;
3321 chip->ecc.read_oob = nand_read_oob_std;
3322 chip->ecc.write_oob = nand_write_oob_std;
3323 if (!chip->ecc.size)
3324 chip->ecc.size = 256;
3325 chip->ecc.bytes = 3;
3326 break;
3327
3328 case NAND_ECC_SOFT_BCH:
3329 if (!mtd_nand_has_bch()) {
3330 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3331 BUG();
3332 }
3333 chip->ecc.calculate = nand_bch_calculate_ecc;
3334 chip->ecc.correct = nand_bch_correct_data;
3335 chip->ecc.read_page = nand_read_page_swecc;
3336 chip->ecc.read_subpage = nand_read_subpage;
3337 chip->ecc.write_page = nand_write_page_swecc;
3338 chip->ecc.read_page_raw = nand_read_page_raw;
3339 chip->ecc.write_page_raw = nand_write_page_raw;
3340 chip->ecc.read_oob = nand_read_oob_std;
3341 chip->ecc.write_oob = nand_write_oob_std;
3342 /*
3343 * Board driver should supply ecc.size and ecc.bytes values to
3344 * select how many bits are correctable; see nand_bch_init()
3345 * for details. Otherwise, default to 4 bits for large page
3346 * devices.
3347 */
3348 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3349 chip->ecc.size = 512;
3350 chip->ecc.bytes = 7;
3351 }
3352 chip->ecc.priv = nand_bch_init(mtd,
3353 chip->ecc.size,
3354 chip->ecc.bytes,
3355 &chip->ecc.layout);
3356 if (!chip->ecc.priv) {
3357 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3358 BUG();
3359 }
3360 break;
3361
3362 case NAND_ECC_NONE:
3363 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3364 "This is not recommended !!\n");
3365 chip->ecc.read_page = nand_read_page_raw;
3366 chip->ecc.write_page = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.read_page_raw = nand_read_page_raw;
3369 chip->ecc.write_page_raw = nand_write_page_raw;
3370 chip->ecc.write_oob = nand_write_oob_std;
3371 chip->ecc.size = mtd->writesize;
3372 chip->ecc.bytes = 0;
3373 break;
3374
3375 default:
3376 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3377 chip->ecc.mode);
3378 BUG();
3379 }
3380
3381 /*
3382 * The number of bytes available for a client to place data into
3383 * the out of band area.
3384 */
3385 chip->ecc.layout->oobavail = 0;
3386 for (i = 0; chip->ecc.layout->oobfree[i].length
3387 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3388 chip->ecc.layout->oobavail +=
3389 chip->ecc.layout->oobfree[i].length;
3390 mtd->oobavail = chip->ecc.layout->oobavail;
3391
3392 /*
3393 * Set the number of read / write steps for one page depending on ECC
3394 * mode.
3395 */
3396 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3397 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3398 printk(KERN_WARNING "Invalid ecc parameters\n");
3399 BUG();
3400 }
3401 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3402
3403 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3404 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3405 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3406 switch (chip->ecc.steps) {
3407 case 2:
3408 mtd->subpage_sft = 1;
3409 break;
3410 case 4:
3411 case 8:
3412 case 16:
3413 mtd->subpage_sft = 2;
3414 break;
3415 }
3416 }
3417 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3418
3419 /* Initialize state */
3420 chip->state = FL_READY;
3421
3422 /* De-select the device */
3423 chip->select_chip(mtd, -1);
3424
3425 /* Invalidate the pagebuffer reference */
3426 chip->pagebuf = -1;
3427
3428 /* Fill in remaining MTD driver data */
3429 mtd->type = MTD_NANDFLASH;
3430 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3431 MTD_CAP_NANDFLASH;
3432 mtd->erase = nand_erase;
3433 mtd->point = NULL;
3434 mtd->unpoint = NULL;
3435 mtd->read = nand_read;
3436 mtd->write = nand_write;
3437 mtd->panic_write = panic_nand_write;
3438 mtd->read_oob = nand_read_oob;
3439 mtd->write_oob = nand_write_oob;
3440 mtd->sync = nand_sync;
3441 mtd->lock = NULL;
3442 mtd->unlock = NULL;
3443 mtd->suspend = nand_suspend;
3444 mtd->resume = nand_resume;
3445 mtd->block_isbad = nand_block_isbad;
3446 mtd->block_markbad = nand_block_markbad;
3447 mtd->writebufsize = mtd->writesize;
3448
3449 /* propagate ecc.layout to mtd_info */
3450 mtd->ecclayout = chip->ecc.layout;
3451
3452 /* Check, if we should skip the bad block table scan */
3453 if (chip->options & NAND_SKIP_BBTSCAN)
3454 return 0;
3455
3456 /* Build bad block table */
3457 return chip->scan_bbt(mtd);
3458 }
3459 EXPORT_SYMBOL(nand_scan_tail);
3460
3461 /*
3462 * is_module_text_address() isn't exported, and it's mostly a pointless
3463 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3464 * to call us from in-kernel code if the core NAND support is modular.
3465 */
3466 #ifdef MODULE
3467 #define caller_is_module() (1)
3468 #else
3469 #define caller_is_module() \
3470 is_module_text_address((unsigned long)__builtin_return_address(0))
3471 #endif
3472
3473 /**
3474 * nand_scan - [NAND Interface] Scan for the NAND device
3475 * @mtd: MTD device structure
3476 * @maxchips: number of chips to scan for
3477 *
3478 * This fills out all the uninitialized function pointers with the defaults.
3479 * The flash ID is read and the mtd/chip structures are filled with the
3480 * appropriate values. The mtd->owner field must be set to the module of the
3481 * caller.
3482 */
3483 int nand_scan(struct mtd_info *mtd, int maxchips)
3484 {
3485 int ret;
3486
3487 /* Many callers got this wrong, so check for it for a while... */
3488 if (!mtd->owner && caller_is_module()) {
3489 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3490 __func__);
3491 BUG();
3492 }
3493
3494 ret = nand_scan_ident(mtd, maxchips, NULL);
3495 if (!ret)
3496 ret = nand_scan_tail(mtd);
3497 return ret;
3498 }
3499 EXPORT_SYMBOL(nand_scan);
3500
3501 /**
3502 * nand_release - [NAND Interface] Free resources held by the NAND device
3503 * @mtd: MTD device structure
3504 */
3505 void nand_release(struct mtd_info *mtd)
3506 {
3507 struct nand_chip *chip = mtd->priv;
3508
3509 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3510 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3511
3512 mtd_device_unregister(mtd);
3513
3514 /* Free bad block table memory */
3515 kfree(chip->bbt);
3516 if (!(chip->options & NAND_OWN_BUFFERS))
3517 kfree(chip->buffers);
3518
3519 /* Free bad block descriptor memory */
3520 if (chip->badblock_pattern && chip->badblock_pattern->options
3521 & NAND_BBT_DYNAMICSTRUCT)
3522 kfree(chip->badblock_pattern);
3523 }
3524 EXPORT_SYMBOL_GPL(nand_release);
3525
3526 static int __init nand_base_init(void)
3527 {
3528 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3529 return 0;
3530 }
3531
3532 static void __exit nand_base_exit(void)
3533 {
3534 led_trigger_unregister_simple(nand_led_trigger);
3535 }
3536
3537 module_init(nand_base_init);
3538 module_exit(nand_base_exit);
3539
3540 MODULE_LICENSE("GPL");
3541 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3542 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3543 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree