include/asm-powerpc/pgtable-ppc32.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
   2 #define _ASM_POWERPC_PGTABLE_PPC32_H
   3
   4 #include <asm-generic/pgtable-nopmd.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/processor.h>              /* For TASK_SIZE */
  10 #include <asm/mmu.h>
  11 #include <asm/page.h>
  12 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  13 struct mm_struct;
  14
  15 extern unsigned long va_to_phys(unsigned long address);
  16 extern pte_t *va_to_pte(unsigned long address);
  17 extern unsigned long ioremap_bot, ioremap_base;
  18 #endif /* __ASSEMBLY__ */
  19
  20 /*
  21  * The PowerPC MMU uses a hash table containing PTEs, together with
  22  * a set of 16 segment registers (on 32-bit implementations), to define
  23  * the virtual to physical address mapping.
  24  *
  25  * We use the hash table as an extended TLB, i.e. a cache of currently
  26  * active mappings.  We maintain a two-level page table tree, much
  27  * like that used by the i386, for the sake of the Linux memory
  28  * management code.  Low-level assembler code in hashtable.S
  29  * (procedure hash_page) is responsible for extracting ptes from the
  30  * tree and putting them into the hash table when necessary, and
  31  * updating the accessed and modified bits in the page table tree.
  32  */
  33
  34 /*
  35  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  36  * We also use the two level tables, but we can put the real bits in them
  37  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  38  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  39  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  40  * based upon user/super access.  The TLB does not have accessed nor write
  41  * protect.  We assume that if the TLB get loaded with an entry it is
  42  * accessed, and overload the changed bit for write protect.  We use
  43  * two bits in the software pte that are supposed to be set to zero in
  44  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  45  * descriptor contains the guarded and writethrough/copyback bits, we can
  46  * set these at the page level since they get copied from the Mx_TWC
  47  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  48  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  49  * These will get masked from the level 2 descriptor at TLB load time, and
  50  * copied to the MD_TWC before it gets loaded.
  51  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  52  * This also allows a TLB hander optimization because we can directly
  53  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  54  * mapping of well known areas.  The PMD (PGD) entries contain control
  55  * flags in addition to the address, so care must be taken that the
  56  * software no longer assumes these are only pointers.
  57  */
  58
  59 /*
  60  * At present, all PowerPC 400-class processors share a similar TLB
  61  * architecture. The instruction and data sides share a unified,
  62  * 64-entry, fully-associative TLB which is maintained totally under
  63  * software control. In addition, the instruction side has a
  64  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  65  * first level to the shared TLB. These two TLBs are known as the UTLB
  66  * and ITLB, respectively (see "mmu.h" for definitions).
  67  */
  68
  69 /*
  70  * The normal case is that PTEs are 32-bits and we have a 1-page
  71  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  72  *
  73  * For any >32-bit physical address platform, we can use the following
  74  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  75  * are an index to the second level table.  The combined pgdir/pmd first
  76  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  77  * -Matt
  78  */
  79 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  80 #define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
  81 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  82 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  83
  84 /*
  85  * entries per page directory level: our page-table tree is two-level, so
  86  * we don't really have any PMD directory.
  87  */
  88 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  89 #define PTRS_PER_PMD    1
  90 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  91
  92 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  93 #define FIRST_USER_ADDRESS      0
  94
  95 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
  96 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
  97
  98 #define pte_ERROR(e) \
  99         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
 100                 (unsigned long long)pte_val(e))
 101 #define pgd_ERROR(e) \
 102         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 103
 104 /*
 105  * Just any arbitrary offset to the start of the vmalloc VM area: the
 106  * current 64MB value just means that there will be a 64MB "hole" after the
 107  * physical memory until the kernel virtual memory starts.  That means that
 108  * any out-of-bounds memory accesses will hopefully be caught.
 109  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 110  * area for the same reason. ;)
 111  *
 112  * We no longer map larger than phys RAM with the BATs so we don't have
 113  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 114  * about clashes between our early calls to ioremap() that start growing down
 115  * from ioremap_base being run into the VM area allocations (growing upwards
 116  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 117  * we actually run into our mappings setup in the early boot with the VM
 118  * system.  This really does become a problem for machines with good amounts
 119  * of RAM.  -- Cort
 120  */
 121 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 122 #ifdef PPC_PIN_SIZE
 123 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 124 #else
 125 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 126 #endif
 127 #define VMALLOC_END     ioremap_bot
 128
 129 /*
 130  * Bits in a linux-style PTE.  These match the bits in the
 131  * (hardware-defined) PowerPC PTE as closely as possible.
 132  */
 133
 134 #if defined(CONFIG_40x)
 135
 136 /* There are several potential gotchas here.  The 40x hardware TLBLO
 137    field looks like this:
 138
 139    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 140    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 141
 142    Where possible we make the Linux PTE bits match up with this
 143
 144    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 145      support down to 1k pages), this is done in the TLBMiss exception
 146      handler.
 147    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 148      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 149      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 150      zone.
 151    - PRESENT *must* be in the bottom two bits because swap cache
 152      entries use the top 30 bits.  Because 40x doesn't support SMP
 153      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 154      is cleared in the TLB miss handler before the TLB entry is loaded.
 155    - All other bits of the PTE are loaded into TLBLO without
 156      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 157      software PTE bits.  We actually use use bits 21, 24, 25, and
 158      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 159      PRESENT.
 160 */
 161
 162 /* Definitions for 40x embedded chips. */
 163 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 164 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 165 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 166 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 167 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 168 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 169 #define _PAGE_RW        0x040   /* software: Writes permitted */
 170 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 171 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 172 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 173 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 174
 175 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 176 #define _PMD_BAD        0x802
 177 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 178 #define _PMD_SIZE_4M    0x0c0
 179 #define _PMD_SIZE_16M   0x0e0
 180 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 181
 182 #elif defined(CONFIG_44x)
 183 /*
 184  * Definitions for PPC440
 185  *
 186  * Because of the 3 word TLB entries to support 36-bit addressing,
 187  * the attribute are difficult to map in such a fashion that they
 188  * are easily loaded during exception processing.  I decided to
 189  * organize the entry so the ERPN is the only portion in the
 190  * upper word of the PTE and the attribute bits below are packed
 191  * in as sensibly as they can be in the area below a 4KB page size
 192  * oriented RPN.  This at least makes it easy to load the RPN and
 193  * ERPN fields in the TLB. -Matt
 194  *
 195  * Note that these bits preclude future use of a page size
 196  * less than 4KB.
 197  *
 198  *
 199  * PPC 440 core has following TLB attribute fields;
 200  *
 201  *   TLB1:
 202  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 203  *   RPN.................................  -  -  -  -  -  - ERPN.......
 204  *
 205  *   TLB2:
 206  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 207  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 208  *
 209  * There are some constrains and options, to decide mapping software bits
 210  * into TLB entry.
 211  *
 212  *   - PRESENT *must* be in the bottom three bits because swap cache
 213  *     entries use the top 29 bits for TLB2.
 214  *
 215  *   - FILE *must* be in the bottom three bits because swap cache
 216  *     entries use the top 29 bits for TLB2.
 217  *
 218  *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
 219  *     doesn't support SMP. So we can use this as software bit, like
 220  *     DIRTY.
 221  *
 222  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
 223  * for memory protection related functions (see PTE structure in
 224  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
 225  * above bits.  Note that the bit values are CPU specific, not architecture
 226  * specific.
 227  *
 228  * The kernel PTE entry holds an arch-dependent swp_entry structure under
 229  * certain situations. In other words, in such situations some portion of
 230  * the PTE bits are used as a swp_entry. In the PPC implementation, the
 231  * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
 232  * hold protection values. That means the three protection bits are
 233  * reserved for both PTE and SWAP entry at the most significant three
 234  * LSBs.
 235  *
 236  * There are three protection bits available for SWAP entry:
 237  *      _PAGE_PRESENT
 238  *      _PAGE_FILE
 239  *      _PAGE_HASHPTE (if HW has)
 240  *
 241  * So those three bits have to be inside of 0-2nd LSB of PTE.
 242  *
 243  */
 244
 245 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 246 #define _PAGE_RW        0x00000002              /* S: Write permission */
 247 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 248 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 249 #define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
 250 #define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
 251 #define _PAGE_USER      0x00000040              /* S: User page */
 252 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 253 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 254 #define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
 255 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 256 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 257
 258 /* TODO: Add large page lowmem mapping support */
 259 #define _PMD_PRESENT    0
 260 #define _PMD_PRESENT_MASK (PAGE_MASK)
 261 #define _PMD_BAD        (~PAGE_MASK)
 262
 263 /* ERPN in a PTE never gets cleared, ignore it */
 264 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 265
 266 #elif defined(CONFIG_FSL_BOOKE)
 267 /*
 268    MMU Assist Register 3:
 269
 270    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
 271    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
 272
 273    - PRESENT *must* be in the bottom three bits because swap cache
 274      entries use the top 29 bits.
 275
 276    - FILE *must* be in the bottom three bits because swap cache
 277      entries use the top 29 bits.
 278 */
 279
 280 /* Definitions for FSL Book-E Cores */
 281 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
 282 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
 283 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
 284 #define _PAGE_ACCESSED  0x00004 /* S: Page referenced */
 285 #define _PAGE_HWWRITE   0x00008 /* H: Dirty & RW, set in exception */
 286 #define _PAGE_RW        0x00010 /* S: Write permission */
 287 #define _PAGE_HWEXEC    0x00020 /* H: UX permission */
 288
 289 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
 290 #define _PAGE_GUARDED   0x00080 /* H: G bit */
 291 #define _PAGE_COHERENT  0x00100 /* H: M bit */
 292 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
 293 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 294
 295 #ifdef CONFIG_PTE_64BIT
 296 #define _PAGE_DIRTY     0x08000 /* S: Page dirty */
 297
 298 /* ERPN in a PTE never gets cleared, ignore it */
 299 #define _PTE_NONE_MASK  0xffffffffffff0000ULL
 300 #else
 301 #define _PAGE_DIRTY     0x00800 /* S: Page dirty */
 302 #endif
 303
 304 #define _PMD_PRESENT    0
 305 #define _PMD_PRESENT_MASK (PAGE_MASK)
 306 #define _PMD_BAD        (~PAGE_MASK)
 307
 308 #elif defined(CONFIG_8xx)
 309 /* Definitions for 8xx embedded chips. */
 310 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 311 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 312 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 313 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 314
 315 /* These five software bits must be masked out when the entry is loaded
 316  * into the TLB.
 317  */
 318 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 319 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 320 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 321 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 322 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 323
 324 /* Setting any bits in the nibble with the follow two controls will
 325  * require a TLB exception handler change.  It is assumed unused bits
 326  * are always zero.
 327  */
 328 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 329 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 330
 331 #define _PMD_PRESENT    0x0001
 332 #define _PMD_BAD        0x0ff0
 333 #define _PMD_PAGE_MASK  0x000c
 334 #define _PMD_PAGE_8M    0x000c
 335
 336 /*
 337  * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
 338  * for an address even if _PAGE_PRESENT is not set, as a performance
 339  * optimization.  This is a bug if you ever want to use swap unless
 340  * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
 341  * definitions for __swp_entry etc. below, which would be gross.
 342  *  -- paulus
 343  */
 344 #define _PTE_NONE_MASK _PAGE_ACCESSED
 345
 346 #else /* CONFIG_6xx */
 347 /* Definitions for 60x, 740/750, etc. */
 348 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 349 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 350 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 351 #define _PAGE_USER      0x004   /* usermode access allowed */
 352 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 353 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 354 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 355 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 356 #define _PAGE_DIRTY     0x080   /* C: page changed */
 357 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 358 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 359 #define _PAGE_RW        0x400   /* software: user write access allowed */
 360
 361 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 362
 363 #define _PMD_PRESENT    0
 364 #define _PMD_PRESENT_MASK (PAGE_MASK)
 365 #define _PMD_BAD        (~PAGE_MASK)
 366 #endif
 367
 368 /*
 369  * Some bits are only used on some cpu families...
 370  */
 371 #ifndef _PAGE_HASHPTE
 372 #define _PAGE_HASHPTE   0
 373 #endif
 374 #ifndef _PTE_NONE_MASK
 375 #define _PTE_NONE_MASK 0
 376 #endif
 377 #ifndef _PAGE_SHARED
 378 #define _PAGE_SHARED    0
 379 #endif
 380 #ifndef _PAGE_HWWRITE
 381 #define _PAGE_HWWRITE   0
 382 #endif
 383 #ifndef _PAGE_HWEXEC
 384 #define _PAGE_HWEXEC    0
 385 #endif
 386 #ifndef _PAGE_EXEC
 387 #define _PAGE_EXEC      0
 388 #endif
 389 #ifndef _PMD_PRESENT_MASK
 390 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 391 #endif
 392 #ifndef _PMD_SIZE
 393 #define _PMD_SIZE       0
 394 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 395 #endif
 396
 397 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 398
 399 /*
 400  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
 401  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
 402  * to have it in the Linux PTE, and in fact the bit could be reused for
 403  * another purpose.  -- paulus.
 404  */
 405
 406 #ifdef CONFIG_44x
 407 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
 408 #else
 409 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 410 #endif
 411 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 412 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 413
 414 #ifdef CONFIG_PPC_STD_MMU
 415 /* On standard PPC MMU, no user access implies kernel read/write access,
 416  * so to write-protect kernel memory we must turn on user access */
 417 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 418 #else
 419 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 420 #endif
 421
 422 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 423 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 424
 425 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
 426 /* We want the debuggers to be able to set breakpoints anywhere, so
 427  * don't write protect the kernel text */
 428 #define _PAGE_RAM_TEXT  _PAGE_RAM
 429 #else
 430 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 431 #endif
 432
 433 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 434 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 435 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 436 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 437 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 438 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 439 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 440
 441 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 442 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 443
 444 /*
 445  * The PowerPC can only do execute protection on a segment (256MB) basis,
 446  * not on a page basis.  So we consider execute permission the same as read.
 447  * Also, write permissions imply read permissions.
 448  * This is the closest we can get..
 449  */
 450 #define __P000  PAGE_NONE
 451 #define __P001  PAGE_READONLY_X
 452 #define __P010  PAGE_COPY
 453 #define __P011  PAGE_COPY_X
 454 #define __P100  PAGE_READONLY
 455 #define __P101  PAGE_READONLY_X
 456 #define __P110  PAGE_COPY
 457 #define __P111  PAGE_COPY_X
 458
 459 #define __S000  PAGE_NONE
 460 #define __S001  PAGE_READONLY_X
 461 #define __S010  PAGE_SHARED
 462 #define __S011  PAGE_SHARED_X
 463 #define __S100  PAGE_READONLY
 464 #define __S101  PAGE_READONLY_X
 465 #define __S110  PAGE_SHARED
 466 #define __S111  PAGE_SHARED_X
 467
 468 #ifndef __ASSEMBLY__
 469 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 470  * kernel without large page PMD support */
 471 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 472
 473 /*
 474  * Conversions between PTE values and page frame numbers.
 475  */
 476
 477 /* in some case we want to additionaly adjust where the pfn is in the pte to
 478  * allow room for more flags */
 479 #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
 480 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
 481 #else
 482 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
 483 #endif
 484
 485 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
 486 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 487
 488 #define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
 489                                         pgprot_val(prot))
 490 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 491
 492 /*
 493  * ZERO_PAGE is a global shared page that is always zero: used
 494  * for zero-mapped memory areas etc..
 495  */
 496 extern unsigned long empty_zero_page[1024];
 497 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 498
 499 #endif /* __ASSEMBLY__ */
 500
 501 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 502 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 503 #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
 504
 505 #define pmd_none(pmd)           (!pmd_val(pmd))
 506 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 507 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 508 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 509
 510 #ifndef __ASSEMBLY__
 511 /*
 512  * The following only work if pte_present() is true.
 513  * Undefined behaviour if not..
 514  */
 515 static inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 516 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 517 static inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_EXEC; }
 518 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 519 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 520 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 521
 522 static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 523 static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 524
 525 static inline pte_t pte_rdprotect(pte_t pte) {
 526         pte_val(pte) &= ~_PAGE_USER; return pte; }
 527 static inline pte_t pte_wrprotect(pte_t pte) {
 528         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 529 static inline pte_t pte_exprotect(pte_t pte) {
 530         pte_val(pte) &= ~_PAGE_EXEC; return pte; }
 531 static inline pte_t pte_mkclean(pte_t pte) {
 532         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 533 static inline pte_t pte_mkold(pte_t pte) {
 534         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 535
 536 static inline pte_t pte_mkread(pte_t pte) {
 537         pte_val(pte) |= _PAGE_USER; return pte; }
 538 static inline pte_t pte_mkexec(pte_t pte) {
 539         pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
 540 static inline pte_t pte_mkwrite(pte_t pte) {
 541         pte_val(pte) |= _PAGE_RW; return pte; }
 542 static inline pte_t pte_mkdirty(pte_t pte) {
 543         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 544 static inline pte_t pte_mkyoung(pte_t pte) {
 545         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 546
 547 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 548 {
 549         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 550         return pte;
 551 }
 552
 553 /*
 554  * When flushing the tlb entry for a page, we also need to flush the hash
 555  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 556  */
 557 extern int flush_hash_pages(unsigned context, unsigned long va,
 558                             unsigned long pmdval, int count);
 559
 560 /* Add an HPTE to the hash table */
 561 extern void add_hash_page(unsigned context, unsigned long va,
 562                           unsigned long pmdval);
 563
 564 /*
 565  * Atomic PTE updates.
 566  *
 567  * pte_update clears and sets bit atomically, and returns
 568  * the old pte value.  In the 64-bit PTE case we lock around the
 569  * low PTE word since we expect ALL flag bits to be there
 570  */
 571 #ifndef CONFIG_PTE_64BIT
 572 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
 573                                        unsigned long set)
 574 {
 575         unsigned long old, tmp;
 576
 577         __asm__ __volatile__("\
 578 1:      lwarx   %0,0,%3\n\
 579         andc    %1,%0,%4\n\
 580         or      %1,%1,%5\n"
 581         PPC405_ERR77(0,%3)
 582 "       stwcx.  %1,0,%3\n\
 583         bne-    1b"
 584         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 585         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 586         : "cc" );
 587         return old;
 588 }
 589 #else
 590 static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
 591                                        unsigned long set)
 592 {
 593         unsigned long long old;
 594         unsigned long tmp;
 595
 596         __asm__ __volatile__("\
 597 1:      lwarx   %L0,0,%4\n\
 598         lwzx    %0,0,%3\n\
 599         andc    %1,%L0,%5\n\
 600         or      %1,%1,%6\n"
 601         PPC405_ERR77(0,%3)
 602 "       stwcx.  %1,0,%4\n\
 603         bne-    1b"
 604         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 605         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 606         : "cc" );
 607         return old;
 608 }
 609 #endif
 610
 611 /*
 612  * set_pte stores a linux PTE into the linux page table.
 613  * On machines which use an MMU hash table we avoid changing the
 614  * _PAGE_HASHPTE bit.
 615  */
 616 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 617                               pte_t *ptep, pte_t pte)
 618 {
 619 #if _PAGE_HASHPTE != 0
 620         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 621 #else
 622         *ptep = pte;
 623 #endif
 624 }
 625
 626 /*
 627  * 2.6 calles this without flushing the TLB entry, this is wrong
 628  * for our hash-based implementation, we fix that up here
 629  */
 630 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 631 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 632 {
 633         unsigned long old;
 634         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 635 #if _PAGE_HASHPTE != 0
 636         if (old & _PAGE_HASHPTE) {
 637                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 638                 flush_hash_pages(context, addr, ptephys, 1);
 639         }
 640 #endif
 641         return (old & _PAGE_ACCESSED) != 0;
 642 }
 643 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 644         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 645
 646 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 647 static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
 648                                             unsigned long addr, pte_t *ptep)
 649 {
 650         return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
 651 }
 652
 653 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 654 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 655                                        pte_t *ptep)
 656 {
 657         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 658 }
 659
 660 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 661 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 662                                       pte_t *ptep)
 663 {
 664         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 665 }
 666
 667 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 668 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 669 {
 670         unsigned long bits = pte_val(entry) &
 671                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 672         pte_update(ptep, 0, bits);
 673 }
 674
 675 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 676 ({                                                                         \
 677         int __changed = !pte_same(*(__ptep), __entry);                     \
 678         if (__changed) {                                                   \
 679                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 680                 flush_tlb_page_nohash(__vma, __address);                   \
 681         }                                                                  \
 682         __changed;                                                         \
 683 })
 684
 685 /*
 686  * Macro to mark a page protection value as "uncacheable".
 687  */
 688 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 689
 690 struct file;
 691 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 692                                      unsigned long size, pgprot_t vma_prot);
 693 #define __HAVE_PHYS_MEM_ACCESS_PROT
 694
 695 #define __HAVE_ARCH_PTE_SAME
 696 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 697
 698 /*
 699  * Note that on Book E processors, the pmd contains the kernel virtual
 700  * (lowmem) address of the pte page.  The physical address is less useful
 701  * because everything runs with translation enabled (even the TLB miss
 702  * handler).  On everything else the pmd contains the physical address
 703  * of the pte page.  -- paulus
 704  */
 705 #ifndef CONFIG_BOOKE
 706 #define pmd_page_vaddr(pmd)     \
 707         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 708 #define pmd_page(pmd)           \
 709         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 710 #else
 711 #define pmd_page_vaddr(pmd)     \
 712         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 713 #define pmd_page(pmd)           \
 714         (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 715 #endif
 716
 717 /* to find an entry in a kernel page-table-directory */
 718 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 719
 720 /* to find an entry in a page-table-directory */
 721 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 722 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 723
 724 /* Find an entry in the third-level page table.. */
 725 #define pte_index(address)              \
 726         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 727 #define pte_offset_kernel(dir, addr)    \
 728         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 729 #define pte_offset_map(dir, addr)               \
 730         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 731 #define pte_offset_map_nested(dir, addr)        \
 732         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 733
 734 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 735 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 736
 737 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 738
 739 extern void paging_init(void);
 740
 741 /*
 742  * Encode and decode a swap entry.
 743  * Note that the bits we use in a PTE for representing a swap entry
 744  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 745  *_PAGE_HASHPTE bit (if used).  -- paulus
 746  */
 747 #define __swp_type(entry)               ((entry).val & 0x1f)
 748 #define __swp_offset(entry)             ((entry).val >> 5)
 749 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 750 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 751 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 752
 753 /* Encode and decode a nonlinear file mapping entry */
 754 #define PTE_FILE_MAX_BITS       29
 755 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 756 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 757
 758 /* CONFIG_APUS */
 759 /* For virtual address to physical address conversion */
 760 extern void cache_clear(__u32 addr, int length);
 761 extern void cache_push(__u32 addr, int length);
 762 extern int mm_end_of_chunk (unsigned long addr, int len);
 763 extern unsigned long iopa(unsigned long addr);
 764 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 765
 766 /* Values for nocacheflag and cmode */
 767 /* These are not used by the APUS kernel_map, but prevents
 768    compilation errors. */
 769 #define KERNELMAP_FULL_CACHING          0
 770 #define KERNELMAP_NOCACHE_SER           1
 771 #define KERNELMAP_NOCACHE_NONSER        2
 772 #define KERNELMAP_NO_COPYBACK           3
 773
 774 /*
 775  * Map some physical address range into the kernel address space.
 776  */
 777 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
 778                                 int nocacheflag, unsigned long *memavailp );
 779
 780 /*
 781  * Set cache mode of (kernel space) address range.
 782  */
 783 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 784                                  unsigned int cmode);
 785
 786 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 787 #define kern_addr_valid(addr)   (1)
 788
 789 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 790                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 791
 792 /*
 793  * No page table caches to initialise
 794  */
 795 #define pgtable_cache_init()    do { } while (0)
 796
 797 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 798                       pmd_t **pmdp);
 799
 800 #endif /* !__ASSEMBLY__ */
 801
 802 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */