drivers/clocksource/sh_tmu.c

   1 /*
   2  * SuperH Timer Support - TMU
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/slab.h>
  34
  35 struct sh_tmu_priv {
  36         void __iomem *mapbase;
  37         struct clk *clk;
  38         struct irqaction irqaction;
  39         struct platform_device *pdev;
  40         unsigned long rate;
  41         unsigned long periodic;
  42         struct clock_event_device ced;
  43         struct clocksource cs;
  44 };
  45
  46 static DEFINE_SPINLOCK(sh_tmu_lock);
  47
  48 #define TSTR -1 /* shared register */
  49 #define TCOR  0 /* channel register */
  50 #define TCNT 1 /* channel register */
  51 #define TCR 2 /* channel register */
  52
  53 static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
  54 {
  55         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  56         void __iomem *base = p->mapbase;
  57         unsigned long offs;
  58
  59         if (reg_nr == TSTR)
  60                 return ioread8(base - cfg->channel_offset);
  61
  62         offs = reg_nr << 2;
  63
  64         if (reg_nr == TCR)
  65                 return ioread16(base + offs);
  66         else
  67                 return ioread32(base + offs);
  68 }
  69
  70 static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
  71                                 unsigned long value)
  72 {
  73         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  74         void __iomem *base = p->mapbase;
  75         unsigned long offs;
  76
  77         if (reg_nr == TSTR) {
  78                 iowrite8(value, base - cfg->channel_offset);
  79                 return;
  80         }
  81
  82         offs = reg_nr << 2;
  83
  84         if (reg_nr == TCR)
  85                 iowrite16(value, base + offs);
  86         else
  87                 iowrite32(value, base + offs);
  88 }
  89
  90 static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
  91 {
  92         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  93         unsigned long flags, value;
  94
  95         /* start stop register shared by multiple timer channels */
  96         spin_lock_irqsave(&sh_tmu_lock, flags);
  97         value = sh_tmu_read(p, TSTR);
  98
  99         if (start)
 100                 value |= 1 << cfg->timer_bit;
 101         else
 102                 value &= ~(1 << cfg->timer_bit);
 103
 104         sh_tmu_write(p, TSTR, value);
 105         spin_unlock_irqrestore(&sh_tmu_lock, flags);
 106 }
 107
 108 static int sh_tmu_enable(struct sh_tmu_priv *p)
 109 {
 110         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
 111         int ret;
 112
 113         /* enable clock */
 114         ret = clk_enable(p->clk);
 115         if (ret) {
 116                 pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
 117                 return ret;
 118         }
 119
 120         /* make sure channel is disabled */
 121         sh_tmu_start_stop_ch(p, 0);
 122
 123         /* maximum timeout */
 124         sh_tmu_write(p, TCOR, 0xffffffff);
 125         sh_tmu_write(p, TCNT, 0xffffffff);
 126
 127         /* configure channel to parent clock / 4, irq off */
 128         p->rate = clk_get_rate(p->clk) / 4;
 129         sh_tmu_write(p, TCR, 0x0000);
 130
 131         /* enable channel */
 132         sh_tmu_start_stop_ch(p, 1);
 133
 134         return 0;
 135 }
 136
 137 static void sh_tmu_disable(struct sh_tmu_priv *p)
 138 {
 139         /* disable channel */
 140         sh_tmu_start_stop_ch(p, 0);
 141
 142         /* disable interrupts in TMU block */
 143         sh_tmu_write(p, TCR, 0x0000);
 144
 145         /* stop clock */
 146         clk_disable(p->clk);
 147 }
 148
 149 static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
 150                             int periodic)
 151 {
 152         /* stop timer */
 153         sh_tmu_start_stop_ch(p, 0);
 154
 155         /* acknowledge interrupt */
 156         sh_tmu_read(p, TCR);
 157
 158         /* enable interrupt */
 159         sh_tmu_write(p, TCR, 0x0020);
 160
 161         /* reload delta value in case of periodic timer */
 162         if (periodic)
 163                 sh_tmu_write(p, TCOR, delta);
 164         else
 165                 sh_tmu_write(p, TCOR, 0xffffffff);
 166
 167         sh_tmu_write(p, TCNT, delta);
 168
 169         /* start timer */
 170         sh_tmu_start_stop_ch(p, 1);
 171 }
 172
 173 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
 174 {
 175         struct sh_tmu_priv *p = dev_id;
 176
 177         /* disable or acknowledge interrupt */
 178         if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
 179                 sh_tmu_write(p, TCR, 0x0000);
 180         else
 181                 sh_tmu_write(p, TCR, 0x0020);
 182
 183         /* notify clockevent layer */
 184         p->ced.event_handler(&p->ced);
 185         return IRQ_HANDLED;
 186 }
 187
 188 static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
 189 {
 190         return container_of(cs, struct sh_tmu_priv, cs);
 191 }
 192
 193 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
 194 {
 195         struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
 196
 197         return sh_tmu_read(p, TCNT) ^ 0xffffffff;
 198 }
 199
 200 static int sh_tmu_clocksource_enable(struct clocksource *cs)
 201 {
 202         struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
 203
 204         return sh_tmu_enable(p);
 205 }
 206
 207 static void sh_tmu_clocksource_disable(struct clocksource *cs)
 208 {
 209         sh_tmu_disable(cs_to_sh_tmu(cs));
 210 }
 211
 212 static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
 213                                        char *name, unsigned long rating)
 214 {
 215         struct clocksource *cs = &p->cs;
 216
 217         cs->name = name;
 218         cs->rating = rating;
 219         cs->read = sh_tmu_clocksource_read;
 220         cs->enable = sh_tmu_clocksource_enable;
 221         cs->disable = sh_tmu_clocksource_disable;
 222         cs->mask = CLOCKSOURCE_MASK(32);
 223         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 224
 225         /* clk_get_rate() needs an enabled clock */
 226         clk_enable(p->clk);
 227         /* channel will be configured at parent clock / 4 */
 228         p->rate = clk_get_rate(p->clk) / 4;
 229         clk_disable(p->clk);
 230         /* TODO: calculate good shift from rate and counter bit width */
 231         cs->shift = 10;
 232         cs->mult = clocksource_hz2mult(p->rate, cs->shift);
 233
 234         pr_info("sh_tmu: %s used as clock source\n", cs->name);
 235         clocksource_register(cs);
 236         return 0;
 237 }
 238
 239 static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
 240 {
 241         return container_of(ced, struct sh_tmu_priv, ced);
 242 }
 243
 244 static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
 245 {
 246         struct clock_event_device *ced = &p->ced;
 247
 248         sh_tmu_enable(p);
 249
 250         /* TODO: calculate good shift from rate and counter bit width */
 251
 252         ced->shift = 32;
 253         ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
 254         ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
 255         ced->min_delta_ns = 5000;
 256
 257         if (periodic) {
 258                 p->periodic = (p->rate + HZ/2) / HZ;
 259                 sh_tmu_set_next(p, p->periodic, 1);
 260         }
 261 }
 262
 263 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
 264                                     struct clock_event_device *ced)
 265 {
 266         struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
 267         int disabled = 0;
 268
 269         /* deal with old setting first */
 270         switch (ced->mode) {
 271         case CLOCK_EVT_MODE_PERIODIC:
 272         case CLOCK_EVT_MODE_ONESHOT:
 273                 sh_tmu_disable(p);
 274                 disabled = 1;
 275                 break;
 276         default:
 277                 break;
 278         }
 279
 280         switch (mode) {
 281         case CLOCK_EVT_MODE_PERIODIC:
 282                 pr_info("sh_tmu: %s used for periodic clock events\n",
 283                         ced->name);
 284                 sh_tmu_clock_event_start(p, 1);
 285                 break;
 286         case CLOCK_EVT_MODE_ONESHOT:
 287                 pr_info("sh_tmu: %s used for oneshot clock events\n",
 288                         ced->name);
 289                 sh_tmu_clock_event_start(p, 0);
 290                 break;
 291         case CLOCK_EVT_MODE_UNUSED:
 292                 if (!disabled)
 293                         sh_tmu_disable(p);
 294                 break;
 295         case CLOCK_EVT_MODE_SHUTDOWN:
 296         default:
 297                 break;
 298         }
 299 }
 300
 301 static int sh_tmu_clock_event_next(unsigned long delta,
 302                                    struct clock_event_device *ced)
 303 {
 304         struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
 305
 306         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 307
 308         /* program new delta value */
 309         sh_tmu_set_next(p, delta, 0);
 310         return 0;
 311 }
 312
 313 static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
 314                                        char *name, unsigned long rating)
 315 {
 316         struct clock_event_device *ced = &p->ced;
 317         int ret;
 318
 319         memset(ced, 0, sizeof(*ced));
 320
 321         ced->name = name;
 322         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 323         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 324         ced->rating = rating;
 325         ced->cpumask = cpumask_of(0);
 326         ced->set_next_event = sh_tmu_clock_event_next;
 327         ced->set_mode = sh_tmu_clock_event_mode;
 328
 329         pr_info("sh_tmu: %s used for clock events\n", ced->name);
 330         clockevents_register_device(ced);
 331
 332         ret = setup_irq(p->irqaction.irq, &p->irqaction);
 333         if (ret) {
 334                 pr_err("sh_tmu: failed to request irq %d\n",
 335                        p->irqaction.irq);
 336                 return;
 337         }
 338 }
 339
 340 static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
 341                     unsigned long clockevent_rating,
 342                     unsigned long clocksource_rating)
 343 {
 344         if (clockevent_rating)
 345                 sh_tmu_register_clockevent(p, name, clockevent_rating);
 346         else if (clocksource_rating)
 347                 sh_tmu_register_clocksource(p, name, clocksource_rating);
 348
 349         return 0;
 350 }
 351
 352 static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
 353 {
 354         struct sh_timer_config *cfg = pdev->dev.platform_data;
 355         struct resource *res;
 356         int irq, ret;
 357         ret = -ENXIO;
 358
 359         memset(p, 0, sizeof(*p));
 360         p->pdev = pdev;
 361
 362         if (!cfg) {
 363                 dev_err(&p->pdev->dev, "missing platform data\n");
 364                 goto err0;
 365         }
 366
 367         platform_set_drvdata(pdev, p);
 368
 369         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 370         if (!res) {
 371                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 372                 goto err0;
 373         }
 374
 375         irq = platform_get_irq(p->pdev, 0);
 376         if (irq < 0) {
 377                 dev_err(&p->pdev->dev, "failed to get irq\n");
 378                 goto err0;
 379         }
 380
 381         /* map memory, let mapbase point to our channel */
 382         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 383         if (p->mapbase == NULL) {
 384                 pr_err("sh_tmu: failed to remap I/O memory\n");
 385                 goto err0;
 386         }
 387
 388         /* setup data for setup_irq() (too early for request_irq()) */
 389         p->irqaction.name = cfg->name;
 390         p->irqaction.handler = sh_tmu_interrupt;
 391         p->irqaction.dev_id = p;
 392         p->irqaction.irq = irq;
 393         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
 394
 395         /* get hold of clock */
 396         p->clk = clk_get(&p->pdev->dev, cfg->clk);
 397         if (IS_ERR(p->clk)) {
 398                 pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
 399                 ret = PTR_ERR(p->clk);
 400                 goto err1;
 401         }
 402
 403         return sh_tmu_register(p, cfg->name,
 404                                cfg->clockevent_rating,
 405                                cfg->clocksource_rating);
 406  err1:
 407         iounmap(p->mapbase);
 408  err0:
 409         return ret;
 410 }
 411
 412 static int __devinit sh_tmu_probe(struct platform_device *pdev)
 413 {
 414         struct sh_tmu_priv *p = platform_get_drvdata(pdev);
 415         struct sh_timer_config *cfg = pdev->dev.platform_data;
 416         int ret;
 417
 418         if (p) {
 419                 pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
 420                 return 0;
 421         }
 422
 423         p = kmalloc(sizeof(*p), GFP_KERNEL);
 424         if (p == NULL) {
 425                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 426                 return -ENOMEM;
 427         }
 428
 429         ret = sh_tmu_setup(p, pdev);
 430         if (ret) {
 431                 kfree(p);
 432                 platform_set_drvdata(pdev, NULL);
 433         }
 434         return ret;
 435 }
 436
 437 static int __devexit sh_tmu_remove(struct platform_device *pdev)
 438 {
 439         return -EBUSY; /* cannot unregister clockevent and clocksource */
 440 }
 441
 442 static struct platform_driver sh_tmu_device_driver = {
 443         .probe          = sh_tmu_probe,
 444         .remove         = __devexit_p(sh_tmu_remove),
 445         .driver         = {
 446                 .name   = "sh_tmu",
 447         }
 448 };
 449
 450 static int __init sh_tmu_init(void)
 451 {
 452         return platform_driver_register(&sh_tmu_device_driver);
 453 }
 454
 455 static void __exit sh_tmu_exit(void)
 456 {
 457         platform_driver_unregister(&sh_tmu_device_driver);
 458 }
 459
 460 early_platform_init("earlytimer", &sh_tmu_device_driver);
 461 module_init(sh_tmu_init);
 462 module_exit(sh_tmu_exit);
 463
 464 MODULE_AUTHOR("Magnus Damm");
 465 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
 466 MODULE_LICENSE("GPL v2");