amd64_edac: unify MCGCTL ECC switching
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1 /*
2 * AMD64 class Memory Controller kernel module
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
10 * Originally Written by Thayne Harbaugh
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
37 * - misc fixes and code cleanups
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
65 #include <linux/module.h>
66 #include <linux/ctype.h>
67 #include <linux/init.h>
68 #include <linux/pci.h>
69 #include <linux/pci_ids.h>
70 #include <linux/slab.h>
71 #include <linux/mmzone.h>
72 #include <linux/edac.h>
73 #include <asm/msr.h>
74 #include "edac_core.h"
75 #include "edac_mce_amd.h"
77 #define amd64_printk(level, fmt, arg...) \
78 edac_printk(level, "amd64", fmt, ##arg)
80 #define amd64_mc_printk(mci, level, fmt, arg...) \
81 edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
84 * Throughout the comments in this code, the following terms are used:
86 * SysAddr, DramAddr, and InputAddr
88 * These terms come directly from the amd64 documentation
89 * (AMD publication #26094). They are defined as follows:
91 * SysAddr:
92 * This is a physical address generated by a CPU core or a device
93 * doing DMA. If generated by a CPU core, a SysAddr is the result of
94 * a virtual to physical address translation by the CPU core's address
95 * translation mechanism (MMU).
97 * DramAddr:
98 * A DramAddr is derived from a SysAddr by subtracting an offset that
99 * depends on which node the SysAddr maps to and whether the SysAddr
100 * is within a range affected by memory hoisting. The DRAM Base
101 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
102 * determine which node a SysAddr maps to.
104 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
105 * is within the range of addresses specified by this register, then
106 * a value x from the DHAR is subtracted from the SysAddr to produce a
107 * DramAddr. Here, x represents the base address for the node that
108 * the SysAddr maps to plus an offset due to memory hoisting. See
109 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
110 * sys_addr_to_dram_addr() below for more information.
112 * If the SysAddr is not affected by the DHAR then a value y is
113 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
114 * base address for the node that the SysAddr maps to. See section
115 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
116 * information.
118 * InputAddr:
119 * A DramAddr is translated to an InputAddr before being passed to the
120 * memory controller for the node that the DramAddr is associated
121 * with. The memory controller then maps the InputAddr to a csrow.
122 * If node interleaving is not in use, then the InputAddr has the same
123 * value as the DramAddr. Otherwise, the InputAddr is produced by
124 * discarding the bits used for node interleaving from the DramAddr.
125 * See section 3.4.4 for more information.
127 * The memory controller for a given node uses its DRAM CS Base and
128 * DRAM CS Mask registers to map an InputAddr to a csrow. See
129 * sections 3.5.4 and 3.5.5 for more information.
132 #define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__
133 #define EDAC_MOD_STR "amd64_edac"
135 #define EDAC_MAX_NUMNODES 8
137 /* Extended Model from CPUID, for CPU Revision numbers */
138 #define OPTERON_CPU_LE_REV_C 0
139 #define OPTERON_CPU_REV_D 1
140 #define OPTERON_CPU_REV_E 2
142 /* NPT processors have the following Extended Models */
143 #define OPTERON_CPU_REV_F 4
144 #define OPTERON_CPU_REV_FA 5
146 /* Hardware limit on ChipSelect rows per MC and processors per system */
147 #define MAX_CS_COUNT 8
148 #define DRAM_REG_COUNT 8
150 #define ON true
151 #define OFF false
154 * PCI-defined configuration space registers
159 * Function 1 - Address Map
161 #define K8_DRAM_BASE_LOW 0x40
162 #define K8_DRAM_LIMIT_LOW 0x44
163 #define K8_DHAR 0xf0
165 #define DHAR_VALID BIT(0)
166 #define F10_DRAM_MEM_HOIST_VALID BIT(1)
168 #define DHAR_BASE_MASK 0xff000000
169 #define dhar_base(dhar) (dhar & DHAR_BASE_MASK)
171 #define K8_DHAR_OFFSET_MASK 0x0000ff00
172 #define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16)
174 #define F10_DHAR_OFFSET_MASK 0x0000ff80
175 /* NOTE: Extra mask bit vs K8 */
176 #define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
179 /* F10 High BASE/LIMIT registers */
180 #define F10_DRAM_BASE_HIGH 0x140
181 #define F10_DRAM_LIMIT_HIGH 0x144
185 * Function 2 - DRAM controller
187 #define K8_DCSB0 0x40
188 #define F10_DCSB1 0x140
190 #define K8_DCSB_CS_ENABLE BIT(0)
191 #define K8_DCSB_NPT_SPARE BIT(1)
192 #define K8_DCSB_NPT_TESTFAIL BIT(2)
195 * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
196 * the address
198 #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL)
199 #define REV_E_DCS_SHIFT 4
201 #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL)
202 #define REV_F_F1Xh_DCS_SHIFT 8
205 * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
206 * to form the address
208 #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL)
209 #define REV_F_DCS_SHIFT 8
211 /* DRAM CS Mask Registers */
212 #define K8_DCSM0 0x60
213 #define F10_DCSM1 0x160
215 /* REV E: select [29:21] and [15:9] from DCSM */
216 #define REV_E_DCSM_MASK_BITS 0x3FE0FE00
218 /* unused bits [24:20] and [12:0] */
219 #define REV_E_DCS_NOTUSED_BITS 0x01F01FFF
221 /* REV F and later: select [28:19] and [13:5] from DCSM */
222 #define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0
224 /* unused bits [26:22] and [12:0] */
225 #define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF
227 #define DBAM0 0x80
228 #define DBAM1 0x180
230 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
231 #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
233 #define DBAM_MAX_VALUE 11
236 #define F10_DCLR_0 0x90
237 #define F10_DCLR_1 0x190
238 #define REVE_WIDTH_128 BIT(16)
239 #define F10_WIDTH_128 BIT(11)
242 #define F10_DCHR_0 0x94
243 #define F10_DCHR_1 0x194
245 #define F10_DCHR_FOUR_RANK_DIMM BIT(18)
246 #define F10_DCHR_Ddr3Mode BIT(8)
247 #define F10_DCHR_MblMode BIT(6)
250 #define F10_DCTL_SEL_LOW 0x110
252 #define dct_sel_baseaddr(pvt) \
253 ((pvt->dram_ctl_select_low) & 0xFFFFF800)
255 #define dct_sel_interleave_addr(pvt) \
256 (((pvt->dram_ctl_select_low) >> 6) & 0x3)
258 enum {
259 F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0),
260 F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2),
261 F10_DCTL_SEL_LOW_DctGangEn = BIT(4),
262 F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5),
263 F10_DCTL_SEL_LOW_DramEnable = BIT(8),
264 F10_DCTL_SEL_LOW_MemCleared = BIT(10),
267 #define dct_high_range_enabled(pvt) \
268 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn)
270 #define dct_interleave_enabled(pvt) \
271 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn)
273 #define dct_ganging_enabled(pvt) \
274 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn)
276 #define dct_data_intlv_enabled(pvt) \
277 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv)
279 #define dct_dram_enabled(pvt) \
280 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable)
282 #define dct_memory_cleared(pvt) \
283 (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared)
286 #define F10_DCTL_SEL_HIGH 0x114
290 * Function 3 - Misc Control
292 #define K8_NBCTL 0x40
294 /* Correctable ECC error reporting enable */
295 #define K8_NBCTL_CECCEn BIT(0)
297 /* UnCorrectable ECC error reporting enable */
298 #define K8_NBCTL_UECCEn BIT(1)
300 #define K8_NBCFG 0x44
301 #define K8_NBCFG_CHIPKILL BIT(23)
302 #define K8_NBCFG_ECC_ENABLE BIT(22)
304 #define K8_NBSL 0x48
307 /* Family F10h: Normalized Extended Error Codes */
308 #define F10_NBSL_EXT_ERR_RES 0x0
309 #define F10_NBSL_EXT_ERR_ECC 0x8
311 /* Next two are overloaded values */
312 #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
313 #define F10_NBSL_EXT_ERR_L3_PROTO 0xB
315 #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
316 #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
317 #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
319 /* Next two are overloaded values */
320 #define F10_NBSL_EXT_ERR_GART_WALK 0xF
321 #define F10_NBSL_EXT_ERR_DEV_WALK 0xF
323 /* 0x10 to 0x1B: Reserved */
324 #define F10_NBSL_EXT_ERR_L3_DATA 0x1C
325 #define F10_NBSL_EXT_ERR_L3_TAG 0x1D
326 #define F10_NBSL_EXT_ERR_L3_LRU 0x1E
328 /* K8: Normalized Extended Error Codes */
329 #define K8_NBSL_EXT_ERR_ECC 0x0
330 #define K8_NBSL_EXT_ERR_CRC 0x1
331 #define K8_NBSL_EXT_ERR_SYNC 0x2
332 #define K8_NBSL_EXT_ERR_MST 0x3
333 #define K8_NBSL_EXT_ERR_TGT 0x4
334 #define K8_NBSL_EXT_ERR_GART 0x5
335 #define K8_NBSL_EXT_ERR_RMW 0x6
336 #define K8_NBSL_EXT_ERR_WDT 0x7
337 #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
338 #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
341 * The following are for BUS type errors AFTER values have been normalized by
342 * shifting right
344 #define K8_NBSL_PP_SRC 0x0
345 #define K8_NBSL_PP_RES 0x1
346 #define K8_NBSL_PP_OBS 0x2
347 #define K8_NBSL_PP_GENERIC 0x3
349 #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
351 #define K8_NBEAL 0x50
352 #define K8_NBEAH 0x54
353 #define K8_SCRCTRL 0x58
355 #define F10_NB_CFG_LOW 0x88
356 #define F10_NB_CFG_LOW_ENABLE_EXT_CFG BIT(14)
358 #define F10_NB_CFG_HIGH 0x8C
360 #define F10_ONLINE_SPARE 0xB0
361 #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
362 #define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
363 #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
364 #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
366 #define F10_NB_ARRAY_ADDR 0xB8
368 #define F10_NB_ARRAY_DRAM_ECC 0x80000000
370 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
371 #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
373 #define F10_NB_ARRAY_DATA 0xBC
375 #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
376 (BIT(((word) & 0xF) + 20) | \
377 BIT(17) | bits)
379 #define SET_NB_DRAM_INJECTION_READ(word, bits) \
380 (BIT(((word) & 0xF) + 20) | \
381 BIT(16) | bits)
383 #define K8_NBCAP 0xE8
384 #define K8_NBCAP_CORES (BIT(12)|BIT(13))
385 #define K8_NBCAP_CHIPKILL BIT(4)
386 #define K8_NBCAP_SECDED BIT(3)
387 #define K8_NBCAP_8_NODE BIT(2)
388 #define K8_NBCAP_DUAL_NODE BIT(1)
389 #define K8_NBCAP_DCT_DUAL BIT(0)
391 /* MSRs */
392 #define K8_MSR_MCGCTL_NBE BIT(4)
394 #define K8_MSR_MC4CTL 0x0410
395 #define K8_MSR_MC4STAT 0x0411
396 #define K8_MSR_MC4ADDR 0x0412
398 /* AMD sets the first MC device at device ID 0x18. */
399 static inline int get_node_id(struct pci_dev *pdev)
401 return PCI_SLOT(pdev->devfn) - 0x18;
404 enum amd64_chipset_families {
405 K8_CPUS = 0,
406 F10_CPUS,
407 F11_CPUS,
410 /* Error injection control structure */
411 struct error_injection {
412 u32 section;
413 u32 word;
414 u32 bit_map;
417 struct amd64_pvt {
418 /* pci_device handles which we utilize */
419 struct pci_dev *addr_f1_ctl;
420 struct pci_dev *dram_f2_ctl;
421 struct pci_dev *misc_f3_ctl;
423 int mc_node_id; /* MC index of this MC node */
424 int ext_model; /* extended model value of this node */
426 struct low_ops *ops; /* pointer to per PCI Device ID func table */
428 int channel_count;
430 /* Raw registers */
431 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
432 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
433 u32 dchr0; /* DRAM Configuration High DCT0 reg */
434 u32 dchr1; /* DRAM Configuration High DCT1 reg */
435 u32 nbcap; /* North Bridge Capabilities */
436 u32 nbcfg; /* F10 North Bridge Configuration */
437 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
438 u32 dhar; /* DRAM Hoist reg */
439 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
440 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
442 /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
443 u32 dcsb0[MAX_CS_COUNT];
444 u32 dcsb1[MAX_CS_COUNT];
446 /* DRAM CS Mask Registers F2x[1,0][6C:60] */
447 u32 dcsm0[MAX_CS_COUNT];
448 u32 dcsm1[MAX_CS_COUNT];
451 * Decoded parts of DRAM BASE and LIMIT Registers
452 * F1x[78,70,68,60,58,50,48,40]
454 u64 dram_base[DRAM_REG_COUNT];
455 u64 dram_limit[DRAM_REG_COUNT];
456 u8 dram_IntlvSel[DRAM_REG_COUNT];
457 u8 dram_IntlvEn[DRAM_REG_COUNT];
458 u8 dram_DstNode[DRAM_REG_COUNT];
459 u8 dram_rw_en[DRAM_REG_COUNT];
462 * The following fields are set at (load) run time, after CPU revision
463 * has been determined, since the dct_base and dct_mask registers vary
464 * based on revision
466 u32 dcsb_base; /* DCSB base bits */
467 u32 dcsm_mask; /* DCSM mask bits */
468 u32 cs_count; /* num chip selects (== num DCSB registers) */
469 u32 num_dcsm; /* Number of DCSM registers */
470 u32 dcs_mask_notused; /* DCSM notused mask bits */
471 u32 dcs_shift; /* DCSB and DCSM shift value */
473 u64 top_mem; /* top of memory below 4GB */
474 u64 top_mem2; /* top of memory above 4GB */
476 u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */
477 u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
478 u32 online_spare; /* On-Line spare Reg */
480 /* temp storage for when input is received from sysfs */
481 struct err_regs ctl_error_info;
483 /* place to store error injection parameters prior to issue */
484 struct error_injection injection;
486 /* Save old hw registers' values before we modified them */
487 u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
488 u32 old_nbctl;
490 /* MC Type Index value: socket F vs Family 10h */
491 u32 mc_type_index;
493 /* misc settings */
494 struct flags {
495 unsigned long cf8_extcfg:1;
496 unsigned long ecc_report:1;
497 } flags;
500 struct scrubrate {
501 u32 scrubval; /* bit pattern for scrub rate */
502 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
505 extern struct scrubrate scrubrates[23];
506 extern u32 revf_quad_ddr2_shift[16];
507 extern const char *tt_msgs[4];
508 extern const char *ll_msgs[4];
509 extern const char *rrrr_msgs[16];
510 extern const char *to_msgs[2];
511 extern const char *pp_msgs[4];
512 extern const char *ii_msgs[4];
513 extern const char *ext_msgs[32];
514 extern const char *htlink_msgs[8];
516 #ifdef CONFIG_EDAC_DEBUG
517 #define NUM_DBG_ATTRS 9
518 #else
519 #define NUM_DBG_ATTRS 0
520 #endif
522 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
523 #define NUM_INJ_ATTRS 5
524 #else
525 #define NUM_INJ_ATTRS 0
526 #endif
528 extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
529 amd64_inj_attrs[NUM_INJ_ATTRS];
532 * Each of the PCI Device IDs types have their own set of hardware accessor
533 * functions and per device encoding/decoding logic.
535 struct low_ops {
536 int (*probe_valid_hardware)(struct amd64_pvt *pvt);
537 int (*early_channel_count)(struct amd64_pvt *pvt);
539 u64 (*get_error_address)(struct mem_ctl_info *mci,
540 struct err_regs *info);
541 void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
542 void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
543 void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
544 struct err_regs *info,
545 u64 SystemAddr);
546 int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
549 struct amd64_family_type {
550 const char *ctl_name;
551 u16 addr_f1_ctl;
552 u16 misc_f3_ctl;
553 struct low_ops ops;
556 static struct amd64_family_type amd64_family_types[];
558 static inline const char *get_amd_family_name(int index)
560 return amd64_family_types[index].ctl_name;
563 static inline struct low_ops *family_ops(int index)
565 return &amd64_family_types[index].ops;
569 * For future CPU versions, verify the following as new 'slow' rates appear and
570 * modify the necessary skip values for the supported CPU.
572 #define K8_MIN_SCRUB_RATE_BITS 0x0
573 #define F10_MIN_SCRUB_RATE_BITS 0x5
574 #define F11_MIN_SCRUB_RATE_BITS 0x6
576 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
577 u64 *hole_offset, u64 *hole_size);