arch/arm/mach-davinci/time.c

   1 /*
   2  * DaVinci timer subsystem
   3  *
   4  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * 2007 (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/device.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <mach/hardware.h>
  25 #include <asm/system.h>
  26 #include <asm/irq.h>
  27 #include <asm/mach/irq.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/errno.h>
  30 #include <mach/io.h>
  31 #include <mach/cputype.h>
  32 #include <mach/time.h>
  33 #include "clock.h"
  34
  35 static struct clock_event_device clockevent_davinci;
  36 static unsigned int davinci_clock_tick_rate;
  37
  38 #define DAVINCI_WDOG_BASE   (IO_PHYS + 0x21C00)
  39
  40 /*
  41  * This driver configures the 2 64-bit count-up timers as 4 independent
  42  * 32-bit count-up timers used as follows:
  43  */
  44
  45 enum {
  46         TID_CLOCKEVENT,
  47         TID_CLOCKSOURCE,
  48 };
  49
  50 /* Timer register offsets */
  51 #define PID12                        0x0
  52 #define TIM12                        0x10
  53 #define TIM34                        0x14
  54 #define PRD12                        0x18
  55 #define PRD34                        0x1c
  56 #define TCR                          0x20
  57 #define TGCR                         0x24
  58 #define WDTCR                        0x28
  59
  60 /* Timer register bitfields */
  61 #define TCR_ENAMODE_DISABLE          0x0
  62 #define TCR_ENAMODE_ONESHOT          0x1
  63 #define TCR_ENAMODE_PERIODIC         0x2
  64 #define TCR_ENAMODE_MASK             0x3
  65
  66 #define TGCR_TIMMODE_SHIFT           2
  67 #define TGCR_TIMMODE_64BIT_GP        0x0
  68 #define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
  69 #define TGCR_TIMMODE_64BIT_WDOG      0x2
  70 #define TGCR_TIMMODE_32BIT_CHAINED   0x3
  71
  72 #define TGCR_TIM12RS_SHIFT           0
  73 #define TGCR_TIM34RS_SHIFT           1
  74 #define TGCR_RESET                   0x0
  75 #define TGCR_UNRESET                 0x1
  76 #define TGCR_RESET_MASK              0x3
  77
  78 #define WDTCR_WDEN_SHIFT             14
  79 #define WDTCR_WDEN_DISABLE           0x0
  80 #define WDTCR_WDEN_ENABLE            0x1
  81 #define WDTCR_WDKEY_SHIFT            16
  82 #define WDTCR_WDKEY_SEQ0             0xa5c6
  83 #define WDTCR_WDKEY_SEQ1             0xda7e
  84
  85 struct timer_s {
  86         char *name;
  87         unsigned int id;
  88         unsigned long period;
  89         unsigned long opts;
  90         void __iomem *base;
  91         unsigned long tim_off;
  92         unsigned long prd_off;
  93         unsigned long enamode_shift;
  94         struct irqaction irqaction;
  95 };
  96 static struct timer_s timers[];
  97
  98 /* values for 'opts' field of struct timer_s */
  99 #define TIMER_OPTS_DISABLED   0x00
 100 #define TIMER_OPTS_ONESHOT    0x01
 101 #define TIMER_OPTS_PERIODIC   0x02
 102
 103 static char *id_to_name[] = {
 104         [T0_BOT]        = "timer0_0",
 105         [T0_TOP]        = "timer0_1",
 106         [T1_BOT]        = "timer1_0",
 107         [T1_TOP]        = "timer1_1",
 108 };
 109
 110 static int timer32_config(struct timer_s *t)
 111 {
 112         u32 tcr = __raw_readl(t->base + TCR);
 113
 114         /* disable timer */
 115         tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
 116         __raw_writel(tcr, t->base + TCR);
 117
 118         /* reset counter to zero, set new period */
 119         __raw_writel(0, t->base + t->tim_off);
 120         __raw_writel(t->period, t->base + t->prd_off);
 121
 122         /* Set enable mode */
 123         if (t->opts & TIMER_OPTS_ONESHOT) {
 124                 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
 125         } else if (t->opts & TIMER_OPTS_PERIODIC) {
 126                 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
 127         }
 128
 129         __raw_writel(tcr, t->base + TCR);
 130         return 0;
 131 }
 132
 133 static inline u32 timer32_read(struct timer_s *t)
 134 {
 135         return __raw_readl(t->base + t->tim_off);
 136 }
 137
 138 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 139 {
 140         struct clock_event_device *evt = &clockevent_davinci;
 141
 142         evt->event_handler(evt);
 143         return IRQ_HANDLED;
 144 }
 145
 146 /* called when 32-bit counter wraps */
 147 static irqreturn_t freerun_interrupt(int irq, void *dev_id)
 148 {
 149         return IRQ_HANDLED;
 150 }
 151
 152 static struct timer_s timers[] = {
 153         [TID_CLOCKEVENT] = {
 154                 .name      = "clockevent",
 155                 .opts      = TIMER_OPTS_DISABLED,
 156                 .irqaction = {
 157                         .flags   = IRQF_DISABLED | IRQF_TIMER,
 158                         .handler = timer_interrupt,
 159                 }
 160         },
 161         [TID_CLOCKSOURCE] = {
 162                 .name       = "free-run counter",
 163                 .period     = ~0,
 164                 .opts       = TIMER_OPTS_PERIODIC,
 165                 .irqaction = {
 166                         .flags   = IRQF_DISABLED | IRQF_TIMER,
 167                         .handler = freerun_interrupt,
 168                 }
 169         },
 170 };
 171
 172 static void __init timer_init(void)
 173 {
 174         struct davinci_soc_info *soc_info = &davinci_soc_info;
 175         struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
 176         int i;
 177
 178         /* Global init of each 64-bit timer as a whole */
 179         for(i=0; i<2; i++) {
 180                 u32 tgcr;
 181                 void __iomem *base = dtip[i].base;
 182
 183                 /* Disabled, Internal clock source */
 184                 __raw_writel(0, base + TCR);
 185
 186                 /* reset both timers, no pre-scaler for timer34 */
 187                 tgcr = 0;
 188                 __raw_writel(tgcr, base + TGCR);
 189
 190                 /* Set both timers to unchained 32-bit */
 191                 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
 192                 __raw_writel(tgcr, base + TGCR);
 193
 194                 /* Unreset timers */
 195                 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 196                         (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
 197                 __raw_writel(tgcr, base + TGCR);
 198
 199                 /* Init both counters to zero */
 200                 __raw_writel(0, base + TIM12);
 201                 __raw_writel(0, base + TIM34);
 202         }
 203
 204         /* Init of each timer as a 32-bit timer */
 205         for (i=0; i< ARRAY_SIZE(timers); i++) {
 206                 struct timer_s *t = &timers[i];
 207                 int timer = ID_TO_TIMER(t->id);
 208                 u32 irq;
 209
 210                 t->base = dtip[timer].base;
 211
 212                 if (IS_TIMER_BOT(t->id)) {
 213                         t->enamode_shift = 6;
 214                         t->tim_off = TIM12;
 215                         t->prd_off = PRD12;
 216                         irq = dtip[timer].bottom_irq;
 217                 } else {
 218                         t->enamode_shift = 22;
 219                         t->tim_off = TIM34;
 220                         t->prd_off = PRD34;
 221                         irq = dtip[timer].top_irq;
 222                 }
 223
 224                 /* Register interrupt */
 225                 t->irqaction.name = t->name;
 226                 t->irqaction.dev_id = (void *)t;
 227                 if (t->irqaction.handler != NULL)
 228                         setup_irq(irq, &t->irqaction);
 229
 230                 timer32_config(&timers[i]);
 231         }
 232 }
 233
 234 /*
 235  * clocksource
 236  */
 237 static cycle_t read_cycles(struct clocksource *cs)
 238 {
 239         struct timer_s *t = &timers[TID_CLOCKSOURCE];
 240
 241         return (cycles_t)timer32_read(t);
 242 }
 243
 244 static struct clocksource clocksource_davinci = {
 245         .rating         = 300,
 246         .read           = read_cycles,
 247         .mask           = CLOCKSOURCE_MASK(32),
 248         .shift          = 24,
 249         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 250 };
 251
 252 /*
 253  * clockevent
 254  */
 255 static int davinci_set_next_event(unsigned long cycles,
 256                                   struct clock_event_device *evt)
 257 {
 258         struct timer_s *t = &timers[TID_CLOCKEVENT];
 259
 260         t->period = cycles;
 261         timer32_config(t);
 262         return 0;
 263 }
 264
 265 static void davinci_set_mode(enum clock_event_mode mode,
 266                              struct clock_event_device *evt)
 267 {
 268         struct timer_s *t = &timers[TID_CLOCKEVENT];
 269
 270         switch (mode) {
 271         case CLOCK_EVT_MODE_PERIODIC:
 272                 t->period = davinci_clock_tick_rate / (HZ);
 273                 t->opts = TIMER_OPTS_PERIODIC;
 274                 timer32_config(t);
 275                 break;
 276         case CLOCK_EVT_MODE_ONESHOT:
 277                 t->opts = TIMER_OPTS_ONESHOT;
 278                 break;
 279         case CLOCK_EVT_MODE_UNUSED:
 280         case CLOCK_EVT_MODE_SHUTDOWN:
 281                 t->opts = TIMER_OPTS_DISABLED;
 282                 break;
 283         case CLOCK_EVT_MODE_RESUME:
 284                 break;
 285         }
 286 }
 287
 288 static struct clock_event_device clockevent_davinci = {
 289         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 290         .shift          = 32,
 291         .set_next_event = davinci_set_next_event,
 292         .set_mode       = davinci_set_mode,
 293 };
 294
 295
 296 static void __init davinci_timer_init(void)
 297 {
 298         struct clk *timer_clk;
 299         struct davinci_soc_info *soc_info = &davinci_soc_info;
 300
 301         static char err[] __initdata = KERN_ERR
 302                 "%s: can't register clocksource!\n";
 303
 304         timers[TID_CLOCKEVENT].id = soc_info->timer_info->clockevent_id;
 305         timers[TID_CLOCKSOURCE].id = soc_info->timer_info->clocksource_id;
 306
 307         /* init timer hw */
 308         timer_init();
 309
 310         timer_clk = clk_get(NULL, "timer0");
 311         BUG_ON(IS_ERR(timer_clk));
 312         clk_enable(timer_clk);
 313
 314         davinci_clock_tick_rate = clk_get_rate(timer_clk);
 315
 316         /* setup clocksource */
 317         clocksource_davinci.name = id_to_name[timers[TID_CLOCKSOURCE].id];
 318         clocksource_davinci.mult =
 319                 clocksource_khz2mult(davinci_clock_tick_rate/1000,
 320                                      clocksource_davinci.shift);
 321         if (clocksource_register(&clocksource_davinci))
 322                 printk(err, clocksource_davinci.name);
 323
 324         /* setup clockevent */
 325         clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
 326         clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
 327                                          clockevent_davinci.shift);
 328         clockevent_davinci.max_delta_ns =
 329                 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
 330         clockevent_davinci.min_delta_ns =
 331                 clockevent_delta2ns(1, &clockevent_davinci);
 332
 333         clockevent_davinci.cpumask = cpumask_of(0);
 334         clockevents_register_device(&clockevent_davinci);
 335 }
 336
 337 struct sys_timer davinci_timer = {
 338         .init   = davinci_timer_init,
 339 };
 340
 341
 342 /* reset board using watchdog timer */
 343 void davinci_watchdog_reset(void)
 344 {
 345         u32 tgcr, wdtcr;
 346         void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
 347         struct clk *wd_clk;
 348
 349         wd_clk = clk_get(&davinci_wdt_device.dev, NULL);
 350         if (WARN_ON(IS_ERR(wd_clk)))
 351                 return;
 352         clk_enable(wd_clk);
 353
 354         /* disable, internal clock source */
 355         __raw_writel(0, base + TCR);
 356
 357         /* reset timer, set mode to 64-bit watchdog, and unreset */
 358         tgcr = 0;
 359         __raw_writel(tgcr, base + TCR);
 360         tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
 361         tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 362                 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
 363         __raw_writel(tgcr, base + TCR);
 364
 365         /* clear counter and period regs */
 366         __raw_writel(0, base + TIM12);
 367         __raw_writel(0, base + TIM34);
 368         __raw_writel(0, base + PRD12);
 369         __raw_writel(0, base + PRD34);
 370
 371         /* enable */
 372         wdtcr = __raw_readl(base + WDTCR);
 373         wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
 374         __raw_writel(wdtcr, base + WDTCR);
 375
 376         /* put watchdog in pre-active state */
 377         wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
 378                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
 379         __raw_writel(wdtcr, base + WDTCR);
 380
 381         /* put watchdog in active state */
 382         wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
 383                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
 384         __raw_writel(wdtcr, base + WDTCR);
 385
 386         /* write an invalid value to the WDKEY field to trigger
 387          * a watchdog reset */
 388         wdtcr = 0x00004000;
 389         __raw_writel(wdtcr, base + WDTCR);
 390 }