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1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
35 #ifndef RT2800_H
36 #define RT2800_H
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 */
55 #define RF2820 0x0001
56 #define RF2850 0x0002
57 #define RF2720 0x0003
58 #define RF2750 0x0004
59 #define RF3020 0x0005
60 #define RF2020 0x0006
61 #define RF3021 0x0007
62 #define RF3022 0x0008
63 #define RF3052 0x0009
64 #define RF2853 0x000a
65 #define RF3320 0x000b
66 #define RF3322 0x000c
67 #define RF3853 0x000d
69 /*
70 * Chipset revisions.
71 */
72 #define REV_RT2860C 0x0100
73 #define REV_RT2860D 0x0101
74 #define REV_RT2872E 0x0200
75 #define REV_RT3070E 0x0200
76 #define REV_RT3070F 0x0201
77 #define REV_RT3071E 0x0211
78 #define REV_RT3090E 0x0211
79 #define REV_RT3390E 0x0211
81 /*
82 * Signal information.
83 * Default offset is required for RSSI <-> dBm conversion.
84 */
85 #define DEFAULT_RSSI_OFFSET 120
87 /*
88 * Register layout information.
89 */
90 #define CSR_REG_BASE 0x1000
91 #define CSR_REG_SIZE 0x0800
92 #define EEPROM_BASE 0x0000
93 #define EEPROM_SIZE 0x0110
94 #define BBP_BASE 0x0000
95 #define BBP_SIZE 0x0080
96 #define RF_BASE 0x0004
97 #define RF_SIZE 0x0010
99 /*
100 * Number of TX queues.
101 */
102 #define NUM_TX_QUEUES 4
104 /*
105 * Registers.
106 */
108 /*
109 * E2PROM_CSR: PCI EEPROM control register.
110 * RELOAD: Write 1 to reload eeprom content.
111 * TYPE: 0: 93c46, 1:93c66.
112 * LOAD_STATUS: 1:loading, 0:done.
113 */
114 #define E2PROM_CSR 0x0004
115 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
116 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
117 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
118 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
119 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
120 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
121 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
123 /*
124 * OPT_14: Unknown register used by rt3xxx devices.
125 */
126 #define OPT_14_CSR 0x0114
127 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
129 /*
130 * INT_SOURCE_CSR: Interrupt source register.
131 * Write one to clear corresponding bit.
132 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
133 */
134 #define INT_SOURCE_CSR 0x0200
135 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
136 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
137 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
138 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
139 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
140 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
141 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
142 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
143 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
144 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
145 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
146 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
147 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
148 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
149 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
150 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
151 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
152 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
154 /*
155 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
156 */
157 #define INT_MASK_CSR 0x0204
158 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
159 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
160 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
161 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
162 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
163 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
164 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
165 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
166 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
167 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
168 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
169 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
170 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
171 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
172 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
173 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
174 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
175 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
177 /*
178 * WPDMA_GLO_CFG
179 */
180 #define WPDMA_GLO_CFG 0x0208
181 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
182 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
183 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
184 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
185 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
186 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
187 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
188 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
189 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
191 /*
192 * WPDMA_RST_IDX
193 */
194 #define WPDMA_RST_IDX 0x020c
195 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
196 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
197 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
198 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
199 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
200 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
201 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
203 /*
204 * DELAY_INT_CFG
205 */
206 #define DELAY_INT_CFG 0x0210
207 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
208 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
209 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
210 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
211 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
212 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
214 /*
215 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
216 * AIFSN0: AC_VO
217 * AIFSN1: AC_VI
218 * AIFSN2: AC_BE
219 * AIFSN3: AC_BK
220 */
221 #define WMM_AIFSN_CFG 0x0214
222 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
223 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
224 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
225 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
227 /*
228 * WMM_CWMIN_CSR: CWmin for each EDCA AC
229 * CWMIN0: AC_VO
230 * CWMIN1: AC_VI
231 * CWMIN2: AC_BE
232 * CWMIN3: AC_BK
233 */
234 #define WMM_CWMIN_CFG 0x0218
235 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
236 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
237 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
238 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
240 /*
241 * WMM_CWMAX_CSR: CWmax for each EDCA AC
242 * CWMAX0: AC_VO
243 * CWMAX1: AC_VI
244 * CWMAX2: AC_BE
245 * CWMAX3: AC_BK
246 */
247 #define WMM_CWMAX_CFG 0x021c
248 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
249 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
250 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
251 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
253 /*
254 * AC_TXOP0: AC_VO/AC_VI TXOP register
255 * AC0TXOP: AC_VO in unit of 32us
256 * AC1TXOP: AC_VI in unit of 32us
257 */
258 #define WMM_TXOP0_CFG 0x0220
259 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
260 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
262 /*
263 * AC_TXOP1: AC_BE/AC_BK TXOP register
264 * AC2TXOP: AC_BE in unit of 32us
265 * AC3TXOP: AC_BK in unit of 32us
266 */
267 #define WMM_TXOP1_CFG 0x0224
268 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
269 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
271 /*
272 * GPIO_CTRL_CFG:
273 */
274 #define GPIO_CTRL_CFG 0x0228
275 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
276 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
277 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
278 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
279 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
280 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
281 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
282 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
283 #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
285 /*
286 * MCU_CMD_CFG
287 */
288 #define MCU_CMD_CFG 0x022c
290 /*
291 * AC_VO register offsets
292 */
293 #define TX_BASE_PTR0 0x0230
294 #define TX_MAX_CNT0 0x0234
295 #define TX_CTX_IDX0 0x0238
296 #define TX_DTX_IDX0 0x023c
298 /*
299 * AC_VI register offsets
300 */
301 #define TX_BASE_PTR1 0x0240
302 #define TX_MAX_CNT1 0x0244
303 #define TX_CTX_IDX1 0x0248
304 #define TX_DTX_IDX1 0x024c
306 /*
307 * AC_BE register offsets
308 */
309 #define TX_BASE_PTR2 0x0250
310 #define TX_MAX_CNT2 0x0254
311 #define TX_CTX_IDX2 0x0258
312 #define TX_DTX_IDX2 0x025c
314 /*
315 * AC_BK register offsets
316 */
317 #define TX_BASE_PTR3 0x0260
318 #define TX_MAX_CNT3 0x0264
319 #define TX_CTX_IDX3 0x0268
320 #define TX_DTX_IDX3 0x026c
322 /*
323 * HCCA register offsets
324 */
325 #define TX_BASE_PTR4 0x0270
326 #define TX_MAX_CNT4 0x0274
327 #define TX_CTX_IDX4 0x0278
328 #define TX_DTX_IDX4 0x027c
330 /*
331 * MGMT register offsets
332 */
333 #define TX_BASE_PTR5 0x0280
334 #define TX_MAX_CNT5 0x0284
335 #define TX_CTX_IDX5 0x0288
336 #define TX_DTX_IDX5 0x028c
338 /*
339 * RX register offsets
340 */
341 #define RX_BASE_PTR 0x0290
342 #define RX_MAX_CNT 0x0294
343 #define RX_CRX_IDX 0x0298
344 #define RX_DRX_IDX 0x029c
346 /*
347 * USB_DMA_CFG
348 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
349 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
350 * PHY_CLEAR: phy watch dog enable.
351 * TX_CLEAR: Clear USB DMA TX path.
352 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
353 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
354 * RX_BULK_EN: Enable USB DMA Rx.
355 * TX_BULK_EN: Enable USB DMA Tx.
356 * EP_OUT_VALID: OUT endpoint data valid.
357 * RX_BUSY: USB DMA RX FSM busy.
358 * TX_BUSY: USB DMA TX FSM busy.
359 */
360 #define USB_DMA_CFG 0x02a0
361 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
362 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
363 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
364 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
365 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
366 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
367 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
368 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
369 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
370 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
371 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
373 /*
374 * US_CYC_CNT
375 */
376 #define US_CYC_CNT 0x02a4
377 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
379 /*
380 * PBF_SYS_CTRL
381 * HOST_RAM_WRITE: enable Host program ram write selection
382 */
383 #define PBF_SYS_CTRL 0x0400
384 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
385 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
387 /*
388 * HOST-MCU shared memory
389 */
390 #define HOST_CMD_CSR 0x0404
391 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
393 /*
394 * PBF registers
395 * Most are for debug. Driver doesn't touch PBF register.
396 */
397 #define PBF_CFG 0x0408
398 #define PBF_MAX_PCNT 0x040c
399 #define PBF_CTRL 0x0410
400 #define PBF_INT_STA 0x0414
401 #define PBF_INT_ENA 0x0418
403 /*
404 * BCN_OFFSET0:
405 */
406 #define BCN_OFFSET0 0x042c
407 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
408 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
409 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
410 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
412 /*
413 * BCN_OFFSET1:
414 */
415 #define BCN_OFFSET1 0x0430
416 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
417 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
418 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
419 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
421 /*
422 * TXRXQ_PCNT: PBF register
423 * PCNT_TX0Q: Page count for TX hardware queue 0
424 * PCNT_TX1Q: Page count for TX hardware queue 1
425 * PCNT_TX2Q: Page count for TX hardware queue 2
426 * PCNT_RX0Q: Page count for RX hardware queue
427 */
428 #define TXRXQ_PCNT 0x0438
429 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
430 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
431 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
432 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
434 /*
435 * PBF register
436 * Debug. Driver doesn't touch PBF register.
437 */
438 #define PBF_DBG 0x043c
440 /*
441 * RF registers
442 */
443 #define RF_CSR_CFG 0x0500
444 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
445 #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
446 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
447 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
449 /*
450 * EFUSE_CSR: RT30x0 EEPROM
451 */
452 #define EFUSE_CTRL 0x0580
453 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
454 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
455 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
456 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
458 /*
459 * EFUSE_DATA0
460 */
461 #define EFUSE_DATA0 0x0590
463 /*
464 * EFUSE_DATA1
465 */
466 #define EFUSE_DATA1 0x0594
468 /*
469 * EFUSE_DATA2
470 */
471 #define EFUSE_DATA2 0x0598
473 /*
474 * EFUSE_DATA3
475 */
476 #define EFUSE_DATA3 0x059c
478 /*
479 * LDO_CFG0
480 */
481 #define LDO_CFG0 0x05d4
482 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
483 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
484 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
485 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
486 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
487 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
488 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
490 /*
491 * GPIO_SWITCH
492 */
493 #define GPIO_SWITCH 0x05dc
494 #define GPIO_SWITCH_0 FIELD32(0x00000001)
495 #define GPIO_SWITCH_1 FIELD32(0x00000002)
496 #define GPIO_SWITCH_2 FIELD32(0x00000004)
497 #define GPIO_SWITCH_3 FIELD32(0x00000008)
498 #define GPIO_SWITCH_4 FIELD32(0x00000010)
499 #define GPIO_SWITCH_5 FIELD32(0x00000020)
500 #define GPIO_SWITCH_6 FIELD32(0x00000040)
501 #define GPIO_SWITCH_7 FIELD32(0x00000080)
503 /*
504 * MAC Control/Status Registers(CSR).
505 * Some values are set in TU, whereas 1 TU == 1024 us.
506 */
508 /*
509 * MAC_CSR0: ASIC revision number.
510 * ASIC_REV: 0
511 * ASIC_VER: 2860 or 2870
512 */
513 #define MAC_CSR0 0x1000
514 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
515 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
517 /*
518 * MAC_SYS_CTRL:
519 */
520 #define MAC_SYS_CTRL 0x1004
521 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
522 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
523 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
524 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
525 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
526 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
527 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
528 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
530 /*
531 * MAC_ADDR_DW0: STA MAC register 0
532 */
533 #define MAC_ADDR_DW0 0x1008
534 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
535 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
536 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
537 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
539 /*
540 * MAC_ADDR_DW1: STA MAC register 1
541 * UNICAST_TO_ME_MASK:
542 * Used to mask off bits from byte 5 of the MAC address
543 * to determine the UNICAST_TO_ME bit for RX frames.
544 * The full mask is complemented by BSS_ID_MASK:
545 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
546 */
547 #define MAC_ADDR_DW1 0x100c
548 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
549 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
550 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
552 /*
553 * MAC_BSSID_DW0: BSSID register 0
554 */
555 #define MAC_BSSID_DW0 0x1010
556 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
557 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
558 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
559 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
561 /*
562 * MAC_BSSID_DW1: BSSID register 1
563 * BSS_ID_MASK:
564 * 0: 1-BSSID mode (BSS index = 0)
565 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
566 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
567 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
568 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
569 * BSSID. This will make sure that those bits will be ignored
570 * when determining the MY_BSS of RX frames.
571 */
572 #define MAC_BSSID_DW1 0x1014
573 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
574 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
575 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
576 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
578 /*
579 * MAX_LEN_CFG: Maximum frame length register.
580 * MAX_MPDU: rt2860b max 16k bytes
581 * MAX_PSDU: Maximum PSDU length
582 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
583 */
584 #define MAX_LEN_CFG 0x1018
585 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
586 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
587 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
588 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
590 /*
591 * BBP_CSR_CFG: BBP serial control register
592 * VALUE: Register value to program into BBP
593 * REG_NUM: Selected BBP register
594 * READ_CONTROL: 0 write BBP, 1 read BBP
595 * BUSY: ASIC is busy executing BBP commands
596 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
597 * BBP_RW_MODE: 0 serial, 1 paralell
598 */
599 #define BBP_CSR_CFG 0x101c
600 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
601 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
602 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
603 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
604 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
605 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
607 /*
608 * RF_CSR_CFG0: RF control register
609 * REGID_AND_VALUE: Register value to program into RF
610 * BITWIDTH: Selected RF register
611 * STANDBYMODE: 0 high when standby, 1 low when standby
612 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
613 * BUSY: ASIC is busy executing RF commands
614 */
615 #define RF_CSR_CFG0 0x1020
616 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
617 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
618 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
619 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
620 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
621 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
623 /*
624 * RF_CSR_CFG1: RF control register
625 * REGID_AND_VALUE: Register value to program into RF
626 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
627 * 0: 3 system clock cycle (37.5usec)
628 * 1: 5 system clock cycle (62.5usec)
629 */
630 #define RF_CSR_CFG1 0x1024
631 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
632 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
634 /*
635 * RF_CSR_CFG2: RF control register
636 * VALUE: Register value to program into RF
637 */
638 #define RF_CSR_CFG2 0x1028
639 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
641 /*
642 * LED_CFG: LED control
643 * color LED's:
644 * 0: off
645 * 1: blinking upon TX2
646 * 2: periodic slow blinking
647 * 3: always on
648 * LED polarity:
649 * 0: active low
650 * 1: active high
651 */
652 #define LED_CFG 0x102c
653 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
654 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
655 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
656 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
657 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
658 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
659 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
661 /*
662 * AMPDU_BA_WINSIZE: Force BlockAck window size
663 * FORCE_WINSIZE_ENABLE:
664 * 0: Disable forcing of BlockAck window size
665 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
666 * window size values in the TXWI
667 * FORCE_WINSIZE: BlockAck window size
668 */
669 #define AMPDU_BA_WINSIZE 0x1040
670 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
671 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
673 /*
674 * XIFS_TIME_CFG: MAC timing
675 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
676 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
677 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
678 * when MAC doesn't reference BBP signal BBRXEND
679 * EIFS: unit 1us
680 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
681 *
682 */
683 #define XIFS_TIME_CFG 0x1100
684 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
685 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
686 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
687 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
688 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
690 /*
691 * BKOFF_SLOT_CFG:
692 */
693 #define BKOFF_SLOT_CFG 0x1104
694 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
695 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
697 /*
698 * NAV_TIME_CFG:
699 */
700 #define NAV_TIME_CFG 0x1108
701 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
702 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
703 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
704 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
706 /*
707 * CH_TIME_CFG: count as channel busy
708 * EIFS_BUSY: Count EIFS as channel busy
709 * NAV_BUSY: Count NAS as channel busy
710 * RX_BUSY: Count RX as channel busy
711 * TX_BUSY: Count TX as channel busy
712 * TMR_EN: Enable channel statistics timer
713 */
714 #define CH_TIME_CFG 0x110c
715 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
716 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
717 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
718 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
719 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
721 /*
722 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
723 */
724 #define PBF_LIFE_TIMER 0x1110
726 /*
727 * BCN_TIME_CFG:
728 * BEACON_INTERVAL: in unit of 1/16 TU
729 * TSF_TICKING: Enable TSF auto counting
730 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
731 * BEACON_GEN: Enable beacon generator
732 */
733 #define BCN_TIME_CFG 0x1114
734 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
735 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
736 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
737 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
738 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
739 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
741 /*
742 * TBTT_SYNC_CFG:
743 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
744 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
745 */
746 #define TBTT_SYNC_CFG 0x1118
747 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
748 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
749 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
750 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
752 /*
753 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
754 */
755 #define TSF_TIMER_DW0 0x111c
756 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
758 /*
759 * TSF_TIMER_DW1: Local msb TSF timer, read-only
760 */
761 #define TSF_TIMER_DW1 0x1120
762 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
764 /*
765 * TBTT_TIMER: TImer remains till next TBTT, read-only
766 */
767 #define TBTT_TIMER 0x1124
769 /*
770 * INT_TIMER_CFG: timer configuration
771 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
772 * GP_TIMER: period of general purpose timer in units of 1/16 TU
773 */
774 #define INT_TIMER_CFG 0x1128
775 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
776 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
778 /*
779 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
780 */
781 #define INT_TIMER_EN 0x112c
782 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
783 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
785 /*
786 * CH_IDLE_STA: channel idle time (in us)
787 */
788 #define CH_IDLE_STA 0x1130
790 /*
791 * CH_BUSY_STA: channel busy time on primary channel (in us)
792 */
793 #define CH_BUSY_STA 0x1134
795 /*
796 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
797 */
798 #define CH_BUSY_STA_SEC 0x1138
800 /*
801 * MAC_STATUS_CFG:
802 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
803 * if 1 or higher one of the 2 registers is busy.
804 */
805 #define MAC_STATUS_CFG 0x1200
806 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
808 /*
809 * PWR_PIN_CFG:
810 */
811 #define PWR_PIN_CFG 0x1204
813 /*
814 * AUTOWAKEUP_CFG: Manual power control / status register
815 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
816 * AUTOWAKE: 0:sleep, 1:awake
817 */
818 #define AUTOWAKEUP_CFG 0x1208
819 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
820 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
821 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
823 /*
824 * EDCA_AC0_CFG:
825 */
826 #define EDCA_AC0_CFG 0x1300
827 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
828 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
829 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
830 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
832 /*
833 * EDCA_AC1_CFG:
834 */
835 #define EDCA_AC1_CFG 0x1304
836 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
837 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
838 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
839 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
841 /*
842 * EDCA_AC2_CFG:
843 */
844 #define EDCA_AC2_CFG 0x1308
845 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
846 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
847 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
848 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
850 /*
851 * EDCA_AC3_CFG:
852 */
853 #define EDCA_AC3_CFG 0x130c
854 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
855 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
856 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
857 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
859 /*
860 * EDCA_TID_AC_MAP:
861 */
862 #define EDCA_TID_AC_MAP 0x1310
864 /*
865 * TX_PWR_CFG:
866 */
867 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
868 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
869 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
870 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
871 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
872 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
873 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
874 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
876 /*
877 * TX_PWR_CFG_0:
878 */
879 #define TX_PWR_CFG_0 0x1314
880 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
881 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
882 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
883 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
884 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
885 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
886 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
887 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
889 /*
890 * TX_PWR_CFG_1:
891 */
892 #define TX_PWR_CFG_1 0x1318
893 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
894 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
895 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
896 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
897 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
898 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
899 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
900 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
902 /*
903 * TX_PWR_CFG_2:
904 */
905 #define TX_PWR_CFG_2 0x131c
906 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
907 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
908 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
909 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
910 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
911 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
912 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
913 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
915 /*
916 * TX_PWR_CFG_3:
917 */
918 #define TX_PWR_CFG_3 0x1320
919 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
920 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
921 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
922 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
923 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
924 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
925 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
926 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
928 /*
929 * TX_PWR_CFG_4:
930 */
931 #define TX_PWR_CFG_4 0x1324
932 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
933 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
934 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
935 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
937 /*
938 * TX_PIN_CFG:
939 */
940 #define TX_PIN_CFG 0x1328
941 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
942 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
943 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
944 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
945 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
946 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
947 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
948 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
949 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
950 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
951 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
952 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
953 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
954 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
955 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
956 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
957 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
958 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
959 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
960 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
962 /*
963 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
964 */
965 #define TX_BAND_CFG 0x132c
966 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
967 #define TX_BAND_CFG_A FIELD32(0x00000002)
968 #define TX_BAND_CFG_BG FIELD32(0x00000004)
970 /*
971 * TX_SW_CFG0:
972 */
973 #define TX_SW_CFG0 0x1330
975 /*
976 * TX_SW_CFG1:
977 */
978 #define TX_SW_CFG1 0x1334
980 /*
981 * TX_SW_CFG2:
982 */
983 #define TX_SW_CFG2 0x1338
985 /*
986 * TXOP_THRES_CFG:
987 */
988 #define TXOP_THRES_CFG 0x133c
990 /*
991 * TXOP_CTRL_CFG:
992 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
993 * AC_TRUN_EN: Enable/Disable truncation for AC change
994 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
995 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
996 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
997 * RESERVED_TRUN_EN: Reserved
998 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
999 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1000 * transmissions if extension CCA is clear).
1001 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1002 * EXT_CWMIN: CwMin for extension channel backoff
1003 * 0: Disabled
1004 *
1005 */
1006 #define TXOP_CTRL_CFG 0x1340
1007 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1008 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1009 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1010 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1011 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1012 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1013 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1014 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1015 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1016 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1018 /*
1019 * TX_RTS_CFG:
1020 * RTS_THRES: unit:byte
1021 * RTS_FBK_EN: enable rts rate fallback
1022 */
1023 #define TX_RTS_CFG 0x1344
1024 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1025 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1026 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1028 /*
1029 * TX_TIMEOUT_CFG:
1030 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1031 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1032 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1033 * it is recommended that:
1034 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1035 */
1036 #define TX_TIMEOUT_CFG 0x1348
1037 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1038 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1039 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1041 /*
1042 * TX_RTY_CFG:
1043 * SHORT_RTY_LIMIT: short retry limit
1044 * LONG_RTY_LIMIT: long retry limit
1045 * LONG_RTY_THRE: Long retry threshoold
1046 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1047 * 0:expired by retry limit, 1: expired by mpdu life timer
1048 * AGG_RTY_MODE: Aggregate MPDU retry mode
1049 * 0:expired by retry limit, 1: expired by mpdu life timer
1050 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1051 */
1052 #define TX_RTY_CFG 0x134c
1053 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1054 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1055 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1056 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1057 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1058 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1060 /*
1061 * TX_LINK_CFG:
1062 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1063 * MFB_ENABLE: TX apply remote MFB 1:enable
1064 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1065 * 0: not apply remote remote unsolicit (MFS=7)
1066 * TX_MRQ_EN: MCS request TX enable
1067 * TX_RDG_EN: RDG TX enable
1068 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1069 * REMOTE_MFB: remote MCS feedback
1070 * REMOTE_MFS: remote MCS feedback sequence number
1071 */
1072 #define TX_LINK_CFG 0x1350
1073 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1074 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1075 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1076 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1077 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1078 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1079 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1080 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1082 /*
1083 * HT_FBK_CFG0:
1084 */
1085 #define HT_FBK_CFG0 0x1354
1086 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1087 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1088 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1089 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1090 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1091 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1092 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1093 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1095 /*
1096 * HT_FBK_CFG1:
1097 */
1098 #define HT_FBK_CFG1 0x1358
1099 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1100 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1101 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1102 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1103 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1104 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1105 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1106 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1108 /*
1109 * LG_FBK_CFG0:
1110 */
1111 #define LG_FBK_CFG0 0x135c
1112 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1113 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1114 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1115 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1116 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1117 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1118 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1119 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1121 /*
1122 * LG_FBK_CFG1:
1123 */
1124 #define LG_FBK_CFG1 0x1360
1125 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1126 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1127 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1128 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1130 /*
1131 * CCK_PROT_CFG: CCK Protection
1132 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1133 * PROTECT_CTRL: Protection control frame type for CCK TX
1134 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1135 * PROTECT_NAV: TXOP protection type for CCK TX
1136 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
1137 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1138 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1139 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1140 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1141 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1142 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1143 * RTS_TH_EN: RTS threshold enable on CCK TX
1144 */
1145 #define CCK_PROT_CFG 0x1364
1146 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1147 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1148 #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1149 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1150 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1151 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1152 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1153 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1154 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1155 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1157 /*
1158 * OFDM_PROT_CFG: OFDM Protection
1159 */
1160 #define OFDM_PROT_CFG 0x1368
1161 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1162 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1163 #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1164 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1165 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1166 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1167 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1168 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1169 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1170 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1172 /*
1173 * MM20_PROT_CFG: MM20 Protection
1174 */
1175 #define MM20_PROT_CFG 0x136c
1176 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1177 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1178 #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1179 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1180 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1181 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1182 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1183 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1184 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1185 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1187 /*
1188 * MM40_PROT_CFG: MM40 Protection
1189 */
1190 #define MM40_PROT_CFG 0x1370
1191 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1192 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1193 #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1194 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1195 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1196 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1197 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1198 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1199 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1200 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1202 /*
1203 * GF20_PROT_CFG: GF20 Protection
1204 */
1205 #define GF20_PROT_CFG 0x1374
1206 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1207 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1208 #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1209 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1210 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1211 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1212 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1213 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1214 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1215 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1217 /*
1218 * GF40_PROT_CFG: GF40 Protection
1219 */
1220 #define GF40_PROT_CFG 0x1378
1221 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1222 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1223 #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1224 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1225 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1226 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1227 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1228 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1229 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1230 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1232 /*
1233 * EXP_CTS_TIME:
1234 */
1235 #define EXP_CTS_TIME 0x137c
1237 /*
1238 * EXP_ACK_TIME:
1239 */
1240 #define EXP_ACK_TIME 0x1380
1242 /*
1243 * RX_FILTER_CFG: RX configuration register.
1244 */
1245 #define RX_FILTER_CFG 0x1400
1246 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1247 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1248 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1249 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1250 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1251 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1252 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1253 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1254 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1255 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1256 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1257 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1258 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1259 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1260 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1261 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1262 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1264 /*
1265 * AUTO_RSP_CFG:
1266 * AUTORESPONDER: 0: disable, 1: enable
1267 * BAC_ACK_POLICY: 0:long, 1:short preamble
1268 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1269 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1270 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1271 * DUAL_CTS_EN: Power bit value in control frame
1272 * ACK_CTS_PSM_BIT:Power bit value in control frame
1273 */
1274 #define AUTO_RSP_CFG 0x1404
1275 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1276 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1277 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1278 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1279 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1280 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1281 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1283 /*
1284 * LEGACY_BASIC_RATE:
1285 */
1286 #define LEGACY_BASIC_RATE 0x1408
1288 /*
1289 * HT_BASIC_RATE:
1290 */
1291 #define HT_BASIC_RATE 0x140c
1293 /*
1294 * HT_CTRL_CFG:
1295 */
1296 #define HT_CTRL_CFG 0x1410
1298 /*
1299 * SIFS_COST_CFG:
1300 */
1301 #define SIFS_COST_CFG 0x1414
1303 /*
1304 * RX_PARSER_CFG:
1305 * Set NAV for all received frames
1306 */
1307 #define RX_PARSER_CFG 0x1418
1309 /*
1310 * TX_SEC_CNT0:
1311 */
1312 #define TX_SEC_CNT0 0x1500
1314 /*
1315 * RX_SEC_CNT0:
1316 */
1317 #define RX_SEC_CNT0 0x1504
1319 /*
1320 * CCMP_FC_MUTE:
1321 */
1322 #define CCMP_FC_MUTE 0x1508
1324 /*
1325 * TXOP_HLDR_ADDR0:
1326 */
1327 #define TXOP_HLDR_ADDR0 0x1600
1329 /*
1330 * TXOP_HLDR_ADDR1:
1331 */
1332 #define TXOP_HLDR_ADDR1 0x1604
1334 /*
1335 * TXOP_HLDR_ET:
1336 */
1337 #define TXOP_HLDR_ET 0x1608
1339 /*
1340 * QOS_CFPOLL_RA_DW0:
1341 */
1342 #define QOS_CFPOLL_RA_DW0 0x160c
1344 /*
1345 * QOS_CFPOLL_RA_DW1:
1346 */
1347 #define QOS_CFPOLL_RA_DW1 0x1610
1349 /*
1350 * QOS_CFPOLL_QC:
1351 */
1352 #define QOS_CFPOLL_QC 0x1614
1354 /*
1355 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1356 */
1357 #define RX_STA_CNT0 0x1700
1358 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1359 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1361 /*
1362 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1363 */
1364 #define RX_STA_CNT1 0x1704
1365 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1366 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1368 /*
1369 * RX_STA_CNT2:
1370 */
1371 #define RX_STA_CNT2 0x1708
1372 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1373 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1375 /*
1376 * TX_STA_CNT0: TX Beacon count
1377 */
1378 #define TX_STA_CNT0 0x170c
1379 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1380 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1382 /*
1383 * TX_STA_CNT1: TX tx count
1384 */
1385 #define TX_STA_CNT1 0x1710
1386 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1387 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1389 /*
1390 * TX_STA_CNT2: TX tx count
1391 */
1392 #define TX_STA_CNT2 0x1714
1393 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1394 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1396 /*
1397 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1398 *
1399 * This register is implemented as FIFO with 16 entries in the HW. Each
1400 * register read fetches the next tx result. If the FIFO is full because
1401 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1402 * triggered, the hw seems to simply drop further tx results.
1403 *
1404 * VALID: 1: this tx result is valid
1405 * 0: no valid tx result -> driver should stop reading
1406 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1407 * to match a frame with its tx result (even though the PID is
1408 * only 4 bits wide).
1409 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1410 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1411 * This identification number is calculated by ((idx % 3) + 1).
1412 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1413 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1414 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1415 * WCID: The wireless client ID.
1416 * MCS: The tx rate used during the last transmission of this frame, be it
1417 * successful or not.
1418 * PHYMODE: The phymode used for the transmission.
1419 */
1420 #define TX_STA_FIFO 0x1718
1421 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1422 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1423 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1424 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1425 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1426 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1427 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1428 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1429 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1430 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1431 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1433 /*
1434 * TX_AGG_CNT: Debug counter
1435 */
1436 #define TX_AGG_CNT 0x171c
1437 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1438 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1440 /*
1441 * TX_AGG_CNT0:
1442 */
1443 #define TX_AGG_CNT0 0x1720
1444 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1445 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1447 /*
1448 * TX_AGG_CNT1:
1449 */
1450 #define TX_AGG_CNT1 0x1724
1451 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1452 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1454 /*
1455 * TX_AGG_CNT2:
1456 */
1457 #define TX_AGG_CNT2 0x1728
1458 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1459 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1461 /*
1462 * TX_AGG_CNT3:
1463 */
1464 #define TX_AGG_CNT3 0x172c
1465 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1466 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1468 /*
1469 * TX_AGG_CNT4:
1470 */
1471 #define TX_AGG_CNT4 0x1730
1472 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1473 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1475 /*
1476 * TX_AGG_CNT5:
1477 */
1478 #define TX_AGG_CNT5 0x1734
1479 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1480 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1482 /*
1483 * TX_AGG_CNT6:
1484 */
1485 #define TX_AGG_CNT6 0x1738
1486 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1487 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1489 /*
1490 * TX_AGG_CNT7:
1491 */
1492 #define TX_AGG_CNT7 0x173c
1493 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1494 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1496 /*
1497 * MPDU_DENSITY_CNT:
1498 * TX_ZERO_DEL: TX zero length delimiter count
1499 * RX_ZERO_DEL: RX zero length delimiter count
1500 */
1501 #define MPDU_DENSITY_CNT 0x1740
1502 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1503 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1505 /*
1506 * Security key table memory.
1507 *
1508 * The pairwise key table shares some memory with the beacon frame
1509 * buffers 6 and 7. That basically means that when beacon 6 & 7
1510 * are used we should only use the reduced pairwise key table which
1511 * has a maximum of 222 entries.
1512 *
1513 * ---------------------------------------------
1514 * |0x4000 | Pairwise Key | Reduced Pairwise |
1515 * | | Table | Key Table |
1516 * | | Size: 256 * 32 | Size: 222 * 32 |
1517 * |0x5BC0 | |-------------------
1518 * | | | Beacon 6 |
1519 * |0x5DC0 | |-------------------
1520 * | | | Beacon 7 |
1521 * |0x5FC0 | |-------------------
1522 * |0x5FFF | |
1523 * --------------------------
1524 *
1525 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1526 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1527 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1528 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1529 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1530 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1531 */
1532 #define MAC_WCID_BASE 0x1800
1533 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1534 #define MAC_IVEIV_TABLE_BASE 0x6000
1535 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1536 #define SHARED_KEY_TABLE_BASE 0x6c00
1537 #define SHARED_KEY_MODE_BASE 0x7000
1539 #define MAC_WCID_ENTRY(__idx) \
1540 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1541 #define PAIRWISE_KEY_ENTRY(__idx) \
1542 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1543 #define MAC_IVEIV_ENTRY(__idx) \
1544 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1545 #define MAC_WCID_ATTR_ENTRY(__idx) \
1546 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1547 #define SHARED_KEY_ENTRY(__idx) \
1548 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1549 #define SHARED_KEY_MODE_ENTRY(__idx) \
1550 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1567 /*
1568 * MAC_WCID_ATTRIBUTE:
1569 */
1570 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1571 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1572 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1573 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1574 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1575 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1576 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1577 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1579 /*
1580 * SHARED_KEY_MODE:
1581 */
1582 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1583 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1584 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1585 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1586 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1587 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1588 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1589 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1591 /*
1592 * HOST-MCU communication
1593 */
1595 /*
1596 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1597 */
1598 #define H2M_MAILBOX_CSR 0x7010
1599 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1600 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1601 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1602 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1604 /*
1605 * H2M_MAILBOX_CID:
1606 */
1607 #define H2M_MAILBOX_CID 0x7014
1608 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1609 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1610 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1611 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1613 /*
1614 * H2M_MAILBOX_STATUS:
1615 */
1616 #define H2M_MAILBOX_STATUS 0x701c
1618 /*
1619 * H2M_INT_SRC:
1620 */
1621 #define H2M_INT_SRC 0x7024
1623 /*
1624 * H2M_BBP_AGENT:
1625 */
1626 #define H2M_BBP_AGENT 0x7028
1628 /*
1629 * MCU_LEDCS: LED control for MCU Mailbox.
1630 */
1631 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1632 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1634 /*
1635 * HW_CS_CTS_BASE:
1636 * Carrier-sense CTS frame base address.
1637 * It's where mac stores carrier-sense frame for carrier-sense function.
1638 */
1639 #define HW_CS_CTS_BASE 0x7700
1641 /*
1642 * HW_DFS_CTS_BASE:
1643 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1644 */
1645 #define HW_DFS_CTS_BASE 0x7780
1647 /*
1648 * TXRX control registers - base address 0x3000
1649 */
1651 /*
1652 * TXRX_CSR1:
1653 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1654 */
1655 #define TXRX_CSR1 0x77d0
1657 /*
1658 * HW_DEBUG_SETTING_BASE:
1659 * since NULL frame won't be that long (256 byte)
1660 * We steal 16 tail bytes to save debugging settings
1661 */
1662 #define HW_DEBUG_SETTING_BASE 0x77f0
1663 #define HW_DEBUG_SETTING_BASE2 0x7770
1665 /*
1666 * HW_BEACON_BASE
1667 * In order to support maximum 8 MBSS and its maximum length
1668 * is 512 bytes for each beacon
1669 * Three section discontinue memory segments will be used.
1670 * 1. The original region for BCN 0~3
1671 * 2. Extract memory from FCE table for BCN 4~5
1672 * 3. Extract memory from Pair-wise key table for BCN 6~7
1673 * It occupied those memory of wcid 238~253 for BCN 6
1674 * and wcid 222~237 for BCN 7 (see Security key table memory
1675 * for more info).
1676 *
1677 * IMPORTANT NOTE: Not sure why legacy driver does this,
1678 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1679 */
1680 #define HW_BEACON_BASE0 0x7800
1681 #define HW_BEACON_BASE1 0x7a00
1682 #define HW_BEACON_BASE2 0x7c00
1683 #define HW_BEACON_BASE3 0x7e00
1684 #define HW_BEACON_BASE4 0x7200
1685 #define HW_BEACON_BASE5 0x7400
1686 #define HW_BEACON_BASE6 0x5dc0
1687 #define HW_BEACON_BASE7 0x5bc0
1689 #define HW_BEACON_OFFSET(__index) \
1690 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1691 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1692 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1694 /*
1695 * BBP registers.
1696 * The wordsize of the BBP is 8 bits.
1697 */
1699 /*
1700 * BBP 1: TX Antenna & Power
1701 * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
1702 * 3 - increase tx power by 6dBm
1703 */
1704 #define BBP1_TX_POWER FIELD8(0x07)
1705 #define BBP1_TX_ANTENNA FIELD8(0x18)
1707 /*
1708 * BBP 3: RX Antenna
1709 */
1710 #define BBP3_RX_ANTENNA FIELD8(0x18)
1711 #define BBP3_HT40_MINUS FIELD8(0x20)
1713 /*
1714 * BBP 4: Bandwidth
1715 */
1716 #define BBP4_TX_BF FIELD8(0x01)
1717 #define BBP4_BANDWIDTH FIELD8(0x18)
1719 /*
1720 * BBP 138: Unknown
1721 */
1722 #define BBP138_RX_ADC1 FIELD8(0x02)
1723 #define BBP138_RX_ADC2 FIELD8(0x04)
1724 #define BBP138_TX_DAC1 FIELD8(0x20)
1725 #define BBP138_TX_DAC2 FIELD8(0x40)
1727 /*
1728 * RFCSR registers
1729 * The wordsize of the RFCSR is 8 bits.
1730 */
1732 /*
1733 * RFCSR 1:
1734 */
1735 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1736 #define RFCSR1_RX0_PD FIELD8(0x04)
1737 #define RFCSR1_TX0_PD FIELD8(0x08)
1738 #define RFCSR1_RX1_PD FIELD8(0x10)
1739 #define RFCSR1_TX1_PD FIELD8(0x20)
1741 /*
1742 * RFCSR 6:
1743 */
1744 #define RFCSR6_R1 FIELD8(0x03)
1745 #define RFCSR6_R2 FIELD8(0x40)
1747 /*
1748 * RFCSR 7:
1749 */
1750 #define RFCSR7_RF_TUNING FIELD8(0x01)
1752 /*
1753 * RFCSR 12:
1754 */
1755 #define RFCSR12_TX_POWER FIELD8(0x1f)
1757 /*
1758 * RFCSR 13:
1759 */
1760 #define RFCSR13_TX_POWER FIELD8(0x1f)
1762 /*
1763 * RFCSR 15:
1764 */
1765 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1767 /*
1768 * RFCSR 17:
1769 */
1770 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1771 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1772 #define RFCSR17_R FIELD8(0x20)
1774 /*
1775 * RFCSR 20:
1776 */
1777 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1779 /*
1780 * RFCSR 21:
1781 */
1782 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1784 /*
1785 * RFCSR 22:
1786 */
1787 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1789 /*
1790 * RFCSR 23:
1791 */
1792 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1794 /*
1795 * RFCSR 27:
1796 */
1797 #define RFCSR27_R1 FIELD8(0x03)
1798 #define RFCSR27_R2 FIELD8(0x04)
1799 #define RFCSR27_R3 FIELD8(0x30)
1800 #define RFCSR27_R4 FIELD8(0x40)
1802 /*
1803 * RFCSR 30:
1804 */
1805 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1807 /*
1808 * RF registers
1809 */
1811 /*
1812 * RF 2
1813 */
1814 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1815 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1816 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1818 /*
1819 * RF 3
1820 */
1821 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1822 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1823 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1825 /*
1826 * RF 4
1827 */
1828 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1829 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1830 #define RF4_TXPOWER_A FIELD32(0x00000780)
1831 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1832 #define RF4_HT40 FIELD32(0x00200000)
1834 /*
1835 * EEPROM content.
1836 * The wordsize of the EEPROM is 16 bits.
1837 */
1839 /*
1840 * EEPROM Version
1841 */
1842 #define EEPROM_VERSION 0x0001
1843 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1844 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1846 /*
1847 * HW MAC address.
1848 */
1849 #define EEPROM_MAC_ADDR_0 0x0002
1850 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1851 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1852 #define EEPROM_MAC_ADDR_1 0x0003
1853 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1854 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1855 #define EEPROM_MAC_ADDR_2 0x0004
1856 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1857 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1859 /*
1860 * EEPROM NIC Configuration 0
1861 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1862 * TXPATH: 1: 1T, 2: 2T, 3: 3T
1863 * RF_TYPE: RFIC type
1864 */
1865 #define EEPROM_NIC_CONF0 0x001a
1866 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
1867 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
1868 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
1870 /*
1871 * EEPROM NIC Configuration 1
1872 * HW_RADIO: 0: disable, 1: enable
1873 * EXTERNAL_TX_ALC: 0: disable, 1: enable
1874 * EXTERNAL_LNA_2G: 0: disable, 1: enable
1875 * EXTERNAL_LNA_5G: 0: disable, 1: enable
1876 * CARDBUS_ACCEL: 0: enable, 1: disable
1877 * BW40M_SB_2G: 0: disable, 1: enable
1878 * BW40M_SB_5G: 0: disable, 1: enable
1879 * WPS_PBC: 0: disable, 1: enable
1880 * BW40M_2G: 0: enable, 1: disable
1881 * BW40M_5G: 0: enable, 1: disable
1882 * BROADBAND_EXT_LNA: 0: disable, 1: enable
1883 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
1884 * 10: Main antenna, 11: Aux antenna
1885 * INTERNAL_TX_ALC: 0: disable, 1: enable
1886 * BT_COEXIST: 0: disable, 1: enable
1887 * DAC_TEST: 0: disable, 1: enable
1888 */
1889 #define EEPROM_NIC_CONF1 0x001b
1890 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
1891 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
1892 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
1893 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
1894 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
1895 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
1896 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
1897 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
1898 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
1899 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
1900 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
1901 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
1902 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
1903 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
1904 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
1906 /*
1907 * EEPROM frequency
1908 */
1909 #define EEPROM_FREQ 0x001d
1910 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1911 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1912 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1914 /*
1915 * EEPROM LED
1916 * POLARITY_RDY_G: Polarity RDY_G setting.
1917 * POLARITY_RDY_A: Polarity RDY_A setting.
1918 * POLARITY_ACT: Polarity ACT setting.
1919 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1920 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1921 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1922 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1923 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1924 * LED_MODE: Led mode.
1925 */
1926 #define EEPROM_LED_AG_CONF 0x001e
1927 #define EEPROM_LED_ACT_CONF 0x001f
1928 #define EEPROM_LED_POLARITY 0x0020
1929 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1930 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1931 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1932 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1933 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1934 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1935 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1936 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1937 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1939 /*
1940 * EEPROM NIC Configuration 2
1941 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
1942 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
1943 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
1944 */
1945 #define EEPROM_NIC_CONF2 0x0021
1946 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
1947 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
1948 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
1950 /*
1951 * EEPROM LNA
1952 */
1953 #define EEPROM_LNA 0x0022
1954 #define EEPROM_LNA_BG FIELD16(0x00ff)
1955 #define EEPROM_LNA_A0 FIELD16(0xff00)
1957 /*
1958 * EEPROM RSSI BG offset
1959 */
1960 #define EEPROM_RSSI_BG 0x0023
1961 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1962 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1964 /*
1965 * EEPROM RSSI BG2 offset
1966 */
1967 #define EEPROM_RSSI_BG2 0x0024
1968 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1969 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1971 /*
1972 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1973 */
1974 #define EEPROM_TXMIXER_GAIN_BG 0x0024
1975 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
1977 /*
1978 * EEPROM RSSI A offset
1979 */
1980 #define EEPROM_RSSI_A 0x0025
1981 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1982 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1984 /*
1985 * EEPROM RSSI A2 offset
1986 */
1987 #define EEPROM_RSSI_A2 0x0026
1988 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1989 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1991 /*
1992 * EEPROM Maximum TX power values
1993 */
1994 #define EEPROM_MAX_TX_POWER 0x0027
1995 #define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff)
1996 #define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00)
1998 /*
1999 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2000 * This is delta in 40MHZ.
2001 * VALUE: Tx Power dalta value (MAX=4)
2002 * TYPE: 1: Plus the delta value, 0: minus the delta value
2003 * TXPOWER: Enable:
2004 */
2005 #define EEPROM_TXPOWER_DELTA 0x0028
2006 #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
2007 #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
2008 #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
2010 /*
2011 * EEPROM TXPOWER 802.11BG
2012 */
2013 #define EEPROM_TXPOWER_BG1 0x0029
2014 #define EEPROM_TXPOWER_BG2 0x0030
2015 #define EEPROM_TXPOWER_BG_SIZE 7
2016 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2017 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2019 /*
2020 * EEPROM TXPOWER 802.11A
2021 */
2022 #define EEPROM_TXPOWER_A1 0x003c
2023 #define EEPROM_TXPOWER_A2 0x0053
2024 #define EEPROM_TXPOWER_A_SIZE 6
2025 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2026 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2028 /*
2029 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2030 */
2031 #define EEPROM_TXPOWER_BYRATE 0x006f
2032 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2034 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2035 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2036 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2037 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2039 /*
2040 * EEPROM BBP.
2041 */
2042 #define EEPROM_BBP_START 0x0078
2043 #define EEPROM_BBP_SIZE 16
2044 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2045 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2047 /*
2048 * MCU mailbox commands.
2049 */
2050 #define MCU_SLEEP 0x30
2051 #define MCU_WAKEUP 0x31
2052 #define MCU_RADIO_OFF 0x35
2053 #define MCU_CURRENT 0x36
2054 #define MCU_LED 0x50
2055 #define MCU_LED_STRENGTH 0x51
2056 #define MCU_LED_AG_CONF 0x52
2057 #define MCU_LED_ACT_CONF 0x53
2058 #define MCU_LED_LED_POLARITY 0x54
2059 #define MCU_RADAR 0x60
2060 #define MCU_BOOT_SIGNAL 0x72
2061 #define MCU_BBP_SIGNAL 0x80
2062 #define MCU_POWER_SAVE 0x83
2064 /*
2065 * MCU mailbox tokens
2066 */
2067 #define TOKEN_WAKUP 3
2069 /*
2070 * DMA descriptor defines.
2071 */
2072 #define TXWI_DESC_SIZE (4 * sizeof(__le32))
2073 #define RXWI_DESC_SIZE (4 * sizeof(__le32))
2075 /*
2076 * TX WI structure
2077 */
2079 /*
2080 * Word0
2081 * FRAG: 1 To inform TKIP engine this is a fragment.
2082 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2083 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2084 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2085 * duplicate the frame to both channels).
2086 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2087 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2088 * aggregate consecutive frames with the same RA and QoS TID. If
2089 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2090 * directly after a frame B with AMPDU=1, frame A might still
2091 * get aggregated into the AMPDU started by frame B. So, setting
2092 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2093 * MPDU, it can still end up in an AMPDU if the previous frame
2094 * was tagged as AMPDU.
2095 */
2096 #define TXWI_W0_FRAG FIELD32(0x00000001)
2097 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2098 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2099 #define TXWI_W0_TS FIELD32(0x00000008)
2100 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2101 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2102 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2103 #define TXWI_W0_MCS FIELD32(0x007f0000)
2104 #define TXWI_W0_BW FIELD32(0x00800000)
2105 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2106 #define TXWI_W0_STBC FIELD32(0x06000000)
2107 #define TXWI_W0_IFS FIELD32(0x08000000)
2108 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2110 /*
2111 * Word1
2112 * ACK: 0: No Ack needed, 1: Ack needed
2113 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2114 * BW_WIN_SIZE: BA windows size of the recipient
2115 * WIRELESS_CLI_ID: Client ID for WCID table access
2116 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2117 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2118 * frame was processed. If multiple frames are aggregated together
2119 * (AMPDU==1) the reported tx status will always contain the packet
2120 * id of the first frame. 0: Don't report tx status for this frame.
2121 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2122 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2123 * This identification number is calculated by ((idx % 3) + 1).
2124 * The (+1) is required to prevent PACKETID to become 0.
2125 */
2126 #define TXWI_W1_ACK FIELD32(0x00000001)
2127 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2128 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2129 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2130 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2131 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2132 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2133 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2135 /*
2136 * Word2
2137 */
2138 #define TXWI_W2_IV FIELD32(0xffffffff)
2140 /*
2141 * Word3
2142 */
2143 #define TXWI_W3_EIV FIELD32(0xffffffff)
2145 /*
2146 * RX WI structure
2147 */
2149 /*
2150 * Word0
2151 */
2152 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2153 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2154 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2155 #define RXWI_W0_UDF FIELD32(0x0000e000)
2156 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2157 #define RXWI_W0_TID FIELD32(0xf0000000)
2159 /*
2160 * Word1
2161 */
2162 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2163 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2164 #define RXWI_W1_MCS FIELD32(0x007f0000)
2165 #define RXWI_W1_BW FIELD32(0x00800000)
2166 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2167 #define RXWI_W1_STBC FIELD32(0x06000000)
2168 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2170 /*
2171 * Word2
2172 */
2173 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2174 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2175 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2177 /*
2178 * Word3
2179 */
2180 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2181 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2183 /*
2184 * Macros for converting txpower from EEPROM to mac80211 value
2185 * and from mac80211 value to register value.
2186 */
2187 #define MIN_G_TXPOWER 0
2188 #define MIN_A_TXPOWER -7
2189 #define MAX_G_TXPOWER 31
2190 #define MAX_A_TXPOWER 15
2191 #define DEFAULT_TXPOWER 5
2193 #define TXPOWER_G_FROM_DEV(__txpower) \
2194 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2196 #define TXPOWER_G_TO_DEV(__txpower) \
2197 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2199 #define TXPOWER_A_FROM_DEV(__txpower) \
2200 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2202 #define TXPOWER_A_TO_DEV(__txpower) \
2203 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)