?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
KVM: x86 emulator: simplify rip relative decoding
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / x86_emulate.c
blob20b604489c3cd7d76799a7a2453b44bc9b9bd4dc
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include <linux/module.h>
32 #include <asm/kvm_x86_emulate.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65 #define MemAbs (1<<9) /* Memory operand is absolute displacement */
66 #define String (1<<10) /* String instruction (rep capable) */
67 #define Stack (1<<11) /* Stack instruction (push/pop) */
68 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70 #define GroupMask 0xff /* Group number stored in bits 0:7 */
71
72 enum {
73 Group1_80, Group1_81, Group1_82, Group1_83,
74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
75 };
76
77 static u16 opcode_table[256] = {
78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 SrcImmByte, SrcImm, 0, 0,
98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
110 /* 0x40 - 0x47 */
111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
112 /* 0x48 - 0x4F */
113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
114 /* 0x50 - 0x57 */
115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 /* 0x58 - 0x5F */
118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 /* 0x60 - 0x67 */
121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
124 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x80 - 0x87 */
134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
141 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
142 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
143 /* 0x90 - 0x97 */
144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
145 /* 0x98 - 0x9F */
146 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
147 /* 0xA0 - 0xA7 */
148 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
149 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
150 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
151 ByteOp | ImplicitOps | String, ImplicitOps | String,
152 /* 0xA8 - 0xAF */
153 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | String, ImplicitOps | String,
156 /* 0xB0 - 0xBF */
157 0, 0, 0, 0, 0, 0, 0, 0,
158 DstReg | SrcImm | Mov, 0, 0, 0, 0, 0, 0, 0,
159 /* 0xC0 - 0xC7 */
160 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
161 0, ImplicitOps | Stack, 0, 0,
162 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
163 /* 0xC8 - 0xCF */
164 0, 0, 0, 0, 0, 0, 0, 0,
165 /* 0xD0 - 0xD7 */
166 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
167 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
168 0, 0, 0, 0,
169 /* 0xD8 - 0xDF */
170 0, 0, 0, 0, 0, 0, 0, 0,
171 /* 0xE0 - 0xE7 */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xE8 - 0xEF */
174 ImplicitOps | Stack, SrcImm | ImplicitOps,
175 ImplicitOps, SrcImmByte | ImplicitOps,
176 0, 0, 0, 0,
177 /* 0xF0 - 0xF7 */
178 0, 0, 0, 0,
179 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
180 /* 0xF8 - 0xFF */
181 ImplicitOps, 0, ImplicitOps, ImplicitOps,
182 0, 0, Group | Group4, Group | Group5,
183 };
184
185 static u16 twobyte_table[256] = {
186 /* 0x00 - 0x0F */
187 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
188 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
189 /* 0x10 - 0x1F */
190 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
191 /* 0x20 - 0x2F */
192 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
193 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x30 - 0x3F */
195 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
196 /* 0x40 - 0x47 */
197 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 /* 0x48 - 0x4F */
202 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
203 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
204 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
205 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
206 /* 0x50 - 0x5F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x60 - 0x6F */
209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
210 /* 0x70 - 0x7F */
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
212 /* 0x80 - 0x8F */
213 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
214 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
215 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
216 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
217 /* 0x90 - 0x9F */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xA0 - 0xA7 */
220 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
221 /* 0xA8 - 0xAF */
222 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
223 /* 0xB0 - 0xB7 */
224 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
225 DstMem | SrcReg | ModRM | BitOp,
226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xB8 - 0xBF */
229 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
230 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
231 DstReg | SrcMem16 | ModRM | Mov,
232 /* 0xC0 - 0xCF */
233 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
234 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0xD0 - 0xDF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
237 /* 0xE0 - 0xEF */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xF0 - 0xFF */
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
241 };
242
243 static u16 group_table[] = {
244 [Group1_80*8] =
245 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
246 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
247 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
248 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
249 [Group1_81*8] =
250 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
251 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
252 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
253 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
254 [Group1_82*8] =
255 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 [Group1_83*8] =
260 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
261 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
262 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
263 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
264 [Group1A*8] =
265 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
266 [Group3_Byte*8] =
267 ByteOp | SrcImm | DstMem | ModRM, 0,
268 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
270 [Group3*8] =
271 DstMem | SrcImm | ModRM | SrcImm, 0,
272 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
273 0, 0, 0, 0,
274 [Group4*8] =
275 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
276 0, 0, 0, 0, 0, 0,
277 [Group5*8] =
278 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
279 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
280 [Group7*8] =
281 0, 0, ModRM | SrcMem, ModRM | SrcMem,
282 SrcNone | ModRM | DstMem | Mov, 0,
283 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
284 };
285
286 static u16 group2_table[] = {
287 [Group7*8] =
288 SrcNone | ModRM, 0, 0, 0,
289 SrcNone | ModRM | DstMem | Mov, 0,
290 SrcMem16 | ModRM | Mov, 0,
291 };
292
293 /* EFLAGS bit definitions. */
294 #define EFLG_OF (1<<11)
295 #define EFLG_DF (1<<10)
296 #define EFLG_SF (1<<7)
297 #define EFLG_ZF (1<<6)
298 #define EFLG_AF (1<<4)
299 #define EFLG_PF (1<<2)
300 #define EFLG_CF (1<<0)
301
302 /*
303 * Instruction emulation:
304 * Most instructions are emulated directly via a fragment of inline assembly
305 * code. This allows us to save/restore EFLAGS and thus very easily pick up
306 * any modified flags.
307 */
308
309 #if defined(CONFIG_X86_64)
310 #define _LO32 "k" /* force 32-bit operand */
311 #define _STK "%%rsp" /* stack pointer */
312 #elif defined(__i386__)
313 #define _LO32 "" /* force 32-bit operand */
314 #define _STK "%%esp" /* stack pointer */
315 #endif
316
317 /*
318 * These EFLAGS bits are restored from saved value during emulation, and
319 * any changes are written back to the saved value after emulation.
320 */
321 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
322
323 /* Before executing instruction: restore necessary bits in EFLAGS. */
324 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
325 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
326 "movl %"_sav",%"_LO32 _tmp"; " \
327 "push %"_tmp"; " \
328 "push %"_tmp"; " \
329 "movl %"_msk",%"_LO32 _tmp"; " \
330 "andl %"_LO32 _tmp",("_STK"); " \
331 "pushf; " \
332 "notl %"_LO32 _tmp"; " \
333 "andl %"_LO32 _tmp",("_STK"); " \
334 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
335 "pop %"_tmp"; " \
336 "orl %"_LO32 _tmp",("_STK"); " \
337 "popf; " \
338 "pop %"_sav"; "
339
340 /* After executing instruction: write-back necessary bits in EFLAGS. */
341 #define _POST_EFLAGS(_sav, _msk, _tmp) \
342 /* _sav |= EFLAGS & _msk; */ \
343 "pushf; " \
344 "pop %"_tmp"; " \
345 "andl %"_msk",%"_LO32 _tmp"; " \
346 "orl %"_LO32 _tmp",%"_sav"; "
347
348 /* Raw emulation: instruction has two explicit operands. */
349 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
350 do { \
351 unsigned long _tmp; \
352 \
353 switch ((_dst).bytes) { \
354 case 2: \
355 __asm__ __volatile__ ( \
356 _PRE_EFLAGS("0", "4", "2") \
357 _op"w %"_wx"3,%1; " \
358 _POST_EFLAGS("0", "4", "2") \
359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
361 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
362 break; \
363 case 4: \
364 __asm__ __volatile__ ( \
365 _PRE_EFLAGS("0", "4", "2") \
366 _op"l %"_lx"3,%1; " \
367 _POST_EFLAGS("0", "4", "2") \
368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
370 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
371 break; \
372 case 8: \
373 __emulate_2op_8byte(_op, _src, _dst, \
374 _eflags, _qx, _qy); \
375 break; \
376 } \
377 } while (0)
378
379 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
380 do { \
381 unsigned long __tmp; \
382 switch ((_dst).bytes) { \
383 case 1: \
384 __asm__ __volatile__ ( \
385 _PRE_EFLAGS("0", "4", "2") \
386 _op"b %"_bx"3,%1; " \
387 _POST_EFLAGS("0", "4", "2") \
388 : "=m" (_eflags), "=m" ((_dst).val), \
389 "=&r" (__tmp) \
390 : _by ((_src).val), "i" (EFLAGS_MASK)); \
391 break; \
392 default: \
393 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
394 _wx, _wy, _lx, _ly, _qx, _qy); \
395 break; \
396 } \
397 } while (0)
398
399 /* Source operand is byte-sized and may be restricted to just %cl. */
400 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
401 __emulate_2op(_op, _src, _dst, _eflags, \
402 "b", "c", "b", "c", "b", "c", "b", "c")
403
404 /* Source operand is byte, word, long or quad sized. */
405 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
406 __emulate_2op(_op, _src, _dst, _eflags, \
407 "b", "q", "w", "r", _LO32, "r", "", "r")
408
409 /* Source operand is word, long or quad sized. */
410 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
411 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
412 "w", "r", _LO32, "r", "", "r")
413
414 /* Instruction has only one explicit operand (no source operand). */
415 #define emulate_1op(_op, _dst, _eflags) \
416 do { \
417 unsigned long _tmp; \
418 \
419 switch ((_dst).bytes) { \
420 case 1: \
421 __asm__ __volatile__ ( \
422 _PRE_EFLAGS("0", "3", "2") \
423 _op"b %1; " \
424 _POST_EFLAGS("0", "3", "2") \
425 : "=m" (_eflags), "=m" ((_dst).val), \
426 "=&r" (_tmp) \
427 : "i" (EFLAGS_MASK)); \
428 break; \
429 case 2: \
430 __asm__ __volatile__ ( \
431 _PRE_EFLAGS("0", "3", "2") \
432 _op"w %1; " \
433 _POST_EFLAGS("0", "3", "2") \
434 : "=m" (_eflags), "=m" ((_dst).val), \
435 "=&r" (_tmp) \
436 : "i" (EFLAGS_MASK)); \
437 break; \
438 case 4: \
439 __asm__ __volatile__ ( \
440 _PRE_EFLAGS("0", "3", "2") \
441 _op"l %1; " \
442 _POST_EFLAGS("0", "3", "2") \
443 : "=m" (_eflags), "=m" ((_dst).val), \
444 "=&r" (_tmp) \
445 : "i" (EFLAGS_MASK)); \
446 break; \
447 case 8: \
448 __emulate_1op_8byte(_op, _dst, _eflags); \
449 break; \
450 } \
451 } while (0)
452
453 /* Emulate an instruction with quadword operands (x86/64 only). */
454 #if defined(CONFIG_X86_64)
455 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
456 do { \
457 __asm__ __volatile__ ( \
458 _PRE_EFLAGS("0", "4", "2") \
459 _op"q %"_qx"3,%1; " \
460 _POST_EFLAGS("0", "4", "2") \
461 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
462 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
463 } while (0)
464
465 #define __emulate_1op_8byte(_op, _dst, _eflags) \
466 do { \
467 __asm__ __volatile__ ( \
468 _PRE_EFLAGS("0", "3", "2") \
469 _op"q %1; " \
470 _POST_EFLAGS("0", "3", "2") \
471 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
472 : "i" (EFLAGS_MASK)); \
473 } while (0)
474
475 #elif defined(__i386__)
476 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
477 #define __emulate_1op_8byte(_op, _dst, _eflags)
478 #endif /* __i386__ */
479
480 /* Fetch next part of the instruction being emulated. */
481 #define insn_fetch(_type, _size, _eip) \
482 ({ unsigned long _x; \
483 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
484 if (rc != 0) \
485 goto done; \
486 (_eip) += (_size); \
487 (_type)_x; \
488 })
489
490 static inline unsigned long ad_mask(struct decode_cache *c)
491 {
492 return (1UL << (c->ad_bytes << 3)) - 1;
493 }
494
495 /* Access/update address held in a register, based on addressing mode. */
496 static inline unsigned long
497 address_mask(struct decode_cache *c, unsigned long reg)
498 {
499 if (c->ad_bytes == sizeof(unsigned long))
500 return reg;
501 else
502 return reg & ad_mask(c);
503 }
504
505 static inline unsigned long
506 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
507 {
508 return base + address_mask(c, reg);
509 }
510
511 static inline void
512 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
513 {
514 if (c->ad_bytes == sizeof(unsigned long))
515 *reg += inc;
516 else
517 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
518 }
519
520 static inline void jmp_rel(struct decode_cache *c, int rel)
521 {
522 register_address_increment(c, &c->eip, rel);
523 }
524
525 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
526 struct x86_emulate_ops *ops,
527 unsigned long linear, u8 *dest)
528 {
529 struct fetch_cache *fc = &ctxt->decode.fetch;
530 int rc;
531 int size;
532
533 if (linear < fc->start || linear >= fc->end) {
534 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
535 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
536 if (rc)
537 return rc;
538 fc->start = linear;
539 fc->end = linear + size;
540 }
541 *dest = fc->data[linear - fc->start];
542 return 0;
543 }
544
545 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
546 struct x86_emulate_ops *ops,
547 unsigned long eip, void *dest, unsigned size)
548 {
549 int rc = 0;
550
551 eip += ctxt->cs_base;
552 while (size--) {
553 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
554 if (rc)
555 return rc;
556 }
557 return 0;
558 }
559
560 /*
561 * Given the 'reg' portion of a ModRM byte, and a register block, return a
562 * pointer into the block that addresses the relevant register.
563 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
564 */
565 static void *decode_register(u8 modrm_reg, unsigned long *regs,
566 int highbyte_regs)
567 {
568 void *p;
569
570 p = &regs[modrm_reg];
571 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
572 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
573 return p;
574 }
575
576 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
577 struct x86_emulate_ops *ops,
578 void *ptr,
579 u16 *size, unsigned long *address, int op_bytes)
580 {
581 int rc;
582
583 if (op_bytes == 2)
584 op_bytes = 3;
585 *address = 0;
586 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
587 ctxt->vcpu);
588 if (rc)
589 return rc;
590 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
591 ctxt->vcpu);
592 return rc;
593 }
594
595 static int test_cc(unsigned int condition, unsigned int flags)
596 {
597 int rc = 0;
598
599 switch ((condition & 15) >> 1) {
600 case 0: /* o */
601 rc |= (flags & EFLG_OF);
602 break;
603 case 1: /* b/c/nae */
604 rc |= (flags & EFLG_CF);
605 break;
606 case 2: /* z/e */
607 rc |= (flags & EFLG_ZF);
608 break;
609 case 3: /* be/na */
610 rc |= (flags & (EFLG_CF|EFLG_ZF));
611 break;
612 case 4: /* s */
613 rc |= (flags & EFLG_SF);
614 break;
615 case 5: /* p/pe */
616 rc |= (flags & EFLG_PF);
617 break;
618 case 7: /* le/ng */
619 rc |= (flags & EFLG_ZF);
620 /* fall through */
621 case 6: /* l/nge */
622 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
623 break;
624 }
625
626 /* Odd condition identifiers (lsb == 1) have inverted sense. */
627 return (!!rc ^ (condition & 1));
628 }
629
630 static void decode_register_operand(struct operand *op,
631 struct decode_cache *c,
632 int inhibit_bytereg)
633 {
634 unsigned reg = c->modrm_reg;
635 int highbyte_regs = c->rex_prefix == 0;
636
637 if (!(c->d & ModRM))
638 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
639 op->type = OP_REG;
640 if ((c->d & ByteOp) && !inhibit_bytereg) {
641 op->ptr = decode_register(reg, c->regs, highbyte_regs);
642 op->val = *(u8 *)op->ptr;
643 op->bytes = 1;
644 } else {
645 op->ptr = decode_register(reg, c->regs, 0);
646 op->bytes = c->op_bytes;
647 switch (op->bytes) {
648 case 2:
649 op->val = *(u16 *)op->ptr;
650 break;
651 case 4:
652 op->val = *(u32 *)op->ptr;
653 break;
654 case 8:
655 op->val = *(u64 *) op->ptr;
656 break;
657 }
658 }
659 op->orig_val = op->val;
660 }
661
662 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
663 struct x86_emulate_ops *ops)
664 {
665 struct decode_cache *c = &ctxt->decode;
666 u8 sib;
667 int index_reg = 0, base_reg = 0, scale;
668 int rc = 0;
669
670 if (c->rex_prefix) {
671 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
672 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
673 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
674 }
675
676 c->modrm = insn_fetch(u8, 1, c->eip);
677 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
678 c->modrm_reg |= (c->modrm & 0x38) >> 3;
679 c->modrm_rm |= (c->modrm & 0x07);
680 c->modrm_ea = 0;
681 c->use_modrm_ea = 1;
682
683 if (c->modrm_mod == 3) {
684 c->modrm_ptr = decode_register(c->modrm_rm,
685 c->regs, c->d & ByteOp);
686 c->modrm_val = *(unsigned long *)c->modrm_ptr;
687 return rc;
688 }
689
690 if (c->ad_bytes == 2) {
691 unsigned bx = c->regs[VCPU_REGS_RBX];
692 unsigned bp = c->regs[VCPU_REGS_RBP];
693 unsigned si = c->regs[VCPU_REGS_RSI];
694 unsigned di = c->regs[VCPU_REGS_RDI];
695
696 /* 16-bit ModR/M decode. */
697 switch (c->modrm_mod) {
698 case 0:
699 if (c->modrm_rm == 6)
700 c->modrm_ea += insn_fetch(u16, 2, c->eip);
701 break;
702 case 1:
703 c->modrm_ea += insn_fetch(s8, 1, c->eip);
704 break;
705 case 2:
706 c->modrm_ea += insn_fetch(u16, 2, c->eip);
707 break;
708 }
709 switch (c->modrm_rm) {
710 case 0:
711 c->modrm_ea += bx + si;
712 break;
713 case 1:
714 c->modrm_ea += bx + di;
715 break;
716 case 2:
717 c->modrm_ea += bp + si;
718 break;
719 case 3:
720 c->modrm_ea += bp + di;
721 break;
722 case 4:
723 c->modrm_ea += si;
724 break;
725 case 5:
726 c->modrm_ea += di;
727 break;
728 case 6:
729 if (c->modrm_mod != 0)
730 c->modrm_ea += bp;
731 break;
732 case 7:
733 c->modrm_ea += bx;
734 break;
735 }
736 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
737 (c->modrm_rm == 6 && c->modrm_mod != 0))
738 if (!c->override_base)
739 c->override_base = &ctxt->ss_base;
740 c->modrm_ea = (u16)c->modrm_ea;
741 } else {
742 /* 32/64-bit ModR/M decode. */
743 if ((c->modrm_rm & 7) == 4) {
744 sib = insn_fetch(u8, 1, c->eip);
745 index_reg |= (sib >> 3) & 7;
746 base_reg |= sib & 7;
747 scale = sib >> 6;
748
749 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
750 c->modrm_ea += insn_fetch(s32, 4, c->eip);
751 else
752 c->modrm_ea += c->regs[base_reg];
753 if (index_reg != 4)
754 c->modrm_ea += c->regs[index_reg] << scale;
755 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
756 if (ctxt->mode == X86EMUL_MODE_PROT64)
757 c->rip_relative = 1;
758 } else
759 c->modrm_ea += c->regs[c->modrm_rm];
760 switch (c->modrm_mod) {
761 case 0:
762 if (c->modrm_rm == 5)
763 c->modrm_ea += insn_fetch(s32, 4, c->eip);
764 break;
765 case 1:
766 c->modrm_ea += insn_fetch(s8, 1, c->eip);
767 break;
768 case 2:
769 c->modrm_ea += insn_fetch(s32, 4, c->eip);
770 break;
771 }
772 }
773 done:
774 return rc;
775 }
776
777 static int decode_abs(struct x86_emulate_ctxt *ctxt,
778 struct x86_emulate_ops *ops)
779 {
780 struct decode_cache *c = &ctxt->decode;
781 int rc = 0;
782
783 switch (c->ad_bytes) {
784 case 2:
785 c->modrm_ea = insn_fetch(u16, 2, c->eip);
786 break;
787 case 4:
788 c->modrm_ea = insn_fetch(u32, 4, c->eip);
789 break;
790 case 8:
791 c->modrm_ea = insn_fetch(u64, 8, c->eip);
792 break;
793 }
794 done:
795 return rc;
796 }
797
798 int
799 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
800 {
801 struct decode_cache *c = &ctxt->decode;
802 int rc = 0;
803 int mode = ctxt->mode;
804 int def_op_bytes, def_ad_bytes, group;
805
806 /* Shadow copy of register state. Committed on successful emulation. */
807
808 memset(c, 0, sizeof(struct decode_cache));
809 c->eip = ctxt->vcpu->arch.rip;
810 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
811
812 switch (mode) {
813 case X86EMUL_MODE_REAL:
814 case X86EMUL_MODE_PROT16:
815 def_op_bytes = def_ad_bytes = 2;
816 break;
817 case X86EMUL_MODE_PROT32:
818 def_op_bytes = def_ad_bytes = 4;
819 break;
820 #ifdef CONFIG_X86_64
821 case X86EMUL_MODE_PROT64:
822 def_op_bytes = 4;
823 def_ad_bytes = 8;
824 break;
825 #endif
826 default:
827 return -1;
828 }
829
830 c->op_bytes = def_op_bytes;
831 c->ad_bytes = def_ad_bytes;
832
833 /* Legacy prefixes. */
834 for (;;) {
835 switch (c->b = insn_fetch(u8, 1, c->eip)) {
836 case 0x66: /* operand-size override */
837 /* switch between 2/4 bytes */
838 c->op_bytes = def_op_bytes ^ 6;
839 break;
840 case 0x67: /* address-size override */
841 if (mode == X86EMUL_MODE_PROT64)
842 /* switch between 4/8 bytes */
843 c->ad_bytes = def_ad_bytes ^ 12;
844 else
845 /* switch between 2/4 bytes */
846 c->ad_bytes = def_ad_bytes ^ 6;
847 break;
848 case 0x2e: /* CS override */
849 c->override_base = &ctxt->cs_base;
850 break;
851 case 0x3e: /* DS override */
852 c->override_base = &ctxt->ds_base;
853 break;
854 case 0x26: /* ES override */
855 c->override_base = &ctxt->es_base;
856 break;
857 case 0x64: /* FS override */
858 c->override_base = &ctxt->fs_base;
859 break;
860 case 0x65: /* GS override */
861 c->override_base = &ctxt->gs_base;
862 break;
863 case 0x36: /* SS override */
864 c->override_base = &ctxt->ss_base;
865 break;
866 case 0x40 ... 0x4f: /* REX */
867 if (mode != X86EMUL_MODE_PROT64)
868 goto done_prefixes;
869 c->rex_prefix = c->b;
870 continue;
871 case 0xf0: /* LOCK */
872 c->lock_prefix = 1;
873 break;
874 case 0xf2: /* REPNE/REPNZ */
875 c->rep_prefix = REPNE_PREFIX;
876 break;
877 case 0xf3: /* REP/REPE/REPZ */
878 c->rep_prefix = REPE_PREFIX;
879 break;
880 default:
881 goto done_prefixes;
882 }
883
884 /* Any legacy prefix after a REX prefix nullifies its effect. */
885
886 c->rex_prefix = 0;
887 }
888
889 done_prefixes:
890
891 /* REX prefix. */
892 if (c->rex_prefix)
893 if (c->rex_prefix & 8)
894 c->op_bytes = 8; /* REX.W */
895
896 /* Opcode byte(s). */
897 c->d = opcode_table[c->b];
898 if (c->d == 0) {
899 /* Two-byte opcode? */
900 if (c->b == 0x0f) {
901 c->twobyte = 1;
902 c->b = insn_fetch(u8, 1, c->eip);
903 c->d = twobyte_table[c->b];
904 }
905 }
906
907 if (c->d & Group) {
908 group = c->d & GroupMask;
909 c->modrm = insn_fetch(u8, 1, c->eip);
910 --c->eip;
911
912 group = (group << 3) + ((c->modrm >> 3) & 7);
913 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
914 c->d = group2_table[group];
915 else
916 c->d = group_table[group];
917 }
918
919 /* Unrecognised? */
920 if (c->d == 0) {
921 DPRINTF("Cannot emulate %02x\n", c->b);
922 return -1;
923 }
924
925 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
926 c->op_bytes = 8;
927
928 /* ModRM and SIB bytes. */
929 if (c->d & ModRM)
930 rc = decode_modrm(ctxt, ops);
931 else if (c->d & MemAbs)
932 rc = decode_abs(ctxt, ops);
933 if (rc)
934 goto done;
935
936 if (!c->override_base)
937 c->override_base = &ctxt->ds_base;
938 if (mode == X86EMUL_MODE_PROT64 &&
939 c->override_base != &ctxt->fs_base &&
940 c->override_base != &ctxt->gs_base)
941 c->override_base = NULL;
942
943 if (c->override_base)
944 c->modrm_ea += *c->override_base;
945
946 if (c->ad_bytes != 8)
947 c->modrm_ea = (u32)c->modrm_ea;
948 /*
949 * Decode and fetch the source operand: register, memory
950 * or immediate.
951 */
952 switch (c->d & SrcMask) {
953 case SrcNone:
954 break;
955 case SrcReg:
956 decode_register_operand(&c->src, c, 0);
957 break;
958 case SrcMem16:
959 c->src.bytes = 2;
960 goto srcmem_common;
961 case SrcMem32:
962 c->src.bytes = 4;
963 goto srcmem_common;
964 case SrcMem:
965 c->src.bytes = (c->d & ByteOp) ? 1 :
966 c->op_bytes;
967 /* Don't fetch the address for invlpg: it could be unmapped. */
968 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
969 break;
970 srcmem_common:
971 /*
972 * For instructions with a ModR/M byte, switch to register
973 * access if Mod = 3.
974 */
975 if ((c->d & ModRM) && c->modrm_mod == 3) {
976 c->src.type = OP_REG;
977 c->src.val = c->modrm_val;
978 c->src.ptr = c->modrm_ptr;
979 break;
980 }
981 c->src.type = OP_MEM;
982 break;
983 case SrcImm:
984 c->src.type = OP_IMM;
985 c->src.ptr = (unsigned long *)c->eip;
986 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
987 if (c->src.bytes == 8)
988 c->src.bytes = 4;
989 /* NB. Immediates are sign-extended as necessary. */
990 switch (c->src.bytes) {
991 case 1:
992 c->src.val = insn_fetch(s8, 1, c->eip);
993 break;
994 case 2:
995 c->src.val = insn_fetch(s16, 2, c->eip);
996 break;
997 case 4:
998 c->src.val = insn_fetch(s32, 4, c->eip);
999 break;
1000 }
1001 break;
1002 case SrcImmByte:
1003 c->src.type = OP_IMM;
1004 c->src.ptr = (unsigned long *)c->eip;
1005 c->src.bytes = 1;
1006 c->src.val = insn_fetch(s8, 1, c->eip);
1007 break;
1008 }
1009
1010 /* Decode and fetch the destination operand: register or memory. */
1011 switch (c->d & DstMask) {
1012 case ImplicitOps:
1013 /* Special instructions do their own operand decoding. */
1014 return 0;
1015 case DstReg:
1016 decode_register_operand(&c->dst, c,
1017 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1018 break;
1019 case DstMem:
1020 if ((c->d & ModRM) && c->modrm_mod == 3) {
1021 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1022 c->dst.type = OP_REG;
1023 c->dst.val = c->dst.orig_val = c->modrm_val;
1024 c->dst.ptr = c->modrm_ptr;
1025 break;
1026 }
1027 c->dst.type = OP_MEM;
1028 break;
1029 }
1030
1031 if (c->rip_relative)
1032 c->modrm_ea += c->eip;
1033
1034 done:
1035 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1036 }
1037
1038 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1039 {
1040 struct decode_cache *c = &ctxt->decode;
1041
1042 c->dst.type = OP_MEM;
1043 c->dst.bytes = c->op_bytes;
1044 c->dst.val = c->src.val;
1045 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1046 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
1047 c->regs[VCPU_REGS_RSP]);
1048 }
1049
1050 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1051 struct x86_emulate_ops *ops)
1052 {
1053 struct decode_cache *c = &ctxt->decode;
1054 int rc;
1055
1056 rc = ops->read_std(register_address(c, ctxt->ss_base,
1057 c->regs[VCPU_REGS_RSP]),
1058 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1059 if (rc != 0)
1060 return rc;
1061
1062 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
1063
1064 return 0;
1065 }
1066
1067 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1068 {
1069 struct decode_cache *c = &ctxt->decode;
1070 switch (c->modrm_reg) {
1071 case 0: /* rol */
1072 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1073 break;
1074 case 1: /* ror */
1075 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1076 break;
1077 case 2: /* rcl */
1078 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1079 break;
1080 case 3: /* rcr */
1081 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1082 break;
1083 case 4: /* sal/shl */
1084 case 6: /* sal/shl */
1085 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1086 break;
1087 case 5: /* shr */
1088 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1089 break;
1090 case 7: /* sar */
1091 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1092 break;
1093 }
1094 }
1095
1096 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1097 struct x86_emulate_ops *ops)
1098 {
1099 struct decode_cache *c = &ctxt->decode;
1100 int rc = 0;
1101
1102 switch (c->modrm_reg) {
1103 case 0 ... 1: /* test */
1104 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1105 break;
1106 case 2: /* not */
1107 c->dst.val = ~c->dst.val;
1108 break;
1109 case 3: /* neg */
1110 emulate_1op("neg", c->dst, ctxt->eflags);
1111 break;
1112 default:
1113 DPRINTF("Cannot emulate %02x\n", c->b);
1114 rc = X86EMUL_UNHANDLEABLE;
1115 break;
1116 }
1117 return rc;
1118 }
1119
1120 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1121 struct x86_emulate_ops *ops)
1122 {
1123 struct decode_cache *c = &ctxt->decode;
1124
1125 switch (c->modrm_reg) {
1126 case 0: /* inc */
1127 emulate_1op("inc", c->dst, ctxt->eflags);
1128 break;
1129 case 1: /* dec */
1130 emulate_1op("dec", c->dst, ctxt->eflags);
1131 break;
1132 case 4: /* jmp abs */
1133 c->eip = c->src.val;
1134 break;
1135 case 6: /* push */
1136 emulate_push(ctxt);
1137 break;
1138 }
1139 return 0;
1140 }
1141
1142 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1143 struct x86_emulate_ops *ops,
1144 unsigned long memop)
1145 {
1146 struct decode_cache *c = &ctxt->decode;
1147 u64 old, new;
1148 int rc;
1149
1150 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1151 if (rc != 0)
1152 return rc;
1153
1154 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1155 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1156
1157 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1158 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1159 ctxt->eflags &= ~EFLG_ZF;
1160
1161 } else {
1162 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1163 (u32) c->regs[VCPU_REGS_RBX];
1164
1165 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1166 if (rc != 0)
1167 return rc;
1168 ctxt->eflags |= EFLG_ZF;
1169 }
1170 return 0;
1171 }
1172
1173 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1174 struct x86_emulate_ops *ops)
1175 {
1176 int rc;
1177 struct decode_cache *c = &ctxt->decode;
1178
1179 switch (c->dst.type) {
1180 case OP_REG:
1181 /* The 4-byte case *is* correct:
1182 * in 64-bit mode we zero-extend.
1183 */
1184 switch (c->dst.bytes) {
1185 case 1:
1186 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1187 break;
1188 case 2:
1189 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1190 break;
1191 case 4:
1192 *c->dst.ptr = (u32)c->dst.val;
1193 break; /* 64b: zero-ext */
1194 case 8:
1195 *c->dst.ptr = c->dst.val;
1196 break;
1197 }
1198 break;
1199 case OP_MEM:
1200 if (c->lock_prefix)
1201 rc = ops->cmpxchg_emulated(
1202 (unsigned long)c->dst.ptr,
1203 &c->dst.orig_val,
1204 &c->dst.val,
1205 c->dst.bytes,
1206 ctxt->vcpu);
1207 else
1208 rc = ops->write_emulated(
1209 (unsigned long)c->dst.ptr,
1210 &c->dst.val,
1211 c->dst.bytes,
1212 ctxt->vcpu);
1213 if (rc != 0)
1214 return rc;
1215 break;
1216 case OP_NONE:
1217 /* no writeback */
1218 break;
1219 default:
1220 break;
1221 }
1222 return 0;
1223 }
1224
1225 int
1226 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1227 {
1228 unsigned long memop = 0;
1229 u64 msr_data;
1230 unsigned long saved_eip = 0;
1231 struct decode_cache *c = &ctxt->decode;
1232 int rc = 0;
1233
1234 /* Shadow copy of register state. Committed on successful emulation.
1235 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1236 * modify them.
1237 */
1238
1239 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1240 saved_eip = c->eip;
1241
1242 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1243 memop = c->modrm_ea;
1244
1245 if (c->rep_prefix && (c->d & String)) {
1246 /* All REP prefixes have the same first termination condition */
1247 if (c->regs[VCPU_REGS_RCX] == 0) {
1248 ctxt->vcpu->arch.rip = c->eip;
1249 goto done;
1250 }
1251 /* The second termination condition only applies for REPE
1252 * and REPNE. Test if the repeat string operation prefix is
1253 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1254 * corresponding termination condition according to:
1255 * - if REPE/REPZ and ZF = 0 then done
1256 * - if REPNE/REPNZ and ZF = 1 then done
1257 */
1258 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1259 (c->b == 0xae) || (c->b == 0xaf)) {
1260 if ((c->rep_prefix == REPE_PREFIX) &&
1261 ((ctxt->eflags & EFLG_ZF) == 0)) {
1262 ctxt->vcpu->arch.rip = c->eip;
1263 goto done;
1264 }
1265 if ((c->rep_prefix == REPNE_PREFIX) &&
1266 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1267 ctxt->vcpu->arch.rip = c->eip;
1268 goto done;
1269 }
1270 }
1271 c->regs[VCPU_REGS_RCX]--;
1272 c->eip = ctxt->vcpu->arch.rip;
1273 }
1274
1275 if (c->src.type == OP_MEM) {
1276 c->src.ptr = (unsigned long *)memop;
1277 c->src.val = 0;
1278 rc = ops->read_emulated((unsigned long)c->src.ptr,
1279 &c->src.val,
1280 c->src.bytes,
1281 ctxt->vcpu);
1282 if (rc != 0)
1283 goto done;
1284 c->src.orig_val = c->src.val;
1285 }
1286
1287 if ((c->d & DstMask) == ImplicitOps)
1288 goto special_insn;
1289
1290
1291 if (c->dst.type == OP_MEM) {
1292 c->dst.ptr = (unsigned long *)memop;
1293 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1294 c->dst.val = 0;
1295 if (c->d & BitOp) {
1296 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1297
1298 c->dst.ptr = (void *)c->dst.ptr +
1299 (c->src.val & mask) / 8;
1300 }
1301 if (!(c->d & Mov) &&
1302 /* optimisation - avoid slow emulated read */
1303 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1304 &c->dst.val,
1305 c->dst.bytes, ctxt->vcpu)) != 0))
1306 goto done;
1307 }
1308 c->dst.orig_val = c->dst.val;
1309
1310 special_insn:
1311
1312 if (c->twobyte)
1313 goto twobyte_insn;
1314
1315 switch (c->b) {
1316 case 0x00 ... 0x05:
1317 add: /* add */
1318 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1319 break;
1320 case 0x08 ... 0x0d:
1321 or: /* or */
1322 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1323 break;
1324 case 0x10 ... 0x15:
1325 adc: /* adc */
1326 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1327 break;
1328 case 0x18 ... 0x1d:
1329 sbb: /* sbb */
1330 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1331 break;
1332 case 0x20 ... 0x23:
1333 and: /* and */
1334 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1335 break;
1336 case 0x24: /* and al imm8 */
1337 c->dst.type = OP_REG;
1338 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1339 c->dst.val = *(u8 *)c->dst.ptr;
1340 c->dst.bytes = 1;
1341 c->dst.orig_val = c->dst.val;
1342 goto and;
1343 case 0x25: /* and ax imm16, or eax imm32 */
1344 c->dst.type = OP_REG;
1345 c->dst.bytes = c->op_bytes;
1346 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1347 if (c->op_bytes == 2)
1348 c->dst.val = *(u16 *)c->dst.ptr;
1349 else
1350 c->dst.val = *(u32 *)c->dst.ptr;
1351 c->dst.orig_val = c->dst.val;
1352 goto and;
1353 case 0x28 ... 0x2d:
1354 sub: /* sub */
1355 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1356 break;
1357 case 0x30 ... 0x35:
1358 xor: /* xor */
1359 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1360 break;
1361 case 0x38 ... 0x3d:
1362 cmp: /* cmp */
1363 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1364 break;
1365 case 0x40 ... 0x47: /* inc r16/r32 */
1366 emulate_1op("inc", c->dst, ctxt->eflags);
1367 break;
1368 case 0x48 ... 0x4f: /* dec r16/r32 */
1369 emulate_1op("dec", c->dst, ctxt->eflags);
1370 break;
1371 case 0x50 ... 0x57: /* push reg */
1372 c->dst.type = OP_MEM;
1373 c->dst.bytes = c->op_bytes;
1374 c->dst.val = c->src.val;
1375 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1376 -c->op_bytes);
1377 c->dst.ptr = (void *) register_address(
1378 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1379 break;
1380 case 0x58 ... 0x5f: /* pop reg */
1381 pop_instruction:
1382 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
1383 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1384 c->op_bytes, ctxt->vcpu)) != 0)
1385 goto done;
1386
1387 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1388 c->op_bytes);
1389 c->dst.type = OP_NONE; /* Disable writeback. */
1390 break;
1391 case 0x63: /* movsxd */
1392 if (ctxt->mode != X86EMUL_MODE_PROT64)
1393 goto cannot_emulate;
1394 c->dst.val = (s32) c->src.val;
1395 break;
1396 case 0x68: /* push imm */
1397 case 0x6a: /* push imm8 */
1398 emulate_push(ctxt);
1399 break;
1400 case 0x6c: /* insb */
1401 case 0x6d: /* insw/insd */
1402 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1403 1,
1404 (c->d & ByteOp) ? 1 : c->op_bytes,
1405 c->rep_prefix ?
1406 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1407 (ctxt->eflags & EFLG_DF),
1408 register_address(c, ctxt->es_base,
1409 c->regs[VCPU_REGS_RDI]),
1410 c->rep_prefix,
1411 c->regs[VCPU_REGS_RDX]) == 0) {
1412 c->eip = saved_eip;
1413 return -1;
1414 }
1415 return 0;
1416 case 0x6e: /* outsb */
1417 case 0x6f: /* outsw/outsd */
1418 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1419 0,
1420 (c->d & ByteOp) ? 1 : c->op_bytes,
1421 c->rep_prefix ?
1422 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1423 (ctxt->eflags & EFLG_DF),
1424 register_address(c, c->override_base ?
1425 *c->override_base :
1426 ctxt->ds_base,
1427 c->regs[VCPU_REGS_RSI]),
1428 c->rep_prefix,
1429 c->regs[VCPU_REGS_RDX]) == 0) {
1430 c->eip = saved_eip;
1431 return -1;
1432 }
1433 return 0;
1434 case 0x70 ... 0x7f: /* jcc (short) */ {
1435 int rel = insn_fetch(s8, 1, c->eip);
1436
1437 if (test_cc(c->b, ctxt->eflags))
1438 jmp_rel(c, rel);
1439 break;
1440 }
1441 case 0x80 ... 0x83: /* Grp1 */
1442 switch (c->modrm_reg) {
1443 case 0:
1444 goto add;
1445 case 1:
1446 goto or;
1447 case 2:
1448 goto adc;
1449 case 3:
1450 goto sbb;
1451 case 4:
1452 goto and;
1453 case 5:
1454 goto sub;
1455 case 6:
1456 goto xor;
1457 case 7:
1458 goto cmp;
1459 }
1460 break;
1461 case 0x84 ... 0x85:
1462 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1463 break;
1464 case 0x86 ... 0x87: /* xchg */
1465 xchg:
1466 /* Write back the register source. */
1467 switch (c->dst.bytes) {
1468 case 1:
1469 *(u8 *) c->src.ptr = (u8) c->dst.val;
1470 break;
1471 case 2:
1472 *(u16 *) c->src.ptr = (u16) c->dst.val;
1473 break;
1474 case 4:
1475 *c->src.ptr = (u32) c->dst.val;
1476 break; /* 64b reg: zero-extend */
1477 case 8:
1478 *c->src.ptr = c->dst.val;
1479 break;
1480 }
1481 /*
1482 * Write back the memory destination with implicit LOCK
1483 * prefix.
1484 */
1485 c->dst.val = c->src.val;
1486 c->lock_prefix = 1;
1487 break;
1488 case 0x88 ... 0x8b: /* mov */
1489 goto mov;
1490 case 0x8c: { /* mov r/m, sreg */
1491 struct kvm_segment segreg;
1492
1493 if (c->modrm_reg <= 5)
1494 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1495 else {
1496 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1497 c->modrm);
1498 goto cannot_emulate;
1499 }
1500 c->dst.val = segreg.selector;
1501 break;
1502 }
1503 case 0x8d: /* lea r16/r32, m */
1504 c->dst.val = c->modrm_ea;
1505 break;
1506 case 0x8e: { /* mov seg, r/m16 */
1507 uint16_t sel;
1508 int type_bits;
1509 int err;
1510
1511 sel = c->src.val;
1512 if (c->modrm_reg <= 5) {
1513 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1514 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1515 type_bits, c->modrm_reg);
1516 } else {
1517 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1518 c->modrm);
1519 goto cannot_emulate;
1520 }
1521
1522 if (err < 0)
1523 goto cannot_emulate;
1524
1525 c->dst.type = OP_NONE; /* Disable writeback. */
1526 break;
1527 }
1528 case 0x8f: /* pop (sole member of Grp1a) */
1529 rc = emulate_grp1a(ctxt, ops);
1530 if (rc != 0)
1531 goto done;
1532 break;
1533 case 0x90: /* nop / xchg r8,rax */
1534 if (!(c->rex_prefix & 1)) { /* nop */
1535 c->dst.type = OP_NONE;
1536 break;
1537 }
1538 case 0x91 ... 0x97: /* xchg reg,rax */
1539 c->src.type = c->dst.type = OP_REG;
1540 c->src.bytes = c->dst.bytes = c->op_bytes;
1541 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1542 c->src.val = *(c->src.ptr);
1543 goto xchg;
1544 case 0x9c: /* pushf */
1545 c->src.val = (unsigned long) ctxt->eflags;
1546 emulate_push(ctxt);
1547 break;
1548 case 0x9d: /* popf */
1549 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1550 goto pop_instruction;
1551 case 0xa0 ... 0xa1: /* mov */
1552 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1553 c->dst.val = c->src.val;
1554 break;
1555 case 0xa2 ... 0xa3: /* mov */
1556 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1557 break;
1558 case 0xa4 ... 0xa5: /* movs */
1559 c->dst.type = OP_MEM;
1560 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1561 c->dst.ptr = (unsigned long *)register_address(c,
1562 ctxt->es_base,
1563 c->regs[VCPU_REGS_RDI]);
1564 if ((rc = ops->read_emulated(register_address(c,
1565 c->override_base ? *c->override_base :
1566 ctxt->ds_base,
1567 c->regs[VCPU_REGS_RSI]),
1568 &c->dst.val,
1569 c->dst.bytes, ctxt->vcpu)) != 0)
1570 goto done;
1571 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1572 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1573 : c->dst.bytes);
1574 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1575 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1576 : c->dst.bytes);
1577 break;
1578 case 0xa6 ... 0xa7: /* cmps */
1579 c->src.type = OP_NONE; /* Disable writeback. */
1580 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1581 c->src.ptr = (unsigned long *)register_address(c,
1582 c->override_base ? *c->override_base :
1583 ctxt->ds_base,
1584 c->regs[VCPU_REGS_RSI]);
1585 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1586 &c->src.val,
1587 c->src.bytes,
1588 ctxt->vcpu)) != 0)
1589 goto done;
1590
1591 c->dst.type = OP_NONE; /* Disable writeback. */
1592 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1593 c->dst.ptr = (unsigned long *)register_address(c,
1594 ctxt->es_base,
1595 c->regs[VCPU_REGS_RDI]);
1596 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1597 &c->dst.val,
1598 c->dst.bytes,
1599 ctxt->vcpu)) != 0)
1600 goto done;
1601
1602 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1603
1604 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1605
1606 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1607 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1608 : c->src.bytes);
1609 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1610 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1611 : c->dst.bytes);
1612
1613 break;
1614 case 0xaa ... 0xab: /* stos */
1615 c->dst.type = OP_MEM;
1616 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1617 c->dst.ptr = (unsigned long *)register_address(c,
1618 ctxt->es_base,
1619 c->regs[VCPU_REGS_RDI]);
1620 c->dst.val = c->regs[VCPU_REGS_RAX];
1621 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1622 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1623 : c->dst.bytes);
1624 break;
1625 case 0xac ... 0xad: /* lods */
1626 c->dst.type = OP_REG;
1627 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1628 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1629 if ((rc = ops->read_emulated(register_address(c,
1630 c->override_base ? *c->override_base :
1631 ctxt->ds_base,
1632 c->regs[VCPU_REGS_RSI]),
1633 &c->dst.val,
1634 c->dst.bytes,
1635 ctxt->vcpu)) != 0)
1636 goto done;
1637 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1638 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1639 : c->dst.bytes);
1640 break;
1641 case 0xae ... 0xaf: /* scas */
1642 DPRINTF("Urk! I don't handle SCAS.\n");
1643 goto cannot_emulate;
1644 case 0xb8: /* mov r, imm */
1645 goto mov;
1646 case 0xc0 ... 0xc1:
1647 emulate_grp2(ctxt);
1648 break;
1649 case 0xc3: /* ret */
1650 c->dst.ptr = &c->eip;
1651 goto pop_instruction;
1652 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1653 mov:
1654 c->dst.val = c->src.val;
1655 break;
1656 case 0xd0 ... 0xd1: /* Grp2 */
1657 c->src.val = 1;
1658 emulate_grp2(ctxt);
1659 break;
1660 case 0xd2 ... 0xd3: /* Grp2 */
1661 c->src.val = c->regs[VCPU_REGS_RCX];
1662 emulate_grp2(ctxt);
1663 break;
1664 case 0xe8: /* call (near) */ {
1665 long int rel;
1666 switch (c->op_bytes) {
1667 case 2:
1668 rel = insn_fetch(s16, 2, c->eip);
1669 break;
1670 case 4:
1671 rel = insn_fetch(s32, 4, c->eip);
1672 break;
1673 default:
1674 DPRINTF("Call: Invalid op_bytes\n");
1675 goto cannot_emulate;
1676 }
1677 c->src.val = (unsigned long) c->eip;
1678 jmp_rel(c, rel);
1679 c->op_bytes = c->ad_bytes;
1680 emulate_push(ctxt);
1681 break;
1682 }
1683 case 0xe9: /* jmp rel */
1684 goto jmp;
1685 case 0xea: /* jmp far */ {
1686 uint32_t eip;
1687 uint16_t sel;
1688
1689 switch (c->op_bytes) {
1690 case 2:
1691 eip = insn_fetch(u16, 2, c->eip);
1692 break;
1693 case 4:
1694 eip = insn_fetch(u32, 4, c->eip);
1695 break;
1696 default:
1697 DPRINTF("jmp far: Invalid op_bytes\n");
1698 goto cannot_emulate;
1699 }
1700 sel = insn_fetch(u16, 2, c->eip);
1701 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1702 DPRINTF("jmp far: Failed to load CS descriptor\n");
1703 goto cannot_emulate;
1704 }
1705
1706 c->eip = eip;
1707 break;
1708 }
1709 case 0xeb:
1710 jmp: /* jmp rel short */
1711 jmp_rel(c, c->src.val);
1712 c->dst.type = OP_NONE; /* Disable writeback. */
1713 break;
1714 case 0xf4: /* hlt */
1715 ctxt->vcpu->arch.halt_request = 1;
1716 goto done;
1717 case 0xf5: /* cmc */
1718 /* complement carry flag from eflags reg */
1719 ctxt->eflags ^= EFLG_CF;
1720 c->dst.type = OP_NONE; /* Disable writeback. */
1721 break;
1722 case 0xf6 ... 0xf7: /* Grp3 */
1723 rc = emulate_grp3(ctxt, ops);
1724 if (rc != 0)
1725 goto done;
1726 break;
1727 case 0xf8: /* clc */
1728 ctxt->eflags &= ~EFLG_CF;
1729 c->dst.type = OP_NONE; /* Disable writeback. */
1730 break;
1731 case 0xfa: /* cli */
1732 ctxt->eflags &= ~X86_EFLAGS_IF;
1733 c->dst.type = OP_NONE; /* Disable writeback. */
1734 break;
1735 case 0xfb: /* sti */
1736 ctxt->eflags |= X86_EFLAGS_IF;
1737 c->dst.type = OP_NONE; /* Disable writeback. */
1738 break;
1739 case 0xfe ... 0xff: /* Grp4/Grp5 */
1740 rc = emulate_grp45(ctxt, ops);
1741 if (rc != 0)
1742 goto done;
1743 break;
1744 }
1745
1746 writeback:
1747 rc = writeback(ctxt, ops);
1748 if (rc != 0)
1749 goto done;
1750
1751 /* Commit shadow register state. */
1752 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1753 ctxt->vcpu->arch.rip = c->eip;
1754
1755 done:
1756 if (rc == X86EMUL_UNHANDLEABLE) {
1757 c->eip = saved_eip;
1758 return -1;
1759 }
1760 return 0;
1761
1762 twobyte_insn:
1763 switch (c->b) {
1764 case 0x01: /* lgdt, lidt, lmsw */
1765 switch (c->modrm_reg) {
1766 u16 size;
1767 unsigned long address;
1768
1769 case 0: /* vmcall */
1770 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1771 goto cannot_emulate;
1772
1773 rc = kvm_fix_hypercall(ctxt->vcpu);
1774 if (rc)
1775 goto done;
1776
1777 /* Let the processor re-execute the fixed hypercall */
1778 c->eip = ctxt->vcpu->arch.rip;
1779 /* Disable writeback. */
1780 c->dst.type = OP_NONE;
1781 break;
1782 case 2: /* lgdt */
1783 rc = read_descriptor(ctxt, ops, c->src.ptr,
1784 &size, &address, c->op_bytes);
1785 if (rc)
1786 goto done;
1787 realmode_lgdt(ctxt->vcpu, size, address);
1788 /* Disable writeback. */
1789 c->dst.type = OP_NONE;
1790 break;
1791 case 3: /* lidt/vmmcall */
1792 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1793 rc = kvm_fix_hypercall(ctxt->vcpu);
1794 if (rc)
1795 goto done;
1796 kvm_emulate_hypercall(ctxt->vcpu);
1797 } else {
1798 rc = read_descriptor(ctxt, ops, c->src.ptr,
1799 &size, &address,
1800 c->op_bytes);
1801 if (rc)
1802 goto done;
1803 realmode_lidt(ctxt->vcpu, size, address);
1804 }
1805 /* Disable writeback. */
1806 c->dst.type = OP_NONE;
1807 break;
1808 case 4: /* smsw */
1809 c->dst.bytes = 2;
1810 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1811 break;
1812 case 6: /* lmsw */
1813 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1814 &ctxt->eflags);
1815 c->dst.type = OP_NONE;
1816 break;
1817 case 7: /* invlpg*/
1818 emulate_invlpg(ctxt->vcpu, memop);
1819 /* Disable writeback. */
1820 c->dst.type = OP_NONE;
1821 break;
1822 default:
1823 goto cannot_emulate;
1824 }
1825 break;
1826 case 0x06:
1827 emulate_clts(ctxt->vcpu);
1828 c->dst.type = OP_NONE;
1829 break;
1830 case 0x08: /* invd */
1831 case 0x09: /* wbinvd */
1832 case 0x0d: /* GrpP (prefetch) */
1833 case 0x18: /* Grp16 (prefetch/nop) */
1834 c->dst.type = OP_NONE;
1835 break;
1836 case 0x20: /* mov cr, reg */
1837 if (c->modrm_mod != 3)
1838 goto cannot_emulate;
1839 c->regs[c->modrm_rm] =
1840 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1841 c->dst.type = OP_NONE; /* no writeback */
1842 break;
1843 case 0x21: /* mov from dr to reg */
1844 if (c->modrm_mod != 3)
1845 goto cannot_emulate;
1846 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1847 if (rc)
1848 goto cannot_emulate;
1849 c->dst.type = OP_NONE; /* no writeback */
1850 break;
1851 case 0x22: /* mov reg, cr */
1852 if (c->modrm_mod != 3)
1853 goto cannot_emulate;
1854 realmode_set_cr(ctxt->vcpu,
1855 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1856 c->dst.type = OP_NONE;
1857 break;
1858 case 0x23: /* mov from reg to dr */
1859 if (c->modrm_mod != 3)
1860 goto cannot_emulate;
1861 rc = emulator_set_dr(ctxt, c->modrm_reg,
1862 c->regs[c->modrm_rm]);
1863 if (rc)
1864 goto cannot_emulate;
1865 c->dst.type = OP_NONE; /* no writeback */
1866 break;
1867 case 0x30:
1868 /* wrmsr */
1869 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1870 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1871 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1872 if (rc) {
1873 kvm_inject_gp(ctxt->vcpu, 0);
1874 c->eip = ctxt->vcpu->arch.rip;
1875 }
1876 rc = X86EMUL_CONTINUE;
1877 c->dst.type = OP_NONE;
1878 break;
1879 case 0x32:
1880 /* rdmsr */
1881 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1882 if (rc) {
1883 kvm_inject_gp(ctxt->vcpu, 0);
1884 c->eip = ctxt->vcpu->arch.rip;
1885 } else {
1886 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1887 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1888 }
1889 rc = X86EMUL_CONTINUE;
1890 c->dst.type = OP_NONE;
1891 break;
1892 case 0x40 ... 0x4f: /* cmov */
1893 c->dst.val = c->dst.orig_val = c->src.val;
1894 if (!test_cc(c->b, ctxt->eflags))
1895 c->dst.type = OP_NONE; /* no writeback */
1896 break;
1897 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1898 long int rel;
1899
1900 switch (c->op_bytes) {
1901 case 2:
1902 rel = insn_fetch(s16, 2, c->eip);
1903 break;
1904 case 4:
1905 rel = insn_fetch(s32, 4, c->eip);
1906 break;
1907 case 8:
1908 rel = insn_fetch(s64, 8, c->eip);
1909 break;
1910 default:
1911 DPRINTF("jnz: Invalid op_bytes\n");
1912 goto cannot_emulate;
1913 }
1914 if (test_cc(c->b, ctxt->eflags))
1915 jmp_rel(c, rel);
1916 c->dst.type = OP_NONE;
1917 break;
1918 }
1919 case 0xa3:
1920 bt: /* bt */
1921 c->dst.type = OP_NONE;
1922 /* only subword offset */
1923 c->src.val &= (c->dst.bytes << 3) - 1;
1924 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1925 break;
1926 case 0xab:
1927 bts: /* bts */
1928 /* only subword offset */
1929 c->src.val &= (c->dst.bytes << 3) - 1;
1930 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1931 break;
1932 case 0xb0 ... 0xb1: /* cmpxchg */
1933 /*
1934 * Save real source value, then compare EAX against
1935 * destination.
1936 */
1937 c->src.orig_val = c->src.val;
1938 c->src.val = c->regs[VCPU_REGS_RAX];
1939 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1940 if (ctxt->eflags & EFLG_ZF) {
1941 /* Success: write back to memory. */
1942 c->dst.val = c->src.orig_val;
1943 } else {
1944 /* Failure: write the value we saw to EAX. */
1945 c->dst.type = OP_REG;
1946 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1947 }
1948 break;
1949 case 0xb3:
1950 btr: /* btr */
1951 /* only subword offset */
1952 c->src.val &= (c->dst.bytes << 3) - 1;
1953 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1954 break;
1955 case 0xb6 ... 0xb7: /* movzx */
1956 c->dst.bytes = c->op_bytes;
1957 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1958 : (u16) c->src.val;
1959 break;
1960 case 0xba: /* Grp8 */
1961 switch (c->modrm_reg & 3) {
1962 case 0:
1963 goto bt;
1964 case 1:
1965 goto bts;
1966 case 2:
1967 goto btr;
1968 case 3:
1969 goto btc;
1970 }
1971 break;
1972 case 0xbb:
1973 btc: /* btc */
1974 /* only subword offset */
1975 c->src.val &= (c->dst.bytes << 3) - 1;
1976 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1977 break;
1978 case 0xbe ... 0xbf: /* movsx */
1979 c->dst.bytes = c->op_bytes;
1980 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1981 (s16) c->src.val;
1982 break;
1983 case 0xc3: /* movnti */
1984 c->dst.bytes = c->op_bytes;
1985 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1986 (u64) c->src.val;
1987 break;
1988 case 0xc7: /* Grp9 (cmpxchg8b) */
1989 rc = emulate_grp9(ctxt, ops, memop);
1990 if (rc != 0)
1991 goto done;
1992 c->dst.type = OP_NONE;
1993 break;
1994 }
1995 goto writeback;
1996
1997 cannot_emulate:
1998 DPRINTF("Cannot emulate %02x\n", c->b);
1999 c->eip = saved_eip;
2000 return -1;
2001 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree