drivers/clocksource/cs5535-clockevt.c

   1 /*
   2  * Clock event driver for the CS5535/CS5536
   3  *
   4  * Copyright (C) 2006, Advanced Micro Devices, Inc.
   5  * Copyright (C) 2007  Andres Salomon <dilinger@debian.org>
   6  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of version 2 of the GNU General Public License
  10  * as published by the Free Software Foundation.
  11  *
  12  * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/cs5535.h>
  20 #include <linux/clockchips.h>
  21
  22 #define DRV_NAME "cs5535-clockevt"
  23
  24 static int timer_irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
  25 module_param_named(irq, timer_irq, int, 0644);
  26 MODULE_PARM_DESC(irq, "Which IRQ to use for the clock source MFGPT ticks.");
  27
  28 /*
  29  * We are using the 32.768kHz input clock - it's the only one that has the
  30  * ranges we find desirable.  The following table lists the suitable
  31  * divisors and the associated Hz, minimum interval and the maximum interval:
  32  *
  33  *  Divisor   Hz      Min Delta (s)  Max Delta (s)
  34  *   1        32768   .00048828125      2.000
  35  *   2        16384   .0009765625       4.000
  36  *   4         8192   .001953125        8.000
  37  *   8         4096   .00390625        16.000
  38  *   16        2048   .0078125         32.000
  39  *   32        1024   .015625          64.000
  40  *   64         512   .03125          128.000
  41  *  128         256   .0625           256.000
  42  *  256         128   .125            512.000
  43  */
  44
  45 static unsigned int cs5535_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
  46 static struct cs5535_mfgpt_timer *cs5535_event_clock;
  47
  48 /* Selected from the table above */
  49
  50 #define MFGPT_DIVISOR 16
  51 #define MFGPT_SCALE  4     /* divisor = 2^(scale) */
  52 #define MFGPT_HZ  (32768 / MFGPT_DIVISOR)
  53 #define MFGPT_PERIODIC (MFGPT_HZ / HZ)
  54
  55 /*
  56  * The MFPGT timers on the CS5536 provide us with suitable timers to use
  57  * as clock event sources - not as good as a HPET or APIC, but certainly
  58  * better than the PIT.  This isn't a general purpose MFGPT driver, but
  59  * a simplified one designed specifically to act as a clock event source.
  60  * For full details about the MFGPT, please consult the CS5536 data sheet.
  61  */
  62
  63 static void disable_timer(struct cs5535_mfgpt_timer *timer)
  64 {
  65         /* avoid races by clearing CMP1 and CMP2 unconditionally */
  66         cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
  67                         (uint16_t) ~MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP1 |
  68                                 MFGPT_SETUP_CMP2);
  69 }
  70
  71 static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta)
  72 {
  73         cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta);
  74         cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0);
  75
  76         cs5535_mfgpt_write(timer, MFGPT_REG_SETUP,
  77                         MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
  78 }
  79
  80 static void mfgpt_set_mode(enum clock_event_mode mode,
  81                 struct clock_event_device *evt)
  82 {
  83         disable_timer(cs5535_event_clock);
  84
  85         if (mode == CLOCK_EVT_MODE_PERIODIC)
  86                 start_timer(cs5535_event_clock, MFGPT_PERIODIC);
  87
  88         cs5535_tick_mode = mode;
  89 }
  90
  91 static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
  92 {
  93         start_timer(cs5535_event_clock, delta);
  94         return 0;
  95 }
  96
  97 static struct clock_event_device cs5535_clockevent = {
  98         .name = DRV_NAME,
  99         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 100         .set_mode = mfgpt_set_mode,
 101         .set_next_event = mfgpt_next_event,
 102         .rating = 250,
 103         .cpumask = cpu_all_mask,
 104         .shift = 32
 105 };
 106
 107 static irqreturn_t mfgpt_tick(int irq, void *dev_id)
 108 {
 109         uint16_t val = cs5535_mfgpt_read(cs5535_event_clock, MFGPT_REG_SETUP);
 110
 111         /* See if the interrupt was for us */
 112         if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
 113                 return IRQ_NONE;
 114
 115         /* Turn off the clock (and clear the event) */
 116         disable_timer(cs5535_event_clock);
 117
 118         if (cs5535_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
 119                 return IRQ_HANDLED;
 120
 121         /* Clear the counter */
 122         cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0);
 123
 124         /* Restart the clock in periodic mode */
 125
 126         if (cs5535_tick_mode == CLOCK_EVT_MODE_PERIODIC)
 127                 cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
 128                                 MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
 129
 130         cs5535_clockevent.event_handler(&cs5535_clockevent);
 131         return IRQ_HANDLED;
 132 }
 133
 134 static struct irqaction mfgptirq  = {
 135         .handler = mfgpt_tick,
 136         .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
 137         .name = DRV_NAME,
 138 };
 139
 140 static int __init cs5535_mfgpt_init(void)
 141 {
 142         struct cs5535_mfgpt_timer *timer;
 143         int ret;
 144         uint16_t val;
 145
 146         timer = cs5535_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
 147         if (!timer) {
 148                 printk(KERN_ERR DRV_NAME ": Could not allocate MFPGT timer\n");
 149                 return -ENODEV;
 150         }
 151         cs5535_event_clock = timer;
 152
 153         /* Set up the IRQ on the MFGPT side */
 154         if (cs5535_mfgpt_setup_irq(timer, MFGPT_CMP2, &timer_irq)) {
 155                 printk(KERN_ERR DRV_NAME ": Could not set up IRQ %d\n",
 156                                 timer_irq);
 157                 return -EIO;
 158         }
 159
 160         /* And register it with the kernel */
 161         ret = setup_irq(timer_irq, &mfgptirq);
 162         if (ret) {
 163                 printk(KERN_ERR DRV_NAME ": Unable to set up the interrupt.\n");
 164                 goto err;
 165         }
 166
 167         /* Set the clock scale and enable the event mode for CMP2 */
 168         val = MFGPT_SCALE | (3 << 8);
 169
 170         cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, val);
 171
 172         /* Set up the clock event */
 173         cs5535_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC,
 174                         cs5535_clockevent.shift);
 175         cs5535_clockevent.min_delta_ns = clockevent_delta2ns(0xF,
 176                         &cs5535_clockevent);
 177         cs5535_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE,
 178                         &cs5535_clockevent);
 179
 180         printk(KERN_INFO DRV_NAME
 181                 ": Registering MFGPT timer as a clock event, using IRQ %d\n",
 182                 timer_irq);
 183         clockevents_register_device(&cs5535_clockevent);
 184
 185         return 0;
 186
 187 err:
 188         cs5535_mfgpt_release_irq(cs5535_event_clock, MFGPT_CMP2, &timer_irq);
 189         printk(KERN_ERR DRV_NAME ": Unable to set up the MFGPT clock source\n");
 190         return -EIO;
 191 }
 192
 193 module_init(cs5535_mfgpt_init);
 194
 195 MODULE_AUTHOR("Andres Salomon <dilinger@collabora.co.uk>");
 196 MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
 197 MODULE_LICENSE("GPL");