2 * linux/arch/arm/mm/proc-xsc3.S
4 * Original Author: Matthew Gilbert
5 * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
7 * Copyright 2004 (C) Intel Corp.
8 * Copyright 2005 (C) MontaVista Software, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
15 * an extension to Intel's original XScale core that adds the following
18 * - ARMv6 Supersections
19 * - Low Locality Reference pages (replaces mini-cache)
22 * - Cache coherency if chipset supports it
24 * Based on original XScale code by Nicolas Pitre.
27 #include <linux/linkage.h>
28 #include <linux/init.h>
29 #include <asm/assembler.h>
30 #include <asm/hwcap.h>
31 #include <mach/hardware.h>
32 #include <asm/pgtable.h>
33 #include <asm/pgtable-hwdef.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
39 * This is the maximum size of an area which will be flushed. If the
40 * area is larger than this, then we flush the whole cache.
42 #define MAX_AREA_SIZE 32768
45 * The cache line size of the L1 I, L1 D and unified L2 cache.
47 #define CACHELINESIZE 32
50 * The size of the L1 D cache.
52 #define CACHESIZE 32768
55 * This macro is used to wait for a CP15 write and is needed when we
56 * have to ensure that the last operation to the coprocessor was
57 * completed before continuing with operation.
59 .macro cpwait_ret, lr, rd
60 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
61 sub pc, \lr, \rd, LSR #32 @ wait for completion and
62 @ flush instruction pipeline
66 * This macro cleans and invalidates the entire L1 D cache.
69 .macro clean_d_cache rd, rs
72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
73 adds \rd, \rd, #0x40000000
82 * cpu_xsc3_proc_init()
84 * Nothing too exciting at the moment
86 ENTRY(cpu_xsc3_proc_init)
92 ENTRY(cpu_xsc3_proc_fin)
93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 bic r0, r0, #0x1800 @ ...IZ...........
95 bic r0, r0, #0x0006 @ .............CA.
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 * cpu_xsc3_reset(loc)
102 * Perform a soft reset of the system. Put the CPU into the
103 * same state as it would be if it had been reset, and branch
104 * to what would be the reset vector.
106 * loc: location to jump to for soft reset
109 ENTRY(cpu_xsc3_reset)
110 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
111 msr cpsr_c, r1 @ reset CPSR
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
113 bic r1, r1, #0x3900 @ ..VIZ..S........
114 bic r1, r1, #0x0086 @ ........B....CA.
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
117 bic r1, r1, #0x0001 @ ...............M
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
119 @ CAUTION: MMU turned off from this point. We count on the pipeline
120 @ already containing those two last instructions to survive.
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
127 * Cause the processor to idle
129 * For now we do nothing but go to idle mode for every case
131 * XScale supports clock switching, but using idle mode support
132 * allows external hardware to react to system state changes.
136 ENTRY(cpu_xsc3_do_idle)
138 mcr p14, 0, r0, c7, c0, 0 @ go to idle
141 /* ================================= CACHE ================================ */
146 * Unconditionally clean and invalidate the entire icache.
148 ENTRY(xsc3_flush_icache_all)
150 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
152 ENDPROC(xsc3_flush_icache_all)
155 * flush_user_cache_all()
157 * Invalidate all cache entries in a particular address
160 ENTRY(xsc3_flush_user_cache_all)
164 * flush_kern_cache_all()
166 * Clean and invalidate the entire cache.
168 ENTRY(xsc3_flush_kern_cache_all)
174 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
176 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
180 * flush_user_cache_range(start, end, vm_flags)
182 * Invalidate a range of cache entries in the specified
185 * - start - start address (may not be aligned)
186 * - end - end address (exclusive, may not be aligned)
187 * - vma - vma_area_struct describing address space
190 ENTRY(xsc3_flush_user_cache_range)
192 sub r3, r1, r0 @ calculate total size
193 cmp r3, #MAX_AREA_SIZE
194 bhs __flush_whole_cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
198 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
199 add r0, r0, #CACHELINESIZE
203 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
205 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
209 * coherent_kern_range(start, end)
211 * Ensure coherency between the I cache and the D cache in the
212 * region described by start. If you have non-snooping
213 * Harvard caches, you need to implement this function.
215 * - start - virtual start address
216 * - end - virtual end address
218 * Note: single I-cache line invalidation isn't used here since
219 * it also trashes the mini I-cache used by JTAG debuggers.
221 ENTRY(xsc3_coherent_kern_range)
223 ENTRY(xsc3_coherent_user_range)
224 bic r0, r0, #CACHELINESIZE - 1
225 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
226 add r0, r0, #CACHELINESIZE
230 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
232 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
236 * flush_kern_dcache_area(void *addr, size_t size)
238 * Ensure no D cache aliasing occurs, either with itself or
241 * - addr - kernel address
242 * - size - region size
244 ENTRY(xsc3_flush_kern_dcache_area)
246 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
247 add r0, r0, #CACHELINESIZE
251 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
253 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
257 * dma_inv_range(start, end)
259 * Invalidate (discard) the specified virtual address range.
260 * May not write back any entries. If 'start' or 'end'
261 * are not cache line aligned, those lines must be written
264 * - start - virtual start address
265 * - end - virtual end address
268 tst r0, #CACHELINESIZE - 1
269 bic r0, r0, #CACHELINESIZE - 1
270 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
271 tst r1, #CACHELINESIZE - 1
272 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
273 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
274 add r0, r0, #CACHELINESIZE
277 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
281 * dma_clean_range(start, end)
283 * Clean the specified virtual address range.
285 * - start - virtual start address
286 * - end - virtual end address
288 xsc3_dma_clean_range:
289 bic r0, r0, #CACHELINESIZE - 1
290 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
291 add r0, r0, #CACHELINESIZE
294 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
298 * dma_flush_range(start, end)
300 * Clean and invalidate the specified virtual address range.
302 * - start - virtual start address
303 * - end - virtual end address
305 ENTRY(xsc3_dma_flush_range)
306 bic r0, r0, #CACHELINESIZE - 1
307 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
308 add r0, r0, #CACHELINESIZE
311 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
315 * dma_map_area(start, size, dir)
316 * - start - kernel virtual start address
317 * - size - size of region
318 * - dir - DMA direction
320 ENTRY(xsc3_dma_map_area)
322 cmp r2, #DMA_TO_DEVICE
323 beq xsc3_dma_clean_range
324 bcs xsc3_dma_inv_range
325 b xsc3_dma_flush_range
326 ENDPROC(xsc3_dma_map_area)
329 * dma_unmap_area(start, size, dir)
330 * - start - kernel virtual start address
331 * - size - size of region
332 * - dir - DMA direction
334 ENTRY(xsc3_dma_unmap_area)
336 ENDPROC(xsc3_dma_unmap_area)
338 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
339 define_cache_functions xsc3
341 ENTRY(cpu_xsc3_dcache_clean_area)
342 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
343 add r0, r0, #CACHELINESIZE
344 subs r1, r1, #CACHELINESIZE
348 /* =============================== PageTable ============================== */
351 * cpu_xsc3_switch_mm(pgd)
353 * Set the translation base pointer to be as described by pgd.
355 * pgd: new page tables
358 ENTRY(cpu_xsc3_switch_mm)
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
361 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
362 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
363 orr r0, r0, #0x18 @ cache the page table in L2
364 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
365 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
369 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
371 * Set a PTE and flush it out
374 .long 0x00 @ L_PTE_MT_UNCACHED
375 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
376 .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
377 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
378 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
380 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
381 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
383 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
385 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
386 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
392 ENTRY(cpu_xsc3_set_pte_ext)
393 xscale_set_pte_ext_prologue
395 tst r1, #L_PTE_SHARED @ shared?
396 and r1, r1, #L_PTE_MT_MASK
397 adr ip, cpu_xsc3_mt_table
399 orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
400 bic r2, r2, #0x0c @ clear old C,B bits
403 xscale_set_pte_ext_epilogue
409 .globl cpu_xsc3_suspend_size
410 .equ cpu_xsc3_suspend_size, 4 * 8
411 #ifdef CONFIG_PM_SLEEP
412 ENTRY(cpu_xsc3_do_suspend)
413 stmfd sp!, {r4 - r10, lr}
414 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
415 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
416 mrc p15, 0, r6, c13, c0, 0 @ PID
417 mrc p15, 0, r7, c3, c0, 0 @ domain ID
418 mrc p15, 0, r8, c2, c0, 0 @ translation table base addr
419 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
420 mrc p15, 0, r10, c1, c0, 0 @ control reg
421 bic r4, r4, #2 @ clear frequency change bit
422 stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs
423 ldmia sp!, {r4 - r10, pc}
424 ENDPROC(cpu_xsc3_do_suspend)
426 ENTRY(cpu_xsc3_do_resume)
427 ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs
429 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
430 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
431 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
432 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
433 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
434 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
435 mcr p15, 0, r6, c13, c0, 0 @ PID
436 mcr p15, 0, r7, c3, c0, 0 @ domain ID
437 mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
438 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
440 @ temporarily map resume_turn_on_mmu into the page table,
441 @ otherwise prefetch abort occurs after MMU is turned on
442 mov r0, r10 @ control register
443 mov r2, r8, lsr #14 @ get TTB0 base
445 ldr r3, =0x542e @ section flags
447 ENDPROC(cpu_xsc3_do_resume)
449 #define cpu_xsc3_do_suspend 0
450 #define cpu_xsc3_do_resume 0
455 .type __xsc3_setup, #function
457 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
459 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
460 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
461 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
462 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
463 orr r4, r4, #0x18 @ cache the page table in L2
464 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
466 mov r0, #1 << 6 @ cp6 access for early sched_clock
467 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
469 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
470 and r0, r0, #2 @ preserve bit P bit setting
471 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
472 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
477 #ifdef CONFIG_CACHE_XSC3L2
478 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
480 orrne r6, r6, #(1 << 26) @ enable L2 if present
483 mrc p15, 0, r0, c1, c0, 0 @ get control register
484 bic r0, r0, r5 @ ..V. ..R. .... ..A.
485 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
486 @ ...I Z..S .... .... (uc)
489 .size __xsc3_setup, . - __xsc3_setup
491 .type xsc3_crval, #object
493 crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
497 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
498 define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
502 string cpu_arch_name, "armv5te"
503 string cpu_elf_name, "v5"
504 string cpu_xsc3_name, "XScale-V3 based processor"
508 .section ".proc.info.init", #alloc, #execinstr
510 .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
511 .type __\name\()_proc_info,#object
512 __\name\()_proc_info:
515 .long PMD_TYPE_SECT | \
516 PMD_SECT_BUFFERABLE | \
517 PMD_SECT_CACHEABLE | \
518 PMD_SECT_AP_WRITE | \
520 .long PMD_TYPE_SECT | \
521 PMD_SECT_AP_WRITE | \
526 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
528 .long xsc3_processor_functions
530 .long xsc3_mc_user_fns
532 .size __\name\()_proc_info, . - __\name\()_proc_info
535 xsc3_proc_info xsc3, 0x69056000, 0xffffe000
537 /* Note: PXA935 changed its implementor ID from Intel to Marvell */
538 xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000