2 * linux/arch/arm/mm/proc-arm6,7.S
4 * Copyright (C) 1997-2000 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * These are the low level assembler for performing cache and TLB
12 * functions on the ARM610 & ARM710.
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/pgtable.h>
21 #include <asm/ptrace.h>
23 #include "proc-macros.S"
25 ENTRY(cpu_arm6_dcache_clean_area)
26 ENTRY(cpu_arm7_dcache_clean_area)
30 * Function: arm6_7_data_abort ()
32 * Params : r2 = address of aborted instruction
33 * : sp = pointer to registers
35 * Purpose : obtain information about current aborted instruction
37 * Returns : r0 = address of abort
41 ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r2] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes.
48 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
51 /* 0 */ b .data_unknown
52 /* 1 */ mov pc, lr @ swp
53 /* 2 */ b .data_unknown
54 /* 3 */ b .data_unknown
55 /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
56 /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
57 /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
58 /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
59 /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
60 /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61 /* a */ b .data_unknown
62 /* b */ b .data_unknown
63 /* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64 /* d */ mov pc, lr @ ldc rd, [rn, #m]
65 /* e */ b .data_unknown
67 .data_unknown: @ Part of jumptable
74 ENTRY(cpu_arm6_data_abort)
75 mrc p15, 0, r1, c5, c0, 0 @ get FSR
76 mrc p15, 0, r0, c6, c0, 0 @ get FAR
77 ldr r8, [r2] @ read arm instruction
78 tst r8, #1 << 20 @ L = 0 -> write?
79 orreq r1, r1, #1 << 11 @ yes.
81 teq r7, #8 << 24 @ was it ldm/stm
85 tst r8, #1 << 21 @ check writeback bit
86 moveq pc, lr @ no writeback -> no fixup
90 and r2, r8, r7, lsl #1
91 add r6, r6, r2, lsr #1
92 and r2, r8, r7, lsl #2
93 add r6, r6, r2, lsr #2
94 and r2, r8, r7, lsl #3
95 add r6, r6, r2, lsr #3
96 add r6, r6, r6, lsr #8
97 add r6, r6, r6, lsr #4
98 and r6, r6, #15 @ r6 = no. of registers to transfer.
99 and r5, r8, #15 << 16 @ Extract 'n' from instruction
100 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
101 tst r8, #1 << 23 @ Check U bit
102 subne r7, r7, r6, lsl #2 @ Undo increment
103 addeq r7, r7, r6, lsl #2 @ Undo decrement
104 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
107 .data_arm_apply_r6_and_rn:
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction
109 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
110 tst r8, #1 << 23 @ Check U bit
111 subne r7, r7, r6 @ Undo incrmenet
112 addeq r7, r7, r6 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
116 .data_arm_lateldrpreconst:
117 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup
119 .data_arm_lateldrpostconst:
120 movs r2, r8, lsl #20 @ Get offset
121 moveq pc, lr @ zero -> no fixup
122 and r5, r8, #15 << 16 @ Extract 'n' from instruction
123 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
124 tst r8, #1 << 23 @ Check U bit
125 subne r7, r7, r2, lsr #20 @ Undo increment
126 addeq r7, r7, r2, lsr #20 @ Undo decrement
127 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
130 .data_arm_lateldrprereg:
131 tst r8, #1 << 21 @ check writeback bit
132 moveq pc, lr @ no writeback -> no fixup
133 .data_arm_lateldrpostreg:
134 and r7, r8, #15 @ Extract 'm' from instruction
135 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
136 mov r5, r8, lsr #7 @ get shift count
138 and r7, r8, #0x70 @ get shift type
139 orreq r7, r7, #8 @ shift count = 0
143 mov r6, r6, lsl r5 @ 0: LSL #!0
144 b .data_arm_apply_r6_and_rn
145 b .data_arm_apply_r6_and_rn @ 1: LSL #0
147 b .data_unknown @ 2: MUL?
149 b .data_unknown @ 3: MUL?
151 mov r6, r6, lsr r5 @ 4: LSR #!0
152 b .data_arm_apply_r6_and_rn
153 mov r6, r6, lsr #32 @ 5: LSR #32
154 b .data_arm_apply_r6_and_rn
155 b .data_unknown @ 6: MUL?
157 b .data_unknown @ 7: MUL?
159 mov r6, r6, asr r5 @ 8: ASR #!0
160 b .data_arm_apply_r6_and_rn
161 mov r6, r6, asr #32 @ 9: ASR #32
162 b .data_arm_apply_r6_and_rn
163 b .data_unknown @ A: MUL?
165 b .data_unknown @ B: MUL?
167 mov r6, r6, ror r5 @ C: ROR #!0
168 b .data_arm_apply_r6_and_rn
169 mov r6, r6, rrx @ D: RRX
170 b .data_arm_apply_r6_and_rn
171 b .data_unknown @ E: MUL?
173 b .data_unknown @ F: MUL?
176 * Function: arm6_7_proc_init (void)
177 * : arm6_7_proc_fin (void)
179 * Notes : This processor does not require these
181 ENTRY(cpu_arm6_proc_init)
182 ENTRY(cpu_arm7_proc_init)
185 ENTRY(cpu_arm6_proc_fin)
186 ENTRY(cpu_arm7_proc_fin)
187 mov r0, #0x31 @ ....S..DP...M
188 mcr p15, 0, r0, c1, c0, 0 @ disable caches
191 ENTRY(cpu_arm6_do_idle)
192 ENTRY(cpu_arm7_do_idle)
196 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
197 * Params : pgd_phys Physical address of page table
198 * Purpose : Perform a task switch, saving the old processes state, and restoring
201 ENTRY(cpu_arm6_switch_mm)
202 ENTRY(cpu_arm7_switch_mm)
205 mcr p15, 0, r1, c7, c0, 0 @ flush cache
206 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
207 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
212 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
213 * Params : r0 = Address to set
214 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache
218 ENTRY(cpu_arm6_set_pte_ext)
219 ENTRY(cpu_arm7_set_pte_ext)
221 armv3_set_pte_ext wc_disable=0
222 #endif /* CONFIG_MMU */
226 * Function: _arm6_7_reset
227 * Params : r0 = address to jump to
228 * Notes : This sets up everything for a reset
230 ENTRY(cpu_arm6_reset)
231 ENTRY(cpu_arm7_reset)
233 mcr p15, 0, r1, c7, c0, 0 @ flush cache
235 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
238 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
243 .type __arm6_setup, #function
244 __arm6_setup: mov r0, #0
245 mcr p15, 0, r0, c7, c0 @ flush caches on v3
247 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
248 mov r0, #0x3d @ . ..RS BLDP WCAM
249 orr r0, r0, #0x100 @ . ..01 0011 1101
251 mov r0, #0x3c @ . ..RS BLDP WCA.
254 .size __arm6_setup, . - __arm6_setup
256 .type __arm7_setup, #function
257 __arm7_setup: mov r0, #0
258 mcr p15, 0, r0, c7, c0 @ flush caches on v3
260 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
261 mcr p15, 0, r0, c3, c0 @ load domain access register
262 mov r0, #0x7d @ . ..RS BLDP WCAM
263 orr r0, r0, #0x100 @ . ..01 0111 1101
265 mov r0, #0x7c @ . ..RS BLDP WCA.
268 .size __arm7_setup, . - __arm7_setup
272 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
273 define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
274 define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
278 string cpu_arch_name, "armv3"
279 string cpu_elf_name, "v3"
280 string cpu_arm6_name, "ARM6"
281 string cpu_arm610_name, "ARM610"
282 string cpu_arm7_name, "ARM7"
283 string cpu_arm710_name, "ARM710"
287 .section ".proc.info.init", #alloc, #execinstr
289 .macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
290 cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
291 .type __\name\()_proc_info, #object
292 __\name\()_proc_info:
295 .long \cpu_mm_mmu_flags
296 .long PMD_TYPE_SECT | \
298 PMD_SECT_AP_WRITE | \
303 .long HWCAP_SWP | HWCAP_26BIT
305 .long \cpu_proc_funcs
309 .size __\name\()_proc_info, . - __\name\()_proc_info
312 arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
313 0x00000c1e, __arm6_setup, arm6_processor_functions
314 arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
315 0x00000c1e, __arm6_setup, arm6_processor_functions
316 arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
317 0x00000c1e, __arm7_setup, arm7_processor_functions
318 arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
320 PMD_SECT_BUFFERABLE | \
321 PMD_SECT_CACHEABLE | \
323 PMD_SECT_AP_WRITE | \
325 __arm7_setup, arm7_processor_functions