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[PATCH] shpchp: fix improper write to Command Completion Detect bit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / asm-alpha / core_cia.h
blob3a70d68bfce83f9d6e1ac87653a8eba8cc15189e
1 #ifndef __ALPHA_CIA__H__
2 #define __ALPHA_CIA__H__
3
4 /* Define to experiment with fitting everything into one 512MB HAE window. */
5 #define CIA_ONE_HAE_WINDOW 1
6
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <asm/compiler.h>
10
11 /*
12 * CIA is the internal name for the 21171 chipset which provides
13 * memory controller and PCI access for the 21164 chip based systems.
14 * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
15 *
16 * The lineage is a bit confused, since the 21174 was reportedly started
17 * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
18 * in 21171 Pass 2 and 21172, but it also contains additional features.
19 *
20 * This file is based on:
21 *
22 * DECchip 21171 Core Logic Chipset
23 * Technical Reference Manual
24 *
25 * EC-QE18B-TE
26 *
27 * david.rusling@reo.mts.dec.com Initial Version.
28 *
29 */
30
31 /*
32 * CIA ADDRESS BIT DEFINITIONS
33 *
34 * 3333 3333 3322 2222 2222 1111 1111 11
35 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
36 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
37 * 1 000
38 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
39 * | |\|
40 * | Byte Enable --+ |
41 * | Transfer Length --+
42 * +-- IO space, not cached
43 *
44 * Byte Transfer
45 * Enable Length Transfer Byte Address
46 * adr<6:5> adr<4:3> Length Enable Adder
47 * ---------------------------------------------
48 * 00 00 Byte 1110 0x000
49 * 01 00 Byte 1101 0x020
50 * 10 00 Byte 1011 0x040
51 * 11 00 Byte 0111 0x060
52 *
53 * 00 01 Word 1100 0x008
54 * 01 01 Word 1001 0x028 <= Not supported in this code.
55 * 10 01 Word 0011 0x048
56 *
57 * 00 10 Tribyte 1000 0x010
58 * 01 10 Tribyte 0001 0x030
59 *
60 * 10 11 Longword 0000 0x058
61 *
62 * Note that byte enables are asserted low.
63 *
64 */
65
66 #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
67 #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
68 #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
69
70 /*
71 * 21171-CA Control and Status Registers
72 */
73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
74 # define CIA_REV_MASK 0xff
75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
77 # define CIA_CTRL_PCI_EN (1 << 0)
78 # define CIA_CTRL_PCI_LOCK_EN (1 << 1)
79 # define CIA_CTRL_PCI_LOOP_EN (1 << 2)
80 # define CIA_CTRL_FST_BB_EN (1 << 3)
81 # define CIA_CTRL_PCI_MST_EN (1 << 4)
82 # define CIA_CTRL_PCI_MEM_EN (1 << 5)
83 # define CIA_CTRL_PCI_REQ64_EN (1 << 6)
84 # define CIA_CTRL_PCI_ACK64_EN (1 << 7)
85 # define CIA_CTRL_ADDR_PE_EN (1 << 8)
86 # define CIA_CTRL_PERR_EN (1 << 9)
87 # define CIA_CTRL_FILL_ERR_EN (1 << 10)
88 # define CIA_CTRL_MCHK_ERR_EN (1 << 11)
89 # define CIA_CTRL_ECC_CHK_EN (1 << 12)
90 # define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
91 # define CIA_CTRL_COM_IDLE_BC (1 << 14)
92 # define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
93 # define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
94 # define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
95 # define CIA_CTRL_ARB_CPU_EN (1 << 18)
96 # define CIA_CTRL_EN_ARB_LINK (1 << 19)
97 # define CIA_CTRL_RD_TYPE_SHIFT 20
98 # define CIA_CTRL_RL_TYPE_SHIFT 24
99 # define CIA_CTRL_RM_TYPE_SHIFT 28
100 # define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
102 # define CIA_CNFG_IOA_BWEN (1 << 0)
103 # define CIA_CNFG_PCI_MWEN (1 << 4)
104 # define CIA_CNFG_PCI_DWEN (1 << 5)
105 # define CIA_CNFG_PCI_WLEN (1 << 8)
106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
111 # define CIA_CACK_EN_LOCK_EN (1 << 0)
112 # define CIA_CACK_EN_MB_EN (1 << 1)
113 # define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
114 # define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
115
116
117 /*
118 * 21171-CA Diagnostic Registers
119 */
120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
121 #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
122
123 /*
124 * 21171-CA Performance Monitor registers
125 */
126 #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
127 #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
128
129 /*
130 * 21171-CA Error registers
131 */
132 #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
133 #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
134 #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
135 # define CIA_ERR_COR_ERR (1 << 0)
136 # define CIA_ERR_UN_COR_ERR (1 << 1)
137 # define CIA_ERR_CPU_PE (1 << 2)
138 # define CIA_ERR_MEM_NEM (1 << 3)
139 # define CIA_ERR_PCI_SERR (1 << 4)
140 # define CIA_ERR_PERR (1 << 5)
141 # define CIA_ERR_PCI_ADDR_PE (1 << 6)
142 # define CIA_ERR_RCVD_MAS_ABT (1 << 7)
143 # define CIA_ERR_RCVD_TAR_ABT (1 << 8)
144 # define CIA_ERR_PA_PTE_INV (1 << 9)
145 # define CIA_ERR_FROM_WRT_ERR (1 << 10)
146 # define CIA_ERR_IOA_TIMEOUT (1 << 11)
147 # define CIA_ERR_LOST_CORR_ERR (1 << 16)
148 # define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
149 # define CIA_ERR_LOST_CPU_PE (1 << 18)
150 # define CIA_ERR_LOST_MEM_NEM (1 << 19)
151 # define CIA_ERR_LOST_PERR (1 << 21)
152 # define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
153 # define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
154 # define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
155 # define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
156 # define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
157 # define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
158 # define CIA_ERR_VALID (1 << 31)
159 #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
160 #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
161 #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
162 #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
163 #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
164 #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
165 #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
166 #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
167
168 /*
169 * 21171-CA System configuration registers
170 */
171 #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
172 #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
173 #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
174 #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
175 #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
176 #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
177 #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
178 #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
179 #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
180 #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
181 #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
182 #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
183
184 /*
185 * 2117A-CA PCI Address and Scatter-Gather Registers.
186 */
187 #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
188
189 #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
190 #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
191 #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
192
193 #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
194 #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
195 #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
196
197 #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
198 #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
199 #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
200
201 #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
202 #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
203 #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
204
205 #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
206 #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
207 #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
208
209 #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
210
211 /*
212 * 2117A-CA Address Translation Registers.
213 */
214
215 /* 8 tag registers, the first 4 of which are lockable. */
216 #define CIA_IOC_TB_TAGn(n) \
217 (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
218
219 /* 4 page registers per tag register. */
220 #define CIA_IOC_TBn_PAGEm(n,m) \
221 (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
222
223 /*
224 * Memory spaces:
225 */
226 #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
227 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
228 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
229 #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
230 #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
231 #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
232 #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
233 #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
234 #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
235 #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
236 #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
237
238 /*
239 * ALCOR's GRU ASIC registers
240 */
241 #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
242 #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
243 #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
244 #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
245 #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
246
247 #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
248 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
249 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
250 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
251
252 #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
253 #define XLT_GRU_INT_REQ_BITS 0x80003fffUL
254 #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
255
256 /*
257 * PYXIS interrupt control registers
258 */
259 #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
260 #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
261 #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
262 #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
263 #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
264 #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
265 #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
266 #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
267 #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
268 #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
269
270 /* Offset between ram physical addresses and pci64 DAC bus addresses. */
271 #define PYXIS_DAC_OFFSET (1UL << 40)
272
273 /*
274 * Data structure for handling CIA machine checks.
275 */
276
277 /* System-specific info. */
278 struct el_CIA_sysdata_mcheck {
279 unsigned long cpu_err0;
280 unsigned long cpu_err1;
281 unsigned long cia_err;
282 unsigned long cia_stat;
283 unsigned long err_mask;
284 unsigned long cia_syn;
285 unsigned long mem_err0;
286 unsigned long mem_err1;
287 unsigned long pci_err0;
288 unsigned long pci_err1;
289 unsigned long pci_err2;
290 };
291
292
293 #ifdef __KERNEL__
294
295 #ifndef __EXTERN_INLINE
296 /* Do not touch, this should *NOT* be static inline */
297 #define __EXTERN_INLINE extern inline
298 #define __IO_EXTERN_INLINE
299 #endif
300
301 /*
302 * I/O functions:
303 *
304 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
305 * series of processors uses a sparse address mapping scheme to
306 * get at PCI memory and I/O.
307 */
308
309 /*
310 * Memory functions. 64-bit and 32-bit accesses are done through
311 * dense memory space, everything else through sparse space.
312 *
313 * For reading and writing 8 and 16 bit quantities we need to
314 * go through one of the three sparse address mapping regions
315 * and use the HAE_MEM CSR to provide some bits of the address.
316 * The following few routines use only sparse address region 1
317 * which gives 1Gbyte of accessible space which relates exactly
318 * to the amount of PCI memory mapping *into* system address space.
319 * See p 6-17 of the specification but it looks something like this:
320 *
321 * 21164 Address:
322 *
323 * 3 2 1
324 * 9876543210987654321098765432109876543210
325 * 1ZZZZ0.PCI.QW.Address............BBLL
326 *
327 * ZZ = SBZ
328 * BB = Byte offset
329 * LL = Transfer length
330 *
331 * PCI Address:
332 *
333 * 3 2 1
334 * 10987654321098765432109876543210
335 * HHH....PCI.QW.Address........ 00
336 *
337 * HHH = 31:29 HAE_MEM CSR
338 *
339 */
340
341 #define vip volatile int __force *
342 #define vuip volatile unsigned int __force *
343 #define vulp volatile unsigned long __force *
344
345 __EXTERN_INLINE unsigned int cia_ioread8(void __iomem *xaddr)
346 {
347 unsigned long addr = (unsigned long) xaddr;
348 unsigned long result, base_and_type;
349
350 if (addr >= CIA_DENSE_MEM)
351 base_and_type = CIA_SPARSE_MEM + 0x00;
352 else
353 base_and_type = CIA_IO + 0x00;
354
355 /* We can use CIA_MEM_R1_MASK for io ports too, since it is large
356 enough to cover all io ports, and smaller than CIA_IO. */
357 addr &= CIA_MEM_R1_MASK;
358 result = *(vip) ((addr << 5) + base_and_type);
359 return __kernel_extbl(result, addr & 3);
360 }
361
362 __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
363 {
364 unsigned long addr = (unsigned long) xaddr;
365 unsigned long w, base_and_type;
366
367 if (addr >= CIA_DENSE_MEM)
368 base_and_type = CIA_SPARSE_MEM + 0x00;
369 else
370 base_and_type = CIA_IO + 0x00;
371
372 addr &= CIA_MEM_R1_MASK;
373 w = __kernel_insbl(b, addr & 3);
374 *(vuip) ((addr << 5) + base_and_type) = w;
375 }
376
377 __EXTERN_INLINE unsigned int cia_ioread16(void __iomem *xaddr)
378 {
379 unsigned long addr = (unsigned long) xaddr;
380 unsigned long result, base_and_type;
381
382 if (addr >= CIA_DENSE_MEM)
383 base_and_type = CIA_SPARSE_MEM + 0x08;
384 else
385 base_and_type = CIA_IO + 0x08;
386
387 addr &= CIA_MEM_R1_MASK;
388 result = *(vip) ((addr << 5) + base_and_type);
389 return __kernel_extwl(result, addr & 3);
390 }
391
392 __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
393 {
394 unsigned long addr = (unsigned long) xaddr;
395 unsigned long w, base_and_type;
396
397 if (addr >= CIA_DENSE_MEM)
398 base_and_type = CIA_SPARSE_MEM + 0x08;
399 else
400 base_and_type = CIA_IO + 0x08;
401
402 addr &= CIA_MEM_R1_MASK;
403 w = __kernel_inswl(b, addr & 3);
404 *(vuip) ((addr << 5) + base_and_type) = w;
405 }
406
407 __EXTERN_INLINE unsigned int cia_ioread32(void __iomem *xaddr)
408 {
409 unsigned long addr = (unsigned long) xaddr;
410 if (addr < CIA_DENSE_MEM)
411 addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
412 return *(vuip)addr;
413 }
414
415 __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
416 {
417 unsigned long addr = (unsigned long) xaddr;
418 if (addr < CIA_DENSE_MEM)
419 addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
420 *(vuip)addr = b;
421 }
422
423 __EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
424 {
425 return (void __iomem *)(addr + CIA_IO);
426 }
427
428 __EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
429 unsigned long size)
430 {
431 return (void __iomem *)(addr + CIA_DENSE_MEM);
432 }
433
434 __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
435 {
436 return addr >= IDENT_ADDR + 0x8000000000UL;
437 }
438
439 __EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
440 {
441 return (unsigned long)addr >= CIA_DENSE_MEM;
442 }
443
444 __EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
445 {
446 return (void __iomem *)(addr + CIA_BW_IO);
447 }
448
449 __EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
450 unsigned long size)
451 {
452 return (void __iomem *)(addr + CIA_BW_MEM);
453 }
454
455 __EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
456 {
457 return addr >= IDENT_ADDR + 0x8000000000UL;
458 }
459
460 __EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
461 {
462 return (unsigned long)addr < CIA_BW_IO;
463 }
464
465 #undef vip
466 #undef vuip
467 #undef vulp
468
469 #undef __IO_PREFIX
470 #define __IO_PREFIX cia
471 #define cia_trivial_rw_bw 2
472 #define cia_trivial_rw_lq 1
473 #define cia_trivial_io_bw 0
474 #define cia_trivial_io_lq 0
475 #define cia_trivial_iounmap 1
476 #include <asm/io_trivial.h>
477
478 #undef __IO_PREFIX
479 #define __IO_PREFIX cia_bwx
480 #define cia_bwx_trivial_rw_bw 1
481 #define cia_bwx_trivial_rw_lq 1
482 #define cia_bwx_trivial_io_bw 1
483 #define cia_bwx_trivial_io_lq 1
484 #define cia_bwx_trivial_iounmap 1
485 #include <asm/io_trivial.h>
486
487 #undef __IO_PREFIX
488 #ifdef CONFIG_ALPHA_PYXIS
489 #define __IO_PREFIX cia_bwx
490 #else
491 #define __IO_PREFIX cia
492 #endif
493
494 #ifdef __IO_EXTERN_INLINE
495 #undef __EXTERN_INLINE
496 #undef __IO_EXTERN_INLINE
497 #endif
498
499 #endif /* __KERNEL__ */
500
501 #endif /* __ALPHA_CIA__H__ */
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