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V4L/DVB (11703): cx18: Have audio decoder drive SIF gain control, and rework AFE...
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / video / cx18 / cx18-av-core.c
blob2b07b156340bc9d54826f0b0b384dbe5a0fcf34f
1 /*
2 * cx18 ADEC audio functions
3 *
4 * Derived from cx25840-core.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * 02110-1301, USA.
23 */
24
25 #include <media/v4l2-chip-ident.h>
26 #include "cx18-driver.h"
27 #include "cx18-io.h"
28 #include "cx18-cards.h"
29
30 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
31 {
32 u32 reg = 0xc40000 + (addr & ~3);
33 u32 mask = 0xff;
34 int shift = (addr & 3) * 8;
35 u32 x = cx18_read_reg(cx, reg);
36
37 x = (x & ~(mask << shift)) | ((u32)value << shift);
38 cx18_write_reg(cx, x, reg);
39 return 0;
40 }
41
42 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
43 {
44 u32 reg = 0xc40000 + (addr & ~3);
45 int shift = (addr & 3) * 8;
46 u32 x = cx18_read_reg(cx, reg);
47
48 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
49 cx18_write_reg_expect(cx, x, reg,
50 ((u32)eval << shift), ((u32)mask << shift));
51 return 0;
52 }
53
54 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
55 {
56 cx18_write_reg(cx, value, 0xc40000 + addr);
57 return 0;
58 }
59
60 int
61 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
62 {
63 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
64 return 0;
65 }
66
67 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
68 {
69 cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
70 return 0;
71 }
72
73 u8 cx18_av_read(struct cx18 *cx, u16 addr)
74 {
75 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
76 int shift = (addr & 3) * 8;
77
78 return (x >> shift) & 0xff;
79 }
80
81 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
82 {
83 return cx18_read_reg(cx, 0xc40000 + addr);
84 }
85
86 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
87 u8 or_value)
88 {
89 return cx18_av_write(cx, addr,
90 (cx18_av_read(cx, addr) & and_mask) |
91 or_value);
92 }
93
94 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
95 u32 or_value)
96 {
97 return cx18_av_write4(cx, addr,
98 (cx18_av_read4(cx, addr) & and_mask) |
99 or_value);
100 }
101
102 static int cx18_av_init(struct v4l2_subdev *sd, u32 val)
103 {
104 struct cx18 *cx = v4l2_get_subdevdata(sd);
105
106 /*
107 * The crystal freq used in calculations in this driver will be
108 * 28.636360 MHz.
109 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
110 */
111
112 /*
113 * VDCLK Integer = 0x0f, Post Divider = 0x04
114 * AIMCLK Integer = 0x0e, Post Divider = 0x16
115 */
116 cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
117
118 /* VDCLK Fraction = 0x2be2fe */
119 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
120 cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
121
122 /* AIMCLK Fraction = 0x05227ad */
123 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
124 cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
125
126 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
127 cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
128 return 0;
129 }
130
131 static void cx18_av_initialize(struct v4l2_subdev *sd)
132 {
133 struct cx18_av_state *state = to_cx18_av_state(sd);
134 struct cx18 *cx = v4l2_get_subdevdata(sd);
135 u32 v;
136
137 cx18_av_loadfw(cx);
138 /* Stop 8051 code execution */
139 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
140 0x03000000, 0x13000000);
141
142 /* initallize the PLL by toggling sleep bit */
143 v = cx18_av_read4(cx, CXADEC_HOST_REG1);
144 /* enable sleep mode - register appears to be read only... */
145 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
146 /* disable sleep mode */
147 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
148 v & 0xfffe, 0xffff);
149
150 /* initialize DLLs */
151 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
152 /* disable FLD */
153 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
154 /* enable FLD */
155 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
156
157 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
158 /* disable FLD */
159 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
160 /* enable FLD */
161 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
162
163 /* set analog bias currents. Set Vreg to 1.20V. */
164 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
165
166 v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
167 /* enable TUNE_FIL_RST */
168 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
169 /* disable TUNE_FIL_RST */
170 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
171 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
172
173 /* enable 656 output */
174 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
175
176 /* video output drive strength */
177 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
178
179 /* reset video */
180 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
181 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
182
183 /*
184 * Disable Video Auto-config of the Analog Front End and Video PLL.
185 *
186 * Since we only use BT.656 pixel mode, which works for both 525 and 625
187 * line systems, it's just easier for us to set registers
188 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
189 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
190 * ourselves, than to run around cleaning up after the auto-config.
191 *
192 * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
193 * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
194 * autoconfig either.)
195 *
196 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
197 */
198 cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
199
200 /* Setup the Video and and Aux/Audio PLLs */
201 cx18_av_init(sd, 0);
202
203 /* set video to auto-detect */
204 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
205 /* set the comb notch = 1 */
206 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
207
208 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
209 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
210 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
211
212 /* Set VGA_TRACK_RANGE to 0x20 */
213 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
214
215 /*
216 * Initial VBI setup
217 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
218 * don't clamp raw samples when codes are in use, 1 byte user D-words,
219 * IDID0 has line #, RP code V bit transition on VBLANK, data during
220 * blanking intervals
221 */
222 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
223
224 /* Set the video input.
225 The setting in MODE_CTRL gets lost when we do the above setup */
226 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
227 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
228
229 /*
230 * Analog Front End (AFE)
231 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
232 * bypass_ch[1-3] use filter
233 * droop_comp_ch[1-3] disable
234 * clamp_en_ch[1-3] disable
235 * aud_in_sel ADC2
236 * luma_in_sel ADC1
237 * chroma_in_sel ADC2
238 * clamp_sel_ch[2-3] midcode
239 * clamp_sel_ch1 video decoder
240 * vga_sel_ch3 audio decoder
241 * vga_sel_ch[1-2] video decoder
242 * half_bw_ch[1-3] disable
243 * +12db_ch[1-3] disable
244 */
245 cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
246
247 /* if(dwEnable && dw3DCombAvailable) { */
248 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
249 /* } else { */
250 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
251 /* } */
252 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
253 state->default_volume = 228 - cx18_av_read(cx, 0x8d4);
254 state->default_volume = ((state->default_volume / 2) + 23) << 9;
255 }
256
257 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
258 {
259 cx18_av_initialize(sd);
260 return 0;
261 }
262
263 static int cx18_av_load_fw(struct v4l2_subdev *sd)
264 {
265 struct cx18_av_state *state = to_cx18_av_state(sd);
266
267 if (!state->is_initialized) {
268 /* initialize on first use */
269 state->is_initialized = 1;
270 cx18_av_initialize(sd);
271 }
272 return 0;
273 }
274
275 void cx18_av_std_setup(struct cx18 *cx)
276 {
277 struct cx18_av_state *state = &cx->av_state;
278 struct v4l2_subdev *sd = &state->sd;
279 v4l2_std_id std = state->std;
280 int hblank, hactive, burst, vblank, vactive, sc;
281 int vblank656, src_decimation;
282 int luma_lpf, uv_lpf, comb;
283 u32 pll_int, pll_frac, pll_post;
284
285 /* datasheet startup, step 8d */
286 if (std & ~V4L2_STD_NTSC)
287 cx18_av_write(cx, 0x49f, 0x11);
288 else
289 cx18_av_write(cx, 0x49f, 0x14);
290
291 if (std & V4L2_STD_625_50) {
292 /* FIXME - revisit these for Sliced VBI */
293 hblank = 132;
294 hactive = 720;
295 burst = 93;
296 vblank = 36;
297 vactive = 580;
298 vblank656 = 40;
299 src_decimation = 0x21f;
300
301 luma_lpf = 2;
302 if (std & V4L2_STD_PAL) {
303 uv_lpf = 1;
304 comb = 0x20;
305 sc = 688739;
306 } else if (std == V4L2_STD_PAL_Nc) {
307 uv_lpf = 1;
308 comb = 0x20;
309 sc = 556453;
310 } else { /* SECAM */
311 uv_lpf = 0;
312 comb = 0;
313 sc = 672351;
314 }
315 } else {
316 /*
317 * The following relationships of half line counts should hold:
318 * 525 = vsync + vactive + vblank656
319 * 12 = vblank656 - vblank
320 *
321 * vsync: always 6 half-lines of vsync pulses
322 * vactive: half lines of active video
323 * vblank656: half lines, after line 3/mid-266, of blanked video
324 * vblank: half lines, after line 9/272, of blanked video
325 *
326 * As far as I can tell:
327 * vblank656 starts counting from the falling edge of the first
328 * vsync pulse (start of line 4 or mid-266)
329 * vblank starts counting from the after the 6 vsync pulses and
330 * 6 or 5 equalization pulses (start of line 10 or 272)
331 *
332 * For 525 line systems the driver will extract VBI information
333 * from lines 10-21 and lines 273-284.
334 */
335 vblank656 = 38; /* lines 4 - 22 & 266 - 284 */
336 vblank = 26; /* lines 10 - 22 & 272 - 284 */
337 vactive = 481; /* lines 23 - 263 & 285 - 525 */
338
339 /*
340 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
341 * is 858 pixels = 720 active + 138 blanking. The Hsync leading
342 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
343 * end of active video, leaving 122 pixels of hblank to ignore
344 * before active video starts.
345 */
346 hactive = 720;
347 hblank = 122;
348 luma_lpf = 1;
349 uv_lpf = 1;
350
351 src_decimation = 0x21f;
352 if (std == V4L2_STD_PAL_60) {
353 burst = 0x5b;
354 luma_lpf = 2;
355 comb = 0x20;
356 sc = 688739;
357 } else if (std == V4L2_STD_PAL_M) {
358 burst = 0x61;
359 comb = 0x20;
360 sc = 555452;
361 } else {
362 burst = 0x5b;
363 comb = 0x66;
364 sc = 556063;
365 }
366 }
367
368 /* DEBUG: Displays configured PLL frequency */
369 pll_int = cx18_av_read(cx, 0x108);
370 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
371 pll_post = cx18_av_read(cx, 0x109);
372 CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
373 pll_int, pll_frac, pll_post);
374
375 if (pll_post) {
376 int fin, fsc, pll;
377
378 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
379 pll /= pll_post;
380 CX18_DEBUG_INFO_DEV(sd, "PLL = %d.%06d MHz\n",
381 pll / 1000000, pll % 1000000);
382 CX18_DEBUG_INFO_DEV(sd, "PLL/8 = %d.%06d MHz\n",
383 pll / 8000000, (pll / 8) % 1000000);
384
385 fin = ((u64)src_decimation * pll) >> 12;
386 CX18_DEBUG_INFO_DEV(sd, "ADC Sampling freq = %d.%06d MHz\n",
387 fin / 1000000, fin % 1000000);
388
389 fsc = (((u64)sc) * pll) >> 24L;
390 CX18_DEBUG_INFO_DEV(sd,
391 "Chroma sub-carrier freq = %d.%06d MHz\n",
392 fsc / 1000000, fsc % 1000000);
393
394 CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
395 "vactive %i, vblank656 %i, src_dec %i, "
396 "burst 0x%02x, luma_lpf %i, uv_lpf %i, "
397 "comb 0x%02x, sc 0x%06x\n",
398 hblank, hactive, vblank, vactive, vblank656,
399 src_decimation, burst, luma_lpf, uv_lpf,
400 comb, sc);
401 }
402
403 /* Sets horizontal blanking delay and active lines */
404 cx18_av_write(cx, 0x470, hblank);
405 cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
406 (hactive << 4)));
407 cx18_av_write(cx, 0x472, hactive >> 4);
408
409 /* Sets burst gate delay */
410 cx18_av_write(cx, 0x473, burst);
411
412 /* Sets vertical blanking delay and active duration */
413 cx18_av_write(cx, 0x474, vblank);
414 cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
415 (vactive << 4)));
416 cx18_av_write(cx, 0x476, vactive >> 4);
417 cx18_av_write(cx, 0x477, vblank656);
418
419 /* Sets src decimation rate */
420 cx18_av_write(cx, 0x478, 0xff & src_decimation);
421 cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
422
423 /* Sets Luma and UV Low pass filters */
424 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
425
426 /* Enables comb filters */
427 cx18_av_write(cx, 0x47b, comb);
428
429 /* Sets SC Step*/
430 cx18_av_write(cx, 0x47c, sc);
431 cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
432 cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
433
434 if (std & V4L2_STD_625_50) {
435 state->slicer_line_delay = 1;
436 state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
437 } else {
438 state->slicer_line_delay = 0;
439 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
440 }
441 cx18_av_write(cx, 0x47f, state->slicer_line_delay);
442 }
443
444 static void input_change(struct cx18 *cx)
445 {
446 struct cx18_av_state *state = &cx->av_state;
447 v4l2_std_id std = state->std;
448 u8 v;
449
450 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
451 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
452 cx18_av_and_or(cx, 0x401, ~0x60, 0);
453 cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
454
455 if (std & V4L2_STD_525_60) {
456 if (std == V4L2_STD_NTSC_M_JP) {
457 /* Japan uses EIAJ audio standard */
458 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
459 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
460 } else if (std == V4L2_STD_NTSC_M_KR) {
461 /* South Korea uses A2 audio standard */
462 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
463 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
464 } else {
465 /* Others use the BTSC audio standard */
466 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
467 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
468 }
469 } else if (std & V4L2_STD_PAL) {
470 /* Follow tuner change procedure for PAL */
471 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
472 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
473 } else if (std & V4L2_STD_SECAM) {
474 /* Select autodetect for SECAM */
475 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
476 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
477 }
478
479 v = cx18_av_read(cx, 0x803);
480 if (v & 0x10) {
481 /* restart audio decoder microcontroller */
482 v &= ~0x10;
483 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
484 v |= 0x10;
485 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
486 }
487 }
488
489 static int cx18_av_s_frequency(struct v4l2_subdev *sd,
490 struct v4l2_frequency *freq)
491 {
492 struct cx18 *cx = v4l2_get_subdevdata(sd);
493 input_change(cx);
494 return 0;
495 }
496
497 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
498 enum cx18_av_audio_input aud_input)
499 {
500 struct cx18_av_state *state = &cx->av_state;
501 struct v4l2_subdev *sd = &state->sd;
502
503 enum analog_signal_type {
504 NONE, CVBS, Y, C, SIF, Pb, Pr
505 } ch[3] = {NONE, NONE, NONE};
506
507 u8 afe_mux_cfg;
508 u8 adc2_cfg;
509 u32 afe_cfg;
510 int i;
511
512 CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
513 vid_input, aud_input);
514
515 if (vid_input >= CX18_AV_COMPOSITE1 &&
516 vid_input <= CX18_AV_COMPOSITE8) {
517 afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
518 ch[0] = CVBS;
519 } else {
520 int luma = vid_input & 0xf0;
521 int chroma = vid_input & 0xf00;
522
523 if ((vid_input & ~0xff0) ||
524 luma < CX18_AV_SVIDEO_LUMA1 ||
525 luma > CX18_AV_SVIDEO_LUMA8 ||
526 chroma < CX18_AV_SVIDEO_CHROMA4 ||
527 chroma > CX18_AV_SVIDEO_CHROMA8) {
528 CX18_ERR_DEV(sd, "0x%04x is not a valid video input!\n",
529 vid_input);
530 return -EINVAL;
531 }
532 afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
533 ch[0] = Y;
534 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
535 afe_mux_cfg &= 0x3f;
536 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
537 ch[2] = C;
538 } else {
539 afe_mux_cfg &= 0xcf;
540 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
541 ch[1] = C;
542 }
543 }
544 /* TODO: LeadTek WinFast DVR3100 H & WinFast PVR2100 can do Y/Pb/Pr */
545
546 switch (aud_input) {
547 case CX18_AV_AUDIO_SERIAL1:
548 case CX18_AV_AUDIO_SERIAL2:
549 /* do nothing, use serial audio input */
550 break;
551 case CX18_AV_AUDIO4:
552 afe_mux_cfg &= ~0x30;
553 ch[1] = SIF;
554 break;
555 case CX18_AV_AUDIO5:
556 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
557 ch[1] = SIF;
558 break;
559 case CX18_AV_AUDIO6:
560 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
561 ch[1] = SIF;
562 break;
563 case CX18_AV_AUDIO7:
564 afe_mux_cfg &= ~0xc0;
565 ch[2] = SIF;
566 break;
567 case CX18_AV_AUDIO8:
568 afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
569 ch[2] = SIF;
570 break;
571
572 default:
573 CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
574 aud_input);
575 return -EINVAL;
576 }
577
578 /* Set up analog front end multiplexers */
579 cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
580 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
581 cx18_av_and_or(cx, 0x401, ~0x6, ch[0] == CVBS ? 0 : 0x02);
582
583 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
584 adc2_cfg = cx18_av_read(cx, 0x102);
585 if (ch[2] == NONE)
586 adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
587 else
588 adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */
589
590 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
591 if (ch[1] != NONE && ch[2] != NONE)
592 adc2_cfg |= 0x4; /* Set dual mode */
593 else
594 adc2_cfg &= ~0x4; /* Clear dual mode */
595 cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
596
597 /* Configure the analog front end */
598 afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
599 afe_cfg &= 0xff000000;
600 afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
601 if (ch[1] != NONE && ch[2] != NONE)
602 afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
603
604 for (i = 0; i < 3; i++) {
605 switch (ch[i]) {
606 default:
607 case NONE:
608 /* CLAMP_SEL = Fixed to midcode clamp level */
609 afe_cfg |= (0x00000200 << i);
610 break;
611 case CVBS:
612 case Y:
613 if (i > 0)
614 afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
615 break;
616 case C:
617 case Pb:
618 case Pr:
619 /* CLAMP_SEL = Fixed to midcode clamp level */
620 afe_cfg |= (0x00000200 << i);
621 if (i == 0 && ch[i] == C)
622 afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
623 break;
624 case SIF:
625 /*
626 * VGA_GAIN_SEL = Audio Decoder
627 * CLAMP_SEL = Fixed to midcode clamp level
628 */
629 afe_cfg |= (0x00000240 << i);
630 if (i == 0)
631 afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
632 break;
633 }
634 }
635
636 cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
637
638 state->vid_input = vid_input;
639 state->aud_input = aud_input;
640 cx18_av_audio_set_path(cx);
641 input_change(cx);
642 return 0;
643 }
644
645 static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
646 u32 input, u32 output, u32 config)
647 {
648 struct cx18_av_state *state = to_cx18_av_state(sd);
649 struct cx18 *cx = v4l2_get_subdevdata(sd);
650 return set_input(cx, input, state->aud_input);
651 }
652
653 static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
654 u32 input, u32 output, u32 config)
655 {
656 struct cx18_av_state *state = to_cx18_av_state(sd);
657 struct cx18 *cx = v4l2_get_subdevdata(sd);
658 return set_input(cx, state->vid_input, input);
659 }
660
661 static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
662 {
663 struct cx18_av_state *state = to_cx18_av_state(sd);
664 struct cx18 *cx = v4l2_get_subdevdata(sd);
665 u8 vpres;
666 u8 mode;
667 int val = 0;
668
669 if (state->radio)
670 return 0;
671
672 vpres = cx18_av_read(cx, 0x40e) & 0x20;
673 vt->signal = vpres ? 0xffff : 0x0;
674
675 vt->capability |=
676 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
677 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
678
679 mode = cx18_av_read(cx, 0x804);
680
681 /* get rxsubchans and audmode */
682 if ((mode & 0xf) == 1)
683 val |= V4L2_TUNER_SUB_STEREO;
684 else
685 val |= V4L2_TUNER_SUB_MONO;
686
687 if (mode == 2 || mode == 4)
688 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
689
690 if (mode & 0x10)
691 val |= V4L2_TUNER_SUB_SAP;
692
693 vt->rxsubchans = val;
694 vt->audmode = state->audmode;
695 return 0;
696 }
697
698 static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
699 {
700 struct cx18_av_state *state = to_cx18_av_state(sd);
701 struct cx18 *cx = v4l2_get_subdevdata(sd);
702 u8 v;
703
704 if (state->radio)
705 return 0;
706
707 v = cx18_av_read(cx, 0x809);
708 v &= ~0xf;
709
710 switch (vt->audmode) {
711 case V4L2_TUNER_MODE_MONO:
712 /* mono -> mono
713 stereo -> mono
714 bilingual -> lang1 */
715 break;
716 case V4L2_TUNER_MODE_STEREO:
717 case V4L2_TUNER_MODE_LANG1:
718 /* mono -> mono
719 stereo -> stereo
720 bilingual -> lang1 */
721 v |= 0x4;
722 break;
723 case V4L2_TUNER_MODE_LANG1_LANG2:
724 /* mono -> mono
725 stereo -> stereo
726 bilingual -> lang1/lang2 */
727 v |= 0x7;
728 break;
729 case V4L2_TUNER_MODE_LANG2:
730 /* mono -> mono
731 stereo -> stereo
732 bilingual -> lang2 */
733 v |= 0x1;
734 break;
735 default:
736 return -EINVAL;
737 }
738 cx18_av_write_expect(cx, 0x809, v, v, 0xff);
739 state->audmode = vt->audmode;
740 return 0;
741 }
742
743 static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
744 {
745 struct cx18_av_state *state = to_cx18_av_state(sd);
746 struct cx18 *cx = v4l2_get_subdevdata(sd);
747
748 u8 fmt = 0; /* zero is autodetect */
749 u8 pal_m = 0;
750
751 if (state->radio == 0 && state->std == norm)
752 return 0;
753
754 state->radio = 0;
755 state->std = norm;
756
757 /* First tests should be against specific std */
758 if (state->std == V4L2_STD_NTSC_M_JP) {
759 fmt = 0x2;
760 } else if (state->std == V4L2_STD_NTSC_443) {
761 fmt = 0x3;
762 } else if (state->std == V4L2_STD_PAL_M) {
763 pal_m = 1;
764 fmt = 0x5;
765 } else if (state->std == V4L2_STD_PAL_N) {
766 fmt = 0x6;
767 } else if (state->std == V4L2_STD_PAL_Nc) {
768 fmt = 0x7;
769 } else if (state->std == V4L2_STD_PAL_60) {
770 fmt = 0x8;
771 } else {
772 /* Then, test against generic ones */
773 if (state->std & V4L2_STD_NTSC)
774 fmt = 0x1;
775 else if (state->std & V4L2_STD_PAL)
776 fmt = 0x4;
777 else if (state->std & V4L2_STD_SECAM)
778 fmt = 0xc;
779 }
780
781 CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
782
783 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
784 Without this PAL may display a vertical ghosting effect.
785 This happens for example with the Yuan MPC622. */
786 if (fmt >= 4 && fmt < 8) {
787 /* Set format to NTSC-M */
788 cx18_av_and_or(cx, 0x400, ~0xf, 1);
789 /* Turn off LCOMB */
790 cx18_av_and_or(cx, 0x47b, ~6, 0);
791 }
792 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
793 cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
794 cx18_av_std_setup(cx);
795 input_change(cx);
796 return 0;
797 }
798
799 static int cx18_av_s_radio(struct v4l2_subdev *sd)
800 {
801 struct cx18_av_state *state = to_cx18_av_state(sd);
802 state->radio = 1;
803 return 0;
804 }
805
806 static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
807 {
808 struct cx18 *cx = v4l2_get_subdevdata(sd);
809
810 switch (ctrl->id) {
811 case V4L2_CID_BRIGHTNESS:
812 if (ctrl->value < 0 || ctrl->value > 255) {
813 CX18_ERR_DEV(sd, "invalid brightness setting %d\n",
814 ctrl->value);
815 return -ERANGE;
816 }
817
818 cx18_av_write(cx, 0x414, ctrl->value - 128);
819 break;
820
821 case V4L2_CID_CONTRAST:
822 if (ctrl->value < 0 || ctrl->value > 127) {
823 CX18_ERR_DEV(sd, "invalid contrast setting %d\n",
824 ctrl->value);
825 return -ERANGE;
826 }
827
828 cx18_av_write(cx, 0x415, ctrl->value << 1);
829 break;
830
831 case V4L2_CID_SATURATION:
832 if (ctrl->value < 0 || ctrl->value > 127) {
833 CX18_ERR_DEV(sd, "invalid saturation setting %d\n",
834 ctrl->value);
835 return -ERANGE;
836 }
837
838 cx18_av_write(cx, 0x420, ctrl->value << 1);
839 cx18_av_write(cx, 0x421, ctrl->value << 1);
840 break;
841
842 case V4L2_CID_HUE:
843 if (ctrl->value < -128 || ctrl->value > 127) {
844 CX18_ERR_DEV(sd, "invalid hue setting %d\n",
845 ctrl->value);
846 return -ERANGE;
847 }
848
849 cx18_av_write(cx, 0x422, ctrl->value);
850 break;
851
852 case V4L2_CID_AUDIO_VOLUME:
853 case V4L2_CID_AUDIO_BASS:
854 case V4L2_CID_AUDIO_TREBLE:
855 case V4L2_CID_AUDIO_BALANCE:
856 case V4L2_CID_AUDIO_MUTE:
857 return cx18_av_audio_s_ctrl(cx, ctrl);
858
859 default:
860 return -EINVAL;
861 }
862 return 0;
863 }
864
865 static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
866 {
867 struct cx18 *cx = v4l2_get_subdevdata(sd);
868
869 switch (ctrl->id) {
870 case V4L2_CID_BRIGHTNESS:
871 ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128;
872 break;
873 case V4L2_CID_CONTRAST:
874 ctrl->value = cx18_av_read(cx, 0x415) >> 1;
875 break;
876 case V4L2_CID_SATURATION:
877 ctrl->value = cx18_av_read(cx, 0x420) >> 1;
878 break;
879 case V4L2_CID_HUE:
880 ctrl->value = (s8)cx18_av_read(cx, 0x422);
881 break;
882 case V4L2_CID_AUDIO_VOLUME:
883 case V4L2_CID_AUDIO_BASS:
884 case V4L2_CID_AUDIO_TREBLE:
885 case V4L2_CID_AUDIO_BALANCE:
886 case V4L2_CID_AUDIO_MUTE:
887 return cx18_av_audio_g_ctrl(cx, ctrl);
888 default:
889 return -EINVAL;
890 }
891 return 0;
892 }
893
894 static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
895 {
896 struct cx18_av_state *state = to_cx18_av_state(sd);
897
898 switch (qc->id) {
899 case V4L2_CID_BRIGHTNESS:
900 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
901 case V4L2_CID_CONTRAST:
902 case V4L2_CID_SATURATION:
903 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
904 case V4L2_CID_HUE:
905 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
906 default:
907 break;
908 }
909
910 switch (qc->id) {
911 case V4L2_CID_AUDIO_VOLUME:
912 return v4l2_ctrl_query_fill(qc, 0, 65535,
913 65535 / 100, state->default_volume);
914 case V4L2_CID_AUDIO_MUTE:
915 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
916 case V4L2_CID_AUDIO_BALANCE:
917 case V4L2_CID_AUDIO_BASS:
918 case V4L2_CID_AUDIO_TREBLE:
919 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
920 default:
921 return -EINVAL;
922 }
923 return -EINVAL;
924 }
925
926 static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
927 {
928 struct cx18 *cx = v4l2_get_subdevdata(sd);
929
930 return cx18_av_vbi_g_fmt(cx, fmt);
931 }
932
933 static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
934 {
935 struct cx18_av_state *state = to_cx18_av_state(sd);
936 struct cx18 *cx = v4l2_get_subdevdata(sd);
937
938 struct v4l2_pix_format *pix;
939 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
940 int is_50Hz = !(state->std & V4L2_STD_525_60);
941
942 switch (fmt->type) {
943 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
944 pix = &(fmt->fmt.pix);
945
946 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
947 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
948
949 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
950 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
951
952 /*
953 * This adjustment reflects the excess of vactive, set in
954 * cx18_av_std_setup(), above standard values:
955 *
956 * 480 + 1 for 60 Hz systems
957 * 576 + 4 for 50 Hz systems
958 */
959 Vlines = pix->height + (is_50Hz ? 4 : 1);
960
961 /*
962 * Invalid height and width scaling requests are:
963 * 1. width less than 1/16 of the source width
964 * 2. width greater than the source width
965 * 3. height less than 1/8 of the source height
966 * 4. height greater than the source height
967 */
968 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
969 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
970 CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
971 pix->width, pix->height);
972 return -ERANGE;
973 }
974
975 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
976 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
977 VSC &= 0x1fff;
978
979 if (pix->width >= 385)
980 filter = 0;
981 else if (pix->width > 192)
982 filter = 1;
983 else if (pix->width > 96)
984 filter = 2;
985 else
986 filter = 3;
987
988 CX18_DEBUG_INFO_DEV(sd,
989 "decoder set size %dx%d -> scale %ux%u\n",
990 pix->width, pix->height, HSC, VSC);
991
992 /* HSCALE=HSC */
993 cx18_av_write(cx, 0x418, HSC & 0xff);
994 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
995 cx18_av_write(cx, 0x41a, HSC >> 16);
996 /* VSCALE=VSC */
997 cx18_av_write(cx, 0x41c, VSC & 0xff);
998 cx18_av_write(cx, 0x41d, VSC >> 8);
999 /* VS_INTRLACE=1 VFILT=filter */
1000 cx18_av_write(cx, 0x41e, 0x8 | filter);
1001 break;
1002
1003 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
1004 return cx18_av_vbi_s_fmt(cx, fmt);
1005
1006 case V4L2_BUF_TYPE_VBI_CAPTURE:
1007 return cx18_av_vbi_s_fmt(cx, fmt);
1008
1009 default:
1010 return -EINVAL;
1011 }
1012 return 0;
1013 }
1014
1015 static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
1016 {
1017 struct cx18 *cx = v4l2_get_subdevdata(sd);
1018
1019 CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
1020 if (enable) {
1021 cx18_av_write(cx, 0x115, 0x8c);
1022 cx18_av_write(cx, 0x116, 0x07);
1023 } else {
1024 cx18_av_write(cx, 0x115, 0x00);
1025 cx18_av_write(cx, 0x116, 0x00);
1026 }
1027 return 0;
1028 }
1029
1030 static void log_video_status(struct cx18 *cx)
1031 {
1032 static const char *const fmt_strs[] = {
1033 "0x0",
1034 "NTSC-M", "NTSC-J", "NTSC-4.43",
1035 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1036 "0x9", "0xA", "0xB",
1037 "SECAM",
1038 "0xD", "0xE", "0xF"
1039 };
1040
1041 struct cx18_av_state *state = &cx->av_state;
1042 struct v4l2_subdev *sd = &state->sd;
1043 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
1044 u8 gen_stat1 = cx18_av_read(cx, 0x40d);
1045 u8 gen_stat2 = cx18_av_read(cx, 0x40e);
1046 int vid_input = state->vid_input;
1047
1048 CX18_INFO_DEV(sd, "Video signal: %spresent\n",
1049 (gen_stat2 & 0x20) ? "" : "not ");
1050 CX18_INFO_DEV(sd, "Detected format: %s\n",
1051 fmt_strs[gen_stat1 & 0xf]);
1052
1053 CX18_INFO_DEV(sd, "Specified standard: %s\n",
1054 vidfmt_sel ? fmt_strs[vidfmt_sel]
1055 : "automatic detection");
1056
1057 if (vid_input >= CX18_AV_COMPOSITE1 &&
1058 vid_input <= CX18_AV_COMPOSITE8) {
1059 CX18_INFO_DEV(sd, "Specified video input: Composite %d\n",
1060 vid_input - CX18_AV_COMPOSITE1 + 1);
1061 } else {
1062 CX18_INFO_DEV(sd, "Specified video input: "
1063 "S-Video (Luma In%d, Chroma In%d)\n",
1064 (vid_input & 0xf0) >> 4,
1065 (vid_input & 0xf00) >> 8);
1066 }
1067
1068 CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
1069 state->audclk_freq);
1070 }
1071
1072 static void log_audio_status(struct cx18 *cx)
1073 {
1074 struct cx18_av_state *state = &cx->av_state;
1075 struct v4l2_subdev *sd = &state->sd;
1076 u8 download_ctl = cx18_av_read(cx, 0x803);
1077 u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
1078 u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1079 u8 audio_config = cx18_av_read(cx, 0x808);
1080 u8 pref_mode = cx18_av_read(cx, 0x809);
1081 u8 afc0 = cx18_av_read(cx, 0x80b);
1082 u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1083 int aud_input = state->aud_input;
1084 char *p;
1085
1086 switch (mod_det_stat0) {
1087 case 0x00: p = "mono"; break;
1088 case 0x01: p = "stereo"; break;
1089 case 0x02: p = "dual"; break;
1090 case 0x04: p = "tri"; break;
1091 case 0x10: p = "mono with SAP"; break;
1092 case 0x11: p = "stereo with SAP"; break;
1093 case 0x12: p = "dual with SAP"; break;
1094 case 0x14: p = "tri with SAP"; break;
1095 case 0xfe: p = "forced mode"; break;
1096 default: p = "not defined"; break;
1097 }
1098 CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p);
1099
1100 switch (mod_det_stat1) {
1101 case 0x00: p = "not defined"; break;
1102 case 0x01: p = "EIAJ"; break;
1103 case 0x02: p = "A2-M"; break;
1104 case 0x03: p = "A2-BG"; break;
1105 case 0x04: p = "A2-DK1"; break;
1106 case 0x05: p = "A2-DK2"; break;
1107 case 0x06: p = "A2-DK3"; break;
1108 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1109 case 0x08: p = "AM-L"; break;
1110 case 0x09: p = "NICAM-BG"; break;
1111 case 0x0a: p = "NICAM-DK"; break;
1112 case 0x0b: p = "NICAM-I"; break;
1113 case 0x0c: p = "NICAM-L"; break;
1114 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1115 case 0x0e: p = "IF FM Radio"; break;
1116 case 0x0f: p = "BTSC"; break;
1117 case 0x10: p = "detected chrominance"; break;
1118 case 0xfd: p = "unknown audio standard"; break;
1119 case 0xfe: p = "forced audio standard"; break;
1120 case 0xff: p = "no detected audio standard"; break;
1121 default: p = "not defined"; break;
1122 }
1123 CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p);
1124 CX18_INFO_DEV(sd, "Audio muted: %s\n",
1125 (mute_ctl & 0x2) ? "yes" : "no");
1126 CX18_INFO_DEV(sd, "Audio microcontroller: %s\n",
1127 (download_ctl & 0x10) ? "running" : "stopped");
1128
1129 switch (audio_config >> 4) {
1130 case 0x00: p = "undefined"; break;
1131 case 0x01: p = "BTSC"; break;
1132 case 0x02: p = "EIAJ"; break;
1133 case 0x03: p = "A2-M"; break;
1134 case 0x04: p = "A2-BG"; break;
1135 case 0x05: p = "A2-DK1"; break;
1136 case 0x06: p = "A2-DK2"; break;
1137 case 0x07: p = "A2-DK3"; break;
1138 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1139 case 0x09: p = "AM-L"; break;
1140 case 0x0a: p = "NICAM-BG"; break;
1141 case 0x0b: p = "NICAM-DK"; break;
1142 case 0x0c: p = "NICAM-I"; break;
1143 case 0x0d: p = "NICAM-L"; break;
1144 case 0x0e: p = "FM radio"; break;
1145 case 0x0f: p = "automatic detection"; break;
1146 default: p = "undefined"; break;
1147 }
1148 CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
1149
1150 if ((audio_config >> 4) < 0xF) {
1151 switch (audio_config & 0xF) {
1152 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1153 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1154 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1155 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1156 case 0x04: p = "STEREO"; break;
1157 case 0x05: p = "DUAL1 (AC)"; break;
1158 case 0x06: p = "DUAL2 (BC)"; break;
1159 case 0x07: p = "DUAL3 (AB)"; break;
1160 default: p = "undefined";
1161 }
1162 CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p);
1163 } else {
1164 switch (audio_config & 0xF) {
1165 case 0x00: p = "BG"; break;
1166 case 0x01: p = "DK1"; break;
1167 case 0x02: p = "DK2"; break;
1168 case 0x03: p = "DK3"; break;
1169 case 0x04: p = "I"; break;
1170 case 0x05: p = "L"; break;
1171 case 0x06: p = "BTSC"; break;
1172 case 0x07: p = "EIAJ"; break;
1173 case 0x08: p = "A2-M"; break;
1174 case 0x09: p = "FM Radio (4.5 MHz)"; break;
1175 case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1176 case 0x0b: p = "S-Video"; break;
1177 case 0x0f: p = "automatic standard and mode detection"; break;
1178 default: p = "undefined"; break;
1179 }
1180 CX18_INFO_DEV(sd, "Configured audio system: %s\n", p);
1181 }
1182
1183 if (aud_input)
1184 CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n",
1185 aud_input);
1186 else
1187 CX18_INFO_DEV(sd, "Specified audio input: External\n");
1188
1189 switch (pref_mode & 0xf) {
1190 case 0: p = "mono/language A"; break;
1191 case 1: p = "language B"; break;
1192 case 2: p = "language C"; break;
1193 case 3: p = "analog fallback"; break;
1194 case 4: p = "stereo"; break;
1195 case 5: p = "language AC"; break;
1196 case 6: p = "language BC"; break;
1197 case 7: p = "language AB"; break;
1198 default: p = "undefined"; break;
1199 }
1200 CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p);
1201
1202 if ((audio_config & 0xf) == 0xf) {
1203 switch ((afc0 >> 3) & 0x1) {
1204 case 0: p = "system DK"; break;
1205 case 1: p = "system L"; break;
1206 }
1207 CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p);
1208
1209 switch (afc0 & 0x7) {
1210 case 0: p = "Chroma"; break;
1211 case 1: p = "BTSC"; break;
1212 case 2: p = "EIAJ"; break;
1213 case 3: p = "A2-M"; break;
1214 case 4: p = "autodetect"; break;
1215 default: p = "undefined"; break;
1216 }
1217 CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p);
1218 }
1219 }
1220
1221 static int cx18_av_log_status(struct v4l2_subdev *sd)
1222 {
1223 struct cx18 *cx = v4l2_get_subdevdata(sd);
1224 log_video_status(cx);
1225 log_audio_status(cx);
1226 return 0;
1227 }
1228
1229 static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match)
1230 {
1231 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1;
1232 }
1233
1234 static int cx18_av_g_chip_ident(struct v4l2_subdev *sd,
1235 struct v4l2_dbg_chip_ident *chip)
1236 {
1237 struct cx18_av_state *state = to_cx18_av_state(sd);
1238
1239 if (cx18_av_dbg_match(&chip->match)) {
1240 chip->ident = state->id;
1241 chip->revision = state->rev;
1242 }
1243 return 0;
1244 }
1245
1246 #ifdef CONFIG_VIDEO_ADV_DEBUG
1247 static int cx18_av_g_register(struct v4l2_subdev *sd,
1248 struct v4l2_dbg_register *reg)
1249 {
1250 struct cx18 *cx = v4l2_get_subdevdata(sd);
1251
1252 if (!cx18_av_dbg_match(&reg->match))
1253 return -EINVAL;
1254 if ((reg->reg & 0x3) != 0)
1255 return -EINVAL;
1256 if (!capable(CAP_SYS_ADMIN))
1257 return -EPERM;
1258 reg->size = 4;
1259 reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1260 return 0;
1261 }
1262
1263 static int cx18_av_s_register(struct v4l2_subdev *sd,
1264 struct v4l2_dbg_register *reg)
1265 {
1266 struct cx18 *cx = v4l2_get_subdevdata(sd);
1267
1268 if (!cx18_av_dbg_match(&reg->match))
1269 return -EINVAL;
1270 if ((reg->reg & 0x3) != 0)
1271 return -EINVAL;
1272 if (!capable(CAP_SYS_ADMIN))
1273 return -EPERM;
1274 cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1275 return 0;
1276 }
1277 #endif
1278
1279 static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1280 .g_chip_ident = cx18_av_g_chip_ident,
1281 .log_status = cx18_av_log_status,
1282 .init = cx18_av_init,
1283 .load_fw = cx18_av_load_fw,
1284 .reset = cx18_av_reset,
1285 .queryctrl = cx18_av_queryctrl,
1286 .g_ctrl = cx18_av_g_ctrl,
1287 .s_ctrl = cx18_av_s_ctrl,
1288 .s_std = cx18_av_s_std,
1289 #ifdef CONFIG_VIDEO_ADV_DEBUG
1290 .g_register = cx18_av_g_register,
1291 .s_register = cx18_av_s_register,
1292 #endif
1293 };
1294
1295 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1296 .s_radio = cx18_av_s_radio,
1297 .s_frequency = cx18_av_s_frequency,
1298 .g_tuner = cx18_av_g_tuner,
1299 .s_tuner = cx18_av_s_tuner,
1300 };
1301
1302 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1303 .s_clock_freq = cx18_av_s_clock_freq,
1304 .s_routing = cx18_av_s_audio_routing,
1305 };
1306
1307 static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1308 .s_routing = cx18_av_s_video_routing,
1309 .decode_vbi_line = cx18_av_decode_vbi_line,
1310 .s_stream = cx18_av_s_stream,
1311 .g_fmt = cx18_av_g_fmt,
1312 .s_fmt = cx18_av_s_fmt,
1313 };
1314
1315 static const struct v4l2_subdev_ops cx18_av_ops = {
1316 .core = &cx18_av_general_ops,
1317 .tuner = &cx18_av_tuner_ops,
1318 .audio = &cx18_av_audio_ops,
1319 .video = &cx18_av_video_ops,
1320 };
1321
1322 int cx18_av_probe(struct cx18 *cx)
1323 {
1324 struct cx18_av_state *state = &cx->av_state;
1325 struct v4l2_subdev *sd;
1326
1327 state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1328 state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO)
1329 ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN;
1330
1331 state->vid_input = CX18_AV_COMPOSITE7;
1332 state->aud_input = CX18_AV_AUDIO8;
1333 state->audclk_freq = 48000;
1334 state->audmode = V4L2_TUNER_MODE_LANG1;
1335 state->slicer_line_delay = 0;
1336 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
1337
1338 sd = &state->sd;
1339 v4l2_subdev_init(sd, &cx18_av_ops);
1340 v4l2_set_subdevdata(sd, cx);
1341 snprintf(sd->name, sizeof(sd->name),
1342 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
1343 sd->grp_id = CX18_HW_418_AV;
1344 return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1345 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree