2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
100 #include <linux/pm.h>
103 #include "s3c2410fb.h"
106 static struct s3c2410fb_mach_info
*mach_info
;
108 /* Debugging stuff */
109 #ifdef CONFIG_FB_S3C2410_DEBUG
110 static int debug
= 1;
112 static int debug
= 0;
115 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
117 /* useful functions */
119 /* s3c2410fb_set_lcdaddr
121 * initialise lcd controller address pointers
124 static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info
*fbi
)
126 struct fb_var_screeninfo
*var
= &fbi
->fb
->var
;
127 unsigned long saddr1
, saddr2
, saddr3
;
129 saddr1
= fbi
->fb
->fix
.smem_start
>> 1;
130 saddr2
= fbi
->fb
->fix
.smem_start
;
131 saddr2
+= (var
->xres
* var
->yres
* var
->bits_per_pixel
)/8;
134 saddr3
= S3C2410_OFFSIZE(0) | S3C2410_PAGEWIDTH(var
->xres
);
136 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1
);
137 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2
);
138 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3
);
140 writel(saddr1
, S3C2410_LCDSADDR1
);
141 writel(saddr2
, S3C2410_LCDSADDR2
);
142 writel(saddr3
, S3C2410_LCDSADDR3
);
145 /* s3c2410fb_calc_pixclk()
147 * calculate divisor for clk->pixclk
150 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info
*fbi
,
151 unsigned long pixclk
)
153 unsigned long clk
= clk_get_rate(fbi
->clk
);
154 unsigned long long div
;
156 /* pixclk is in picoseoncds, our clock is in Hz
158 * Hz -> picoseconds is / 10^-12
161 div
= (unsigned long long)clk
* pixclk
;
162 do_div(div
,1000000UL);
163 do_div(div
,1000000UL);
165 dprintk("pixclk %ld, divisor is %ld\n", pixclk
, (long)div
);
170 * s3c2410fb_check_var():
171 * Get the video params out of 'var'. If a value doesn't fit, round it up,
172 * if it's too big, return -EINVAL.
175 static int s3c2410fb_check_var(struct fb_var_screeninfo
*var
,
176 struct fb_info
*info
)
178 struct s3c2410fb_info
*fbi
= info
->par
;
180 dprintk("check_var(var=%p, info=%p)\n", var
, info
);
182 /* validate x/y resolution */
184 if (var
->yres
> fbi
->mach_info
->yres
.max
)
185 var
->yres
= fbi
->mach_info
->yres
.max
;
186 else if (var
->yres
< fbi
->mach_info
->yres
.min
)
187 var
->yres
= fbi
->mach_info
->yres
.min
;
189 if (var
->xres
> fbi
->mach_info
->xres
.max
)
190 var
->yres
= fbi
->mach_info
->xres
.max
;
191 else if (var
->xres
< fbi
->mach_info
->xres
.min
)
192 var
->xres
= fbi
->mach_info
->xres
.min
;
196 if (var
->bits_per_pixel
> fbi
->mach_info
->bpp
.max
)
197 var
->bits_per_pixel
= fbi
->mach_info
->bpp
.max
;
198 else if (var
->bits_per_pixel
< fbi
->mach_info
->bpp
.min
)
199 var
->bits_per_pixel
= fbi
->mach_info
->bpp
.min
;
201 /* set r/g/b positions */
203 if (var
->bits_per_pixel
== 16) {
204 var
->red
.offset
= 11;
205 var
->green
.offset
= 5;
206 var
->blue
.offset
= 0;
208 var
->green
.length
= 6;
209 var
->blue
.length
= 5;
210 var
->transp
.length
= 0;
212 var
->red
.length
= var
->bits_per_pixel
;
214 var
->green
.length
= var
->bits_per_pixel
;
215 var
->green
.offset
= 0;
216 var
->blue
.length
= var
->bits_per_pixel
;
217 var
->blue
.offset
= 0;
218 var
->transp
.length
= 0;
224 /* s3c2410fb_activate_var
226 * activate (set) the controller from the given framebuffer
230 static void s3c2410fb_activate_var(struct s3c2410fb_info
*fbi
,
231 struct fb_var_screeninfo
*var
)
233 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_MODEMASK
;
235 dprintk("%s: var->xres = %d\n", __FUNCTION__
, var
->xres
);
236 dprintk("%s: var->yres = %d\n", __FUNCTION__
, var
->yres
);
237 dprintk("%s: var->bpp = %d\n", __FUNCTION__
, var
->bits_per_pixel
);
239 switch (var
->bits_per_pixel
) {
241 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT1BPP
;
244 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT2BPP
;
247 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT4BPP
;
250 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT8BPP
;
253 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_TFT16BPP
;
257 /* check to see if we need to update sync/borders */
259 if (!fbi
->mach_info
->fixed_syncs
) {
260 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
261 var
->upper_margin
, var
->lower_margin
,
264 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
265 var
->left_margin
, var
->right_margin
,
269 S3C2410_LCDCON2_VBPD(var
->upper_margin
- 1) |
270 S3C2410_LCDCON2_VFPD(var
->lower_margin
- 1) |
271 S3C2410_LCDCON2_VSPW(var
->vsync_len
- 1);
274 S3C2410_LCDCON3_HBPD(var
->right_margin
- 1) |
275 S3C2410_LCDCON3_HFPD(var
->left_margin
- 1);
277 fbi
->regs
.lcdcon4
&= ~S3C2410_LCDCON4_HSPW(0xff);
278 fbi
->regs
.lcdcon4
|= S3C2410_LCDCON4_HSPW(var
->hsync_len
- 1);
281 /* update X/Y info */
283 fbi
->regs
.lcdcon2
&= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
284 fbi
->regs
.lcdcon2
|= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1);
286 fbi
->regs
.lcdcon3
&= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
287 fbi
->regs
.lcdcon3
|= S3C2410_LCDCON3_HOZVAL(var
->xres
- 1);
289 if (var
->pixclock
> 0) {
290 int clkdiv
= s3c2410fb_calc_pixclk(fbi
, var
->pixclock
);
292 clkdiv
= (clkdiv
/ 2) -1;
296 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
297 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_CLKVAL(clkdiv
);
300 /* write new registers */
302 dprintk("new register set:\n");
303 dprintk("lcdcon[1] = 0x%08lx\n", fbi
->regs
.lcdcon1
);
304 dprintk("lcdcon[2] = 0x%08lx\n", fbi
->regs
.lcdcon2
);
305 dprintk("lcdcon[3] = 0x%08lx\n", fbi
->regs
.lcdcon3
);
306 dprintk("lcdcon[4] = 0x%08lx\n", fbi
->regs
.lcdcon4
);
307 dprintk("lcdcon[5] = 0x%08lx\n", fbi
->regs
.lcdcon5
);
309 writel(fbi
->regs
.lcdcon1
& ~S3C2410_LCDCON1_ENVID
, S3C2410_LCDCON1
);
310 writel(fbi
->regs
.lcdcon2
, S3C2410_LCDCON2
);
311 writel(fbi
->regs
.lcdcon3
, S3C2410_LCDCON3
);
312 writel(fbi
->regs
.lcdcon4
, S3C2410_LCDCON4
);
313 writel(fbi
->regs
.lcdcon5
, S3C2410_LCDCON5
);
315 /* set lcd address pointers */
316 s3c2410fb_set_lcdaddr(fbi
);
318 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
323 * s3c2410fb_set_par - Optional function. Alters the hardware state.
324 * @info: frame buffer structure that represents a single frame buffer
327 static int s3c2410fb_set_par(struct fb_info
*info
)
329 struct s3c2410fb_info
*fbi
= info
->par
;
330 struct fb_var_screeninfo
*var
= &info
->var
;
332 if (var
->bits_per_pixel
== 16)
333 fbi
->fb
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
335 fbi
->fb
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
337 fbi
->fb
->fix
.line_length
= (var
->width
*var
->bits_per_pixel
)/8;
339 /* activate this new configuration */
341 s3c2410fb_activate_var(fbi
, var
);
345 static void schedule_palette_update(struct s3c2410fb_info
*fbi
,
346 unsigned int regno
, unsigned int val
)
351 local_irq_save(flags
);
353 fbi
->palette_buffer
[regno
] = val
;
355 if (!fbi
->palette_ready
) {
356 fbi
->palette_ready
= 1;
359 irqen
= readl(S3C2410_LCDINTMSK
);
360 irqen
&= ~S3C2410_LCDINT_FRSYNC
;
361 writel(irqen
, S3C2410_LCDINTMSK
);
364 local_irq_restore(flags
);
368 static inline unsigned int chan_to_field(unsigned int chan
, struct fb_bitfield
*bf
)
371 chan
>>= 16 - bf
->length
;
372 return chan
<< bf
->offset
;
375 static int s3c2410fb_setcolreg(unsigned regno
,
376 unsigned red
, unsigned green
, unsigned blue
,
377 unsigned transp
, struct fb_info
*info
)
379 struct s3c2410fb_info
*fbi
= info
->par
;
382 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", regno, red, green, blue); */
384 switch (fbi
->fb
->fix
.visual
) {
385 case FB_VISUAL_TRUECOLOR
:
386 /* true-colour, use pseuo-palette */
389 u32
*pal
= fbi
->fb
->pseudo_palette
;
391 val
= chan_to_field(red
, &fbi
->fb
->var
.red
);
392 val
|= chan_to_field(green
, &fbi
->fb
->var
.green
);
393 val
|= chan_to_field(blue
, &fbi
->fb
->var
.blue
);
399 case FB_VISUAL_PSEUDOCOLOR
:
401 /* currently assume RGB 5-6-5 mode */
403 val
= ((red
>> 0) & 0xf800);
404 val
|= ((green
>> 5) & 0x07e0);
405 val
|= ((blue
>> 11) & 0x001f);
407 writel(val
, S3C2410_TFTPAL(regno
));
408 schedule_palette_update(fbi
, regno
, val
);
414 return 1; /* unknown type */
423 * @blank_mode: the blank mode we want.
424 * @info: frame buffer structure that represents a single frame buffer
426 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
427 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
428 * video mode which doesn't support it. Implements VESA suspend
429 * and powerdown modes on hardware that supports disabling hsync/vsync:
430 * blank_mode == 2: suspend vsync
431 * blank_mode == 3: suspend hsync
432 * blank_mode == 4: powerdown
434 * Returns negative errno on error, or zero on success.
437 static int s3c2410fb_blank(int blank_mode
, struct fb_info
*info
)
439 dprintk("blank(mode=%d, info=%p)\n", blank_mode
, info
);
441 if (mach_info
== NULL
)
444 if (blank_mode
== FB_BLANK_UNBLANK
)
445 writel(0x0, S3C2410_TPAL
);
447 dprintk("setting TPAL to output 0x000000\n");
448 writel(S3C2410_TPAL_EN
, S3C2410_TPAL
);
454 static int s3c2410fb_debug_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
456 return snprintf(buf
, PAGE_SIZE
, "%s\n", debug
? "on" : "off");
458 static int s3c2410fb_debug_store(struct device
*dev
, struct device_attribute
*attr
,
459 const char *buf
, size_t len
)
461 if (mach_info
== NULL
)
467 if (strnicmp(buf
, "on", 2) == 0 ||
468 strnicmp(buf
, "1", 1) == 0) {
470 printk(KERN_DEBUG
"s3c2410fb: Debug On");
471 } else if (strnicmp(buf
, "off", 3) == 0 ||
472 strnicmp(buf
, "0", 1) == 0) {
474 printk(KERN_DEBUG
"s3c2410fb: Debug Off");
483 static DEVICE_ATTR(debug
, 0666,
484 s3c2410fb_debug_show
,
485 s3c2410fb_debug_store
);
487 static struct fb_ops s3c2410fb_ops
= {
488 .owner
= THIS_MODULE
,
489 .fb_check_var
= s3c2410fb_check_var
,
490 .fb_set_par
= s3c2410fb_set_par
,
491 .fb_blank
= s3c2410fb_blank
,
492 .fb_setcolreg
= s3c2410fb_setcolreg
,
493 .fb_fillrect
= cfb_fillrect
,
494 .fb_copyarea
= cfb_copyarea
,
495 .fb_imageblit
= cfb_imageblit
,
500 * s3c2410fb_map_video_memory():
501 * Allocates the DRAM memory for the frame buffer. This buffer is
502 * remapped into a non-cached, non-buffered, memory region to
503 * allow palette and pixel writes to occur without flushing the
504 * cache. Once this area is remapped, all virtual memory
505 * access to the video memory should occur at the new region.
507 static int __init
s3c2410fb_map_video_memory(struct s3c2410fb_info
*fbi
)
509 dprintk("map_video_memory(fbi=%p)\n", fbi
);
511 fbi
->map_size
= PAGE_ALIGN(fbi
->fb
->fix
.smem_len
+ PAGE_SIZE
);
512 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
513 &fbi
->map_dma
, GFP_KERNEL
);
515 fbi
->map_size
= fbi
->fb
->fix
.smem_len
;
518 /* prevent initial garbage on screen */
519 dprintk("map_video_memory: clear %p:%08x\n",
520 fbi
->map_cpu
, fbi
->map_size
);
521 memset(fbi
->map_cpu
, 0xf0, fbi
->map_size
);
523 fbi
->screen_dma
= fbi
->map_dma
;
524 fbi
->fb
->screen_base
= fbi
->map_cpu
;
525 fbi
->fb
->fix
.smem_start
= fbi
->screen_dma
;
527 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
528 fbi
->map_dma
, fbi
->map_cpu
, fbi
->fb
->fix
.smem_len
);
531 return fbi
->map_cpu
? 0 : -ENOMEM
;
534 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info
*fbi
)
536 dma_free_writecombine(fbi
->dev
,fbi
->map_size
,fbi
->map_cpu
, fbi
->map_dma
);
539 static inline void modify_gpio(void __iomem
*reg
,
540 unsigned long set
, unsigned long mask
)
544 tmp
= readl(reg
) & ~mask
;
545 writel(tmp
| set
, reg
);
550 * s3c2410fb_init_registers - Initialise all LCD-related registers
553 static int s3c2410fb_init_registers(struct s3c2410fb_info
*fbi
)
557 /* Initialise LCD with values from haret */
559 local_irq_save(flags
);
561 /* modify the gpio(s) with interrupts set (bjd) */
563 modify_gpio(S3C2410_GPCUP
, mach_info
->gpcup
, mach_info
->gpcup_mask
);
564 modify_gpio(S3C2410_GPCCON
, mach_info
->gpccon
, mach_info
->gpccon_mask
);
565 modify_gpio(S3C2410_GPDUP
, mach_info
->gpdup
, mach_info
->gpdup_mask
);
566 modify_gpio(S3C2410_GPDCON
, mach_info
->gpdcon
, mach_info
->gpdcon_mask
);
568 local_irq_restore(flags
);
570 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
571 writel(fbi
->regs
.lcdcon2
, S3C2410_LCDCON2
);
572 writel(fbi
->regs
.lcdcon3
, S3C2410_LCDCON3
);
573 writel(fbi
->regs
.lcdcon4
, S3C2410_LCDCON4
);
574 writel(fbi
->regs
.lcdcon5
, S3C2410_LCDCON5
);
576 s3c2410fb_set_lcdaddr(fbi
);
578 dprintk("LPCSEL = 0x%08lx\n", mach_info
->lpcsel
);
579 writel(mach_info
->lpcsel
, S3C2410_LPCSEL
);
581 dprintk("replacing TPAL %08x\n", readl(S3C2410_TPAL
));
583 /* ensure temporary palette disabled */
584 writel(0x00, S3C2410_TPAL
);
586 /* Enable video by setting the ENVID bit to 1 */
587 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
;
588 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
592 static void s3c2410fb_write_palette(struct s3c2410fb_info
*fbi
)
597 fbi
->palette_ready
= 0;
599 for (i
= 0; i
< 256; i
++) {
600 if ((ent
= fbi
->palette_buffer
[i
]) == PALETTE_BUFF_CLEAR
)
603 writel(ent
, S3C2410_TFTPAL(i
));
605 /* it seems the only way to know exactly
606 * if the palette wrote ok, is to check
607 * to see if the value verifies ok
610 if (readw(S3C2410_TFTPAL(i
)) == ent
)
611 fbi
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
613 fbi
->palette_ready
= 1; /* retry */
617 static irqreturn_t
s3c2410fb_irq(int irq
, void *dev_id
, struct pt_regs
*r
)
619 struct s3c2410fb_info
*fbi
= dev_id
;
620 unsigned long lcdirq
= readl(S3C2410_LCDINTPND
);
622 if (lcdirq
& S3C2410_LCDINT_FRSYNC
) {
623 if (fbi
->palette_ready
)
624 s3c2410fb_write_palette(fbi
);
626 writel(S3C2410_LCDINT_FRSYNC
, S3C2410_LCDINTPND
);
627 writel(S3C2410_LCDINT_FRSYNC
, S3C2410_LCDSRCPND
);
633 static char driver_name
[]="s3c2410fb";
635 static int __init
s3c2410fb_probe(struct platform_device
*pdev
)
637 struct s3c2410fb_info
*info
;
638 struct fb_info
*fbinfo
;
639 struct s3c2410fb_hw
*mregs
;
645 mach_info
= pdev
->dev
.platform_data
;
646 if (mach_info
== NULL
) {
647 dev_err(&pdev
->dev
,"no platform data for lcd, cannot attach\n");
651 mregs
= &mach_info
->regs
;
653 irq
= platform_get_irq(pdev
, 0);
655 dev_err(&pdev
->dev
, "no irq for device\n");
659 fbinfo
= framebuffer_alloc(sizeof(struct s3c2410fb_info
), &pdev
->dev
);
667 platform_set_drvdata(pdev
, fbinfo
);
669 dprintk("devinit\n");
671 strcpy(fbinfo
->fix
.id
, driver_name
);
673 memcpy(&info
->regs
, &mach_info
->regs
, sizeof(info
->regs
));
675 /* Stop the video and unset ENVID if set */
676 info
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
677 lcdcon1
= readl(S3C2410_LCDCON1
);
678 writel(lcdcon1
& ~S3C2410_LCDCON1_ENVID
, S3C2410_LCDCON1
);
680 info
->mach_info
= pdev
->dev
.platform_data
;
682 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
683 fbinfo
->fix
.type_aux
= 0;
684 fbinfo
->fix
.xpanstep
= 0;
685 fbinfo
->fix
.ypanstep
= 0;
686 fbinfo
->fix
.ywrapstep
= 0;
687 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
689 fbinfo
->var
.nonstd
= 0;
690 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
691 fbinfo
->var
.height
= mach_info
->height
;
692 fbinfo
->var
.width
= mach_info
->width
;
693 fbinfo
->var
.accel_flags
= 0;
694 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
696 fbinfo
->fbops
= &s3c2410fb_ops
;
697 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
698 fbinfo
->pseudo_palette
= &info
->pseudo_pal
;
700 fbinfo
->var
.xres
= mach_info
->xres
.defval
;
701 fbinfo
->var
.xres_virtual
= mach_info
->xres
.defval
;
702 fbinfo
->var
.yres
= mach_info
->yres
.defval
;
703 fbinfo
->var
.yres_virtual
= mach_info
->yres
.defval
;
704 fbinfo
->var
.bits_per_pixel
= mach_info
->bpp
.defval
;
706 fbinfo
->var
.upper_margin
= S3C2410_LCDCON2_GET_VBPD(mregs
->lcdcon2
) + 1;
707 fbinfo
->var
.lower_margin
= S3C2410_LCDCON2_GET_VFPD(mregs
->lcdcon2
) + 1;
708 fbinfo
->var
.vsync_len
= S3C2410_LCDCON2_GET_VSPW(mregs
->lcdcon2
) + 1;
710 fbinfo
->var
.left_margin
= S3C2410_LCDCON3_GET_HFPD(mregs
->lcdcon3
) + 1;
711 fbinfo
->var
.right_margin
= S3C2410_LCDCON3_GET_HBPD(mregs
->lcdcon3
) + 1;
712 fbinfo
->var
.hsync_len
= S3C2410_LCDCON4_GET_HSPW(mregs
->lcdcon4
) + 1;
714 fbinfo
->var
.red
.offset
= 11;
715 fbinfo
->var
.green
.offset
= 5;
716 fbinfo
->var
.blue
.offset
= 0;
717 fbinfo
->var
.transp
.offset
= 0;
718 fbinfo
->var
.red
.length
= 5;
719 fbinfo
->var
.green
.length
= 6;
720 fbinfo
->var
.blue
.length
= 5;
721 fbinfo
->var
.transp
.length
= 0;
722 fbinfo
->fix
.smem_len
= mach_info
->xres
.max
*
723 mach_info
->yres
.max
*
724 mach_info
->bpp
.max
/ 8;
726 for (i
= 0; i
< 256; i
++)
727 info
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
729 if (!request_mem_region((unsigned long)S3C24XX_VA_LCD
, SZ_1M
, "s3c2410-lcd")) {
735 dprintk("got LCD region\n");
737 ret
= request_irq(irq
, s3c2410fb_irq
, IRQF_DISABLED
, pdev
->name
, info
);
739 dev_err(&pdev
->dev
, "cannot get irq %d - err %d\n", irq
, ret
);
744 info
->clk
= clk_get(NULL
, "lcd");
745 if (!info
->clk
|| IS_ERR(info
->clk
)) {
746 printk(KERN_ERR
"failed to get lcd clock source\n");
751 clk_enable(info
->clk
);
752 dprintk("got and enabled clock\n");
756 /* Initialize video memory */
757 ret
= s3c2410fb_map_video_memory(info
);
759 printk( KERN_ERR
"Failed to allocate video RAM: %d\n", ret
);
763 dprintk("got video memory\n");
765 ret
= s3c2410fb_init_registers(info
);
767 ret
= s3c2410fb_check_var(&fbinfo
->var
, fbinfo
);
769 ret
= register_framebuffer(fbinfo
);
771 printk(KERN_ERR
"Failed to register framebuffer device: %d\n", ret
);
772 goto free_video_memory
;
775 /* create device files */
776 device_create_file(&pdev
->dev
, &dev_attr_debug
);
778 printk(KERN_INFO
"fb%d: %s frame buffer device\n",
779 fbinfo
->node
, fbinfo
->fix
.id
);
784 s3c2410fb_unmap_video_memory(info
);
786 clk_disable(info
->clk
);
791 release_mem_region((unsigned long)S3C24XX_VA_LCD
, S3C24XX_SZ_LCD
);
793 framebuffer_release(fbinfo
);
797 /* s3c2410fb_stop_lcd
799 * shutdown the lcd controller
802 static void s3c2410fb_stop_lcd(struct s3c2410fb_info
*fbi
)
806 local_irq_save(flags
);
808 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
809 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
811 local_irq_restore(flags
);
817 static int s3c2410fb_remove(struct platform_device
*pdev
)
819 struct fb_info
*fbinfo
= platform_get_drvdata(pdev
);
820 struct s3c2410fb_info
*info
= fbinfo
->par
;
823 s3c2410fb_stop_lcd(info
);
826 s3c2410fb_unmap_video_memory(info
);
829 clk_disable(info
->clk
);
834 irq
= platform_get_irq(pdev
, 0);
836 release_mem_region((unsigned long)S3C24XX_VA_LCD
, S3C24XX_SZ_LCD
);
837 unregister_framebuffer(fbinfo
);
844 /* suspend and resume support for the lcd controller */
846 static int s3c2410fb_suspend(struct platform_device
*dev
, pm_message_t state
)
848 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
849 struct s3c2410fb_info
*info
= fbinfo
->par
;
851 s3c2410fb_stop_lcd(info
);
853 /* sleep before disabling the clock, we need to ensure
854 * the LCD DMA engine is not going to get back on the bus
855 * before the clock goes off again (bjd) */
858 clk_disable(info
->clk
);
863 static int s3c2410fb_resume(struct platform_device
*dev
)
865 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
866 struct s3c2410fb_info
*info
= fbinfo
->par
;
868 clk_enable(info
->clk
);
871 s3c2410fb_init_registers(info
);
877 #define s3c2410fb_suspend NULL
878 #define s3c2410fb_resume NULL
881 static struct platform_driver s3c2410fb_driver
= {
882 .probe
= s3c2410fb_probe
,
883 .remove
= s3c2410fb_remove
,
884 .suspend
= s3c2410fb_suspend
,
885 .resume
= s3c2410fb_resume
,
887 .name
= "s3c2410-lcd",
888 .owner
= THIS_MODULE
,
892 int __devinit
s3c2410fb_init(void)
894 return platform_driver_register(&s3c2410fb_driver
);
897 static void __exit
s3c2410fb_cleanup(void)
899 platform_driver_unregister(&s3c2410fb_driver
);
903 module_init(s3c2410fb_init
);
904 module_exit(s3c2410fb_cleanup
);
906 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, Ben Dooks <ben-linux@fluff.org>");
907 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
908 MODULE_LICENSE("GPL");