2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return (le32_to_cpu(trb
->link
.control
) & TRB_TYPE_BITMASK
)
117 == TRB_TYPE(TRB_LINK
);
120 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
122 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
123 return ((le32_to_cpu(link
->control
) & TRB_TYPE_BITMASK
) ==
127 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
128 * TRB is in a new segment. This does not skip over link TRBs, and it does not
129 * effect the ring dequeue or enqueue pointers.
131 static void next_trb(struct xhci_hcd
*xhci
,
132 struct xhci_ring
*ring
,
133 struct xhci_segment
**seg
,
134 union xhci_trb
**trb
)
136 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
138 *trb
= ((*seg
)->trbs
);
145 * See Cycle bit rules. SW is the consumer for the event ring only.
146 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
148 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
150 union xhci_trb
*next
= ++(ring
->dequeue
);
151 unsigned long long addr
;
154 /* Update the dequeue pointer further if that was a link TRB or we're at
155 * the end of an event ring segment (which doesn't have link TRBS)
157 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
158 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
159 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
161 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
163 (unsigned int) ring
->cycle_state
);
165 ring
->deq_seg
= ring
->deq_seg
->next
;
166 ring
->dequeue
= ring
->deq_seg
->trbs
;
167 next
= ring
->dequeue
;
169 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
173 * See Cycle bit rules. SW is the consumer for the event ring only.
174 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
177 * chain bit is set), then set the chain bit in all the following link TRBs.
178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
179 * have their chain bit cleared (so that each Link TRB is a separate TD).
181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
182 * set, but other sections talk about dealing with the chain bit set. This was
183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
184 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
186 * @more_trbs_coming: Will you enqueue more TRBs before calling
187 * prepare_transfer()?
189 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
190 bool consumer
, bool more_trbs_coming
)
193 union xhci_trb
*next
;
194 unsigned long long addr
;
196 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
197 next
= ++(ring
->enqueue
);
200 /* Update the dequeue pointer further if that was a link TRB or we're at
201 * the end of an event ring segment (which doesn't have link TRBS)
203 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
205 if (ring
!= xhci
->event_ring
) {
207 * If the caller doesn't plan on enqueueing more
208 * TDs before ringing the doorbell, then we
209 * don't want to give the link TRB to the
210 * hardware just yet. We'll give the link TRB
211 * back in prepare_ring() just before we enqueue
212 * the TD at the top of the ring.
214 if (!chain
&& !more_trbs_coming
)
217 /* If we're not dealing with 0.95 hardware,
218 * carry over the chain bit of the previous TRB
219 * (which may mean the chain bit is cleared).
221 if (!xhci_link_trb_quirk(xhci
)) {
222 next
->link
.control
&=
223 cpu_to_le32(~TRB_CHAIN
);
224 next
->link
.control
|=
227 /* Give this link TRB to the hardware */
229 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
231 /* Toggle the cycle bit after the last ring segment. */
232 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
233 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
235 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
237 (unsigned int) ring
->cycle_state
);
240 ring
->enq_seg
= ring
->enq_seg
->next
;
241 ring
->enqueue
= ring
->enq_seg
->trbs
;
242 next
= ring
->enqueue
;
244 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
248 * Check to see if there's room to enqueue num_trbs on the ring. See rules
250 * FIXME: this would be simpler and faster if we just kept track of the number
251 * of free TRBs in a ring.
253 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
254 unsigned int num_trbs
)
257 union xhci_trb
*enq
= ring
->enqueue
;
258 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
259 struct xhci_segment
*cur_seg
;
260 unsigned int left_on_ring
;
262 /* If we are currently pointing to a link TRB, advance the
263 * enqueue pointer before checking for space */
264 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
265 enq_seg
= enq_seg
->next
;
269 /* Check if ring is empty */
270 if (enq
== ring
->dequeue
) {
271 /* Can't use link trbs */
272 left_on_ring
= TRBS_PER_SEGMENT
- 1;
273 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
274 cur_seg
= cur_seg
->next
)
275 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
277 /* Always need one TRB free in the ring. */
279 if (num_trbs
> left_on_ring
) {
280 xhci_warn(xhci
, "Not enough room on ring; "
281 "need %u TRBs, %u TRBs left\n",
282 num_trbs
, left_on_ring
);
287 /* Make sure there's an extra empty TRB available */
288 for (i
= 0; i
<= num_trbs
; ++i
) {
289 if (enq
== ring
->dequeue
)
292 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
293 enq_seg
= enq_seg
->next
;
300 /* Ring the host controller doorbell after placing a command on the ring */
301 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
303 xhci_dbg(xhci
, "// Ding dong!\n");
304 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
305 /* Flush PCI posted writes */
306 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
309 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
310 unsigned int slot_id
,
311 unsigned int ep_index
,
312 unsigned int stream_id
)
314 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
315 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
316 unsigned int ep_state
= ep
->ep_state
;
318 /* Don't ring the doorbell for this endpoint if there are pending
319 * cancellations because we don't want to interrupt processing.
320 * We don't want to restart any stream rings if there's a set dequeue
321 * pointer command pending because the device can choose to start any
322 * stream once the endpoint is on the HW schedule.
323 * FIXME - check all the stream rings for pending cancellations.
325 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
326 (ep_state
& EP_HALTED
))
328 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
329 /* The CPU has better things to do at this point than wait for a
330 * write-posting flush. It'll get there soon enough.
334 /* Ring the doorbell for any rings with pending URBs */
335 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
336 unsigned int slot_id
,
337 unsigned int ep_index
)
339 unsigned int stream_id
;
340 struct xhci_virt_ep
*ep
;
342 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
344 /* A ring has pending URBs if its TD list is not empty */
345 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
346 if (!(list_empty(&ep
->ring
->td_list
)))
347 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
351 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
353 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
354 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
355 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
361 * Find the segment that trb is in. Start searching in start_seg.
362 * If we must move past a segment that has a link TRB with a toggle cycle state
363 * bit set, then we will toggle the value pointed at by cycle_state.
365 static struct xhci_segment
*find_trb_seg(
366 struct xhci_segment
*start_seg
,
367 union xhci_trb
*trb
, int *cycle_state
)
369 struct xhci_segment
*cur_seg
= start_seg
;
370 struct xhci_generic_trb
*generic_trb
;
372 while (cur_seg
->trbs
> trb
||
373 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
374 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
375 if (le32_to_cpu(generic_trb
->field
[3]) & LINK_TOGGLE
)
377 cur_seg
= cur_seg
->next
;
378 if (cur_seg
== start_seg
)
379 /* Looped over the entire list. Oops! */
386 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
387 unsigned int slot_id
, unsigned int ep_index
,
388 unsigned int stream_id
)
390 struct xhci_virt_ep
*ep
;
392 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
393 /* Common case: no streams */
394 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
397 if (stream_id
== 0) {
399 "WARN: Slot ID %u, ep index %u has streams, "
400 "but URB has no stream ID.\n",
405 if (stream_id
< ep
->stream_info
->num_streams
)
406 return ep
->stream_info
->stream_rings
[stream_id
];
409 "WARN: Slot ID %u, ep index %u has "
410 "stream IDs 1 to %u allocated, "
411 "but stream ID %u is requested.\n",
413 ep
->stream_info
->num_streams
- 1,
418 /* Get the right ring for the given URB.
419 * If the endpoint supports streams, boundary check the URB's stream ID.
420 * If the endpoint doesn't support streams, return the singular endpoint ring.
422 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
425 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
426 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
430 * Move the xHC's endpoint ring dequeue pointer past cur_td.
431 * Record the new state of the xHC's endpoint ring dequeue segment,
432 * dequeue pointer, and new consumer cycle state in state.
433 * Update our internal representation of the ring's dequeue pointer.
435 * We do this in three jumps:
436 * - First we update our new ring state to be the same as when the xHC stopped.
437 * - Then we traverse the ring to find the segment that contains
438 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
439 * any link TRBs with the toggle cycle bit set.
440 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
441 * if we've moved it past a link TRB with the toggle cycle bit set.
443 * Some of the uses of xhci_generic_trb are grotty, but if they're done
444 * with correct __le32 accesses they should work fine. Only users of this are
447 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
448 unsigned int slot_id
, unsigned int ep_index
,
449 unsigned int stream_id
, struct xhci_td
*cur_td
,
450 struct xhci_dequeue_state
*state
)
452 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
453 struct xhci_ring
*ep_ring
;
454 struct xhci_generic_trb
*trb
;
455 struct xhci_ep_ctx
*ep_ctx
;
458 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
459 ep_index
, stream_id
);
461 xhci_warn(xhci
, "WARN can't find new dequeue state "
462 "for invalid stream ID %u.\n",
466 state
->new_cycle_state
= 0;
467 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
468 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
469 dev
->eps
[ep_index
].stopped_trb
,
470 &state
->new_cycle_state
);
471 if (!state
->new_deq_seg
) {
476 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
477 xhci_dbg(xhci
, "Finding endpoint context\n");
478 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
479 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
481 state
->new_deq_ptr
= cur_td
->last_trb
;
482 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
483 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
485 &state
->new_cycle_state
);
486 if (!state
->new_deq_seg
) {
491 trb
= &state
->new_deq_ptr
->generic
;
492 if ((le32_to_cpu(trb
->field
[3]) & TRB_TYPE_BITMASK
) ==
493 TRB_TYPE(TRB_LINK
) && (le32_to_cpu(trb
->field
[3]) & LINK_TOGGLE
))
494 state
->new_cycle_state
^= 0x1;
495 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
498 * If there is only one segment in a ring, find_trb_seg()'s while loop
499 * will not run, and it will return before it has a chance to see if it
500 * needs to toggle the cycle bit. It can't tell if the stalled transfer
501 * ended just before the link TRB on a one-segment ring, or if the TD
502 * wrapped around the top of the ring, because it doesn't have the TD in
503 * question. Look for the one-segment case where stalled TRB's address
504 * is greater than the new dequeue pointer address.
506 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
507 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
508 state
->new_cycle_state
^= 0x1;
509 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
511 /* Don't update the ring cycle state for the producer (us). */
512 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
514 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
515 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
516 (unsigned long long) addr
);
519 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
520 struct xhci_td
*cur_td
)
522 struct xhci_segment
*cur_seg
;
523 union xhci_trb
*cur_trb
;
525 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
527 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
528 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) & TRB_TYPE_BITMASK
)
529 == TRB_TYPE(TRB_LINK
)) {
530 /* Unchain any chained Link TRBs, but
531 * leave the pointers intact.
533 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
534 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
535 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
536 "in seg %p (0x%llx dma)\n",
538 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
540 (unsigned long long)cur_seg
->dma
);
542 cur_trb
->generic
.field
[0] = 0;
543 cur_trb
->generic
.field
[1] = 0;
544 cur_trb
->generic
.field
[2] = 0;
545 /* Preserve only the cycle bit of this TRB */
546 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
547 cur_trb
->generic
.field
[3] |= cpu_to_le32(
548 TRB_TYPE(TRB_TR_NOOP
));
549 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
550 "in seg %p (0x%llx dma)\n",
552 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
554 (unsigned long long)cur_seg
->dma
);
556 if (cur_trb
== cur_td
->last_trb
)
561 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
562 unsigned int ep_index
, unsigned int stream_id
,
563 struct xhci_segment
*deq_seg
,
564 union xhci_trb
*deq_ptr
, u32 cycle_state
);
566 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
567 unsigned int slot_id
, unsigned int ep_index
,
568 unsigned int stream_id
,
569 struct xhci_dequeue_state
*deq_state
)
571 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
573 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
574 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
575 deq_state
->new_deq_seg
,
576 (unsigned long long)deq_state
->new_deq_seg
->dma
,
577 deq_state
->new_deq_ptr
,
578 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
579 deq_state
->new_cycle_state
);
580 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
581 deq_state
->new_deq_seg
,
582 deq_state
->new_deq_ptr
,
583 (u32
) deq_state
->new_cycle_state
);
584 /* Stop the TD queueing code from ringing the doorbell until
585 * this command completes. The HC won't set the dequeue pointer
586 * if the ring is running, and ringing the doorbell starts the
589 ep
->ep_state
|= SET_DEQ_PENDING
;
592 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
593 struct xhci_virt_ep
*ep
)
595 ep
->ep_state
&= ~EP_HALT_PENDING
;
596 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
597 * timer is running on another CPU, we don't decrement stop_cmds_pending
598 * (since we didn't successfully stop the watchdog timer).
600 if (del_timer(&ep
->stop_cmd_timer
))
601 ep
->stop_cmds_pending
--;
604 /* Must be called with xhci->lock held in interrupt context */
605 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
606 struct xhci_td
*cur_td
, int status
, char *adjective
)
610 struct urb_priv
*urb_priv
;
613 urb_priv
= urb
->hcpriv
;
615 hcd
= bus_to_hcd(urb
->dev
->bus
);
617 /* Only giveback urb when this is the last td in urb */
618 if (urb_priv
->td_cnt
== urb_priv
->length
) {
619 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
620 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
621 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
622 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
623 usb_amd_quirk_pll_enable();
626 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
628 spin_unlock(&xhci
->lock
);
629 usb_hcd_giveback_urb(hcd
, urb
, status
);
630 xhci_urb_free_priv(xhci
, urb_priv
);
631 spin_lock(&xhci
->lock
);
636 * When we get a command completion for a Stop Endpoint Command, we need to
637 * unlink any cancelled TDs from the ring. There are two ways to do that:
639 * 1. If the HW was in the middle of processing the TD that needs to be
640 * cancelled, then we must move the ring's dequeue pointer past the last TRB
641 * in the TD with a Set Dequeue Pointer Command.
642 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
643 * bit cleared) so that the HW will skip over them.
645 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
646 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
648 unsigned int slot_id
;
649 unsigned int ep_index
;
650 struct xhci_virt_device
*virt_dev
;
651 struct xhci_ring
*ep_ring
;
652 struct xhci_virt_ep
*ep
;
653 struct list_head
*entry
;
654 struct xhci_td
*cur_td
= NULL
;
655 struct xhci_td
*last_unlinked_td
;
657 struct xhci_dequeue_state deq_state
;
659 if (unlikely(TRB_TO_SUSPEND_PORT(
660 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
661 slot_id
= TRB_TO_SLOT_ID(
662 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
663 virt_dev
= xhci
->devs
[slot_id
];
665 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
668 xhci_warn(xhci
, "Stop endpoint command "
669 "completion for disabled slot %u\n",
674 memset(&deq_state
, 0, sizeof(deq_state
));
675 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
676 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
677 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
679 if (list_empty(&ep
->cancelled_td_list
)) {
680 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
681 ep
->stopped_td
= NULL
;
682 ep
->stopped_trb
= NULL
;
683 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
687 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
688 * We have the xHCI lock, so nothing can modify this list until we drop
689 * it. We're also in the event handler, so we can't get re-interrupted
690 * if another Stop Endpoint command completes
692 list_for_each(entry
, &ep
->cancelled_td_list
) {
693 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
694 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
696 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
697 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
699 /* This shouldn't happen unless a driver is mucking
700 * with the stream ID after submission. This will
701 * leave the TD on the hardware ring, and the hardware
702 * will try to execute it, and may access a buffer
703 * that has already been freed. In the best case, the
704 * hardware will execute it, and the event handler will
705 * ignore the completion event for that TD, since it was
706 * removed from the td_list for that endpoint. In
707 * short, don't muck with the stream ID after
710 xhci_warn(xhci
, "WARN Cancelled URB %p "
711 "has invalid stream ID %u.\n",
713 cur_td
->urb
->stream_id
);
714 goto remove_finished_td
;
717 * If we stopped on the TD we need to cancel, then we have to
718 * move the xHC endpoint ring dequeue pointer past this TD.
720 if (cur_td
== ep
->stopped_td
)
721 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
722 cur_td
->urb
->stream_id
,
725 td_to_noop(xhci
, ep_ring
, cur_td
);
728 * The event handler won't see a completion for this TD anymore,
729 * so remove it from the endpoint ring's TD list. Keep it in
730 * the cancelled TD list for URB completion later.
732 list_del(&cur_td
->td_list
);
734 last_unlinked_td
= cur_td
;
735 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
737 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
738 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
739 xhci_queue_new_dequeue_state(xhci
,
741 ep
->stopped_td
->urb
->stream_id
,
743 xhci_ring_cmd_db(xhci
);
745 /* Otherwise ring the doorbell(s) to restart queued transfers */
746 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
748 ep
->stopped_td
= NULL
;
749 ep
->stopped_trb
= NULL
;
752 * Drop the lock and complete the URBs in the cancelled TD list.
753 * New TDs to be cancelled might be added to the end of the list before
754 * we can complete all the URBs for the TDs we already unlinked.
755 * So stop when we've completed the URB for the last TD we unlinked.
758 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
759 struct xhci_td
, cancelled_td_list
);
760 list_del(&cur_td
->cancelled_td_list
);
762 /* Clean up the cancelled URB */
763 /* Doesn't matter what we pass for status, since the core will
764 * just overwrite it (because the URB has been unlinked).
766 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
768 /* Stop processing the cancelled list if the watchdog timer is
771 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
773 } while (cur_td
!= last_unlinked_td
);
775 /* Return to the event handler with xhci->lock re-acquired */
778 /* Watchdog timer function for when a stop endpoint command fails to complete.
779 * In this case, we assume the host controller is broken or dying or dead. The
780 * host may still be completing some other events, so we have to be careful to
781 * let the event ring handler and the URB dequeueing/enqueueing functions know
782 * through xhci->state.
784 * The timer may also fire if the host takes a very long time to respond to the
785 * command, and the stop endpoint command completion handler cannot delete the
786 * timer before the timer function is called. Another endpoint cancellation may
787 * sneak in before the timer function can grab the lock, and that may queue
788 * another stop endpoint command and add the timer back. So we cannot use a
789 * simple flag to say whether there is a pending stop endpoint command for a
790 * particular endpoint.
792 * Instead we use a combination of that flag and a counter for the number of
793 * pending stop endpoint commands. If the timer is the tail end of the last
794 * stop endpoint command, and the endpoint's command is still pending, we assume
797 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
799 struct xhci_hcd
*xhci
;
800 struct xhci_virt_ep
*ep
;
801 struct xhci_virt_ep
*temp_ep
;
802 struct xhci_ring
*ring
;
803 struct xhci_td
*cur_td
;
806 ep
= (struct xhci_virt_ep
*) arg
;
809 spin_lock(&xhci
->lock
);
811 ep
->stop_cmds_pending
--;
812 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
813 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
814 "xHCI as DYING, exiting.\n");
815 spin_unlock(&xhci
->lock
);
818 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
819 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
821 spin_unlock(&xhci
->lock
);
825 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
826 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
827 /* Oops, HC is dead or dying or at least not responding to the stop
830 xhci
->xhc_state
|= XHCI_STATE_DYING
;
831 /* Disable interrupts from the host controller and start halting it */
833 spin_unlock(&xhci
->lock
);
835 ret
= xhci_halt(xhci
);
837 spin_lock(&xhci
->lock
);
839 /* This is bad; the host is not responding to commands and it's
840 * not allowing itself to be halted. At least interrupts are
841 * disabled. If we call usb_hc_died(), it will attempt to
842 * disconnect all device drivers under this host. Those
843 * disconnect() methods will wait for all URBs to be unlinked,
844 * so we must complete them.
846 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
847 xhci_warn(xhci
, "Completing active URBs anyway.\n");
848 /* We could turn all TDs on the rings to no-ops. This won't
849 * help if the host has cached part of the ring, and is slow if
850 * we want to preserve the cycle bit. Skip it and hope the host
851 * doesn't touch the memory.
854 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
857 for (j
= 0; j
< 31; j
++) {
858 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
859 ring
= temp_ep
->ring
;
862 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
863 "ep index %u\n", i
, j
);
864 while (!list_empty(&ring
->td_list
)) {
865 cur_td
= list_first_entry(&ring
->td_list
,
868 list_del(&cur_td
->td_list
);
869 if (!list_empty(&cur_td
->cancelled_td_list
))
870 list_del(&cur_td
->cancelled_td_list
);
871 xhci_giveback_urb_in_irq(xhci
, cur_td
,
872 -ESHUTDOWN
, "killed");
874 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
875 cur_td
= list_first_entry(
876 &temp_ep
->cancelled_td_list
,
879 list_del(&cur_td
->cancelled_td_list
);
880 xhci_giveback_urb_in_irq(xhci
, cur_td
,
881 -ESHUTDOWN
, "killed");
885 spin_unlock(&xhci
->lock
);
886 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
887 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
888 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
892 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
893 * we need to clear the set deq pending flag in the endpoint ring state, so that
894 * the TD queueing code can ring the doorbell again. We also need to ring the
895 * endpoint doorbell to restart the ring, but only if there aren't more
896 * cancellations pending.
898 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
899 struct xhci_event_cmd
*event
,
902 unsigned int slot_id
;
903 unsigned int ep_index
;
904 unsigned int stream_id
;
905 struct xhci_ring
*ep_ring
;
906 struct xhci_virt_device
*dev
;
907 struct xhci_ep_ctx
*ep_ctx
;
908 struct xhci_slot_ctx
*slot_ctx
;
910 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
911 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
912 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
913 dev
= xhci
->devs
[slot_id
];
915 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
917 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
918 "freed stream ID %u\n",
920 /* XXX: Harmless??? */
921 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
925 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
926 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
928 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
929 unsigned int ep_state
;
930 unsigned int slot_state
;
932 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
934 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
935 "of stream ID configuration\n");
938 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
939 "to incorrect slot or ep state.\n");
940 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
941 ep_state
&= EP_STATE_MASK
;
942 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
943 slot_state
= GET_SLOT_STATE(slot_state
);
944 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
945 slot_state
, ep_state
);
948 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
949 "slot %u was not enabled.\n", slot_id
);
952 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
953 "completion code of %u.\n",
954 GET_COMP_CODE(le32_to_cpu(event
->status
)));
957 /* OK what do we do now? The endpoint state is hosed, and we
958 * should never get to this point if the synchronization between
959 * queueing, and endpoint state are correct. This might happen
960 * if the device gets disconnected after we've finished
961 * cancelling URBs, which might not be an error...
964 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
965 le64_to_cpu(ep_ctx
->deq
));
966 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
967 dev
->eps
[ep_index
].queued_deq_ptr
) ==
968 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
969 /* Update the ring's dequeue segment and dequeue pointer
970 * to reflect the new position.
972 ep_ring
->deq_seg
= dev
->eps
[ep_index
].queued_deq_seg
;
973 ep_ring
->dequeue
= dev
->eps
[ep_index
].queued_deq_ptr
;
975 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
976 "Ptr command & xHCI internal state.\n");
977 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
978 dev
->eps
[ep_index
].queued_deq_seg
,
979 dev
->eps
[ep_index
].queued_deq_ptr
);
983 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
984 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
985 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
986 /* Restart any rings with pending URBs */
987 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
990 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
991 struct xhci_event_cmd
*event
,
995 unsigned int ep_index
;
997 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
998 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
999 /* This command will only fail if the endpoint wasn't halted,
1000 * but we don't care.
1002 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1003 (unsigned int) GET_COMP_CODE(le32_to_cpu(event
->status
)));
1005 /* HW with the reset endpoint quirk needs to have a configure endpoint
1006 * command complete before the endpoint can be used. Queue that here
1007 * because the HW can't handle two commands being queued in a row.
1009 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1010 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1011 xhci_queue_configure_endpoint(xhci
,
1012 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1014 xhci_ring_cmd_db(xhci
);
1016 /* Clear our internal halted state and restart the ring(s) */
1017 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1018 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1022 /* Check to see if a command in the device's command queue matches this one.
1023 * Signal the completion or free the command, and return 1. Return 0 if the
1024 * completed command isn't at the head of the command list.
1026 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1027 struct xhci_virt_device
*virt_dev
,
1028 struct xhci_event_cmd
*event
)
1030 struct xhci_command
*command
;
1032 if (list_empty(&virt_dev
->cmd_list
))
1035 command
= list_entry(virt_dev
->cmd_list
.next
,
1036 struct xhci_command
, cmd_list
);
1037 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1040 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1041 list_del(&command
->cmd_list
);
1042 if (command
->completion
)
1043 complete(command
->completion
);
1045 xhci_free_command(xhci
, command
);
1049 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1050 struct xhci_event_cmd
*event
)
1052 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1054 dma_addr_t cmd_dequeue_dma
;
1055 struct xhci_input_control_ctx
*ctrl_ctx
;
1056 struct xhci_virt_device
*virt_dev
;
1057 unsigned int ep_index
;
1058 struct xhci_ring
*ep_ring
;
1059 unsigned int ep_state
;
1061 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1062 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1063 xhci
->cmd_ring
->dequeue
);
1064 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1065 if (cmd_dequeue_dma
== 0) {
1066 xhci
->error_bitmask
|= 1 << 4;
1069 /* Does the DMA address match our internal dequeue pointer address? */
1070 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1071 xhci
->error_bitmask
|= 1 << 5;
1074 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1075 & TRB_TYPE_BITMASK
) {
1076 case TRB_TYPE(TRB_ENABLE_SLOT
):
1077 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1078 xhci
->slot_id
= slot_id
;
1081 complete(&xhci
->addr_dev
);
1083 case TRB_TYPE(TRB_DISABLE_SLOT
):
1084 if (xhci
->devs
[slot_id
])
1085 xhci_free_virt_device(xhci
, slot_id
);
1087 case TRB_TYPE(TRB_CONFIG_EP
):
1088 virt_dev
= xhci
->devs
[slot_id
];
1089 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1092 * Configure endpoint commands can come from the USB core
1093 * configuration or alt setting changes, or because the HW
1094 * needed an extra configure endpoint command after a reset
1095 * endpoint command or streams were being configured.
1096 * If the command was for a halted endpoint, the xHCI driver
1097 * is not waiting on the configure endpoint command.
1099 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1101 /* Input ctx add_flags are the endpoint index plus one */
1102 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1103 /* A usb_set_interface() call directly after clearing a halted
1104 * condition may race on this quirky hardware. Not worth
1105 * worrying about, since this is prototype hardware. Not sure
1106 * if this will work for streams, but streams support was
1107 * untested on this prototype.
1109 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1110 ep_index
!= (unsigned int) -1 &&
1111 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1112 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1113 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1114 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1115 if (!(ep_state
& EP_HALTED
))
1116 goto bandwidth_change
;
1117 xhci_dbg(xhci
, "Completed config ep cmd - "
1118 "last ep index = %d, state = %d\n",
1119 ep_index
, ep_state
);
1120 /* Clear internal halted state and restart ring(s) */
1121 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1123 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1127 xhci_dbg(xhci
, "Completed config ep cmd\n");
1128 xhci
->devs
[slot_id
]->cmd_status
=
1129 GET_COMP_CODE(le32_to_cpu(event
->status
));
1130 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1132 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1133 virt_dev
= xhci
->devs
[slot_id
];
1134 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1136 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1137 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1139 case TRB_TYPE(TRB_ADDR_DEV
):
1140 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1141 complete(&xhci
->addr_dev
);
1143 case TRB_TYPE(TRB_STOP_RING
):
1144 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1146 case TRB_TYPE(TRB_SET_DEQ
):
1147 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1149 case TRB_TYPE(TRB_CMD_NOOP
):
1151 case TRB_TYPE(TRB_RESET_EP
):
1152 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1154 case TRB_TYPE(TRB_RESET_DEV
):
1155 xhci_dbg(xhci
, "Completed reset device command.\n");
1156 slot_id
= TRB_TO_SLOT_ID(
1157 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1158 virt_dev
= xhci
->devs
[slot_id
];
1160 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1162 xhci_warn(xhci
, "Reset device command completion "
1163 "for disabled slot %u\n", slot_id
);
1165 case TRB_TYPE(TRB_NEC_GET_FW
):
1166 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1167 xhci
->error_bitmask
|= 1 << 6;
1170 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1171 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1172 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1175 /* Skip over unknown commands on the event ring */
1176 xhci
->error_bitmask
|= 1 << 6;
1179 inc_deq(xhci
, xhci
->cmd_ring
, false);
1182 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1183 union xhci_trb
*event
)
1187 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1188 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1189 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1190 handle_cmd_completion(xhci
, &event
->event_cmd
);
1193 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1194 * port registers -- USB 3.0 and USB 2.0).
1196 * Returns a zero-based port number, which is suitable for indexing into each of
1197 * the split roothubs' port arrays and bus state arrays.
1199 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1200 struct xhci_hcd
*xhci
, u32 port_id
)
1203 unsigned int num_similar_speed_ports
= 0;
1205 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1206 * and usb2_ports are 0-based indexes. Count the number of similar
1207 * speed ports, up to 1 port before this port.
1209 for (i
= 0; i
< (port_id
- 1); i
++) {
1210 u8 port_speed
= xhci
->port_array
[i
];
1213 * Skip ports that don't have known speeds, or have duplicate
1214 * Extended Capabilities port speed entries.
1216 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1220 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1221 * 1.1 ports are under the USB 2.0 hub. If the port speed
1222 * matches the device speed, it's a similar speed port.
1224 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1225 num_similar_speed_ports
++;
1227 return num_similar_speed_ports
;
1230 static void handle_port_status(struct xhci_hcd
*xhci
,
1231 union xhci_trb
*event
)
1233 struct usb_hcd
*hcd
;
1238 unsigned int faked_port_index
;
1240 struct xhci_bus_state
*bus_state
;
1241 __le32 __iomem
**port_array
;
1242 bool bogus_port_status
= false;
1244 /* Port status change events always have a successful completion code */
1245 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1246 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1247 xhci
->error_bitmask
|= 1 << 8;
1249 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1250 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1252 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1253 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1254 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1255 bogus_port_status
= true;
1259 /* Figure out which usb_hcd this port is attached to:
1260 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1262 major_revision
= xhci
->port_array
[port_id
- 1];
1263 if (major_revision
== 0) {
1264 xhci_warn(xhci
, "Event for port %u not in "
1265 "Extended Capabilities, ignoring.\n",
1267 bogus_port_status
= true;
1270 if (major_revision
== DUPLICATE_ENTRY
) {
1271 xhci_warn(xhci
, "Event for port %u duplicated in"
1272 "Extended Capabilities, ignoring.\n",
1274 bogus_port_status
= true;
1279 * Hardware port IDs reported by a Port Status Change Event include USB
1280 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1281 * resume event, but we first need to translate the hardware port ID
1282 * into the index into the ports on the correct split roothub, and the
1283 * correct bus_state structure.
1285 /* Find the right roothub. */
1286 hcd
= xhci_to_hcd(xhci
);
1287 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1288 hcd
= xhci
->shared_hcd
;
1289 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1290 if (hcd
->speed
== HCD_USB3
)
1291 port_array
= xhci
->usb3_ports
;
1293 port_array
= xhci
->usb2_ports
;
1294 /* Find the faked port hub number */
1295 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1298 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1299 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1300 xhci_dbg(xhci
, "resume root hub\n");
1301 usb_hcd_resume_root_hub(hcd
);
1304 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1305 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1307 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1308 if (!(temp1
& CMD_RUN
)) {
1309 xhci_warn(xhci
, "xHC is not running.\n");
1313 if (DEV_SUPERSPEED(temp
)) {
1314 xhci_dbg(xhci
, "resume SS port %d\n", port_id
);
1315 temp
= xhci_port_state_to_neutral(temp
);
1316 temp
&= ~PORT_PLS_MASK
;
1317 temp
|= PORT_LINK_STROBE
| XDEV_U0
;
1318 xhci_writel(xhci
, temp
, port_array
[faked_port_index
]);
1319 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1322 xhci_dbg(xhci
, "slot_id is zero\n");
1325 xhci_ring_device(xhci
, slot_id
);
1326 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1327 /* Clear PORT_PLC */
1328 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1329 temp
= xhci_port_state_to_neutral(temp
);
1331 xhci_writel(xhci
, temp
, port_array
[faked_port_index
]);
1333 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1334 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1335 msecs_to_jiffies(20);
1336 mod_timer(&hcd
->rh_timer
,
1337 bus_state
->resume_done
[faked_port_index
]);
1338 /* Do the rest in GetPortStatus */
1343 /* Update event ring dequeue pointer before dropping the lock */
1344 inc_deq(xhci
, xhci
->event_ring
, true);
1346 /* Don't make the USB core poll the roothub if we got a bad port status
1347 * change event. Besides, at that point we can't tell which roothub
1348 * (USB 2.0 or USB 3.0) to kick.
1350 if (bogus_port_status
)
1353 spin_unlock(&xhci
->lock
);
1354 /* Pass this up to the core */
1355 usb_hcd_poll_rh_status(hcd
);
1356 spin_lock(&xhci
->lock
);
1360 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1361 * at end_trb, which may be in another segment. If the suspect DMA address is a
1362 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1365 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1366 union xhci_trb
*start_trb
,
1367 union xhci_trb
*end_trb
,
1368 dma_addr_t suspect_dma
)
1370 dma_addr_t start_dma
;
1371 dma_addr_t end_seg_dma
;
1372 dma_addr_t end_trb_dma
;
1373 struct xhci_segment
*cur_seg
;
1375 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1376 cur_seg
= start_seg
;
1381 /* We may get an event for a Link TRB in the middle of a TD */
1382 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1383 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1384 /* If the end TRB isn't in this segment, this is set to 0 */
1385 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1387 if (end_trb_dma
> 0) {
1388 /* The end TRB is in this segment, so suspect should be here */
1389 if (start_dma
<= end_trb_dma
) {
1390 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1393 /* Case for one segment with
1394 * a TD wrapped around to the top
1396 if ((suspect_dma
>= start_dma
&&
1397 suspect_dma
<= end_seg_dma
) ||
1398 (suspect_dma
>= cur_seg
->dma
&&
1399 suspect_dma
<= end_trb_dma
))
1404 /* Might still be somewhere in this segment */
1405 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1408 cur_seg
= cur_seg
->next
;
1409 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1410 } while (cur_seg
!= start_seg
);
1415 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1416 unsigned int slot_id
, unsigned int ep_index
,
1417 unsigned int stream_id
,
1418 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1420 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1421 ep
->ep_state
|= EP_HALTED
;
1422 ep
->stopped_td
= td
;
1423 ep
->stopped_trb
= event_trb
;
1424 ep
->stopped_stream
= stream_id
;
1426 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1427 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1429 ep
->stopped_td
= NULL
;
1430 ep
->stopped_trb
= NULL
;
1431 ep
->stopped_stream
= 0;
1433 xhci_ring_cmd_db(xhci
);
1436 /* Check if an error has halted the endpoint ring. The class driver will
1437 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1438 * However, a babble and other errors also halt the endpoint ring, and the class
1439 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1440 * Ring Dequeue Pointer command manually.
1442 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1443 struct xhci_ep_ctx
*ep_ctx
,
1444 unsigned int trb_comp_code
)
1446 /* TRB completion codes that may require a manual halt cleanup */
1447 if (trb_comp_code
== COMP_TX_ERR
||
1448 trb_comp_code
== COMP_BABBLE
||
1449 trb_comp_code
== COMP_SPLIT_ERR
)
1450 /* The 0.96 spec says a babbling control endpoint
1451 * is not halted. The 0.96 spec says it is. Some HW
1452 * claims to be 0.95 compliant, but it halts the control
1453 * endpoint anyway. Check if a babble halted the
1456 if ((le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) == EP_STATE_HALTED
)
1462 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1464 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1465 /* Vendor defined "informational" completion code,
1466 * treat as not-an-error.
1468 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1470 xhci_dbg(xhci
, "Treating code as success.\n");
1477 * Finish the td processing, remove the td from td list;
1478 * Return 1 if the urb can be given back.
1480 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1481 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1482 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1484 struct xhci_virt_device
*xdev
;
1485 struct xhci_ring
*ep_ring
;
1486 unsigned int slot_id
;
1488 struct urb
*urb
= NULL
;
1489 struct xhci_ep_ctx
*ep_ctx
;
1491 struct urb_priv
*urb_priv
;
1494 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1495 xdev
= xhci
->devs
[slot_id
];
1496 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1497 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1498 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1499 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1504 if (trb_comp_code
== COMP_STOP_INVAL
||
1505 trb_comp_code
== COMP_STOP
) {
1506 /* The Endpoint Stop Command completion will take care of any
1507 * stopped TDs. A stopped TD may be restarted, so don't update
1508 * the ring dequeue pointer or take this TD off any lists yet.
1510 ep
->stopped_td
= td
;
1511 ep
->stopped_trb
= event_trb
;
1514 if (trb_comp_code
== COMP_STALL
) {
1515 /* The transfer is completed from the driver's
1516 * perspective, but we need to issue a set dequeue
1517 * command for this stalled endpoint to move the dequeue
1518 * pointer past the TD. We can't do that here because
1519 * the halt condition must be cleared first. Let the
1520 * USB class driver clear the stall later.
1522 ep
->stopped_td
= td
;
1523 ep
->stopped_trb
= event_trb
;
1524 ep
->stopped_stream
= ep_ring
->stream_id
;
1525 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1526 ep_ctx
, trb_comp_code
)) {
1527 /* Other types of errors halt the endpoint, but the
1528 * class driver doesn't call usb_reset_endpoint() unless
1529 * the error is -EPIPE. Clear the halted status in the
1530 * xHCI hardware manually.
1532 xhci_cleanup_halted_endpoint(xhci
,
1533 slot_id
, ep_index
, ep_ring
->stream_id
,
1536 /* Update ring dequeue pointer */
1537 while (ep_ring
->dequeue
!= td
->last_trb
)
1538 inc_deq(xhci
, ep_ring
, false);
1539 inc_deq(xhci
, ep_ring
, false);
1543 /* Clean up the endpoint's TD list */
1545 urb_priv
= urb
->hcpriv
;
1547 /* Do one last check of the actual transfer length.
1548 * If the host controller said we transferred more data than
1549 * the buffer length, urb->actual_length will be a very big
1550 * number (since it's unsigned). Play it safe and say we didn't
1551 * transfer anything.
1553 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1554 xhci_warn(xhci
, "URB transfer length is wrong, "
1555 "xHC issue? req. len = %u, "
1557 urb
->transfer_buffer_length
,
1558 urb
->actual_length
);
1559 urb
->actual_length
= 0;
1560 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1561 *status
= -EREMOTEIO
;
1565 list_del(&td
->td_list
);
1566 /* Was this TD slated to be cancelled but completed anyway? */
1567 if (!list_empty(&td
->cancelled_td_list
))
1568 list_del(&td
->cancelled_td_list
);
1571 /* Giveback the urb when all the tds are completed */
1572 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1574 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1575 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1576 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1578 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1579 usb_amd_quirk_pll_enable();
1589 * Process control tds, update urb status and actual_length.
1591 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1592 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1593 struct xhci_virt_ep
*ep
, int *status
)
1595 struct xhci_virt_device
*xdev
;
1596 struct xhci_ring
*ep_ring
;
1597 unsigned int slot_id
;
1599 struct xhci_ep_ctx
*ep_ctx
;
1602 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1603 xdev
= xhci
->devs
[slot_id
];
1604 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1605 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1606 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1607 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1609 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1610 switch (trb_comp_code
) {
1612 if (event_trb
== ep_ring
->dequeue
) {
1613 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1614 "without IOC set??\n");
1615 *status
= -ESHUTDOWN
;
1616 } else if (event_trb
!= td
->last_trb
) {
1617 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1618 "without IOC set??\n");
1619 *status
= -ESHUTDOWN
;
1625 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1626 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1627 *status
= -EREMOTEIO
;
1631 case COMP_STOP_INVAL
:
1633 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1635 if (!xhci_requires_manual_halt_cleanup(xhci
,
1636 ep_ctx
, trb_comp_code
))
1638 xhci_dbg(xhci
, "TRB error code %u, "
1639 "halted endpoint index = %u\n",
1640 trb_comp_code
, ep_index
);
1641 /* else fall through */
1643 /* Did we transfer part of the data (middle) phase? */
1644 if (event_trb
!= ep_ring
->dequeue
&&
1645 event_trb
!= td
->last_trb
)
1646 td
->urb
->actual_length
=
1647 td
->urb
->transfer_buffer_length
1648 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1650 td
->urb
->actual_length
= 0;
1652 xhci_cleanup_halted_endpoint(xhci
,
1653 slot_id
, ep_index
, 0, td
, event_trb
);
1654 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1657 * Did we transfer any data, despite the errors that might have
1658 * happened? I.e. did we get past the setup stage?
1660 if (event_trb
!= ep_ring
->dequeue
) {
1661 /* The event was for the status stage */
1662 if (event_trb
== td
->last_trb
) {
1663 if (td
->urb
->actual_length
!= 0) {
1664 /* Don't overwrite a previously set error code
1666 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1667 (td
->urb
->transfer_flags
1668 & URB_SHORT_NOT_OK
))
1669 /* Did we already see a short data
1671 *status
= -EREMOTEIO
;
1673 td
->urb
->actual_length
=
1674 td
->urb
->transfer_buffer_length
;
1677 /* Maybe the event was for the data stage? */
1678 td
->urb
->actual_length
=
1679 td
->urb
->transfer_buffer_length
-
1680 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1681 xhci_dbg(xhci
, "Waiting for status "
1687 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1691 * Process isochronous tds, update urb packet status and actual_length.
1693 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1694 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1695 struct xhci_virt_ep
*ep
, int *status
)
1697 struct xhci_ring
*ep_ring
;
1698 struct urb_priv
*urb_priv
;
1701 union xhci_trb
*cur_trb
;
1702 struct xhci_segment
*cur_seg
;
1703 struct usb_iso_packet_descriptor
*frame
;
1705 bool skip_td
= false;
1707 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1708 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1709 urb_priv
= td
->urb
->hcpriv
;
1710 idx
= urb_priv
->td_cnt
;
1711 frame
= &td
->urb
->iso_frame_desc
[idx
];
1713 /* handle completion code */
1714 switch (trb_comp_code
) {
1719 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1723 frame
->status
= -ECOMM
;
1726 case COMP_BUFF_OVER
:
1728 frame
->status
= -EOVERFLOW
;
1732 frame
->status
= -EPROTO
;
1736 case COMP_STOP_INVAL
:
1743 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1744 frame
->actual_length
= frame
->length
;
1745 td
->urb
->actual_length
+= frame
->length
;
1747 for (cur_trb
= ep_ring
->dequeue
,
1748 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1749 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1750 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) &
1751 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1752 (le32_to_cpu(cur_trb
->generic
.field
[3]) &
1753 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1754 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1756 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1757 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1759 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1760 frame
->actual_length
= len
;
1761 td
->urb
->actual_length
+= len
;
1765 if ((idx
== urb_priv
->length
- 1) && *status
== -EINPROGRESS
)
1768 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1771 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1772 struct xhci_transfer_event
*event
,
1773 struct xhci_virt_ep
*ep
, int *status
)
1775 struct xhci_ring
*ep_ring
;
1776 struct urb_priv
*urb_priv
;
1777 struct usb_iso_packet_descriptor
*frame
;
1780 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1781 urb_priv
= td
->urb
->hcpriv
;
1782 idx
= urb_priv
->td_cnt
;
1783 frame
= &td
->urb
->iso_frame_desc
[idx
];
1785 /* The transfer is partly done */
1787 frame
->status
= -EXDEV
;
1789 /* calc actual length */
1790 frame
->actual_length
= 0;
1792 /* Update ring dequeue pointer */
1793 while (ep_ring
->dequeue
!= td
->last_trb
)
1794 inc_deq(xhci
, ep_ring
, false);
1795 inc_deq(xhci
, ep_ring
, false);
1797 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1801 * Process bulk and interrupt tds, update urb status and actual_length.
1803 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1804 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1805 struct xhci_virt_ep
*ep
, int *status
)
1807 struct xhci_ring
*ep_ring
;
1808 union xhci_trb
*cur_trb
;
1809 struct xhci_segment
*cur_seg
;
1812 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1813 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1815 switch (trb_comp_code
) {
1817 /* Double check that the HW transferred everything. */
1818 if (event_trb
!= td
->last_trb
) {
1819 xhci_warn(xhci
, "WARN Successful completion "
1821 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1822 *status
= -EREMOTEIO
;
1830 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1831 *status
= -EREMOTEIO
;
1836 /* Others already handled above */
1839 if (trb_comp_code
== COMP_SHORT_TX
)
1840 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1841 "%d bytes untransferred\n",
1842 td
->urb
->ep
->desc
.bEndpointAddress
,
1843 td
->urb
->transfer_buffer_length
,
1844 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1845 /* Fast path - was this the last TRB in the TD for this URB? */
1846 if (event_trb
== td
->last_trb
) {
1847 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1848 td
->urb
->actual_length
=
1849 td
->urb
->transfer_buffer_length
-
1850 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1851 if (td
->urb
->transfer_buffer_length
<
1852 td
->urb
->actual_length
) {
1853 xhci_warn(xhci
, "HC gave bad length "
1854 "of %d bytes left\n",
1855 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1856 td
->urb
->actual_length
= 0;
1857 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1858 *status
= -EREMOTEIO
;
1862 /* Don't overwrite a previously set error code */
1863 if (*status
== -EINPROGRESS
) {
1864 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1865 *status
= -EREMOTEIO
;
1870 td
->urb
->actual_length
=
1871 td
->urb
->transfer_buffer_length
;
1872 /* Ignore a short packet completion if the
1873 * untransferred length was zero.
1875 if (*status
== -EREMOTEIO
)
1879 /* Slow path - walk the list, starting from the dequeue
1880 * pointer, to get the actual length transferred.
1882 td
->urb
->actual_length
= 0;
1883 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1884 cur_trb
!= event_trb
;
1885 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1886 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) &
1887 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1888 (le32_to_cpu(cur_trb
->generic
.field
[3]) &
1889 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1890 td
->urb
->actual_length
+=
1891 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1893 /* If the ring didn't stop on a Link or No-op TRB, add
1894 * in the actual bytes transferred from the Normal TRB
1896 if (trb_comp_code
!= COMP_STOP_INVAL
)
1897 td
->urb
->actual_length
+=
1898 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1899 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1902 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1906 * If this function returns an error condition, it means it got a Transfer
1907 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1908 * At this point, the host controller is probably hosed and should be reset.
1910 static int handle_tx_event(struct xhci_hcd
*xhci
,
1911 struct xhci_transfer_event
*event
)
1913 struct xhci_virt_device
*xdev
;
1914 struct xhci_virt_ep
*ep
;
1915 struct xhci_ring
*ep_ring
;
1916 unsigned int slot_id
;
1918 struct xhci_td
*td
= NULL
;
1919 dma_addr_t event_dma
;
1920 struct xhci_segment
*event_seg
;
1921 union xhci_trb
*event_trb
;
1922 struct urb
*urb
= NULL
;
1923 int status
= -EINPROGRESS
;
1924 struct urb_priv
*urb_priv
;
1925 struct xhci_ep_ctx
*ep_ctx
;
1929 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1930 xdev
= xhci
->devs
[slot_id
];
1932 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1936 /* Endpoint ID is 1 based, our index is zero based */
1937 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1938 ep
= &xdev
->eps
[ep_index
];
1939 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1940 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1942 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
1943 EP_STATE_DISABLED
) {
1944 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1945 "or incorrect stream ring\n");
1949 event_dma
= le64_to_cpu(event
->buffer
);
1950 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1951 /* Look for common error cases */
1952 switch (trb_comp_code
) {
1953 /* Skip codes that require special handling depending on
1960 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1962 case COMP_STOP_INVAL
:
1963 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1966 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1967 ep
->ep_state
|= EP_HALTED
;
1971 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1974 case COMP_SPLIT_ERR
:
1976 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1980 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1981 status
= -EOVERFLOW
;
1984 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1988 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
1990 case COMP_BUFF_OVER
:
1991 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
1995 * When the Isoch ring is empty, the xHC will generate
1996 * a Ring Overrun Event for IN Isoch endpoint or Ring
1997 * Underrun Event for OUT Isoch endpoint.
1999 xhci_dbg(xhci
, "underrun event on endpoint\n");
2000 if (!list_empty(&ep_ring
->td_list
))
2001 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2002 "still with TDs queued?\n",
2003 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2007 xhci_dbg(xhci
, "overrun event on endpoint\n");
2008 if (!list_empty(&ep_ring
->td_list
))
2009 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2010 "still with TDs queued?\n",
2011 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2014 case COMP_MISSED_INT
:
2016 * When encounter missed service error, one or more isoc tds
2017 * may be missed by xHC.
2018 * Set skip flag of the ep_ring; Complete the missed tds as
2019 * short transfer when process the ep_ring next time.
2022 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2025 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2029 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2035 /* This TRB should be in the TD at the head of this ring's
2038 if (list_empty(&ep_ring
->td_list
)) {
2039 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2040 "with no TDs queued?\n",
2041 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2043 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2044 (unsigned int) (le32_to_cpu(event
->flags
)
2045 & TRB_TYPE_BITMASK
)>>10);
2046 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2049 xhci_dbg(xhci
, "td_list is empty while skip "
2050 "flag set. Clear skip flag.\n");
2056 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2058 /* Is this a TRB in the currently executing TD? */
2059 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2060 td
->last_trb
, event_dma
);
2063 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2064 /* HC is busted, give up! */
2066 "ERROR Transfer event TRB DMA ptr not "
2067 "part of current TD\n");
2071 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2076 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2080 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2081 sizeof(*event_trb
)];
2083 * No-op TRB should not trigger interrupts.
2084 * If event_trb is a no-op TRB, it means the
2085 * corresponding TD has been cancelled. Just ignore
2088 if ((le32_to_cpu(event_trb
->generic
.field
[3])
2090 == TRB_TYPE(TRB_TR_NOOP
)) {
2092 "event_trb is a no-op TRB. Skip it\n");
2096 /* Now update the urb's actual_length and give back to
2099 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2100 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2102 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2103 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2106 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2111 * Do not update event ring dequeue pointer if ep->skip is set.
2112 * Will roll back to continue process missed tds.
2114 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2115 inc_deq(xhci
, xhci
->event_ring
, true);
2120 urb_priv
= urb
->hcpriv
;
2121 /* Leave the TD around for the reset endpoint function
2122 * to use(but only if it's not a control endpoint,
2123 * since we already queued the Set TR dequeue pointer
2124 * command for stalled control endpoints).
2126 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2127 (trb_comp_code
!= COMP_STALL
&&
2128 trb_comp_code
!= COMP_BABBLE
))
2129 xhci_urb_free_priv(xhci
, urb_priv
);
2131 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2132 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2133 (urb
->transfer_flags
&
2134 URB_SHORT_NOT_OK
)) ||
2136 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2137 "expected = %x, status = %d\n",
2138 urb
, urb
->actual_length
,
2139 urb
->transfer_buffer_length
,
2141 spin_unlock(&xhci
->lock
);
2142 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2143 spin_lock(&xhci
->lock
);
2147 * If ep->skip is set, it means there are missed tds on the
2148 * endpoint ring need to take care of.
2149 * Process them as short transfer until reach the td pointed by
2152 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2158 * This function handles all OS-owned events on the event ring. It may drop
2159 * xhci->lock between event processing (e.g. to pass up port status changes).
2160 * Returns >0 for "possibly more events to process" (caller should call again),
2161 * otherwise 0 if done. In future, <0 returns should indicate error code.
2163 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2165 union xhci_trb
*event
;
2166 int update_ptrs
= 1;
2169 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2170 xhci
->error_bitmask
|= 1 << 1;
2174 event
= xhci
->event_ring
->dequeue
;
2175 /* Does the HC or OS own the TRB? */
2176 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2177 xhci
->event_ring
->cycle_state
) {
2178 xhci
->error_bitmask
|= 1 << 2;
2183 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2184 * speculative reads of the event's flags/data below.
2187 /* FIXME: Handle more event types. */
2188 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2189 case TRB_TYPE(TRB_COMPLETION
):
2190 handle_cmd_completion(xhci
, &event
->event_cmd
);
2192 case TRB_TYPE(TRB_PORT_STATUS
):
2193 handle_port_status(xhci
, event
);
2196 case TRB_TYPE(TRB_TRANSFER
):
2197 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2199 xhci
->error_bitmask
|= 1 << 9;
2204 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2206 handle_vendor_event(xhci
, event
);
2208 xhci
->error_bitmask
|= 1 << 3;
2210 /* Any of the above functions may drop and re-acquire the lock, so check
2211 * to make sure a watchdog timer didn't mark the host as non-responsive.
2213 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2214 xhci_dbg(xhci
, "xHCI host dying, returning from "
2215 "event handler.\n");
2220 /* Update SW event ring dequeue pointer */
2221 inc_deq(xhci
, xhci
->event_ring
, true);
2223 /* Are there more items on the event ring? Caller will call us again to
2230 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2231 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2232 * indicators of an event TRB error, but we check the status *first* to be safe.
2234 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2236 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2238 union xhci_trb
*trb
;
2240 union xhci_trb
*event_ring_deq
;
2243 spin_lock(&xhci
->lock
);
2244 trb
= xhci
->event_ring
->dequeue
;
2245 /* Check if the xHC generated the interrupt, or the irq is shared */
2246 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2247 if (status
== 0xffffffff)
2250 if (!(status
& STS_EINT
)) {
2251 spin_unlock(&xhci
->lock
);
2254 if (status
& STS_FATAL
) {
2255 xhci_warn(xhci
, "WARNING: Host System Error\n");
2258 spin_unlock(&xhci
->lock
);
2263 * Clear the op reg interrupt status first,
2264 * so we can receive interrupts from other MSI-X interrupters.
2265 * Write 1 to clear the interrupt status.
2268 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2269 /* FIXME when MSI-X is supported and there are multiple vectors */
2270 /* Clear the MSI-X event interrupt status */
2272 if (hcd
->irq
!= -1) {
2274 /* Acknowledge the PCI interrupt */
2275 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2277 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2280 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2281 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2282 "Shouldn't IRQs be disabled?\n");
2283 /* Clear the event handler busy flag (RW1C);
2284 * the event ring should be empty.
2286 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2287 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2288 &xhci
->ir_set
->erst_dequeue
);
2289 spin_unlock(&xhci
->lock
);
2294 event_ring_deq
= xhci
->event_ring
->dequeue
;
2295 /* FIXME this should be a delayed service routine
2296 * that clears the EHB.
2298 while (xhci_handle_event(xhci
) > 0) {}
2300 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2301 /* If necessary, update the HW's version of the event ring deq ptr. */
2302 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2303 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2304 xhci
->event_ring
->dequeue
);
2306 xhci_warn(xhci
, "WARN something wrong with SW event "
2307 "ring dequeue ptr.\n");
2308 /* Update HC event ring dequeue pointer */
2309 temp_64
&= ERST_PTR_MASK
;
2310 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2313 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2314 temp_64
|= ERST_EHB
;
2315 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2317 spin_unlock(&xhci
->lock
);
2322 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2325 struct xhci_hcd
*xhci
;
2327 xhci
= hcd_to_xhci(hcd
);
2328 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
2329 if (xhci
->shared_hcd
)
2330 set_bit(HCD_FLAG_SAW_IRQ
, &xhci
->shared_hcd
->flags
);
2332 ret
= xhci_irq(hcd
);
2337 /**** Endpoint Ring Operations ****/
2340 * Generic function for queueing a TRB on a ring.
2341 * The caller must have checked to make sure there's room on the ring.
2343 * @more_trbs_coming: Will you enqueue more TRBs before calling
2344 * prepare_transfer()?
2346 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2347 bool consumer
, bool more_trbs_coming
,
2348 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2350 struct xhci_generic_trb
*trb
;
2352 trb
= &ring
->enqueue
->generic
;
2353 trb
->field
[0] = cpu_to_le32(field1
);
2354 trb
->field
[1] = cpu_to_le32(field2
);
2355 trb
->field
[2] = cpu_to_le32(field3
);
2356 trb
->field
[3] = cpu_to_le32(field4
);
2357 inc_enq(xhci
, ring
, consumer
, more_trbs_coming
);
2361 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2362 * FIXME allocate segments if the ring is full.
2364 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2365 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2367 /* Make sure the endpoint has been added to xHC schedule */
2369 case EP_STATE_DISABLED
:
2371 * USB core changed config/interfaces without notifying us,
2372 * or hardware is reporting the wrong state.
2374 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2376 case EP_STATE_ERROR
:
2377 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2378 /* FIXME event handling code for error needs to clear it */
2379 /* XXX not sure if this should be -ENOENT or not */
2381 case EP_STATE_HALTED
:
2382 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2383 case EP_STATE_STOPPED
:
2384 case EP_STATE_RUNNING
:
2387 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2389 * FIXME issue Configure Endpoint command to try to get the HC
2390 * back into a known state.
2394 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
2395 /* FIXME allocate more room */
2396 xhci_err(xhci
, "ERROR no room on ep ring\n");
2400 if (enqueue_is_link_trb(ep_ring
)) {
2401 struct xhci_ring
*ring
= ep_ring
;
2402 union xhci_trb
*next
;
2404 next
= ring
->enqueue
;
2406 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2407 /* If we're not dealing with 0.95 hardware,
2408 * clear the chain bit.
2410 if (!xhci_link_trb_quirk(xhci
))
2411 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2413 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2416 next
->link
.control
^= cpu_to_le32((u32
) TRB_CYCLE
);
2418 /* Toggle the cycle bit after the last ring segment. */
2419 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2420 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2421 if (!in_interrupt()) {
2422 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
2423 "state for ring %p = %i\n",
2424 ring
, (unsigned int)ring
->cycle_state
);
2427 ring
->enq_seg
= ring
->enq_seg
->next
;
2428 ring
->enqueue
= ring
->enq_seg
->trbs
;
2429 next
= ring
->enqueue
;
2436 static int prepare_transfer(struct xhci_hcd
*xhci
,
2437 struct xhci_virt_device
*xdev
,
2438 unsigned int ep_index
,
2439 unsigned int stream_id
,
2440 unsigned int num_trbs
,
2442 unsigned int td_index
,
2446 struct urb_priv
*urb_priv
;
2448 struct xhci_ring
*ep_ring
;
2449 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2451 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2453 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2458 ret
= prepare_ring(xhci
, ep_ring
,
2459 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2460 num_trbs
, mem_flags
);
2464 urb_priv
= urb
->hcpriv
;
2465 td
= urb_priv
->td
[td_index
];
2467 INIT_LIST_HEAD(&td
->td_list
);
2468 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2470 if (td_index
== 0) {
2471 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2472 if (unlikely(ret
)) {
2473 xhci_urb_free_priv(xhci
, urb_priv
);
2480 /* Add this TD to the tail of the endpoint ring's TD list */
2481 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2482 td
->start_seg
= ep_ring
->enq_seg
;
2483 td
->first_trb
= ep_ring
->enqueue
;
2485 urb_priv
->td
[td_index
] = td
;
2490 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2492 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2493 struct scatterlist
*sg
;
2496 num_sgs
= urb
->num_sgs
;
2497 temp
= urb
->transfer_buffer_length
;
2499 xhci_dbg(xhci
, "count sg list trbs: \n");
2501 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2502 unsigned int previous_total_trbs
= num_trbs
;
2503 unsigned int len
= sg_dma_len(sg
);
2505 /* Scatter gather list entries may cross 64KB boundaries */
2506 running_total
= TRB_MAX_BUFF_SIZE
-
2507 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2508 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2509 if (running_total
!= 0)
2512 /* How many more 64KB chunks to transfer, how many more TRBs? */
2513 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2515 running_total
+= TRB_MAX_BUFF_SIZE
;
2517 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2518 i
, (unsigned long long)sg_dma_address(sg
),
2519 len
, len
, num_trbs
- previous_total_trbs
);
2521 len
= min_t(int, len
, temp
);
2526 xhci_dbg(xhci
, "\n");
2527 if (!in_interrupt())
2528 xhci_dbg(xhci
, "ep %#x - urb len = %d, sglist used, "
2530 urb
->ep
->desc
.bEndpointAddress
,
2531 urb
->transfer_buffer_length
,
2536 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2539 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2540 "TRBs, %d left\n", __func__
,
2541 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2542 if (running_total
!= urb
->transfer_buffer_length
)
2543 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2544 "queued %#x (%d), asked for %#x (%d)\n",
2546 urb
->ep
->desc
.bEndpointAddress
,
2547 running_total
, running_total
,
2548 urb
->transfer_buffer_length
,
2549 urb
->transfer_buffer_length
);
2552 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2553 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2554 struct xhci_generic_trb
*start_trb
)
2557 * Pass all the TRBs to the hardware at once and make sure this write
2562 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2564 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2565 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2569 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2570 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2571 * (comprised of sg list entries) can take several service intervals to
2574 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2575 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2577 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2578 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2582 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2583 ep_interval
= urb
->interval
;
2584 /* Convert to microframes */
2585 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2586 urb
->dev
->speed
== USB_SPEED_FULL
)
2588 /* FIXME change this to a warning and a suggestion to use the new API
2589 * to set the polling interval (once the API is added).
2591 if (xhci_interval
!= ep_interval
) {
2592 if (printk_ratelimit())
2593 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2594 " (%d microframe%s) than xHCI "
2595 "(%d microframe%s)\n",
2597 ep_interval
== 1 ? "" : "s",
2599 xhci_interval
== 1 ? "" : "s");
2600 urb
->interval
= xhci_interval
;
2601 /* Convert back to frames for LS/FS devices */
2602 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2603 urb
->dev
->speed
== USB_SPEED_FULL
)
2606 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
2610 * The TD size is the number of bytes remaining in the TD (including this TRB),
2611 * right shifted by 10.
2612 * It must fit in bits 21:17, so it can't be bigger than 31.
2614 static u32
xhci_td_remainder(unsigned int remainder
)
2616 u32 max
= (1 << (21 - 17 + 1)) - 1;
2618 if ((remainder
>> 10) >= max
)
2621 return (remainder
>> 10) << 17;
2625 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2626 * the TD (*not* including this TRB).
2628 * Total TD packet count = total_packet_count =
2629 * roundup(TD size in bytes / wMaxPacketSize)
2631 * Packets transferred up to and including this TRB = packets_transferred =
2632 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2634 * TD size = total_packet_count - packets_transferred
2636 * It must fit in bits 21:17, so it can't be bigger than 31.
2639 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2640 unsigned int total_packet_count
, struct urb
*urb
)
2642 int packets_transferred
;
2644 /* All the TRB queueing functions don't count the current TRB in
2647 packets_transferred
= (running_total
+ trb_buff_len
) /
2648 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
);
2650 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2653 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2654 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2656 struct xhci_ring
*ep_ring
;
2657 unsigned int num_trbs
;
2658 struct urb_priv
*urb_priv
;
2660 struct scatterlist
*sg
;
2662 int trb_buff_len
, this_sg_len
, running_total
;
2663 unsigned int total_packet_count
;
2666 bool more_trbs_coming
;
2668 struct xhci_generic_trb
*start_trb
;
2671 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2675 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2676 num_sgs
= urb
->num_sgs
;
2677 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2678 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
2680 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2681 ep_index
, urb
->stream_id
,
2682 num_trbs
, urb
, 0, mem_flags
);
2683 if (trb_buff_len
< 0)
2684 return trb_buff_len
;
2686 urb_priv
= urb
->hcpriv
;
2687 td
= urb_priv
->td
[0];
2690 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2691 * until we've finished creating all the other TRBs. The ring's cycle
2692 * state may change as we enqueue the other TRBs, so save it too.
2694 start_trb
= &ep_ring
->enqueue
->generic
;
2695 start_cycle
= ep_ring
->cycle_state
;
2699 * How much data is in the first TRB?
2701 * There are three forces at work for TRB buffer pointers and lengths:
2702 * 1. We don't want to walk off the end of this sg-list entry buffer.
2703 * 2. The transfer length that the driver requested may be smaller than
2704 * the amount of memory allocated for this scatter-gather list.
2705 * 3. TRBs buffers can't cross 64KB boundaries.
2708 addr
= (u64
) sg_dma_address(sg
);
2709 this_sg_len
= sg_dma_len(sg
);
2710 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2711 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2712 if (trb_buff_len
> urb
->transfer_buffer_length
)
2713 trb_buff_len
= urb
->transfer_buffer_length
;
2714 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2718 /* Queue the first TRB, even if it's zero-length */
2721 u32 length_field
= 0;
2724 /* Don't change the cycle bit of the first TRB until later */
2727 if (start_cycle
== 0)
2730 field
|= ep_ring
->cycle_state
;
2732 /* Chain all the TRBs together; clear the chain bit in the last
2733 * TRB to indicate it's the last TRB in the chain.
2738 /* FIXME - add check for ZERO_PACKET flag before this */
2739 td
->last_trb
= ep_ring
->enqueue
;
2743 /* Only set interrupt on short packet for IN endpoints */
2744 if (usb_urb_dir_in(urb
))
2747 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2748 "64KB boundary at %#x, end dma = %#x\n",
2749 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2750 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2751 (unsigned int) addr
+ trb_buff_len
);
2752 if (TRB_MAX_BUFF_SIZE
-
2753 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2754 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2755 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2756 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2757 (unsigned int) addr
+ trb_buff_len
);
2760 /* Set the TRB length, TD size, and interrupter fields. */
2761 if (xhci
->hci_version
< 0x100) {
2762 remainder
= xhci_td_remainder(
2763 urb
->transfer_buffer_length
-
2766 remainder
= xhci_v1_0_td_remainder(running_total
,
2767 trb_buff_len
, total_packet_count
, urb
);
2769 length_field
= TRB_LEN(trb_buff_len
) |
2774 more_trbs_coming
= true;
2776 more_trbs_coming
= false;
2777 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2778 lower_32_bits(addr
),
2779 upper_32_bits(addr
),
2781 field
| TRB_TYPE(TRB_NORMAL
));
2783 running_total
+= trb_buff_len
;
2785 /* Calculate length for next transfer --
2786 * Are we done queueing all the TRBs for this sg entry?
2788 this_sg_len
-= trb_buff_len
;
2789 if (this_sg_len
== 0) {
2794 addr
= (u64
) sg_dma_address(sg
);
2795 this_sg_len
= sg_dma_len(sg
);
2797 addr
+= trb_buff_len
;
2800 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2801 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2802 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2803 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2805 urb
->transfer_buffer_length
- running_total
;
2806 } while (running_total
< urb
->transfer_buffer_length
);
2808 check_trb_math(urb
, num_trbs
, running_total
);
2809 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2810 start_cycle
, start_trb
);
2814 /* This is very similar to what ehci-q.c qtd_fill() does */
2815 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2816 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2818 struct xhci_ring
*ep_ring
;
2819 struct urb_priv
*urb_priv
;
2822 struct xhci_generic_trb
*start_trb
;
2824 bool more_trbs_coming
;
2826 u32 field
, length_field
;
2828 int running_total
, trb_buff_len
, ret
;
2829 unsigned int total_packet_count
;
2833 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2835 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2840 /* How much data is (potentially) left before the 64KB boundary? */
2841 running_total
= TRB_MAX_BUFF_SIZE
-
2842 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2843 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2845 /* If there's some data on this 64KB chunk, or we have to send a
2846 * zero-length transfer, we need at least one TRB
2848 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2850 /* How many more 64KB chunks to transfer, how many more TRBs? */
2851 while (running_total
< urb
->transfer_buffer_length
) {
2853 running_total
+= TRB_MAX_BUFF_SIZE
;
2855 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2857 if (!in_interrupt())
2858 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d), "
2859 "addr = %#llx, num_trbs = %d\n",
2860 urb
->ep
->desc
.bEndpointAddress
,
2861 urb
->transfer_buffer_length
,
2862 urb
->transfer_buffer_length
,
2863 (unsigned long long)urb
->transfer_dma
,
2866 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2867 ep_index
, urb
->stream_id
,
2868 num_trbs
, urb
, 0, mem_flags
);
2872 urb_priv
= urb
->hcpriv
;
2873 td
= urb_priv
->td
[0];
2876 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2877 * until we've finished creating all the other TRBs. The ring's cycle
2878 * state may change as we enqueue the other TRBs, so save it too.
2880 start_trb
= &ep_ring
->enqueue
->generic
;
2881 start_cycle
= ep_ring
->cycle_state
;
2884 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2885 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
2886 /* How much data is in the first TRB? */
2887 addr
= (u64
) urb
->transfer_dma
;
2888 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2889 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2890 if (trb_buff_len
> urb
->transfer_buffer_length
)
2891 trb_buff_len
= urb
->transfer_buffer_length
;
2895 /* Queue the first TRB, even if it's zero-length */
2900 /* Don't change the cycle bit of the first TRB until later */
2903 if (start_cycle
== 0)
2906 field
|= ep_ring
->cycle_state
;
2908 /* Chain all the TRBs together; clear the chain bit in the last
2909 * TRB to indicate it's the last TRB in the chain.
2914 /* FIXME - add check for ZERO_PACKET flag before this */
2915 td
->last_trb
= ep_ring
->enqueue
;
2919 /* Only set interrupt on short packet for IN endpoints */
2920 if (usb_urb_dir_in(urb
))
2923 /* Set the TRB length, TD size, and interrupter fields. */
2924 if (xhci
->hci_version
< 0x100) {
2925 remainder
= xhci_td_remainder(
2926 urb
->transfer_buffer_length
-
2929 remainder
= xhci_v1_0_td_remainder(running_total
,
2930 trb_buff_len
, total_packet_count
, urb
);
2932 length_field
= TRB_LEN(trb_buff_len
) |
2937 more_trbs_coming
= true;
2939 more_trbs_coming
= false;
2940 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2941 lower_32_bits(addr
),
2942 upper_32_bits(addr
),
2944 field
| TRB_TYPE(TRB_NORMAL
));
2946 running_total
+= trb_buff_len
;
2948 /* Calculate length for next transfer */
2949 addr
+= trb_buff_len
;
2950 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2951 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2952 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2953 } while (running_total
< urb
->transfer_buffer_length
);
2955 check_trb_math(urb
, num_trbs
, running_total
);
2956 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2957 start_cycle
, start_trb
);
2961 /* Caller must have locked xhci->lock */
2962 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2963 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2965 struct xhci_ring
*ep_ring
;
2968 struct usb_ctrlrequest
*setup
;
2969 struct xhci_generic_trb
*start_trb
;
2971 u32 field
, length_field
;
2972 struct urb_priv
*urb_priv
;
2975 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2980 * Need to copy setup packet into setup TRB, so we can't use the setup
2983 if (!urb
->setup_packet
)
2986 if (!in_interrupt())
2987 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
2989 /* 1 TRB for setup, 1 for status */
2992 * Don't need to check if we need additional event data and normal TRBs,
2993 * since data in control transfers will never get bigger than 16MB
2994 * XXX: can we get a buffer that crosses 64KB boundaries?
2996 if (urb
->transfer_buffer_length
> 0)
2998 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2999 ep_index
, urb
->stream_id
,
3000 num_trbs
, urb
, 0, mem_flags
);
3004 urb_priv
= urb
->hcpriv
;
3005 td
= urb_priv
->td
[0];
3008 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3009 * until we've finished creating all the other TRBs. The ring's cycle
3010 * state may change as we enqueue the other TRBs, so save it too.
3012 start_trb
= &ep_ring
->enqueue
->generic
;
3013 start_cycle
= ep_ring
->cycle_state
;
3015 /* Queue setup TRB - see section 6.4.1.2.1 */
3016 /* FIXME better way to translate setup_packet into two u32 fields? */
3017 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3019 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3020 if (start_cycle
== 0)
3023 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3024 if (xhci
->hci_version
== 0x100) {
3025 if (urb
->transfer_buffer_length
> 0) {
3026 if (setup
->bRequestType
& USB_DIR_IN
)
3027 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3029 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3033 queue_trb(xhci
, ep_ring
, false, true,
3034 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3035 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3036 TRB_LEN(8) | TRB_INTR_TARGET(0),
3037 /* Immediate data in pointer */
3040 /* If there's data, queue data TRBs */
3041 /* Only set interrupt on short packet for IN endpoints */
3042 if (usb_urb_dir_in(urb
))
3043 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3045 field
= TRB_TYPE(TRB_DATA
);
3047 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3048 xhci_td_remainder(urb
->transfer_buffer_length
) |
3050 if (urb
->transfer_buffer_length
> 0) {
3051 if (setup
->bRequestType
& USB_DIR_IN
)
3052 field
|= TRB_DIR_IN
;
3053 queue_trb(xhci
, ep_ring
, false, true,
3054 lower_32_bits(urb
->transfer_dma
),
3055 upper_32_bits(urb
->transfer_dma
),
3057 field
| ep_ring
->cycle_state
);
3060 /* Save the DMA address of the last TRB in the TD */
3061 td
->last_trb
= ep_ring
->enqueue
;
3063 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3064 /* If the device sent data, the status stage is an OUT transfer */
3065 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3069 queue_trb(xhci
, ep_ring
, false, false,
3073 /* Event on completion */
3074 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3076 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3077 start_cycle
, start_trb
);
3081 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3082 struct urb
*urb
, int i
)
3085 u64 addr
, td_len
, running_total
;
3087 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3088 td_len
= urb
->iso_frame_desc
[i
].length
;
3090 running_total
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3091 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3092 if (running_total
!= 0)
3095 while (running_total
< td_len
) {
3097 running_total
+= TRB_MAX_BUFF_SIZE
;
3104 * The transfer burst count field of the isochronous TRB defines the number of
3105 * bursts that are required to move all packets in this TD. Only SuperSpeed
3106 * devices can burst up to bMaxBurst number of packets per service interval.
3107 * This field is zero based, meaning a value of zero in the field means one
3108 * burst. Basically, for everything but SuperSpeed devices, this field will be
3109 * zero. Only xHCI 1.0 host controllers support this field.
3111 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3112 struct usb_device
*udev
,
3113 struct urb
*urb
, unsigned int total_packet_count
)
3115 unsigned int max_burst
;
3117 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3120 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3121 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3125 * Returns the number of packets in the last "burst" of packets. This field is
3126 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3127 * the last burst packet count is equal to the total number of packets in the
3128 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3129 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3130 * contain 1 to (bMaxBurst + 1) packets.
3132 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3133 struct usb_device
*udev
,
3134 struct urb
*urb
, unsigned int total_packet_count
)
3136 unsigned int max_burst
;
3137 unsigned int residue
;
3139 if (xhci
->hci_version
< 0x100)
3142 switch (udev
->speed
) {
3143 case USB_SPEED_SUPER
:
3144 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3145 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3146 residue
= total_packet_count
% (max_burst
+ 1);
3147 /* If residue is zero, the last burst contains (max_burst + 1)
3148 * number of packets, but the TLBPC field is zero-based.
3154 if (total_packet_count
== 0)
3156 return total_packet_count
- 1;
3160 /* This is for isoc transfer */
3161 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3162 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3164 struct xhci_ring
*ep_ring
;
3165 struct urb_priv
*urb_priv
;
3167 int num_tds
, trbs_per_td
;
3168 struct xhci_generic_trb
*start_trb
;
3171 u32 field
, length_field
;
3172 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3173 u64 start_addr
, addr
;
3175 bool more_trbs_coming
;
3177 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3179 num_tds
= urb
->number_of_packets
;
3181 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3185 if (!in_interrupt())
3186 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d),"
3187 " addr = %#llx, num_tds = %d\n",
3188 urb
->ep
->desc
.bEndpointAddress
,
3189 urb
->transfer_buffer_length
,
3190 urb
->transfer_buffer_length
,
3191 (unsigned long long)urb
->transfer_dma
,
3194 start_addr
= (u64
) urb
->transfer_dma
;
3195 start_trb
= &ep_ring
->enqueue
->generic
;
3196 start_cycle
= ep_ring
->cycle_state
;
3198 /* Queue the first TRB, even if it's zero-length */
3199 for (i
= 0; i
< num_tds
; i
++) {
3200 unsigned int total_packet_count
;
3201 unsigned int burst_count
;
3202 unsigned int residue
;
3206 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3207 td_len
= urb
->iso_frame_desc
[i
].length
;
3208 td_remain_len
= td_len
;
3209 /* FIXME: Ignoring zero-length packets, can those happen? */
3210 total_packet_count
= roundup(td_len
,
3211 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
3212 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3213 total_packet_count
);
3214 residue
= xhci_get_last_burst_packet_count(xhci
,
3215 urb
->dev
, urb
, total_packet_count
);
3217 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3219 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3220 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3224 urb_priv
= urb
->hcpriv
;
3225 td
= urb_priv
->td
[i
];
3227 for (j
= 0; j
< trbs_per_td
; j
++) {
3229 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3232 /* Queue the isoc TRB */
3233 field
|= TRB_TYPE(TRB_ISOC
);
3234 /* Assume URB_ISO_ASAP is set */
3237 if (start_cycle
== 0)
3240 field
|= ep_ring
->cycle_state
;
3243 /* Queue other normal TRBs */
3244 field
|= TRB_TYPE(TRB_NORMAL
);
3245 field
|= ep_ring
->cycle_state
;
3248 /* Only set interrupt on short packet for IN EPs */
3249 if (usb_urb_dir_in(urb
))
3252 /* Chain all the TRBs together; clear the chain bit in
3253 * the last TRB to indicate it's the last TRB in the
3256 if (j
< trbs_per_td
- 1) {
3258 more_trbs_coming
= true;
3260 td
->last_trb
= ep_ring
->enqueue
;
3262 if (xhci
->hci_version
== 0x100) {
3263 /* Set BEI bit except for the last td */
3264 if (i
< num_tds
- 1)
3267 more_trbs_coming
= false;
3270 /* Calculate TRB length */
3271 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3272 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3273 if (trb_buff_len
> td_remain_len
)
3274 trb_buff_len
= td_remain_len
;
3276 /* Set the TRB length, TD size, & interrupter fields. */
3277 if (xhci
->hci_version
< 0x100) {
3278 remainder
= xhci_td_remainder(
3279 td_len
- running_total
);
3281 remainder
= xhci_v1_0_td_remainder(
3282 running_total
, trb_buff_len
,
3283 total_packet_count
, urb
);
3285 length_field
= TRB_LEN(trb_buff_len
) |
3289 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
3290 lower_32_bits(addr
),
3291 upper_32_bits(addr
),
3294 running_total
+= trb_buff_len
;
3296 addr
+= trb_buff_len
;
3297 td_remain_len
-= trb_buff_len
;
3300 /* Check TD length */
3301 if (running_total
!= td_len
) {
3302 xhci_err(xhci
, "ISOC TD length unmatch\n");
3307 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3308 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3309 usb_amd_quirk_pll_disable();
3311 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3313 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3314 start_cycle
, start_trb
);
3319 * Check transfer ring to guarantee there is enough room for the urb.
3320 * Update ISO URB start_frame and interval.
3321 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3322 * update the urb->start_frame by now.
3323 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3325 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3326 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3328 struct xhci_virt_device
*xdev
;
3329 struct xhci_ring
*ep_ring
;
3330 struct xhci_ep_ctx
*ep_ctx
;
3334 int num_tds
, num_trbs
, i
;
3337 xdev
= xhci
->devs
[slot_id
];
3338 ep_ring
= xdev
->eps
[ep_index
].ring
;
3339 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3342 num_tds
= urb
->number_of_packets
;
3343 for (i
= 0; i
< num_tds
; i
++)
3344 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3346 /* Check the ring to guarantee there is enough room for the whole urb.
3347 * Do not insert any td of the urb to the ring if the check failed.
3349 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3350 num_trbs
, mem_flags
);
3354 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3355 start_frame
&= 0x3fff;
3357 urb
->start_frame
= start_frame
;
3358 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3359 urb
->dev
->speed
== USB_SPEED_FULL
)
3360 urb
->start_frame
>>= 3;
3362 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3363 ep_interval
= urb
->interval
;
3364 /* Convert to microframes */
3365 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3366 urb
->dev
->speed
== USB_SPEED_FULL
)
3368 /* FIXME change this to a warning and a suggestion to use the new API
3369 * to set the polling interval (once the API is added).
3371 if (xhci_interval
!= ep_interval
) {
3372 if (printk_ratelimit())
3373 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3374 " (%d microframe%s) than xHCI "
3375 "(%d microframe%s)\n",
3377 ep_interval
== 1 ? "" : "s",
3379 xhci_interval
== 1 ? "" : "s");
3380 urb
->interval
= xhci_interval
;
3381 /* Convert back to frames for LS/FS devices */
3382 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3383 urb
->dev
->speed
== USB_SPEED_FULL
)
3386 return xhci_queue_isoc_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
3389 /**** Command Ring Operations ****/
3391 /* Generic function for queueing a command TRB on the command ring.
3392 * Check to make sure there's room on the command ring for one command TRB.
3393 * Also check that there's room reserved for commands that must not fail.
3394 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3395 * then only check for the number of reserved spots.
3396 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3397 * because the command event handler may want to resubmit a failed command.
3399 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3400 u32 field3
, u32 field4
, bool command_must_succeed
)
3402 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3405 if (!command_must_succeed
)
3408 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3409 reserved_trbs
, GFP_ATOMIC
);
3411 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3412 if (command_must_succeed
)
3413 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3414 "unfailable commands failed.\n");
3417 queue_trb(xhci
, xhci
->cmd_ring
, false, false, field1
, field2
, field3
,
3418 field4
| xhci
->cmd_ring
->cycle_state
);
3422 /* Queue a slot enable or disable request on the command ring */
3423 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3425 return queue_command(xhci
, 0, 0, 0,
3426 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3429 /* Queue an address device command TRB */
3430 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3433 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3434 upper_32_bits(in_ctx_ptr
), 0,
3435 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3439 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3440 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3442 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3445 /* Queue a reset device command TRB */
3446 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3448 return queue_command(xhci
, 0, 0, 0,
3449 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3453 /* Queue a configure endpoint command TRB */
3454 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3455 u32 slot_id
, bool command_must_succeed
)
3457 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3458 upper_32_bits(in_ctx_ptr
), 0,
3459 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3460 command_must_succeed
);
3463 /* Queue an evaluate context command TRB */
3464 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3467 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3468 upper_32_bits(in_ctx_ptr
), 0,
3469 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3474 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3475 * activity on an endpoint that is about to be suspended.
3477 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3478 unsigned int ep_index
, int suspend
)
3480 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3481 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3482 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3483 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3485 return queue_command(xhci
, 0, 0, 0,
3486 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3489 /* Set Transfer Ring Dequeue Pointer command.
3490 * This should not be used for endpoints that have streams enabled.
3492 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3493 unsigned int ep_index
, unsigned int stream_id
,
3494 struct xhci_segment
*deq_seg
,
3495 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3498 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3499 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3500 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3501 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3502 struct xhci_virt_ep
*ep
;
3504 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3506 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3507 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3511 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3512 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3513 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3514 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3517 ep
->queued_deq_seg
= deq_seg
;
3518 ep
->queued_deq_ptr
= deq_ptr
;
3519 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3520 upper_32_bits(addr
), trb_stream_id
,
3521 trb_slot_id
| trb_ep_index
| type
, false);
3524 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3525 unsigned int ep_index
)
3527 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3528 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3529 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3531 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,