2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2009 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-rnm-defs.h>
18 static struct octeon_cf_data octeon_cf_data
;
20 static int __init
octeon_cf_device_init(void)
22 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg
;
23 unsigned long base_ptr
, region_base
, region_size
;
24 struct platform_device
*pd
;
25 struct resource cf_resources
[3];
26 unsigned int num_resources
;
30 /* Setup octeon-cf platform device if present. */
32 if (octeon_bootinfo
->major_version
== 1
33 && octeon_bootinfo
->minor_version
>= 1) {
34 if (octeon_bootinfo
->compact_flash_common_base_addr
)
36 octeon_bootinfo
->compact_flash_common_base_addr
;
38 base_ptr
= 0x1d000800;
44 /* Find CS0 region. */
45 for (i
= 0; i
< 8; i
++) {
46 mio_boot_reg_cfg
.u64
= cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i
));
47 region_base
= mio_boot_reg_cfg
.s
.base
<< 16;
48 region_size
= (mio_boot_reg_cfg
.s
.size
+ 1) << 16;
49 if (mio_boot_reg_cfg
.s
.en
&& base_ptr
>= region_base
50 && base_ptr
< region_base
+ region_size
)
54 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
57 octeon_cf_data
.base_region
= i
;
58 octeon_cf_data
.is16bit
= mio_boot_reg_cfg
.s
.width
;
59 octeon_cf_data
.base_region_bias
= base_ptr
- region_base
;
60 memset(cf_resources
, 0, sizeof(cf_resources
));
62 cf_resources
[num_resources
].flags
= IORESOURCE_MEM
;
63 cf_resources
[num_resources
].start
= region_base
;
64 cf_resources
[num_resources
].end
= region_base
+ region_size
- 1;
68 if (!(base_ptr
& 0xfffful
)) {
70 * Boot loader signals availability of DMA (true_ide
71 * mode) by setting low order bits of base_ptr to
75 /* Asume that CS1 immediately follows. */
76 mio_boot_reg_cfg
.u64
=
77 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i
+ 1));
78 region_base
= mio_boot_reg_cfg
.s
.base
<< 16;
79 region_size
= (mio_boot_reg_cfg
.s
.size
+ 1) << 16;
80 if (!mio_boot_reg_cfg
.s
.en
)
83 cf_resources
[num_resources
].flags
= IORESOURCE_MEM
;
84 cf_resources
[num_resources
].start
= region_base
;
85 cf_resources
[num_resources
].end
= region_base
+ region_size
- 1;
88 octeon_cf_data
.dma_engine
= 0;
89 cf_resources
[num_resources
].flags
= IORESOURCE_IRQ
;
90 cf_resources
[num_resources
].start
= OCTEON_IRQ_BOOTDMA
;
91 cf_resources
[num_resources
].end
= OCTEON_IRQ_BOOTDMA
;
94 octeon_cf_data
.dma_engine
= -1;
97 pd
= platform_device_alloc("pata_octeon_cf", -1);
102 pd
->dev
.platform_data
= &octeon_cf_data
;
104 ret
= platform_device_add_resources(pd
, cf_resources
, num_resources
);
108 ret
= platform_device_add(pd
);
114 platform_device_put(pd
);
118 device_initcall(octeon_cf_device_init
);
120 /* Octeon Random Number Generator. */
121 static int __init
octeon_rng_device_init(void)
123 struct platform_device
*pd
;
126 struct resource rng_resources
[] = {
128 .flags
= IORESOURCE_MEM
,
129 .start
= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS
),
130 .end
= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS
) + 0xf
132 .flags
= IORESOURCE_MEM
,
133 .start
= cvmx_build_io_address(8, 0),
134 .end
= cvmx_build_io_address(8, 0) + 0x7
138 pd
= platform_device_alloc("octeon_rng", -1);
144 ret
= platform_device_add_resources(pd
, rng_resources
,
145 ARRAY_SIZE(rng_resources
));
149 ret
= platform_device_add(pd
);
155 platform_device_put(pd
);
160 device_initcall(octeon_rng_device_init
);
163 #define OCTEON_I2C_IO_BASE 0x1180000001000ull
164 #define OCTEON_I2C_IO_UNIT_OFFSET 0x200
166 static struct octeon_i2c_data octeon_i2c_data
[2];
168 static int __init
octeon_i2c_device_init(void)
170 struct platform_device
*pd
;
174 struct resource i2c_resources
[] = {
176 .flags
= IORESOURCE_MEM
,
178 .flags
= IORESOURCE_IRQ
,
182 if (OCTEON_IS_MODEL(OCTEON_CN56XX
) || OCTEON_IS_MODEL(OCTEON_CN52XX
))
187 for (port
= 0; port
< num_ports
; port
++) {
188 octeon_i2c_data
[port
].sys_freq
= octeon_get_clock_rate();
189 /*FIXME: should be examined. At the moment is set for 100Khz */
190 octeon_i2c_data
[port
].i2c_freq
= 100000;
192 pd
= platform_device_alloc("i2c-octeon", port
);
198 pd
->dev
.platform_data
= octeon_i2c_data
+ port
;
200 i2c_resources
[0].start
=
201 OCTEON_I2C_IO_BASE
+ (port
* OCTEON_I2C_IO_UNIT_OFFSET
);
202 i2c_resources
[0].end
= i2c_resources
[0].start
+ 0x1f;
205 i2c_resources
[1].start
= OCTEON_IRQ_TWSI
;
206 i2c_resources
[1].end
= OCTEON_IRQ_TWSI
;
209 i2c_resources
[1].start
= OCTEON_IRQ_TWSI2
;
210 i2c_resources
[1].end
= OCTEON_IRQ_TWSI2
;
216 ret
= platform_device_add_resources(pd
,
218 ARRAY_SIZE(i2c_resources
));
222 ret
= platform_device_add(pd
);
228 platform_device_put(pd
);
232 device_initcall(octeon_i2c_device_init
);
234 /* Octeon SMI/MDIO interface. */
235 static int __init
octeon_mdiobus_device_init(void)
237 struct platform_device
*pd
;
240 if (octeon_is_simulation())
241 return 0; /* No mdio in the simulator. */
243 /* The bus number is the platform_device id. */
244 pd
= platform_device_alloc("mdio-octeon", 0);
250 ret
= platform_device_add(pd
);
256 platform_device_put(pd
);
262 device_initcall(octeon_mdiobus_device_init
);
264 /* Octeon mgmt port Ethernet interface. */
265 static int __init
octeon_mgmt_device_init(void)
267 struct platform_device
*pd
;
271 struct resource mgmt_port_resource
= {
272 .flags
= IORESOURCE_IRQ
,
277 if (!OCTEON_IS_MODEL(OCTEON_CN56XX
) && !OCTEON_IS_MODEL(OCTEON_CN52XX
))
280 if (OCTEON_IS_MODEL(OCTEON_CN56XX
))
285 for (port
= 0; port
< num_ports
; port
++) {
286 pd
= platform_device_alloc("octeon_mgmt", port
);
293 mgmt_port_resource
.start
= OCTEON_IRQ_MII0
;
296 mgmt_port_resource
.start
= OCTEON_IRQ_MII1
;
301 mgmt_port_resource
.end
= mgmt_port_resource
.start
;
303 ret
= platform_device_add_resources(pd
, &mgmt_port_resource
, 1);
308 ret
= platform_device_add(pd
);
314 platform_device_put(pd
);
320 device_initcall(octeon_mgmt_device_init
);
322 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
323 MODULE_LICENSE("GPL");
324 MODULE_DESCRIPTION("Platform driver for Octeon SOC");