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KVM: SVM: Use svm_flush_tlb instead of force_new_asid
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob7272b364580ca9d441508eebd0a3a30596a25f39
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
62 static bool erratum_383_found __read_mostly;
63
64 static const u32 host_save_user_msrs[] = {
65 #ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68 #endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70 };
71
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74 struct kvm_vcpu;
75
76 struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
79 u64 vm_cr_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87 u64 vmcb_iopm;
88
89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
125 struct {
126 u16 fs;
127 u16 gs;
128 u16 ldt;
129 u64 gs_base;
130 } host;
131
132 u32 *msrpm;
133
134 struct nested_state nested;
135
136 bool nmi_singlestep;
137
138 unsigned int3_injected;
139 unsigned long int3_rip;
140 u32 apf_reason;
141 };
142
143 #define MSR_INVALID 0xffffffffU
144
145 static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148 } direct_access_msrs[] = {
149 { .index = MSR_STAR, .always = true },
150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151 #ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158 #endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
164 };
165
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled = true;
169 #else
170 static bool npt_enabled;
171 #endif
172 static int npt = 1;
173
174 module_param(npt, int, S_IRUGO);
175
176 static int nested = 1;
177 module_param(nested, int, S_IRUGO);
178
179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
180 static void svm_complete_interrupts(struct vcpu_svm *svm);
181
182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
183 static int nested_svm_intercept(struct vcpu_svm *svm);
184 static int nested_svm_vmexit(struct vcpu_svm *svm);
185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
188 enum {
189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
192 VMCB_ASID, /* ASID */
193 VMCB_INTR, /* int_ctl, int_vector */
194 VMCB_NPT, /* npt_en, nCR3, gPAT */
195 VMCB_CR, /* CR0, CR3, CR4, EFER */
196 VMCB_DR, /* DR6, DR7 */
197 VMCB_DT, /* GDT, IDT */
198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
199 VMCB_CR2, /* CR2 only */
200 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
201 VMCB_DIRTY_MAX,
202 };
203
204 /* TPR and CR2 are always written before VMRUN */
205 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
206
207 static inline void mark_all_dirty(struct vmcb *vmcb)
208 {
209 vmcb->control.clean = 0;
210 }
211
212 static inline void mark_all_clean(struct vmcb *vmcb)
213 {
214 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
215 & ~VMCB_ALWAYS_DIRTY_MASK;
216 }
217
218 static inline void mark_dirty(struct vmcb *vmcb, int bit)
219 {
220 vmcb->control.clean &= ~(1 << bit);
221 }
222
223 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
224 {
225 return container_of(vcpu, struct vcpu_svm, vcpu);
226 }
227
228 static void recalc_intercepts(struct vcpu_svm *svm)
229 {
230 struct vmcb_control_area *c, *h;
231 struct nested_state *g;
232
233 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
234
235 if (!is_guest_mode(&svm->vcpu))
236 return;
237
238 c = &svm->vmcb->control;
239 h = &svm->nested.hsave->control;
240 g = &svm->nested;
241
242 c->intercept_cr = h->intercept_cr | g->intercept_cr;
243 c->intercept_dr = h->intercept_dr | g->intercept_dr;
244 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
245 c->intercept = h->intercept | g->intercept;
246 }
247
248 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
249 {
250 if (is_guest_mode(&svm->vcpu))
251 return svm->nested.hsave;
252 else
253 return svm->vmcb;
254 }
255
256 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
257 {
258 struct vmcb *vmcb = get_host_vmcb(svm);
259
260 vmcb->control.intercept_cr |= (1U << bit);
261
262 recalc_intercepts(svm);
263 }
264
265 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
266 {
267 struct vmcb *vmcb = get_host_vmcb(svm);
268
269 vmcb->control.intercept_cr &= ~(1U << bit);
270
271 recalc_intercepts(svm);
272 }
273
274 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
275 {
276 struct vmcb *vmcb = get_host_vmcb(svm);
277
278 return vmcb->control.intercept_cr & (1U << bit);
279 }
280
281 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_dr |= (1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_dr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297 }
298
299 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
300 {
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 vmcb->control.intercept_exceptions |= (1U << bit);
304
305 recalc_intercepts(svm);
306 }
307
308 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
309 {
310 struct vmcb *vmcb = get_host_vmcb(svm);
311
312 vmcb->control.intercept_exceptions &= ~(1U << bit);
313
314 recalc_intercepts(svm);
315 }
316
317 static inline void set_intercept(struct vcpu_svm *svm, int bit)
318 {
319 struct vmcb *vmcb = get_host_vmcb(svm);
320
321 vmcb->control.intercept |= (1ULL << bit);
322
323 recalc_intercepts(svm);
324 }
325
326 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
327 {
328 struct vmcb *vmcb = get_host_vmcb(svm);
329
330 vmcb->control.intercept &= ~(1ULL << bit);
331
332 recalc_intercepts(svm);
333 }
334
335 static inline void enable_gif(struct vcpu_svm *svm)
336 {
337 svm->vcpu.arch.hflags |= HF_GIF_MASK;
338 }
339
340 static inline void disable_gif(struct vcpu_svm *svm)
341 {
342 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
343 }
344
345 static inline bool gif_set(struct vcpu_svm *svm)
346 {
347 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
348 }
349
350 static unsigned long iopm_base;
351
352 struct kvm_ldttss_desc {
353 u16 limit0;
354 u16 base0;
355 unsigned base1:8, type:5, dpl:2, p:1;
356 unsigned limit1:4, zero0:3, g:1, base2:8;
357 u32 base3;
358 u32 zero1;
359 } __attribute__((packed));
360
361 struct svm_cpu_data {
362 int cpu;
363
364 u64 asid_generation;
365 u32 max_asid;
366 u32 next_asid;
367 struct kvm_ldttss_desc *tss_desc;
368
369 struct page *save_area;
370 };
371
372 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
373 static uint32_t svm_features;
374
375 struct svm_init_data {
376 int cpu;
377 int r;
378 };
379
380 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
381
382 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
383 #define MSRS_RANGE_SIZE 2048
384 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
385
386 static u32 svm_msrpm_offset(u32 msr)
387 {
388 u32 offset;
389 int i;
390
391 for (i = 0; i < NUM_MSR_MAPS; i++) {
392 if (msr < msrpm_ranges[i] ||
393 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
394 continue;
395
396 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
397 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
398
399 /* Now we have the u8 offset - but need the u32 offset */
400 return offset / 4;
401 }
402
403 /* MSR not in any range */
404 return MSR_INVALID;
405 }
406
407 #define MAX_INST_SIZE 15
408
409 static inline void clgi(void)
410 {
411 asm volatile (__ex(SVM_CLGI));
412 }
413
414 static inline void stgi(void)
415 {
416 asm volatile (__ex(SVM_STGI));
417 }
418
419 static inline void invlpga(unsigned long addr, u32 asid)
420 {
421 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
422 }
423
424 static int get_npt_level(void)
425 {
426 #ifdef CONFIG_X86_64
427 return PT64_ROOT_LEVEL;
428 #else
429 return PT32E_ROOT_LEVEL;
430 #endif
431 }
432
433 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
434 {
435 vcpu->arch.efer = efer;
436 if (!npt_enabled && !(efer & EFER_LMA))
437 efer &= ~EFER_LME;
438
439 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
440 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
441 }
442
443 static int is_external_interrupt(u32 info)
444 {
445 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
446 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
447 }
448
449 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
450 {
451 struct vcpu_svm *svm = to_svm(vcpu);
452 u32 ret = 0;
453
454 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
455 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
456 return ret & mask;
457 }
458
459 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
460 {
461 struct vcpu_svm *svm = to_svm(vcpu);
462
463 if (mask == 0)
464 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
465 else
466 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
467
468 }
469
470 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
471 {
472 struct vcpu_svm *svm = to_svm(vcpu);
473
474 if (svm->vmcb->control.next_rip != 0)
475 svm->next_rip = svm->vmcb->control.next_rip;
476
477 if (!svm->next_rip) {
478 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
479 EMULATE_DONE)
480 printk(KERN_DEBUG "%s: NOP\n", __func__);
481 return;
482 }
483 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
484 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
485 __func__, kvm_rip_read(vcpu), svm->next_rip);
486
487 kvm_rip_write(vcpu, svm->next_rip);
488 svm_set_interrupt_shadow(vcpu, 0);
489 }
490
491 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
492 bool has_error_code, u32 error_code,
493 bool reinject)
494 {
495 struct vcpu_svm *svm = to_svm(vcpu);
496
497 /*
498 * If we are within a nested VM we'd better #VMEXIT and let the guest
499 * handle the exception
500 */
501 if (!reinject &&
502 nested_svm_check_exception(svm, nr, has_error_code, error_code))
503 return;
504
505 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
506 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
507
508 /*
509 * For guest debugging where we have to reinject #BP if some
510 * INT3 is guest-owned:
511 * Emulate nRIP by moving RIP forward. Will fail if injection
512 * raises a fault that is not intercepted. Still better than
513 * failing in all cases.
514 */
515 skip_emulated_instruction(&svm->vcpu);
516 rip = kvm_rip_read(&svm->vcpu);
517 svm->int3_rip = rip + svm->vmcb->save.cs.base;
518 svm->int3_injected = rip - old_rip;
519 }
520
521 svm->vmcb->control.event_inj = nr
522 | SVM_EVTINJ_VALID
523 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
524 | SVM_EVTINJ_TYPE_EXEPT;
525 svm->vmcb->control.event_inj_err = error_code;
526 }
527
528 static void svm_init_erratum_383(void)
529 {
530 u32 low, high;
531 int err;
532 u64 val;
533
534 if (!cpu_has_amd_erratum(amd_erratum_383))
535 return;
536
537 /* Use _safe variants to not break nested virtualization */
538 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
539 if (err)
540 return;
541
542 val |= (1ULL << 47);
543
544 low = lower_32_bits(val);
545 high = upper_32_bits(val);
546
547 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
548
549 erratum_383_found = true;
550 }
551
552 static int has_svm(void)
553 {
554 const char *msg;
555
556 if (!cpu_has_svm(&msg)) {
557 printk(KERN_INFO "has_svm: %s\n", msg);
558 return 0;
559 }
560
561 return 1;
562 }
563
564 static void svm_hardware_disable(void *garbage)
565 {
566 cpu_svm_disable();
567 }
568
569 static int svm_hardware_enable(void *garbage)
570 {
571
572 struct svm_cpu_data *sd;
573 uint64_t efer;
574 struct desc_ptr gdt_descr;
575 struct desc_struct *gdt;
576 int me = raw_smp_processor_id();
577
578 rdmsrl(MSR_EFER, efer);
579 if (efer & EFER_SVME)
580 return -EBUSY;
581
582 if (!has_svm()) {
583 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
584 me);
585 return -EINVAL;
586 }
587 sd = per_cpu(svm_data, me);
588
589 if (!sd) {
590 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
591 me);
592 return -EINVAL;
593 }
594
595 sd->asid_generation = 1;
596 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
597 sd->next_asid = sd->max_asid + 1;
598
599 native_store_gdt(&gdt_descr);
600 gdt = (struct desc_struct *)gdt_descr.address;
601 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
602
603 wrmsrl(MSR_EFER, efer | EFER_SVME);
604
605 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
606
607 svm_init_erratum_383();
608
609 return 0;
610 }
611
612 static void svm_cpu_uninit(int cpu)
613 {
614 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
615
616 if (!sd)
617 return;
618
619 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
620 __free_page(sd->save_area);
621 kfree(sd);
622 }
623
624 static int svm_cpu_init(int cpu)
625 {
626 struct svm_cpu_data *sd;
627 int r;
628
629 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
630 if (!sd)
631 return -ENOMEM;
632 sd->cpu = cpu;
633 sd->save_area = alloc_page(GFP_KERNEL);
634 r = -ENOMEM;
635 if (!sd->save_area)
636 goto err_1;
637
638 per_cpu(svm_data, cpu) = sd;
639
640 return 0;
641
642 err_1:
643 kfree(sd);
644 return r;
645
646 }
647
648 static bool valid_msr_intercept(u32 index)
649 {
650 int i;
651
652 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
653 if (direct_access_msrs[i].index == index)
654 return true;
655
656 return false;
657 }
658
659 static void set_msr_interception(u32 *msrpm, unsigned msr,
660 int read, int write)
661 {
662 u8 bit_read, bit_write;
663 unsigned long tmp;
664 u32 offset;
665
666 /*
667 * If this warning triggers extend the direct_access_msrs list at the
668 * beginning of the file
669 */
670 WARN_ON(!valid_msr_intercept(msr));
671
672 offset = svm_msrpm_offset(msr);
673 bit_read = 2 * (msr & 0x0f);
674 bit_write = 2 * (msr & 0x0f) + 1;
675 tmp = msrpm[offset];
676
677 BUG_ON(offset == MSR_INVALID);
678
679 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
680 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
681
682 msrpm[offset] = tmp;
683 }
684
685 static void svm_vcpu_init_msrpm(u32 *msrpm)
686 {
687 int i;
688
689 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
690
691 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
692 if (!direct_access_msrs[i].always)
693 continue;
694
695 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
696 }
697 }
698
699 static void add_msr_offset(u32 offset)
700 {
701 int i;
702
703 for (i = 0; i < MSRPM_OFFSETS; ++i) {
704
705 /* Offset already in list? */
706 if (msrpm_offsets[i] == offset)
707 return;
708
709 /* Slot used by another offset? */
710 if (msrpm_offsets[i] != MSR_INVALID)
711 continue;
712
713 /* Add offset to list */
714 msrpm_offsets[i] = offset;
715
716 return;
717 }
718
719 /*
720 * If this BUG triggers the msrpm_offsets table has an overflow. Just
721 * increase MSRPM_OFFSETS in this case.
722 */
723 BUG();
724 }
725
726 static void init_msrpm_offsets(void)
727 {
728 int i;
729
730 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
731
732 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
733 u32 offset;
734
735 offset = svm_msrpm_offset(direct_access_msrs[i].index);
736 BUG_ON(offset == MSR_INVALID);
737
738 add_msr_offset(offset);
739 }
740 }
741
742 static void svm_enable_lbrv(struct vcpu_svm *svm)
743 {
744 u32 *msrpm = svm->msrpm;
745
746 svm->vmcb->control.lbr_ctl = 1;
747 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
748 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
749 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
750 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
751 }
752
753 static void svm_disable_lbrv(struct vcpu_svm *svm)
754 {
755 u32 *msrpm = svm->msrpm;
756
757 svm->vmcb->control.lbr_ctl = 0;
758 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
759 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
760 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
761 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
762 }
763
764 static __init int svm_hardware_setup(void)
765 {
766 int cpu;
767 struct page *iopm_pages;
768 void *iopm_va;
769 int r;
770
771 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
772
773 if (!iopm_pages)
774 return -ENOMEM;
775
776 iopm_va = page_address(iopm_pages);
777 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
778 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
779
780 init_msrpm_offsets();
781
782 if (boot_cpu_has(X86_FEATURE_NX))
783 kvm_enable_efer_bits(EFER_NX);
784
785 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
786 kvm_enable_efer_bits(EFER_FFXSR);
787
788 if (nested) {
789 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
790 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
791 }
792
793 for_each_possible_cpu(cpu) {
794 r = svm_cpu_init(cpu);
795 if (r)
796 goto err;
797 }
798
799 svm_features = cpuid_edx(SVM_CPUID_FUNC);
800
801 if (!boot_cpu_has(X86_FEATURE_NPT))
802 npt_enabled = false;
803
804 if (npt_enabled && !npt) {
805 printk(KERN_INFO "kvm: Nested Paging disabled\n");
806 npt_enabled = false;
807 }
808
809 if (npt_enabled) {
810 printk(KERN_INFO "kvm: Nested Paging enabled\n");
811 kvm_enable_tdp();
812 } else
813 kvm_disable_tdp();
814
815 return 0;
816
817 err:
818 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
819 iopm_base = 0;
820 return r;
821 }
822
823 static __exit void svm_hardware_unsetup(void)
824 {
825 int cpu;
826
827 for_each_possible_cpu(cpu)
828 svm_cpu_uninit(cpu);
829
830 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
831 iopm_base = 0;
832 }
833
834 static void init_seg(struct vmcb_seg *seg)
835 {
836 seg->selector = 0;
837 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
838 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
839 seg->limit = 0xffff;
840 seg->base = 0;
841 }
842
843 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
844 {
845 seg->selector = 0;
846 seg->attrib = SVM_SELECTOR_P_MASK | type;
847 seg->limit = 0xffff;
848 seg->base = 0;
849 }
850
851 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
852 {
853 struct vcpu_svm *svm = to_svm(vcpu);
854 u64 g_tsc_offset = 0;
855
856 if (is_guest_mode(vcpu)) {
857 g_tsc_offset = svm->vmcb->control.tsc_offset -
858 svm->nested.hsave->control.tsc_offset;
859 svm->nested.hsave->control.tsc_offset = offset;
860 }
861
862 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
863
864 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
865 }
866
867 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
868 {
869 struct vcpu_svm *svm = to_svm(vcpu);
870
871 svm->vmcb->control.tsc_offset += adjustment;
872 if (is_guest_mode(vcpu))
873 svm->nested.hsave->control.tsc_offset += adjustment;
874 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
875 }
876
877 static void init_vmcb(struct vcpu_svm *svm)
878 {
879 struct vmcb_control_area *control = &svm->vmcb->control;
880 struct vmcb_save_area *save = &svm->vmcb->save;
881
882 svm->vcpu.fpu_active = 1;
883 svm->vcpu.arch.hflags = 0;
884
885 set_cr_intercept(svm, INTERCEPT_CR0_READ);
886 set_cr_intercept(svm, INTERCEPT_CR3_READ);
887 set_cr_intercept(svm, INTERCEPT_CR4_READ);
888 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
889 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
890 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
891 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
892
893 set_dr_intercept(svm, INTERCEPT_DR0_READ);
894 set_dr_intercept(svm, INTERCEPT_DR1_READ);
895 set_dr_intercept(svm, INTERCEPT_DR2_READ);
896 set_dr_intercept(svm, INTERCEPT_DR3_READ);
897 set_dr_intercept(svm, INTERCEPT_DR4_READ);
898 set_dr_intercept(svm, INTERCEPT_DR5_READ);
899 set_dr_intercept(svm, INTERCEPT_DR6_READ);
900 set_dr_intercept(svm, INTERCEPT_DR7_READ);
901
902 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
903 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
904 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
910
911 set_exception_intercept(svm, PF_VECTOR);
912 set_exception_intercept(svm, UD_VECTOR);
913 set_exception_intercept(svm, MC_VECTOR);
914
915 set_intercept(svm, INTERCEPT_INTR);
916 set_intercept(svm, INTERCEPT_NMI);
917 set_intercept(svm, INTERCEPT_SMI);
918 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
919 set_intercept(svm, INTERCEPT_CPUID);
920 set_intercept(svm, INTERCEPT_INVD);
921 set_intercept(svm, INTERCEPT_HLT);
922 set_intercept(svm, INTERCEPT_INVLPG);
923 set_intercept(svm, INTERCEPT_INVLPGA);
924 set_intercept(svm, INTERCEPT_IOIO_PROT);
925 set_intercept(svm, INTERCEPT_MSR_PROT);
926 set_intercept(svm, INTERCEPT_TASK_SWITCH);
927 set_intercept(svm, INTERCEPT_SHUTDOWN);
928 set_intercept(svm, INTERCEPT_VMRUN);
929 set_intercept(svm, INTERCEPT_VMMCALL);
930 set_intercept(svm, INTERCEPT_VMLOAD);
931 set_intercept(svm, INTERCEPT_VMSAVE);
932 set_intercept(svm, INTERCEPT_STGI);
933 set_intercept(svm, INTERCEPT_CLGI);
934 set_intercept(svm, INTERCEPT_SKINIT);
935 set_intercept(svm, INTERCEPT_WBINVD);
936 set_intercept(svm, INTERCEPT_MONITOR);
937 set_intercept(svm, INTERCEPT_MWAIT);
938
939 control->iopm_base_pa = iopm_base;
940 control->msrpm_base_pa = __pa(svm->msrpm);
941 control->int_ctl = V_INTR_MASKING_MASK;
942
943 init_seg(&save->es);
944 init_seg(&save->ss);
945 init_seg(&save->ds);
946 init_seg(&save->fs);
947 init_seg(&save->gs);
948
949 save->cs.selector = 0xf000;
950 /* Executable/Readable Code Segment */
951 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
952 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
953 save->cs.limit = 0xffff;
954 /*
955 * cs.base should really be 0xffff0000, but vmx can't handle that, so
956 * be consistent with it.
957 *
958 * Replace when we have real mode working for vmx.
959 */
960 save->cs.base = 0xf0000;
961
962 save->gdtr.limit = 0xffff;
963 save->idtr.limit = 0xffff;
964
965 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
966 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
967
968 svm_set_efer(&svm->vcpu, 0);
969 save->dr6 = 0xffff0ff0;
970 save->dr7 = 0x400;
971 save->rflags = 2;
972 save->rip = 0x0000fff0;
973 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
974
975 /*
976 * This is the guest-visible cr0 value.
977 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
978 */
979 svm->vcpu.arch.cr0 = 0;
980 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
981
982 save->cr4 = X86_CR4_PAE;
983 /* rdx = ?? */
984
985 if (npt_enabled) {
986 /* Setup VMCB for Nested Paging */
987 control->nested_ctl = 1;
988 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
989 clr_intercept(svm, INTERCEPT_INVLPG);
990 clr_exception_intercept(svm, PF_VECTOR);
991 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
992 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
993 save->g_pat = 0x0007040600070406ULL;
994 save->cr3 = 0;
995 save->cr4 = 0;
996 }
997 svm->asid_generation = 0;
998
999 svm->nested.vmcb = 0;
1000 svm->vcpu.arch.hflags = 0;
1001
1002 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1003 control->pause_filter_count = 3000;
1004 set_intercept(svm, INTERCEPT_PAUSE);
1005 }
1006
1007 mark_all_dirty(svm->vmcb);
1008
1009 enable_gif(svm);
1010 }
1011
1012 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1013 {
1014 struct vcpu_svm *svm = to_svm(vcpu);
1015
1016 init_vmcb(svm);
1017
1018 if (!kvm_vcpu_is_bsp(vcpu)) {
1019 kvm_rip_write(vcpu, 0);
1020 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1021 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1022 }
1023 vcpu->arch.regs_avail = ~0;
1024 vcpu->arch.regs_dirty = ~0;
1025
1026 return 0;
1027 }
1028
1029 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1030 {
1031 struct vcpu_svm *svm;
1032 struct page *page;
1033 struct page *msrpm_pages;
1034 struct page *hsave_page;
1035 struct page *nested_msrpm_pages;
1036 int err;
1037
1038 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1039 if (!svm) {
1040 err = -ENOMEM;
1041 goto out;
1042 }
1043
1044 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1045 if (err)
1046 goto free_svm;
1047
1048 err = -ENOMEM;
1049 page = alloc_page(GFP_KERNEL);
1050 if (!page)
1051 goto uninit;
1052
1053 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1054 if (!msrpm_pages)
1055 goto free_page1;
1056
1057 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1058 if (!nested_msrpm_pages)
1059 goto free_page2;
1060
1061 hsave_page = alloc_page(GFP_KERNEL);
1062 if (!hsave_page)
1063 goto free_page3;
1064
1065 svm->nested.hsave = page_address(hsave_page);
1066
1067 svm->msrpm = page_address(msrpm_pages);
1068 svm_vcpu_init_msrpm(svm->msrpm);
1069
1070 svm->nested.msrpm = page_address(nested_msrpm_pages);
1071 svm_vcpu_init_msrpm(svm->nested.msrpm);
1072
1073 svm->vmcb = page_address(page);
1074 clear_page(svm->vmcb);
1075 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1076 svm->asid_generation = 0;
1077 init_vmcb(svm);
1078 kvm_write_tsc(&svm->vcpu, 0);
1079
1080 err = fx_init(&svm->vcpu);
1081 if (err)
1082 goto free_page4;
1083
1084 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1085 if (kvm_vcpu_is_bsp(&svm->vcpu))
1086 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1087
1088 return &svm->vcpu;
1089
1090 free_page4:
1091 __free_page(hsave_page);
1092 free_page3:
1093 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1094 free_page2:
1095 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1096 free_page1:
1097 __free_page(page);
1098 uninit:
1099 kvm_vcpu_uninit(&svm->vcpu);
1100 free_svm:
1101 kmem_cache_free(kvm_vcpu_cache, svm);
1102 out:
1103 return ERR_PTR(err);
1104 }
1105
1106 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1107 {
1108 struct vcpu_svm *svm = to_svm(vcpu);
1109
1110 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1111 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1112 __free_page(virt_to_page(svm->nested.hsave));
1113 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1114 kvm_vcpu_uninit(vcpu);
1115 kmem_cache_free(kvm_vcpu_cache, svm);
1116 }
1117
1118 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1119 {
1120 struct vcpu_svm *svm = to_svm(vcpu);
1121 int i;
1122
1123 if (unlikely(cpu != vcpu->cpu)) {
1124 svm->asid_generation = 0;
1125 mark_all_dirty(svm->vmcb);
1126 }
1127
1128 #ifdef CONFIG_X86_64
1129 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1130 #endif
1131 savesegment(fs, svm->host.fs);
1132 savesegment(gs, svm->host.gs);
1133 svm->host.ldt = kvm_read_ldt();
1134
1135 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1136 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1137 }
1138
1139 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1140 {
1141 struct vcpu_svm *svm = to_svm(vcpu);
1142 int i;
1143
1144 ++vcpu->stat.host_state_reload;
1145 kvm_load_ldt(svm->host.ldt);
1146 #ifdef CONFIG_X86_64
1147 loadsegment(fs, svm->host.fs);
1148 load_gs_index(svm->host.gs);
1149 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1150 #else
1151 loadsegment(gs, svm->host.gs);
1152 #endif
1153 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1154 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1155 }
1156
1157 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1158 {
1159 return to_svm(vcpu)->vmcb->save.rflags;
1160 }
1161
1162 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1163 {
1164 to_svm(vcpu)->vmcb->save.rflags = rflags;
1165 }
1166
1167 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1168 {
1169 switch (reg) {
1170 case VCPU_EXREG_PDPTR:
1171 BUG_ON(!npt_enabled);
1172 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1173 break;
1174 default:
1175 BUG();
1176 }
1177 }
1178
1179 static void svm_set_vintr(struct vcpu_svm *svm)
1180 {
1181 set_intercept(svm, INTERCEPT_VINTR);
1182 }
1183
1184 static void svm_clear_vintr(struct vcpu_svm *svm)
1185 {
1186 clr_intercept(svm, INTERCEPT_VINTR);
1187 }
1188
1189 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1190 {
1191 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1192
1193 switch (seg) {
1194 case VCPU_SREG_CS: return &save->cs;
1195 case VCPU_SREG_DS: return &save->ds;
1196 case VCPU_SREG_ES: return &save->es;
1197 case VCPU_SREG_FS: return &save->fs;
1198 case VCPU_SREG_GS: return &save->gs;
1199 case VCPU_SREG_SS: return &save->ss;
1200 case VCPU_SREG_TR: return &save->tr;
1201 case VCPU_SREG_LDTR: return &save->ldtr;
1202 }
1203 BUG();
1204 return NULL;
1205 }
1206
1207 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1208 {
1209 struct vmcb_seg *s = svm_seg(vcpu, seg);
1210
1211 return s->base;
1212 }
1213
1214 static void svm_get_segment(struct kvm_vcpu *vcpu,
1215 struct kvm_segment *var, int seg)
1216 {
1217 struct vmcb_seg *s = svm_seg(vcpu, seg);
1218
1219 var->base = s->base;
1220 var->limit = s->limit;
1221 var->selector = s->selector;
1222 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1223 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1224 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1225 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1226 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1227 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1228 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1229 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1230
1231 /*
1232 * AMD's VMCB does not have an explicit unusable field, so emulate it
1233 * for cross vendor migration purposes by "not present"
1234 */
1235 var->unusable = !var->present || (var->type == 0);
1236
1237 switch (seg) {
1238 case VCPU_SREG_CS:
1239 /*
1240 * SVM always stores 0 for the 'G' bit in the CS selector in
1241 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1242 * Intel's VMENTRY has a check on the 'G' bit.
1243 */
1244 var->g = s->limit > 0xfffff;
1245 break;
1246 case VCPU_SREG_TR:
1247 /*
1248 * Work around a bug where the busy flag in the tr selector
1249 * isn't exposed
1250 */
1251 var->type |= 0x2;
1252 break;
1253 case VCPU_SREG_DS:
1254 case VCPU_SREG_ES:
1255 case VCPU_SREG_FS:
1256 case VCPU_SREG_GS:
1257 /*
1258 * The accessed bit must always be set in the segment
1259 * descriptor cache, although it can be cleared in the
1260 * descriptor, the cached bit always remains at 1. Since
1261 * Intel has a check on this, set it here to support
1262 * cross-vendor migration.
1263 */
1264 if (!var->unusable)
1265 var->type |= 0x1;
1266 break;
1267 case VCPU_SREG_SS:
1268 /*
1269 * On AMD CPUs sometimes the DB bit in the segment
1270 * descriptor is left as 1, although the whole segment has
1271 * been made unusable. Clear it here to pass an Intel VMX
1272 * entry check when cross vendor migrating.
1273 */
1274 if (var->unusable)
1275 var->db = 0;
1276 break;
1277 }
1278 }
1279
1280 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1281 {
1282 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1283
1284 return save->cpl;
1285 }
1286
1287 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1288 {
1289 struct vcpu_svm *svm = to_svm(vcpu);
1290
1291 dt->size = svm->vmcb->save.idtr.limit;
1292 dt->address = svm->vmcb->save.idtr.base;
1293 }
1294
1295 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1296 {
1297 struct vcpu_svm *svm = to_svm(vcpu);
1298
1299 svm->vmcb->save.idtr.limit = dt->size;
1300 svm->vmcb->save.idtr.base = dt->address ;
1301 mark_dirty(svm->vmcb, VMCB_DT);
1302 }
1303
1304 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1305 {
1306 struct vcpu_svm *svm = to_svm(vcpu);
1307
1308 dt->size = svm->vmcb->save.gdtr.limit;
1309 dt->address = svm->vmcb->save.gdtr.base;
1310 }
1311
1312 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1313 {
1314 struct vcpu_svm *svm = to_svm(vcpu);
1315
1316 svm->vmcb->save.gdtr.limit = dt->size;
1317 svm->vmcb->save.gdtr.base = dt->address ;
1318 mark_dirty(svm->vmcb, VMCB_DT);
1319 }
1320
1321 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1322 {
1323 }
1324
1325 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1326 {
1327 }
1328
1329 static void update_cr0_intercept(struct vcpu_svm *svm)
1330 {
1331 ulong gcr0 = svm->vcpu.arch.cr0;
1332 u64 *hcr0 = &svm->vmcb->save.cr0;
1333
1334 if (!svm->vcpu.fpu_active)
1335 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1336 else
1337 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1338 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1339
1340 mark_dirty(svm->vmcb, VMCB_CR);
1341
1342 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1343 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1344 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1345 } else {
1346 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1347 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1348 }
1349 }
1350
1351 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1352 {
1353 struct vcpu_svm *svm = to_svm(vcpu);
1354
1355 if (is_guest_mode(vcpu)) {
1356 /*
1357 * We are here because we run in nested mode, the host kvm
1358 * intercepts cr0 writes but the l1 hypervisor does not.
1359 * But the L1 hypervisor may intercept selective cr0 writes.
1360 * This needs to be checked here.
1361 */
1362 unsigned long old, new;
1363
1364 /* Remove bits that would trigger a real cr0 write intercept */
1365 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1366 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1367
1368 if (old == new) {
1369 /* cr0 write with ts and mp unchanged */
1370 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1371 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1372 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1373 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1374 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1375 return;
1376 }
1377 }
1378 }
1379
1380 #ifdef CONFIG_X86_64
1381 if (vcpu->arch.efer & EFER_LME) {
1382 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1383 vcpu->arch.efer |= EFER_LMA;
1384 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1385 }
1386
1387 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1388 vcpu->arch.efer &= ~EFER_LMA;
1389 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1390 }
1391 }
1392 #endif
1393 vcpu->arch.cr0 = cr0;
1394
1395 if (!npt_enabled)
1396 cr0 |= X86_CR0_PG | X86_CR0_WP;
1397
1398 if (!vcpu->fpu_active)
1399 cr0 |= X86_CR0_TS;
1400 /*
1401 * re-enable caching here because the QEMU bios
1402 * does not do it - this results in some delay at
1403 * reboot
1404 */
1405 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1406 svm->vmcb->save.cr0 = cr0;
1407 mark_dirty(svm->vmcb, VMCB_CR);
1408 update_cr0_intercept(svm);
1409 }
1410
1411 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1412 {
1413 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1414 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1415
1416 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1417 svm_flush_tlb(vcpu);
1418
1419 vcpu->arch.cr4 = cr4;
1420 if (!npt_enabled)
1421 cr4 |= X86_CR4_PAE;
1422 cr4 |= host_cr4_mce;
1423 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1424 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1425 }
1426
1427 static void svm_set_segment(struct kvm_vcpu *vcpu,
1428 struct kvm_segment *var, int seg)
1429 {
1430 struct vcpu_svm *svm = to_svm(vcpu);
1431 struct vmcb_seg *s = svm_seg(vcpu, seg);
1432
1433 s->base = var->base;
1434 s->limit = var->limit;
1435 s->selector = var->selector;
1436 if (var->unusable)
1437 s->attrib = 0;
1438 else {
1439 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1440 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1441 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1442 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1443 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1444 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1445 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1446 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1447 }
1448 if (seg == VCPU_SREG_CS)
1449 svm->vmcb->save.cpl
1450 = (svm->vmcb->save.cs.attrib
1451 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1452
1453 mark_dirty(svm->vmcb, VMCB_SEG);
1454 }
1455
1456 static void update_db_intercept(struct kvm_vcpu *vcpu)
1457 {
1458 struct vcpu_svm *svm = to_svm(vcpu);
1459
1460 clr_exception_intercept(svm, DB_VECTOR);
1461 clr_exception_intercept(svm, BP_VECTOR);
1462
1463 if (svm->nmi_singlestep)
1464 set_exception_intercept(svm, DB_VECTOR);
1465
1466 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1467 if (vcpu->guest_debug &
1468 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1469 set_exception_intercept(svm, DB_VECTOR);
1470 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1471 set_exception_intercept(svm, BP_VECTOR);
1472 } else
1473 vcpu->guest_debug = 0;
1474 }
1475
1476 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1477 {
1478 struct vcpu_svm *svm = to_svm(vcpu);
1479
1480 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1481 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1482 else
1483 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1484
1485 mark_dirty(svm->vmcb, VMCB_DR);
1486
1487 update_db_intercept(vcpu);
1488 }
1489
1490 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1491 {
1492 if (sd->next_asid > sd->max_asid) {
1493 ++sd->asid_generation;
1494 sd->next_asid = 1;
1495 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1496 }
1497
1498 svm->asid_generation = sd->asid_generation;
1499 svm->vmcb->control.asid = sd->next_asid++;
1500
1501 mark_dirty(svm->vmcb, VMCB_ASID);
1502 }
1503
1504 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1505 {
1506 struct vcpu_svm *svm = to_svm(vcpu);
1507
1508 svm->vmcb->save.dr7 = value;
1509 mark_dirty(svm->vmcb, VMCB_DR);
1510 }
1511
1512 static int pf_interception(struct vcpu_svm *svm)
1513 {
1514 u64 fault_address = svm->vmcb->control.exit_info_2;
1515 u32 error_code;
1516 int r = 1;
1517
1518 switch (svm->apf_reason) {
1519 default:
1520 error_code = svm->vmcb->control.exit_info_1;
1521
1522 trace_kvm_page_fault(fault_address, error_code);
1523 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1524 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1525 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1526 break;
1527 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1528 svm->apf_reason = 0;
1529 local_irq_disable();
1530 kvm_async_pf_task_wait(fault_address);
1531 local_irq_enable();
1532 break;
1533 case KVM_PV_REASON_PAGE_READY:
1534 svm->apf_reason = 0;
1535 local_irq_disable();
1536 kvm_async_pf_task_wake(fault_address);
1537 local_irq_enable();
1538 break;
1539 }
1540 return r;
1541 }
1542
1543 static int db_interception(struct vcpu_svm *svm)
1544 {
1545 struct kvm_run *kvm_run = svm->vcpu.run;
1546
1547 if (!(svm->vcpu.guest_debug &
1548 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1549 !svm->nmi_singlestep) {
1550 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1551 return 1;
1552 }
1553
1554 if (svm->nmi_singlestep) {
1555 svm->nmi_singlestep = false;
1556 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1557 svm->vmcb->save.rflags &=
1558 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1559 update_db_intercept(&svm->vcpu);
1560 }
1561
1562 if (svm->vcpu.guest_debug &
1563 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1564 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1565 kvm_run->debug.arch.pc =
1566 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1567 kvm_run->debug.arch.exception = DB_VECTOR;
1568 return 0;
1569 }
1570
1571 return 1;
1572 }
1573
1574 static int bp_interception(struct vcpu_svm *svm)
1575 {
1576 struct kvm_run *kvm_run = svm->vcpu.run;
1577
1578 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1579 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1580 kvm_run->debug.arch.exception = BP_VECTOR;
1581 return 0;
1582 }
1583
1584 static int ud_interception(struct vcpu_svm *svm)
1585 {
1586 int er;
1587
1588 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1589 if (er != EMULATE_DONE)
1590 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1591 return 1;
1592 }
1593
1594 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1595 {
1596 struct vcpu_svm *svm = to_svm(vcpu);
1597
1598 clr_exception_intercept(svm, NM_VECTOR);
1599
1600 svm->vcpu.fpu_active = 1;
1601 update_cr0_intercept(svm);
1602 }
1603
1604 static int nm_interception(struct vcpu_svm *svm)
1605 {
1606 svm_fpu_activate(&svm->vcpu);
1607 return 1;
1608 }
1609
1610 static bool is_erratum_383(void)
1611 {
1612 int err, i;
1613 u64 value;
1614
1615 if (!erratum_383_found)
1616 return false;
1617
1618 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1619 if (err)
1620 return false;
1621
1622 /* Bit 62 may or may not be set for this mce */
1623 value &= ~(1ULL << 62);
1624
1625 if (value != 0xb600000000010015ULL)
1626 return false;
1627
1628 /* Clear MCi_STATUS registers */
1629 for (i = 0; i < 6; ++i)
1630 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1631
1632 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1633 if (!err) {
1634 u32 low, high;
1635
1636 value &= ~(1ULL << 2);
1637 low = lower_32_bits(value);
1638 high = upper_32_bits(value);
1639
1640 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1641 }
1642
1643 /* Flush tlb to evict multi-match entries */
1644 __flush_tlb_all();
1645
1646 return true;
1647 }
1648
1649 static void svm_handle_mce(struct vcpu_svm *svm)
1650 {
1651 if (is_erratum_383()) {
1652 /*
1653 * Erratum 383 triggered. Guest state is corrupt so kill the
1654 * guest.
1655 */
1656 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1657
1658 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1659
1660 return;
1661 }
1662
1663 /*
1664 * On an #MC intercept the MCE handler is not called automatically in
1665 * the host. So do it by hand here.
1666 */
1667 asm volatile (
1668 "int $0x12\n");
1669 /* not sure if we ever come back to this point */
1670
1671 return;
1672 }
1673
1674 static int mc_interception(struct vcpu_svm *svm)
1675 {
1676 return 1;
1677 }
1678
1679 static int shutdown_interception(struct vcpu_svm *svm)
1680 {
1681 struct kvm_run *kvm_run = svm->vcpu.run;
1682
1683 /*
1684 * VMCB is undefined after a SHUTDOWN intercept
1685 * so reinitialize it.
1686 */
1687 clear_page(svm->vmcb);
1688 init_vmcb(svm);
1689
1690 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1691 return 0;
1692 }
1693
1694 static int io_interception(struct vcpu_svm *svm)
1695 {
1696 struct kvm_vcpu *vcpu = &svm->vcpu;
1697 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1698 int size, in, string;
1699 unsigned port;
1700
1701 ++svm->vcpu.stat.io_exits;
1702 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1703 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1704 if (string || in)
1705 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1706
1707 port = io_info >> 16;
1708 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1709 svm->next_rip = svm->vmcb->control.exit_info_2;
1710 skip_emulated_instruction(&svm->vcpu);
1711
1712 return kvm_fast_pio_out(vcpu, size, port);
1713 }
1714
1715 static int nmi_interception(struct vcpu_svm *svm)
1716 {
1717 return 1;
1718 }
1719
1720 static int intr_interception(struct vcpu_svm *svm)
1721 {
1722 ++svm->vcpu.stat.irq_exits;
1723 return 1;
1724 }
1725
1726 static int nop_on_interception(struct vcpu_svm *svm)
1727 {
1728 return 1;
1729 }
1730
1731 static int halt_interception(struct vcpu_svm *svm)
1732 {
1733 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1734 skip_emulated_instruction(&svm->vcpu);
1735 return kvm_emulate_halt(&svm->vcpu);
1736 }
1737
1738 static int vmmcall_interception(struct vcpu_svm *svm)
1739 {
1740 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1741 skip_emulated_instruction(&svm->vcpu);
1742 kvm_emulate_hypercall(&svm->vcpu);
1743 return 1;
1744 }
1745
1746 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1747 {
1748 struct vcpu_svm *svm = to_svm(vcpu);
1749
1750 return svm->nested.nested_cr3;
1751 }
1752
1753 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1754 unsigned long root)
1755 {
1756 struct vcpu_svm *svm = to_svm(vcpu);
1757
1758 svm->vmcb->control.nested_cr3 = root;
1759 mark_dirty(svm->vmcb, VMCB_NPT);
1760 svm_flush_tlb(vcpu);
1761 }
1762
1763 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1764 struct x86_exception *fault)
1765 {
1766 struct vcpu_svm *svm = to_svm(vcpu);
1767
1768 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1769 svm->vmcb->control.exit_code_hi = 0;
1770 svm->vmcb->control.exit_info_1 = fault->error_code;
1771 svm->vmcb->control.exit_info_2 = fault->address;
1772
1773 nested_svm_vmexit(svm);
1774 }
1775
1776 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1777 {
1778 int r;
1779
1780 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1781
1782 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1783 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1784 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1785 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1786 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1787
1788 return r;
1789 }
1790
1791 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1792 {
1793 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1794 }
1795
1796 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1797 {
1798 if (!(svm->vcpu.arch.efer & EFER_SVME)
1799 || !is_paging(&svm->vcpu)) {
1800 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1801 return 1;
1802 }
1803
1804 if (svm->vmcb->save.cpl) {
1805 kvm_inject_gp(&svm->vcpu, 0);
1806 return 1;
1807 }
1808
1809 return 0;
1810 }
1811
1812 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1813 bool has_error_code, u32 error_code)
1814 {
1815 int vmexit;
1816
1817 if (!is_guest_mode(&svm->vcpu))
1818 return 0;
1819
1820 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1821 svm->vmcb->control.exit_code_hi = 0;
1822 svm->vmcb->control.exit_info_1 = error_code;
1823 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1824
1825 vmexit = nested_svm_intercept(svm);
1826 if (vmexit == NESTED_EXIT_DONE)
1827 svm->nested.exit_required = true;
1828
1829 return vmexit;
1830 }
1831
1832 /* This function returns true if it is save to enable the irq window */
1833 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1834 {
1835 if (!is_guest_mode(&svm->vcpu))
1836 return true;
1837
1838 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1839 return true;
1840
1841 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1842 return false;
1843
1844 /*
1845 * if vmexit was already requested (by intercepted exception
1846 * for instance) do not overwrite it with "external interrupt"
1847 * vmexit.
1848 */
1849 if (svm->nested.exit_required)
1850 return false;
1851
1852 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1853 svm->vmcb->control.exit_info_1 = 0;
1854 svm->vmcb->control.exit_info_2 = 0;
1855
1856 if (svm->nested.intercept & 1ULL) {
1857 /*
1858 * The #vmexit can't be emulated here directly because this
1859 * code path runs with irqs and preemtion disabled. A
1860 * #vmexit emulation might sleep. Only signal request for
1861 * the #vmexit here.
1862 */
1863 svm->nested.exit_required = true;
1864 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1865 return false;
1866 }
1867
1868 return true;
1869 }
1870
1871 /* This function returns true if it is save to enable the nmi window */
1872 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1873 {
1874 if (!is_guest_mode(&svm->vcpu))
1875 return true;
1876
1877 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1878 return true;
1879
1880 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1881 svm->nested.exit_required = true;
1882
1883 return false;
1884 }
1885
1886 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1887 {
1888 struct page *page;
1889
1890 might_sleep();
1891
1892 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1893 if (is_error_page(page))
1894 goto error;
1895
1896 *_page = page;
1897
1898 return kmap(page);
1899
1900 error:
1901 kvm_release_page_clean(page);
1902 kvm_inject_gp(&svm->vcpu, 0);
1903
1904 return NULL;
1905 }
1906
1907 static void nested_svm_unmap(struct page *page)
1908 {
1909 kunmap(page);
1910 kvm_release_page_dirty(page);
1911 }
1912
1913 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1914 {
1915 unsigned port;
1916 u8 val, bit;
1917 u64 gpa;
1918
1919 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1920 return NESTED_EXIT_HOST;
1921
1922 port = svm->vmcb->control.exit_info_1 >> 16;
1923 gpa = svm->nested.vmcb_iopm + (port / 8);
1924 bit = port % 8;
1925 val = 0;
1926
1927 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1928 val &= (1 << bit);
1929
1930 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1931 }
1932
1933 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1934 {
1935 u32 offset, msr, value;
1936 int write, mask;
1937
1938 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1939 return NESTED_EXIT_HOST;
1940
1941 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1942 offset = svm_msrpm_offset(msr);
1943 write = svm->vmcb->control.exit_info_1 & 1;
1944 mask = 1 << ((2 * (msr & 0xf)) + write);
1945
1946 if (offset == MSR_INVALID)
1947 return NESTED_EXIT_DONE;
1948
1949 /* Offset is in 32 bit units but need in 8 bit units */
1950 offset *= 4;
1951
1952 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1953 return NESTED_EXIT_DONE;
1954
1955 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1956 }
1957
1958 static int nested_svm_exit_special(struct vcpu_svm *svm)
1959 {
1960 u32 exit_code = svm->vmcb->control.exit_code;
1961
1962 switch (exit_code) {
1963 case SVM_EXIT_INTR:
1964 case SVM_EXIT_NMI:
1965 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1966 return NESTED_EXIT_HOST;
1967 case SVM_EXIT_NPF:
1968 /* For now we are always handling NPFs when using them */
1969 if (npt_enabled)
1970 return NESTED_EXIT_HOST;
1971 break;
1972 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1973 /* When we're shadowing, trap PFs, but not async PF */
1974 if (!npt_enabled && svm->apf_reason == 0)
1975 return NESTED_EXIT_HOST;
1976 break;
1977 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1978 nm_interception(svm);
1979 break;
1980 default:
1981 break;
1982 }
1983
1984 return NESTED_EXIT_CONTINUE;
1985 }
1986
1987 /*
1988 * If this function returns true, this #vmexit was already handled
1989 */
1990 static int nested_svm_intercept(struct vcpu_svm *svm)
1991 {
1992 u32 exit_code = svm->vmcb->control.exit_code;
1993 int vmexit = NESTED_EXIT_HOST;
1994
1995 switch (exit_code) {
1996 case SVM_EXIT_MSR:
1997 vmexit = nested_svm_exit_handled_msr(svm);
1998 break;
1999 case SVM_EXIT_IOIO:
2000 vmexit = nested_svm_intercept_ioio(svm);
2001 break;
2002 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2003 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2004 if (svm->nested.intercept_cr & bit)
2005 vmexit = NESTED_EXIT_DONE;
2006 break;
2007 }
2008 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2009 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2010 if (svm->nested.intercept_dr & bit)
2011 vmexit = NESTED_EXIT_DONE;
2012 break;
2013 }
2014 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2015 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2016 if (svm->nested.intercept_exceptions & excp_bits)
2017 vmexit = NESTED_EXIT_DONE;
2018 /* async page fault always cause vmexit */
2019 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2020 svm->apf_reason != 0)
2021 vmexit = NESTED_EXIT_DONE;
2022 break;
2023 }
2024 case SVM_EXIT_ERR: {
2025 vmexit = NESTED_EXIT_DONE;
2026 break;
2027 }
2028 default: {
2029 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2030 if (svm->nested.intercept & exit_bits)
2031 vmexit = NESTED_EXIT_DONE;
2032 }
2033 }
2034
2035 return vmexit;
2036 }
2037
2038 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2039 {
2040 int vmexit;
2041
2042 vmexit = nested_svm_intercept(svm);
2043
2044 if (vmexit == NESTED_EXIT_DONE)
2045 nested_svm_vmexit(svm);
2046
2047 return vmexit;
2048 }
2049
2050 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2051 {
2052 struct vmcb_control_area *dst = &dst_vmcb->control;
2053 struct vmcb_control_area *from = &from_vmcb->control;
2054
2055 dst->intercept_cr = from->intercept_cr;
2056 dst->intercept_dr = from->intercept_dr;
2057 dst->intercept_exceptions = from->intercept_exceptions;
2058 dst->intercept = from->intercept;
2059 dst->iopm_base_pa = from->iopm_base_pa;
2060 dst->msrpm_base_pa = from->msrpm_base_pa;
2061 dst->tsc_offset = from->tsc_offset;
2062 dst->asid = from->asid;
2063 dst->tlb_ctl = from->tlb_ctl;
2064 dst->int_ctl = from->int_ctl;
2065 dst->int_vector = from->int_vector;
2066 dst->int_state = from->int_state;
2067 dst->exit_code = from->exit_code;
2068 dst->exit_code_hi = from->exit_code_hi;
2069 dst->exit_info_1 = from->exit_info_1;
2070 dst->exit_info_2 = from->exit_info_2;
2071 dst->exit_int_info = from->exit_int_info;
2072 dst->exit_int_info_err = from->exit_int_info_err;
2073 dst->nested_ctl = from->nested_ctl;
2074 dst->event_inj = from->event_inj;
2075 dst->event_inj_err = from->event_inj_err;
2076 dst->nested_cr3 = from->nested_cr3;
2077 dst->lbr_ctl = from->lbr_ctl;
2078 }
2079
2080 static int nested_svm_vmexit(struct vcpu_svm *svm)
2081 {
2082 struct vmcb *nested_vmcb;
2083 struct vmcb *hsave = svm->nested.hsave;
2084 struct vmcb *vmcb = svm->vmcb;
2085 struct page *page;
2086
2087 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2088 vmcb->control.exit_info_1,
2089 vmcb->control.exit_info_2,
2090 vmcb->control.exit_int_info,
2091 vmcb->control.exit_int_info_err);
2092
2093 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2094 if (!nested_vmcb)
2095 return 1;
2096
2097 /* Exit Guest-Mode */
2098 leave_guest_mode(&svm->vcpu);
2099 svm->nested.vmcb = 0;
2100
2101 /* Give the current vmcb to the guest */
2102 disable_gif(svm);
2103
2104 nested_vmcb->save.es = vmcb->save.es;
2105 nested_vmcb->save.cs = vmcb->save.cs;
2106 nested_vmcb->save.ss = vmcb->save.ss;
2107 nested_vmcb->save.ds = vmcb->save.ds;
2108 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2109 nested_vmcb->save.idtr = vmcb->save.idtr;
2110 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2111 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2112 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
2113 nested_vmcb->save.cr2 = vmcb->save.cr2;
2114 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2115 nested_vmcb->save.rflags = vmcb->save.rflags;
2116 nested_vmcb->save.rip = vmcb->save.rip;
2117 nested_vmcb->save.rsp = vmcb->save.rsp;
2118 nested_vmcb->save.rax = vmcb->save.rax;
2119 nested_vmcb->save.dr7 = vmcb->save.dr7;
2120 nested_vmcb->save.dr6 = vmcb->save.dr6;
2121 nested_vmcb->save.cpl = vmcb->save.cpl;
2122
2123 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2124 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2125 nested_vmcb->control.int_state = vmcb->control.int_state;
2126 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2127 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2128 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2129 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2130 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2131 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2132 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2133
2134 /*
2135 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2136 * to make sure that we do not lose injected events. So check event_inj
2137 * here and copy it to exit_int_info if it is valid.
2138 * Exit_int_info and event_inj can't be both valid because the case
2139 * below only happens on a VMRUN instruction intercept which has
2140 * no valid exit_int_info set.
2141 */
2142 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2143 struct vmcb_control_area *nc = &nested_vmcb->control;
2144
2145 nc->exit_int_info = vmcb->control.event_inj;
2146 nc->exit_int_info_err = vmcb->control.event_inj_err;
2147 }
2148
2149 nested_vmcb->control.tlb_ctl = 0;
2150 nested_vmcb->control.event_inj = 0;
2151 nested_vmcb->control.event_inj_err = 0;
2152
2153 /* We always set V_INTR_MASKING and remember the old value in hflags */
2154 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2155 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2156
2157 /* Restore the original control entries */
2158 copy_vmcb_control_area(vmcb, hsave);
2159
2160 kvm_clear_exception_queue(&svm->vcpu);
2161 kvm_clear_interrupt_queue(&svm->vcpu);
2162
2163 svm->nested.nested_cr3 = 0;
2164
2165 /* Restore selected save entries */
2166 svm->vmcb->save.es = hsave->save.es;
2167 svm->vmcb->save.cs = hsave->save.cs;
2168 svm->vmcb->save.ss = hsave->save.ss;
2169 svm->vmcb->save.ds = hsave->save.ds;
2170 svm->vmcb->save.gdtr = hsave->save.gdtr;
2171 svm->vmcb->save.idtr = hsave->save.idtr;
2172 svm->vmcb->save.rflags = hsave->save.rflags;
2173 svm_set_efer(&svm->vcpu, hsave->save.efer);
2174 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2175 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2176 if (npt_enabled) {
2177 svm->vmcb->save.cr3 = hsave->save.cr3;
2178 svm->vcpu.arch.cr3 = hsave->save.cr3;
2179 } else {
2180 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2181 }
2182 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2183 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2184 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2185 svm->vmcb->save.dr7 = 0;
2186 svm->vmcb->save.cpl = 0;
2187 svm->vmcb->control.exit_int_info = 0;
2188
2189 mark_all_dirty(svm->vmcb);
2190
2191 nested_svm_unmap(page);
2192
2193 nested_svm_uninit_mmu_context(&svm->vcpu);
2194 kvm_mmu_reset_context(&svm->vcpu);
2195 kvm_mmu_load(&svm->vcpu);
2196
2197 return 0;
2198 }
2199
2200 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2201 {
2202 /*
2203 * This function merges the msr permission bitmaps of kvm and the
2204 * nested vmcb. It is omptimized in that it only merges the parts where
2205 * the kvm msr permission bitmap may contain zero bits
2206 */
2207 int i;
2208
2209 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2210 return true;
2211
2212 for (i = 0; i < MSRPM_OFFSETS; i++) {
2213 u32 value, p;
2214 u64 offset;
2215
2216 if (msrpm_offsets[i] == 0xffffffff)
2217 break;
2218
2219 p = msrpm_offsets[i];
2220 offset = svm->nested.vmcb_msrpm + (p * 4);
2221
2222 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2223 return false;
2224
2225 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2226 }
2227
2228 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2229
2230 return true;
2231 }
2232
2233 static bool nested_vmcb_checks(struct vmcb *vmcb)
2234 {
2235 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2236 return false;
2237
2238 if (vmcb->control.asid == 0)
2239 return false;
2240
2241 if (vmcb->control.nested_ctl && !npt_enabled)
2242 return false;
2243
2244 return true;
2245 }
2246
2247 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2248 {
2249 struct vmcb *nested_vmcb;
2250 struct vmcb *hsave = svm->nested.hsave;
2251 struct vmcb *vmcb = svm->vmcb;
2252 struct page *page;
2253 u64 vmcb_gpa;
2254
2255 vmcb_gpa = svm->vmcb->save.rax;
2256
2257 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2258 if (!nested_vmcb)
2259 return false;
2260
2261 if (!nested_vmcb_checks(nested_vmcb)) {
2262 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2263 nested_vmcb->control.exit_code_hi = 0;
2264 nested_vmcb->control.exit_info_1 = 0;
2265 nested_vmcb->control.exit_info_2 = 0;
2266
2267 nested_svm_unmap(page);
2268
2269 return false;
2270 }
2271
2272 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2273 nested_vmcb->save.rip,
2274 nested_vmcb->control.int_ctl,
2275 nested_vmcb->control.event_inj,
2276 nested_vmcb->control.nested_ctl);
2277
2278 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2279 nested_vmcb->control.intercept_cr >> 16,
2280 nested_vmcb->control.intercept_exceptions,
2281 nested_vmcb->control.intercept);
2282
2283 /* Clear internal status */
2284 kvm_clear_exception_queue(&svm->vcpu);
2285 kvm_clear_interrupt_queue(&svm->vcpu);
2286
2287 /*
2288 * Save the old vmcb, so we don't need to pick what we save, but can
2289 * restore everything when a VMEXIT occurs
2290 */
2291 hsave->save.es = vmcb->save.es;
2292 hsave->save.cs = vmcb->save.cs;
2293 hsave->save.ss = vmcb->save.ss;
2294 hsave->save.ds = vmcb->save.ds;
2295 hsave->save.gdtr = vmcb->save.gdtr;
2296 hsave->save.idtr = vmcb->save.idtr;
2297 hsave->save.efer = svm->vcpu.arch.efer;
2298 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2299 hsave->save.cr4 = svm->vcpu.arch.cr4;
2300 hsave->save.rflags = vmcb->save.rflags;
2301 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2302 hsave->save.rsp = vmcb->save.rsp;
2303 hsave->save.rax = vmcb->save.rax;
2304 if (npt_enabled)
2305 hsave->save.cr3 = vmcb->save.cr3;
2306 else
2307 hsave->save.cr3 = svm->vcpu.arch.cr3;
2308
2309 copy_vmcb_control_area(hsave, vmcb);
2310
2311 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2312 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2313 else
2314 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2315
2316 if (nested_vmcb->control.nested_ctl) {
2317 kvm_mmu_unload(&svm->vcpu);
2318 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2319 nested_svm_init_mmu_context(&svm->vcpu);
2320 }
2321
2322 /* Load the nested guest state */
2323 svm->vmcb->save.es = nested_vmcb->save.es;
2324 svm->vmcb->save.cs = nested_vmcb->save.cs;
2325 svm->vmcb->save.ss = nested_vmcb->save.ss;
2326 svm->vmcb->save.ds = nested_vmcb->save.ds;
2327 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2328 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2329 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2330 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2331 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2332 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2333 if (npt_enabled) {
2334 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2335 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2336 } else
2337 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2338
2339 /* Guest paging mode is active - reset mmu */
2340 kvm_mmu_reset_context(&svm->vcpu);
2341
2342 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2343 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2344 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2345 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2346
2347 /* In case we don't even reach vcpu_run, the fields are not updated */
2348 svm->vmcb->save.rax = nested_vmcb->save.rax;
2349 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2350 svm->vmcb->save.rip = nested_vmcb->save.rip;
2351 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2352 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2353 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2354
2355 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2356 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2357
2358 /* cache intercepts */
2359 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2360 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2361 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2362 svm->nested.intercept = nested_vmcb->control.intercept;
2363
2364 svm_flush_tlb(&svm->vcpu);
2365 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2366 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2367 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2368 else
2369 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2370
2371 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2372 /* We only want the cr8 intercept bits of the guest */
2373 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2374 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2375 }
2376
2377 /* We don't want to see VMMCALLs from a nested guest */
2378 clr_intercept(svm, INTERCEPT_VMMCALL);
2379
2380 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2381 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2382 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2383 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2384 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2385 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2386
2387 nested_svm_unmap(page);
2388
2389 /* Enter Guest-Mode */
2390 enter_guest_mode(&svm->vcpu);
2391
2392 /*
2393 * Merge guest and host intercepts - must be called with vcpu in
2394 * guest-mode to take affect here
2395 */
2396 recalc_intercepts(svm);
2397
2398 svm->nested.vmcb = vmcb_gpa;
2399
2400 enable_gif(svm);
2401
2402 mark_all_dirty(svm->vmcb);
2403
2404 return true;
2405 }
2406
2407 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2408 {
2409 to_vmcb->save.fs = from_vmcb->save.fs;
2410 to_vmcb->save.gs = from_vmcb->save.gs;
2411 to_vmcb->save.tr = from_vmcb->save.tr;
2412 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2413 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2414 to_vmcb->save.star = from_vmcb->save.star;
2415 to_vmcb->save.lstar = from_vmcb->save.lstar;
2416 to_vmcb->save.cstar = from_vmcb->save.cstar;
2417 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2418 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2419 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2420 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2421 }
2422
2423 static int vmload_interception(struct vcpu_svm *svm)
2424 {
2425 struct vmcb *nested_vmcb;
2426 struct page *page;
2427
2428 if (nested_svm_check_permissions(svm))
2429 return 1;
2430
2431 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2432 skip_emulated_instruction(&svm->vcpu);
2433
2434 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2435 if (!nested_vmcb)
2436 return 1;
2437
2438 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2439 nested_svm_unmap(page);
2440
2441 return 1;
2442 }
2443
2444 static int vmsave_interception(struct vcpu_svm *svm)
2445 {
2446 struct vmcb *nested_vmcb;
2447 struct page *page;
2448
2449 if (nested_svm_check_permissions(svm))
2450 return 1;
2451
2452 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2453 skip_emulated_instruction(&svm->vcpu);
2454
2455 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2456 if (!nested_vmcb)
2457 return 1;
2458
2459 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2460 nested_svm_unmap(page);
2461
2462 return 1;
2463 }
2464
2465 static int vmrun_interception(struct vcpu_svm *svm)
2466 {
2467 if (nested_svm_check_permissions(svm))
2468 return 1;
2469
2470 /* Save rip after vmrun instruction */
2471 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2472
2473 if (!nested_svm_vmrun(svm))
2474 return 1;
2475
2476 if (!nested_svm_vmrun_msrpm(svm))
2477 goto failed;
2478
2479 return 1;
2480
2481 failed:
2482
2483 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2484 svm->vmcb->control.exit_code_hi = 0;
2485 svm->vmcb->control.exit_info_1 = 0;
2486 svm->vmcb->control.exit_info_2 = 0;
2487
2488 nested_svm_vmexit(svm);
2489
2490 return 1;
2491 }
2492
2493 static int stgi_interception(struct vcpu_svm *svm)
2494 {
2495 if (nested_svm_check_permissions(svm))
2496 return 1;
2497
2498 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2499 skip_emulated_instruction(&svm->vcpu);
2500 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2501
2502 enable_gif(svm);
2503
2504 return 1;
2505 }
2506
2507 static int clgi_interception(struct vcpu_svm *svm)
2508 {
2509 if (nested_svm_check_permissions(svm))
2510 return 1;
2511
2512 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2513 skip_emulated_instruction(&svm->vcpu);
2514
2515 disable_gif(svm);
2516
2517 /* After a CLGI no interrupts should come */
2518 svm_clear_vintr(svm);
2519 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2520
2521 mark_dirty(svm->vmcb, VMCB_INTR);
2522
2523 return 1;
2524 }
2525
2526 static int invlpga_interception(struct vcpu_svm *svm)
2527 {
2528 struct kvm_vcpu *vcpu = &svm->vcpu;
2529
2530 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2531 vcpu->arch.regs[VCPU_REGS_RAX]);
2532
2533 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2534 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2535
2536 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2537 skip_emulated_instruction(&svm->vcpu);
2538 return 1;
2539 }
2540
2541 static int skinit_interception(struct vcpu_svm *svm)
2542 {
2543 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2544
2545 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2546 return 1;
2547 }
2548
2549 static int invalid_op_interception(struct vcpu_svm *svm)
2550 {
2551 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2552 return 1;
2553 }
2554
2555 static int task_switch_interception(struct vcpu_svm *svm)
2556 {
2557 u16 tss_selector;
2558 int reason;
2559 int int_type = svm->vmcb->control.exit_int_info &
2560 SVM_EXITINTINFO_TYPE_MASK;
2561 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2562 uint32_t type =
2563 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2564 uint32_t idt_v =
2565 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2566 bool has_error_code = false;
2567 u32 error_code = 0;
2568
2569 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2570
2571 if (svm->vmcb->control.exit_info_2 &
2572 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2573 reason = TASK_SWITCH_IRET;
2574 else if (svm->vmcb->control.exit_info_2 &
2575 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2576 reason = TASK_SWITCH_JMP;
2577 else if (idt_v)
2578 reason = TASK_SWITCH_GATE;
2579 else
2580 reason = TASK_SWITCH_CALL;
2581
2582 if (reason == TASK_SWITCH_GATE) {
2583 switch (type) {
2584 case SVM_EXITINTINFO_TYPE_NMI:
2585 svm->vcpu.arch.nmi_injected = false;
2586 break;
2587 case SVM_EXITINTINFO_TYPE_EXEPT:
2588 if (svm->vmcb->control.exit_info_2 &
2589 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2590 has_error_code = true;
2591 error_code =
2592 (u32)svm->vmcb->control.exit_info_2;
2593 }
2594 kvm_clear_exception_queue(&svm->vcpu);
2595 break;
2596 case SVM_EXITINTINFO_TYPE_INTR:
2597 kvm_clear_interrupt_queue(&svm->vcpu);
2598 break;
2599 default:
2600 break;
2601 }
2602 }
2603
2604 if (reason != TASK_SWITCH_GATE ||
2605 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2606 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2607 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2608 skip_emulated_instruction(&svm->vcpu);
2609
2610 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2611 has_error_code, error_code) == EMULATE_FAIL) {
2612 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2613 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2614 svm->vcpu.run->internal.ndata = 0;
2615 return 0;
2616 }
2617 return 1;
2618 }
2619
2620 static int cpuid_interception(struct vcpu_svm *svm)
2621 {
2622 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2623 kvm_emulate_cpuid(&svm->vcpu);
2624 return 1;
2625 }
2626
2627 static int iret_interception(struct vcpu_svm *svm)
2628 {
2629 ++svm->vcpu.stat.nmi_window_exits;
2630 clr_intercept(svm, INTERCEPT_IRET);
2631 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2632 return 1;
2633 }
2634
2635 static int invlpg_interception(struct vcpu_svm *svm)
2636 {
2637 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2638 }
2639
2640 static int emulate_on_interception(struct vcpu_svm *svm)
2641 {
2642 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2643 }
2644
2645 static int cr0_write_interception(struct vcpu_svm *svm)
2646 {
2647 struct kvm_vcpu *vcpu = &svm->vcpu;
2648 int r;
2649
2650 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2651
2652 if (svm->nested.vmexit_rip) {
2653 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2654 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2655 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2656 svm->nested.vmexit_rip = 0;
2657 }
2658
2659 return r == EMULATE_DONE;
2660 }
2661
2662 static int cr8_write_interception(struct vcpu_svm *svm)
2663 {
2664 struct kvm_run *kvm_run = svm->vcpu.run;
2665
2666 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2667 /* instruction emulation calls kvm_set_cr8() */
2668 emulate_instruction(&svm->vcpu, 0, 0, 0);
2669 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2670 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2671 return 1;
2672 }
2673 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2674 return 1;
2675 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2676 return 0;
2677 }
2678
2679 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2680 {
2681 struct vcpu_svm *svm = to_svm(vcpu);
2682
2683 switch (ecx) {
2684 case MSR_IA32_TSC: {
2685 struct vmcb *vmcb = get_host_vmcb(svm);
2686
2687 *data = vmcb->control.tsc_offset + native_read_tsc();
2688 break;
2689 }
2690 case MSR_STAR:
2691 *data = svm->vmcb->save.star;
2692 break;
2693 #ifdef CONFIG_X86_64
2694 case MSR_LSTAR:
2695 *data = svm->vmcb->save.lstar;
2696 break;
2697 case MSR_CSTAR:
2698 *data = svm->vmcb->save.cstar;
2699 break;
2700 case MSR_KERNEL_GS_BASE:
2701 *data = svm->vmcb->save.kernel_gs_base;
2702 break;
2703 case MSR_SYSCALL_MASK:
2704 *data = svm->vmcb->save.sfmask;
2705 break;
2706 #endif
2707 case MSR_IA32_SYSENTER_CS:
2708 *data = svm->vmcb->save.sysenter_cs;
2709 break;
2710 case MSR_IA32_SYSENTER_EIP:
2711 *data = svm->sysenter_eip;
2712 break;
2713 case MSR_IA32_SYSENTER_ESP:
2714 *data = svm->sysenter_esp;
2715 break;
2716 /*
2717 * Nobody will change the following 5 values in the VMCB so we can
2718 * safely return them on rdmsr. They will always be 0 until LBRV is
2719 * implemented.
2720 */
2721 case MSR_IA32_DEBUGCTLMSR:
2722 *data = svm->vmcb->save.dbgctl;
2723 break;
2724 case MSR_IA32_LASTBRANCHFROMIP:
2725 *data = svm->vmcb->save.br_from;
2726 break;
2727 case MSR_IA32_LASTBRANCHTOIP:
2728 *data = svm->vmcb->save.br_to;
2729 break;
2730 case MSR_IA32_LASTINTFROMIP:
2731 *data = svm->vmcb->save.last_excp_from;
2732 break;
2733 case MSR_IA32_LASTINTTOIP:
2734 *data = svm->vmcb->save.last_excp_to;
2735 break;
2736 case MSR_VM_HSAVE_PA:
2737 *data = svm->nested.hsave_msr;
2738 break;
2739 case MSR_VM_CR:
2740 *data = svm->nested.vm_cr_msr;
2741 break;
2742 case MSR_IA32_UCODE_REV:
2743 *data = 0x01000065;
2744 break;
2745 default:
2746 return kvm_get_msr_common(vcpu, ecx, data);
2747 }
2748 return 0;
2749 }
2750
2751 static int rdmsr_interception(struct vcpu_svm *svm)
2752 {
2753 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2754 u64 data;
2755
2756 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2757 trace_kvm_msr_read_ex(ecx);
2758 kvm_inject_gp(&svm->vcpu, 0);
2759 } else {
2760 trace_kvm_msr_read(ecx, data);
2761
2762 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2763 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2764 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2765 skip_emulated_instruction(&svm->vcpu);
2766 }
2767 return 1;
2768 }
2769
2770 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2771 {
2772 struct vcpu_svm *svm = to_svm(vcpu);
2773 int svm_dis, chg_mask;
2774
2775 if (data & ~SVM_VM_CR_VALID_MASK)
2776 return 1;
2777
2778 chg_mask = SVM_VM_CR_VALID_MASK;
2779
2780 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2781 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2782
2783 svm->nested.vm_cr_msr &= ~chg_mask;
2784 svm->nested.vm_cr_msr |= (data & chg_mask);
2785
2786 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2787
2788 /* check for svm_disable while efer.svme is set */
2789 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2790 return 1;
2791
2792 return 0;
2793 }
2794
2795 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2796 {
2797 struct vcpu_svm *svm = to_svm(vcpu);
2798
2799 switch (ecx) {
2800 case MSR_IA32_TSC:
2801 kvm_write_tsc(vcpu, data);
2802 break;
2803 case MSR_STAR:
2804 svm->vmcb->save.star = data;
2805 break;
2806 #ifdef CONFIG_X86_64
2807 case MSR_LSTAR:
2808 svm->vmcb->save.lstar = data;
2809 break;
2810 case MSR_CSTAR:
2811 svm->vmcb->save.cstar = data;
2812 break;
2813 case MSR_KERNEL_GS_BASE:
2814 svm->vmcb->save.kernel_gs_base = data;
2815 break;
2816 case MSR_SYSCALL_MASK:
2817 svm->vmcb->save.sfmask = data;
2818 break;
2819 #endif
2820 case MSR_IA32_SYSENTER_CS:
2821 svm->vmcb->save.sysenter_cs = data;
2822 break;
2823 case MSR_IA32_SYSENTER_EIP:
2824 svm->sysenter_eip = data;
2825 svm->vmcb->save.sysenter_eip = data;
2826 break;
2827 case MSR_IA32_SYSENTER_ESP:
2828 svm->sysenter_esp = data;
2829 svm->vmcb->save.sysenter_esp = data;
2830 break;
2831 case MSR_IA32_DEBUGCTLMSR:
2832 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2833 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2834 __func__, data);
2835 break;
2836 }
2837 if (data & DEBUGCTL_RESERVED_BITS)
2838 return 1;
2839
2840 svm->vmcb->save.dbgctl = data;
2841 mark_dirty(svm->vmcb, VMCB_LBR);
2842 if (data & (1ULL<<0))
2843 svm_enable_lbrv(svm);
2844 else
2845 svm_disable_lbrv(svm);
2846 break;
2847 case MSR_VM_HSAVE_PA:
2848 svm->nested.hsave_msr = data;
2849 break;
2850 case MSR_VM_CR:
2851 return svm_set_vm_cr(vcpu, data);
2852 case MSR_VM_IGNNE:
2853 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2854 break;
2855 default:
2856 return kvm_set_msr_common(vcpu, ecx, data);
2857 }
2858 return 0;
2859 }
2860
2861 static int wrmsr_interception(struct vcpu_svm *svm)
2862 {
2863 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2864 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2865 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2866
2867
2868 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2869 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2870 trace_kvm_msr_write_ex(ecx, data);
2871 kvm_inject_gp(&svm->vcpu, 0);
2872 } else {
2873 trace_kvm_msr_write(ecx, data);
2874 skip_emulated_instruction(&svm->vcpu);
2875 }
2876 return 1;
2877 }
2878
2879 static int msr_interception(struct vcpu_svm *svm)
2880 {
2881 if (svm->vmcb->control.exit_info_1)
2882 return wrmsr_interception(svm);
2883 else
2884 return rdmsr_interception(svm);
2885 }
2886
2887 static int interrupt_window_interception(struct vcpu_svm *svm)
2888 {
2889 struct kvm_run *kvm_run = svm->vcpu.run;
2890
2891 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2892 svm_clear_vintr(svm);
2893 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2894 mark_dirty(svm->vmcb, VMCB_INTR);
2895 /*
2896 * If the user space waits to inject interrupts, exit as soon as
2897 * possible
2898 */
2899 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2900 kvm_run->request_interrupt_window &&
2901 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2902 ++svm->vcpu.stat.irq_window_exits;
2903 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2904 return 0;
2905 }
2906
2907 return 1;
2908 }
2909
2910 static int pause_interception(struct vcpu_svm *svm)
2911 {
2912 kvm_vcpu_on_spin(&(svm->vcpu));
2913 return 1;
2914 }
2915
2916 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2917 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2918 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2919 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2920 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2921 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2922 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2923 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2924 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2925 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2926 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2927 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2928 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2929 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2930 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2931 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2932 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2933 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2934 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2935 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2936 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2937 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2938 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2939 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2940 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2941 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2942 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2943 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2944 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2945 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2946 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2947 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2948 [SVM_EXIT_INTR] = intr_interception,
2949 [SVM_EXIT_NMI] = nmi_interception,
2950 [SVM_EXIT_SMI] = nop_on_interception,
2951 [SVM_EXIT_INIT] = nop_on_interception,
2952 [SVM_EXIT_VINTR] = interrupt_window_interception,
2953 [SVM_EXIT_CPUID] = cpuid_interception,
2954 [SVM_EXIT_IRET] = iret_interception,
2955 [SVM_EXIT_INVD] = emulate_on_interception,
2956 [SVM_EXIT_PAUSE] = pause_interception,
2957 [SVM_EXIT_HLT] = halt_interception,
2958 [SVM_EXIT_INVLPG] = invlpg_interception,
2959 [SVM_EXIT_INVLPGA] = invlpga_interception,
2960 [SVM_EXIT_IOIO] = io_interception,
2961 [SVM_EXIT_MSR] = msr_interception,
2962 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2963 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2964 [SVM_EXIT_VMRUN] = vmrun_interception,
2965 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2966 [SVM_EXIT_VMLOAD] = vmload_interception,
2967 [SVM_EXIT_VMSAVE] = vmsave_interception,
2968 [SVM_EXIT_STGI] = stgi_interception,
2969 [SVM_EXIT_CLGI] = clgi_interception,
2970 [SVM_EXIT_SKINIT] = skinit_interception,
2971 [SVM_EXIT_WBINVD] = emulate_on_interception,
2972 [SVM_EXIT_MONITOR] = invalid_op_interception,
2973 [SVM_EXIT_MWAIT] = invalid_op_interception,
2974 [SVM_EXIT_NPF] = pf_interception,
2975 };
2976
2977 void dump_vmcb(struct kvm_vcpu *vcpu)
2978 {
2979 struct vcpu_svm *svm = to_svm(vcpu);
2980 struct vmcb_control_area *control = &svm->vmcb->control;
2981 struct vmcb_save_area *save = &svm->vmcb->save;
2982
2983 pr_err("VMCB Control Area:\n");
2984 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2985 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
2986 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2987 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
2988 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2989 pr_err("intercepts: %016llx\n", control->intercept);
2990 pr_err("pause filter count: %d\n", control->pause_filter_count);
2991 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2992 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2993 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2994 pr_err("asid: %d\n", control->asid);
2995 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2996 pr_err("int_ctl: %08x\n", control->int_ctl);
2997 pr_err("int_vector: %08x\n", control->int_vector);
2998 pr_err("int_state: %08x\n", control->int_state);
2999 pr_err("exit_code: %08x\n", control->exit_code);
3000 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3001 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3002 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3003 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3004 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3005 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3006 pr_err("event_inj: %08x\n", control->event_inj);
3007 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3008 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3009 pr_err("next_rip: %016llx\n", control->next_rip);
3010 pr_err("VMCB State Save Area:\n");
3011 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3012 save->es.selector, save->es.attrib,
3013 save->es.limit, save->es.base);
3014 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3015 save->cs.selector, save->cs.attrib,
3016 save->cs.limit, save->cs.base);
3017 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3018 save->ss.selector, save->ss.attrib,
3019 save->ss.limit, save->ss.base);
3020 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3021 save->ds.selector, save->ds.attrib,
3022 save->ds.limit, save->ds.base);
3023 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3024 save->fs.selector, save->fs.attrib,
3025 save->fs.limit, save->fs.base);
3026 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3027 save->gs.selector, save->gs.attrib,
3028 save->gs.limit, save->gs.base);
3029 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3030 save->gdtr.selector, save->gdtr.attrib,
3031 save->gdtr.limit, save->gdtr.base);
3032 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3033 save->ldtr.selector, save->ldtr.attrib,
3034 save->ldtr.limit, save->ldtr.base);
3035 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3036 save->idtr.selector, save->idtr.attrib,
3037 save->idtr.limit, save->idtr.base);
3038 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3039 save->tr.selector, save->tr.attrib,
3040 save->tr.limit, save->tr.base);
3041 pr_err("cpl: %d efer: %016llx\n",
3042 save->cpl, save->efer);
3043 pr_err("cr0: %016llx cr2: %016llx\n",
3044 save->cr0, save->cr2);
3045 pr_err("cr3: %016llx cr4: %016llx\n",
3046 save->cr3, save->cr4);
3047 pr_err("dr6: %016llx dr7: %016llx\n",
3048 save->dr6, save->dr7);
3049 pr_err("rip: %016llx rflags: %016llx\n",
3050 save->rip, save->rflags);
3051 pr_err("rsp: %016llx rax: %016llx\n",
3052 save->rsp, save->rax);
3053 pr_err("star: %016llx lstar: %016llx\n",
3054 save->star, save->lstar);
3055 pr_err("cstar: %016llx sfmask: %016llx\n",
3056 save->cstar, save->sfmask);
3057 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3058 save->kernel_gs_base, save->sysenter_cs);
3059 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3060 save->sysenter_esp, save->sysenter_eip);
3061 pr_err("gpat: %016llx dbgctl: %016llx\n",
3062 save->g_pat, save->dbgctl);
3063 pr_err("br_from: %016llx br_to: %016llx\n",
3064 save->br_from, save->br_to);
3065 pr_err("excp_from: %016llx excp_to: %016llx\n",
3066 save->last_excp_from, save->last_excp_to);
3067
3068 }
3069
3070 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3071 {
3072 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3073
3074 *info1 = control->exit_info_1;
3075 *info2 = control->exit_info_2;
3076 }
3077
3078 static int handle_exit(struct kvm_vcpu *vcpu)
3079 {
3080 struct vcpu_svm *svm = to_svm(vcpu);
3081 struct kvm_run *kvm_run = vcpu->run;
3082 u32 exit_code = svm->vmcb->control.exit_code;
3083
3084 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3085
3086 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3087 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3088 if (npt_enabled)
3089 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3090
3091 if (unlikely(svm->nested.exit_required)) {
3092 nested_svm_vmexit(svm);
3093 svm->nested.exit_required = false;
3094
3095 return 1;
3096 }
3097
3098 if (is_guest_mode(vcpu)) {
3099 int vmexit;
3100
3101 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3102 svm->vmcb->control.exit_info_1,
3103 svm->vmcb->control.exit_info_2,
3104 svm->vmcb->control.exit_int_info,
3105 svm->vmcb->control.exit_int_info_err);
3106
3107 vmexit = nested_svm_exit_special(svm);
3108
3109 if (vmexit == NESTED_EXIT_CONTINUE)
3110 vmexit = nested_svm_exit_handled(svm);
3111
3112 if (vmexit == NESTED_EXIT_DONE)
3113 return 1;
3114 }
3115
3116 svm_complete_interrupts(svm);
3117
3118 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3119 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3120 kvm_run->fail_entry.hardware_entry_failure_reason
3121 = svm->vmcb->control.exit_code;
3122 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3123 dump_vmcb(vcpu);
3124 return 0;
3125 }
3126
3127 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3128 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3129 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3130 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3131 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3132 "exit_code 0x%x\n",
3133 __func__, svm->vmcb->control.exit_int_info,
3134 exit_code);
3135
3136 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3137 || !svm_exit_handlers[exit_code]) {
3138 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3139 kvm_run->hw.hardware_exit_reason = exit_code;
3140 return 0;
3141 }
3142
3143 return svm_exit_handlers[exit_code](svm);
3144 }
3145
3146 static void reload_tss(struct kvm_vcpu *vcpu)
3147 {
3148 int cpu = raw_smp_processor_id();
3149
3150 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3151 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3152 load_TR_desc();
3153 }
3154
3155 static void pre_svm_run(struct vcpu_svm *svm)
3156 {
3157 int cpu = raw_smp_processor_id();
3158
3159 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3160
3161 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3162 /* FIXME: handle wraparound of asid_generation */
3163 if (svm->asid_generation != sd->asid_generation)
3164 new_asid(svm, sd);
3165 }
3166
3167 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3168 {
3169 struct vcpu_svm *svm = to_svm(vcpu);
3170
3171 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3172 vcpu->arch.hflags |= HF_NMI_MASK;
3173 set_intercept(svm, INTERCEPT_IRET);
3174 ++vcpu->stat.nmi_injections;
3175 }
3176
3177 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3178 {
3179 struct vmcb_control_area *control;
3180
3181 control = &svm->vmcb->control;
3182 control->int_vector = irq;
3183 control->int_ctl &= ~V_INTR_PRIO_MASK;
3184 control->int_ctl |= V_IRQ_MASK |
3185 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3186 mark_dirty(svm->vmcb, VMCB_INTR);
3187 }
3188
3189 static void svm_set_irq(struct kvm_vcpu *vcpu)
3190 {
3191 struct vcpu_svm *svm = to_svm(vcpu);
3192
3193 BUG_ON(!(gif_set(svm)));
3194
3195 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3196 ++vcpu->stat.irq_injections;
3197
3198 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3199 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3200 }
3201
3202 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3203 {
3204 struct vcpu_svm *svm = to_svm(vcpu);
3205
3206 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3207 return;
3208
3209 if (irr == -1)
3210 return;
3211
3212 if (tpr >= irr)
3213 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3214 }
3215
3216 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3217 {
3218 struct vcpu_svm *svm = to_svm(vcpu);
3219 struct vmcb *vmcb = svm->vmcb;
3220 int ret;
3221 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3222 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3223 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3224
3225 return ret;
3226 }
3227
3228 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3229 {
3230 struct vcpu_svm *svm = to_svm(vcpu);
3231
3232 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3233 }
3234
3235 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3236 {
3237 struct vcpu_svm *svm = to_svm(vcpu);
3238
3239 if (masked) {
3240 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3241 set_intercept(svm, INTERCEPT_IRET);
3242 } else {
3243 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3244 clr_intercept(svm, INTERCEPT_IRET);
3245 }
3246 }
3247
3248 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3249 {
3250 struct vcpu_svm *svm = to_svm(vcpu);
3251 struct vmcb *vmcb = svm->vmcb;
3252 int ret;
3253
3254 if (!gif_set(svm) ||
3255 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3256 return 0;
3257
3258 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3259
3260 if (is_guest_mode(vcpu))
3261 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3262
3263 return ret;
3264 }
3265
3266 static void enable_irq_window(struct kvm_vcpu *vcpu)
3267 {
3268 struct vcpu_svm *svm = to_svm(vcpu);
3269
3270 /*
3271 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3272 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3273 * get that intercept, this function will be called again though and
3274 * we'll get the vintr intercept.
3275 */
3276 if (gif_set(svm) && nested_svm_intr(svm)) {
3277 svm_set_vintr(svm);
3278 svm_inject_irq(svm, 0x0);
3279 }
3280 }
3281
3282 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3283 {
3284 struct vcpu_svm *svm = to_svm(vcpu);
3285
3286 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3287 == HF_NMI_MASK)
3288 return; /* IRET will cause a vm exit */
3289
3290 /*
3291 * Something prevents NMI from been injected. Single step over possible
3292 * problem (IRET or exception injection or interrupt shadow)
3293 */
3294 svm->nmi_singlestep = true;
3295 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3296 update_db_intercept(vcpu);
3297 }
3298
3299 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3300 {
3301 return 0;
3302 }
3303
3304 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3305 {
3306 to_svm(vcpu)->asid_generation--;
3307 }
3308
3309 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3310 {
3311 }
3312
3313 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3314 {
3315 struct vcpu_svm *svm = to_svm(vcpu);
3316
3317 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3318 return;
3319
3320 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3321 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3322 kvm_set_cr8(vcpu, cr8);
3323 }
3324 }
3325
3326 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3327 {
3328 struct vcpu_svm *svm = to_svm(vcpu);
3329 u64 cr8;
3330
3331 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3332 return;
3333
3334 cr8 = kvm_get_cr8(vcpu);
3335 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3336 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3337 }
3338
3339 static void svm_complete_interrupts(struct vcpu_svm *svm)
3340 {
3341 u8 vector;
3342 int type;
3343 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3344 unsigned int3_injected = svm->int3_injected;
3345
3346 svm->int3_injected = 0;
3347
3348 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3349 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3350 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3351 }
3352
3353 svm->vcpu.arch.nmi_injected = false;
3354 kvm_clear_exception_queue(&svm->vcpu);
3355 kvm_clear_interrupt_queue(&svm->vcpu);
3356
3357 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3358 return;
3359
3360 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3361
3362 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3363 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3364
3365 switch (type) {
3366 case SVM_EXITINTINFO_TYPE_NMI:
3367 svm->vcpu.arch.nmi_injected = true;
3368 break;
3369 case SVM_EXITINTINFO_TYPE_EXEPT:
3370 /*
3371 * In case of software exceptions, do not reinject the vector,
3372 * but re-execute the instruction instead. Rewind RIP first
3373 * if we emulated INT3 before.
3374 */
3375 if (kvm_exception_is_soft(vector)) {
3376 if (vector == BP_VECTOR && int3_injected &&
3377 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3378 kvm_rip_write(&svm->vcpu,
3379 kvm_rip_read(&svm->vcpu) -
3380 int3_injected);
3381 break;
3382 }
3383 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3384 u32 err = svm->vmcb->control.exit_int_info_err;
3385 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3386
3387 } else
3388 kvm_requeue_exception(&svm->vcpu, vector);
3389 break;
3390 case SVM_EXITINTINFO_TYPE_INTR:
3391 kvm_queue_interrupt(&svm->vcpu, vector, false);
3392 break;
3393 default:
3394 break;
3395 }
3396 }
3397
3398 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3399 {
3400 struct vcpu_svm *svm = to_svm(vcpu);
3401 struct vmcb_control_area *control = &svm->vmcb->control;
3402
3403 control->exit_int_info = control->event_inj;
3404 control->exit_int_info_err = control->event_inj_err;
3405 control->event_inj = 0;
3406 svm_complete_interrupts(svm);
3407 }
3408
3409 #ifdef CONFIG_X86_64
3410 #define R "r"
3411 #else
3412 #define R "e"
3413 #endif
3414
3415 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3416 {
3417 struct vcpu_svm *svm = to_svm(vcpu);
3418
3419 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3420 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3421 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3422
3423 /*
3424 * A vmexit emulation is required before the vcpu can be executed
3425 * again.
3426 */
3427 if (unlikely(svm->nested.exit_required))
3428 return;
3429
3430 pre_svm_run(svm);
3431
3432 sync_lapic_to_cr8(vcpu);
3433
3434 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3435
3436 clgi();
3437
3438 local_irq_enable();
3439
3440 asm volatile (
3441 "push %%"R"bp; \n\t"
3442 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3443 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3444 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3445 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3446 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3447 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3448 #ifdef CONFIG_X86_64
3449 "mov %c[r8](%[svm]), %%r8 \n\t"
3450 "mov %c[r9](%[svm]), %%r9 \n\t"
3451 "mov %c[r10](%[svm]), %%r10 \n\t"
3452 "mov %c[r11](%[svm]), %%r11 \n\t"
3453 "mov %c[r12](%[svm]), %%r12 \n\t"
3454 "mov %c[r13](%[svm]), %%r13 \n\t"
3455 "mov %c[r14](%[svm]), %%r14 \n\t"
3456 "mov %c[r15](%[svm]), %%r15 \n\t"
3457 #endif
3458
3459 /* Enter guest mode */
3460 "push %%"R"ax \n\t"
3461 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3462 __ex(SVM_VMLOAD) "\n\t"
3463 __ex(SVM_VMRUN) "\n\t"
3464 __ex(SVM_VMSAVE) "\n\t"
3465 "pop %%"R"ax \n\t"
3466
3467 /* Save guest registers, load host registers */
3468 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3469 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3470 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3471 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3472 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3473 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3474 #ifdef CONFIG_X86_64
3475 "mov %%r8, %c[r8](%[svm]) \n\t"
3476 "mov %%r9, %c[r9](%[svm]) \n\t"
3477 "mov %%r10, %c[r10](%[svm]) \n\t"
3478 "mov %%r11, %c[r11](%[svm]) \n\t"
3479 "mov %%r12, %c[r12](%[svm]) \n\t"
3480 "mov %%r13, %c[r13](%[svm]) \n\t"
3481 "mov %%r14, %c[r14](%[svm]) \n\t"
3482 "mov %%r15, %c[r15](%[svm]) \n\t"
3483 #endif
3484 "pop %%"R"bp"
3485 :
3486 : [svm]"a"(svm),
3487 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3488 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3489 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3490 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3491 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3492 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3493 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3494 #ifdef CONFIG_X86_64
3495 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3496 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3497 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3498 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3499 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3500 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3501 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3502 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3503 #endif
3504 : "cc", "memory"
3505 , R"bx", R"cx", R"dx", R"si", R"di"
3506 #ifdef CONFIG_X86_64
3507 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3508 #endif
3509 );
3510
3511 #ifdef CONFIG_X86_64
3512 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3513 #else
3514 loadsegment(fs, svm->host.fs);
3515 #endif
3516
3517 reload_tss(vcpu);
3518
3519 local_irq_disable();
3520
3521 stgi();
3522
3523 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3524 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3525 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3526 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3527
3528 sync_cr8_to_lapic(vcpu);
3529
3530 svm->next_rip = 0;
3531
3532 /* if exit due to PF check for async PF */
3533 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3534 svm->apf_reason = kvm_read_and_reset_pf_reason();
3535
3536 if (npt_enabled) {
3537 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3538 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3539 }
3540
3541 /*
3542 * We need to handle MC intercepts here before the vcpu has a chance to
3543 * change the physical cpu
3544 */
3545 if (unlikely(svm->vmcb->control.exit_code ==
3546 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3547 svm_handle_mce(svm);
3548
3549 mark_all_clean(svm->vmcb);
3550 }
3551
3552 #undef R
3553
3554 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3555 {
3556 struct vcpu_svm *svm = to_svm(vcpu);
3557
3558 svm->vmcb->save.cr3 = root;
3559 mark_dirty(svm->vmcb, VMCB_CR);
3560 svm_flush_tlb(vcpu);
3561 }
3562
3563 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3564 {
3565 struct vcpu_svm *svm = to_svm(vcpu);
3566
3567 svm->vmcb->control.nested_cr3 = root;
3568 mark_dirty(svm->vmcb, VMCB_NPT);
3569
3570 /* Also sync guest cr3 here in case we live migrate */
3571 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3572 mark_dirty(svm->vmcb, VMCB_CR);
3573
3574 svm_flush_tlb(vcpu);
3575 }
3576
3577 static int is_disabled(void)
3578 {
3579 u64 vm_cr;
3580
3581 rdmsrl(MSR_VM_CR, vm_cr);
3582 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3583 return 1;
3584
3585 return 0;
3586 }
3587
3588 static void
3589 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3590 {
3591 /*
3592 * Patch in the VMMCALL instruction:
3593 */
3594 hypercall[0] = 0x0f;
3595 hypercall[1] = 0x01;
3596 hypercall[2] = 0xd9;
3597 }
3598
3599 static void svm_check_processor_compat(void *rtn)
3600 {
3601 *(int *)rtn = 0;
3602 }
3603
3604 static bool svm_cpu_has_accelerated_tpr(void)
3605 {
3606 return false;
3607 }
3608
3609 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3610 {
3611 return 0;
3612 }
3613
3614 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3615 {
3616 }
3617
3618 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3619 {
3620 switch (func) {
3621 case 0x00000001:
3622 /* Mask out xsave bit as long as it is not supported by SVM */
3623 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3624 break;
3625 case 0x80000001:
3626 if (nested)
3627 entry->ecx |= (1 << 2); /* Set SVM bit */
3628 break;
3629 case 0x8000000A:
3630 entry->eax = 1; /* SVM revision 1 */
3631 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3632 ASID emulation to nested SVM */
3633 entry->ecx = 0; /* Reserved */
3634 entry->edx = 0; /* Per default do not support any
3635 additional features */
3636
3637 /* Support next_rip if host supports it */
3638 if (boot_cpu_has(X86_FEATURE_NRIPS))
3639 entry->edx |= SVM_FEATURE_NRIP;
3640
3641 /* Support NPT for the guest if enabled */
3642 if (npt_enabled)
3643 entry->edx |= SVM_FEATURE_NPT;
3644
3645 break;
3646 }
3647 }
3648
3649 static const struct trace_print_flags svm_exit_reasons_str[] = {
3650 { SVM_EXIT_READ_CR0, "read_cr0" },
3651 { SVM_EXIT_READ_CR3, "read_cr3" },
3652 { SVM_EXIT_READ_CR4, "read_cr4" },
3653 { SVM_EXIT_READ_CR8, "read_cr8" },
3654 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3655 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3656 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3657 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3658 { SVM_EXIT_READ_DR0, "read_dr0" },
3659 { SVM_EXIT_READ_DR1, "read_dr1" },
3660 { SVM_EXIT_READ_DR2, "read_dr2" },
3661 { SVM_EXIT_READ_DR3, "read_dr3" },
3662 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3663 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3664 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3665 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3666 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3667 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3668 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3669 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3670 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3671 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3672 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3673 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3674 { SVM_EXIT_INTR, "interrupt" },
3675 { SVM_EXIT_NMI, "nmi" },
3676 { SVM_EXIT_SMI, "smi" },
3677 { SVM_EXIT_INIT, "init" },
3678 { SVM_EXIT_VINTR, "vintr" },
3679 { SVM_EXIT_CPUID, "cpuid" },
3680 { SVM_EXIT_INVD, "invd" },
3681 { SVM_EXIT_HLT, "hlt" },
3682 { SVM_EXIT_INVLPG, "invlpg" },
3683 { SVM_EXIT_INVLPGA, "invlpga" },
3684 { SVM_EXIT_IOIO, "io" },
3685 { SVM_EXIT_MSR, "msr" },
3686 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3687 { SVM_EXIT_SHUTDOWN, "shutdown" },
3688 { SVM_EXIT_VMRUN, "vmrun" },
3689 { SVM_EXIT_VMMCALL, "hypercall" },
3690 { SVM_EXIT_VMLOAD, "vmload" },
3691 { SVM_EXIT_VMSAVE, "vmsave" },
3692 { SVM_EXIT_STGI, "stgi" },
3693 { SVM_EXIT_CLGI, "clgi" },
3694 { SVM_EXIT_SKINIT, "skinit" },
3695 { SVM_EXIT_WBINVD, "wbinvd" },
3696 { SVM_EXIT_MONITOR, "monitor" },
3697 { SVM_EXIT_MWAIT, "mwait" },
3698 { SVM_EXIT_NPF, "npf" },
3699 { -1, NULL }
3700 };
3701
3702 static int svm_get_lpage_level(void)
3703 {
3704 return PT_PDPE_LEVEL;
3705 }
3706
3707 static bool svm_rdtscp_supported(void)
3708 {
3709 return false;
3710 }
3711
3712 static bool svm_has_wbinvd_exit(void)
3713 {
3714 return true;
3715 }
3716
3717 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3718 {
3719 struct vcpu_svm *svm = to_svm(vcpu);
3720
3721 set_exception_intercept(svm, NM_VECTOR);
3722 update_cr0_intercept(svm);
3723 }
3724
3725 static struct kvm_x86_ops svm_x86_ops = {
3726 .cpu_has_kvm_support = has_svm,
3727 .disabled_by_bios = is_disabled,
3728 .hardware_setup = svm_hardware_setup,
3729 .hardware_unsetup = svm_hardware_unsetup,
3730 .check_processor_compatibility = svm_check_processor_compat,
3731 .hardware_enable = svm_hardware_enable,
3732 .hardware_disable = svm_hardware_disable,
3733 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3734
3735 .vcpu_create = svm_create_vcpu,
3736 .vcpu_free = svm_free_vcpu,
3737 .vcpu_reset = svm_vcpu_reset,
3738
3739 .prepare_guest_switch = svm_prepare_guest_switch,
3740 .vcpu_load = svm_vcpu_load,
3741 .vcpu_put = svm_vcpu_put,
3742
3743 .set_guest_debug = svm_guest_debug,
3744 .get_msr = svm_get_msr,
3745 .set_msr = svm_set_msr,
3746 .get_segment_base = svm_get_segment_base,
3747 .get_segment = svm_get_segment,
3748 .set_segment = svm_set_segment,
3749 .get_cpl = svm_get_cpl,
3750 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3751 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3752 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3753 .set_cr0 = svm_set_cr0,
3754 .set_cr3 = svm_set_cr3,
3755 .set_cr4 = svm_set_cr4,
3756 .set_efer = svm_set_efer,
3757 .get_idt = svm_get_idt,
3758 .set_idt = svm_set_idt,
3759 .get_gdt = svm_get_gdt,
3760 .set_gdt = svm_set_gdt,
3761 .set_dr7 = svm_set_dr7,
3762 .cache_reg = svm_cache_reg,
3763 .get_rflags = svm_get_rflags,
3764 .set_rflags = svm_set_rflags,
3765 .fpu_activate = svm_fpu_activate,
3766 .fpu_deactivate = svm_fpu_deactivate,
3767
3768 .tlb_flush = svm_flush_tlb,
3769
3770 .run = svm_vcpu_run,
3771 .handle_exit = handle_exit,
3772 .skip_emulated_instruction = skip_emulated_instruction,
3773 .set_interrupt_shadow = svm_set_interrupt_shadow,
3774 .get_interrupt_shadow = svm_get_interrupt_shadow,
3775 .patch_hypercall = svm_patch_hypercall,
3776 .set_irq = svm_set_irq,
3777 .set_nmi = svm_inject_nmi,
3778 .queue_exception = svm_queue_exception,
3779 .cancel_injection = svm_cancel_injection,
3780 .interrupt_allowed = svm_interrupt_allowed,
3781 .nmi_allowed = svm_nmi_allowed,
3782 .get_nmi_mask = svm_get_nmi_mask,
3783 .set_nmi_mask = svm_set_nmi_mask,
3784 .enable_nmi_window = enable_nmi_window,
3785 .enable_irq_window = enable_irq_window,
3786 .update_cr8_intercept = update_cr8_intercept,
3787
3788 .set_tss_addr = svm_set_tss_addr,
3789 .get_tdp_level = get_npt_level,
3790 .get_mt_mask = svm_get_mt_mask,
3791
3792 .get_exit_info = svm_get_exit_info,
3793 .exit_reasons_str = svm_exit_reasons_str,
3794
3795 .get_lpage_level = svm_get_lpage_level,
3796
3797 .cpuid_update = svm_cpuid_update,
3798
3799 .rdtscp_supported = svm_rdtscp_supported,
3800
3801 .set_supported_cpuid = svm_set_supported_cpuid,
3802
3803 .has_wbinvd_exit = svm_has_wbinvd_exit,
3804
3805 .write_tsc_offset = svm_write_tsc_offset,
3806 .adjust_tsc_offset = svm_adjust_tsc_offset,
3807
3808 .set_tdp_cr3 = set_tdp_cr3,
3809 };
3810
3811 static int __init svm_init(void)
3812 {
3813 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3814 __alignof__(struct vcpu_svm), THIS_MODULE);
3815 }
3816
3817 static void __exit svm_exit(void)
3818 {
3819 kvm_exit();
3820 }
3821
3822 module_init(svm_init)
3823 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree