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drm/radeon/kms: bail on BTC parts if MC ucode is missing
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
blobc3f0d428c51dac44f773d14a1e5a1d44a25229e4
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45 {
46 u16 ctl, v;
47 int cap, err;
48
49 cap = pci_pcie_cap(rdev->pdev);
50 if (!cap)
51 return;
52
53 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54 if (err)
55 return;
56
57 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
59 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60 * to avoid hangs or perfomance issues
61 */
62 if ((v == 0) || (v == 6) || (v == 7)) {
63 ctl &= ~PCI_EXP_DEVCTL_READRQ;
64 ctl |= (2 << 12);
65 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66 }
67 }
68
69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
70 {
71 /* enable the pflip int */
72 radeon_irq_kms_pflip_irq_get(rdev, crtc);
73 }
74
75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
76 {
77 /* disable the pflip int */
78 radeon_irq_kms_pflip_irq_put(rdev, crtc);
79 }
80
81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82 {
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85 int i;
86
87 /* Lock the graphics update lock */
88 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
89 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
90
91 /* update the scanout addresses */
92 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
93 upper_32_bits(crtc_base));
94 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
95 (u32)crtc_base);
96
97 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
98 upper_32_bits(crtc_base));
99 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
100 (u32)crtc_base);
101
102 /* Wait for update_pending to go high. */
103 for (i = 0; i < rdev->usec_timeout; i++) {
104 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
105 break;
106 udelay(1);
107 }
108 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
109
110 /* Unlock the lock, so double-buffering can take place inside vblank */
111 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
112 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
113
114 /* Return current update_pending status: */
115 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
116 }
117
118 /* get temperature in millidegrees */
119 int evergreen_get_temp(struct radeon_device *rdev)
120 {
121 u32 temp, toffset;
122 int actual_temp = 0;
123
124 if (rdev->family == CHIP_JUNIPER) {
125 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
126 TOFFSET_SHIFT;
127 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
128 TS0_ADC_DOUT_SHIFT;
129
130 if (toffset & 0x100)
131 actual_temp = temp / 2 - (0x200 - toffset);
132 else
133 actual_temp = temp / 2 + toffset;
134
135 actual_temp = actual_temp * 1000;
136
137 } else {
138 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
139 ASIC_T_SHIFT;
140
141 if (temp & 0x400)
142 actual_temp = -256;
143 else if (temp & 0x200)
144 actual_temp = 255;
145 else if (temp & 0x100) {
146 actual_temp = temp & 0x1ff;
147 actual_temp |= ~0x1ff;
148 } else
149 actual_temp = temp & 0xff;
150
151 actual_temp = (actual_temp * 1000) / 2;
152 }
153
154 return actual_temp;
155 }
156
157 int sumo_get_temp(struct radeon_device *rdev)
158 {
159 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
160 int actual_temp = temp - 49;
161
162 return actual_temp * 1000;
163 }
164
165 void evergreen_pm_misc(struct radeon_device *rdev)
166 {
167 int req_ps_idx = rdev->pm.requested_power_state_index;
168 int req_cm_idx = rdev->pm.requested_clock_mode_index;
169 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
170 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
171
172 if (voltage->type == VOLTAGE_SW) {
173 /* 0xff01 is a flag rather then an actual voltage */
174 if (voltage->voltage == 0xff01)
175 return;
176 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
177 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
178 rdev->pm.current_vddc = voltage->voltage;
179 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
180 }
181 /* 0xff01 is a flag rather then an actual voltage */
182 if (voltage->vddci == 0xff01)
183 return;
184 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
185 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
186 rdev->pm.current_vddci = voltage->vddci;
187 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
188 }
189 }
190 }
191
192 void evergreen_pm_prepare(struct radeon_device *rdev)
193 {
194 struct drm_device *ddev = rdev->ddev;
195 struct drm_crtc *crtc;
196 struct radeon_crtc *radeon_crtc;
197 u32 tmp;
198
199 /* disable any active CRTCs */
200 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
201 radeon_crtc = to_radeon_crtc(crtc);
202 if (radeon_crtc->enabled) {
203 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
204 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
205 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
206 }
207 }
208 }
209
210 void evergreen_pm_finish(struct radeon_device *rdev)
211 {
212 struct drm_device *ddev = rdev->ddev;
213 struct drm_crtc *crtc;
214 struct radeon_crtc *radeon_crtc;
215 u32 tmp;
216
217 /* enable any active CRTCs */
218 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
219 radeon_crtc = to_radeon_crtc(crtc);
220 if (radeon_crtc->enabled) {
221 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
222 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
223 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
224 }
225 }
226 }
227
228 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
229 {
230 bool connected = false;
231
232 switch (hpd) {
233 case RADEON_HPD_1:
234 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
235 connected = true;
236 break;
237 case RADEON_HPD_2:
238 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
239 connected = true;
240 break;
241 case RADEON_HPD_3:
242 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
243 connected = true;
244 break;
245 case RADEON_HPD_4:
246 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
247 connected = true;
248 break;
249 case RADEON_HPD_5:
250 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
251 connected = true;
252 break;
253 case RADEON_HPD_6:
254 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
255 connected = true;
256 break;
257 default:
258 break;
259 }
260
261 return connected;
262 }
263
264 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
265 enum radeon_hpd_id hpd)
266 {
267 u32 tmp;
268 bool connected = evergreen_hpd_sense(rdev, hpd);
269
270 switch (hpd) {
271 case RADEON_HPD_1:
272 tmp = RREG32(DC_HPD1_INT_CONTROL);
273 if (connected)
274 tmp &= ~DC_HPDx_INT_POLARITY;
275 else
276 tmp |= DC_HPDx_INT_POLARITY;
277 WREG32(DC_HPD1_INT_CONTROL, tmp);
278 break;
279 case RADEON_HPD_2:
280 tmp = RREG32(DC_HPD2_INT_CONTROL);
281 if (connected)
282 tmp &= ~DC_HPDx_INT_POLARITY;
283 else
284 tmp |= DC_HPDx_INT_POLARITY;
285 WREG32(DC_HPD2_INT_CONTROL, tmp);
286 break;
287 case RADEON_HPD_3:
288 tmp = RREG32(DC_HPD3_INT_CONTROL);
289 if (connected)
290 tmp &= ~DC_HPDx_INT_POLARITY;
291 else
292 tmp |= DC_HPDx_INT_POLARITY;
293 WREG32(DC_HPD3_INT_CONTROL, tmp);
294 break;
295 case RADEON_HPD_4:
296 tmp = RREG32(DC_HPD4_INT_CONTROL);
297 if (connected)
298 tmp &= ~DC_HPDx_INT_POLARITY;
299 else
300 tmp |= DC_HPDx_INT_POLARITY;
301 WREG32(DC_HPD4_INT_CONTROL, tmp);
302 break;
303 case RADEON_HPD_5:
304 tmp = RREG32(DC_HPD5_INT_CONTROL);
305 if (connected)
306 tmp &= ~DC_HPDx_INT_POLARITY;
307 else
308 tmp |= DC_HPDx_INT_POLARITY;
309 WREG32(DC_HPD5_INT_CONTROL, tmp);
310 break;
311 case RADEON_HPD_6:
312 tmp = RREG32(DC_HPD6_INT_CONTROL);
313 if (connected)
314 tmp &= ~DC_HPDx_INT_POLARITY;
315 else
316 tmp |= DC_HPDx_INT_POLARITY;
317 WREG32(DC_HPD6_INT_CONTROL, tmp);
318 break;
319 default:
320 break;
321 }
322 }
323
324 void evergreen_hpd_init(struct radeon_device *rdev)
325 {
326 struct drm_device *dev = rdev->ddev;
327 struct drm_connector *connector;
328 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
329 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
330
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
334 case RADEON_HPD_1:
335 WREG32(DC_HPD1_CONTROL, tmp);
336 rdev->irq.hpd[0] = true;
337 break;
338 case RADEON_HPD_2:
339 WREG32(DC_HPD2_CONTROL, tmp);
340 rdev->irq.hpd[1] = true;
341 break;
342 case RADEON_HPD_3:
343 WREG32(DC_HPD3_CONTROL, tmp);
344 rdev->irq.hpd[2] = true;
345 break;
346 case RADEON_HPD_4:
347 WREG32(DC_HPD4_CONTROL, tmp);
348 rdev->irq.hpd[3] = true;
349 break;
350 case RADEON_HPD_5:
351 WREG32(DC_HPD5_CONTROL, tmp);
352 rdev->irq.hpd[4] = true;
353 break;
354 case RADEON_HPD_6:
355 WREG32(DC_HPD6_CONTROL, tmp);
356 rdev->irq.hpd[5] = true;
357 break;
358 default:
359 break;
360 }
361 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
362 }
363 if (rdev->irq.installed)
364 evergreen_irq_set(rdev);
365 }
366
367 void evergreen_hpd_fini(struct radeon_device *rdev)
368 {
369 struct drm_device *dev = rdev->ddev;
370 struct drm_connector *connector;
371
372 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
373 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
374 switch (radeon_connector->hpd.hpd) {
375 case RADEON_HPD_1:
376 WREG32(DC_HPD1_CONTROL, 0);
377 rdev->irq.hpd[0] = false;
378 break;
379 case RADEON_HPD_2:
380 WREG32(DC_HPD2_CONTROL, 0);
381 rdev->irq.hpd[1] = false;
382 break;
383 case RADEON_HPD_3:
384 WREG32(DC_HPD3_CONTROL, 0);
385 rdev->irq.hpd[2] = false;
386 break;
387 case RADEON_HPD_4:
388 WREG32(DC_HPD4_CONTROL, 0);
389 rdev->irq.hpd[3] = false;
390 break;
391 case RADEON_HPD_5:
392 WREG32(DC_HPD5_CONTROL, 0);
393 rdev->irq.hpd[4] = false;
394 break;
395 case RADEON_HPD_6:
396 WREG32(DC_HPD6_CONTROL, 0);
397 rdev->irq.hpd[5] = false;
398 break;
399 default:
400 break;
401 }
402 }
403 }
404
405 /* watermark setup */
406
407 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
408 struct radeon_crtc *radeon_crtc,
409 struct drm_display_mode *mode,
410 struct drm_display_mode *other_mode)
411 {
412 u32 tmp;
413 /*
414 * Line Buffer Setup
415 * There are 3 line buffers, each one shared by 2 display controllers.
416 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
417 * the display controllers. The paritioning is done via one of four
418 * preset allocations specified in bits 2:0:
419 * first display controller
420 * 0 - first half of lb (3840 * 2)
421 * 1 - first 3/4 of lb (5760 * 2)
422 * 2 - whole lb (7680 * 2), other crtc must be disabled
423 * 3 - first 1/4 of lb (1920 * 2)
424 * second display controller
425 * 4 - second half of lb (3840 * 2)
426 * 5 - second 3/4 of lb (5760 * 2)
427 * 6 - whole lb (7680 * 2), other crtc must be disabled
428 * 7 - last 1/4 of lb (1920 * 2)
429 */
430 /* this can get tricky if we have two large displays on a paired group
431 * of crtcs. Ideally for multiple large displays we'd assign them to
432 * non-linked crtcs for maximum line buffer allocation.
433 */
434 if (radeon_crtc->base.enabled && mode) {
435 if (other_mode)
436 tmp = 0; /* 1/2 */
437 else
438 tmp = 2; /* whole */
439 } else
440 tmp = 0;
441
442 /* second controller of the pair uses second half of the lb */
443 if (radeon_crtc->crtc_id % 2)
444 tmp += 4;
445 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
446
447 if (radeon_crtc->base.enabled && mode) {
448 switch (tmp) {
449 case 0:
450 case 4:
451 default:
452 if (ASIC_IS_DCE5(rdev))
453 return 4096 * 2;
454 else
455 return 3840 * 2;
456 case 1:
457 case 5:
458 if (ASIC_IS_DCE5(rdev))
459 return 6144 * 2;
460 else
461 return 5760 * 2;
462 case 2:
463 case 6:
464 if (ASIC_IS_DCE5(rdev))
465 return 8192 * 2;
466 else
467 return 7680 * 2;
468 case 3:
469 case 7:
470 if (ASIC_IS_DCE5(rdev))
471 return 2048 * 2;
472 else
473 return 1920 * 2;
474 }
475 }
476
477 /* controller not enabled, so no lb used */
478 return 0;
479 }
480
481 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
482 {
483 u32 tmp = RREG32(MC_SHARED_CHMAP);
484
485 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
486 case 0:
487 default:
488 return 1;
489 case 1:
490 return 2;
491 case 2:
492 return 4;
493 case 3:
494 return 8;
495 }
496 }
497
498 struct evergreen_wm_params {
499 u32 dram_channels; /* number of dram channels */
500 u32 yclk; /* bandwidth per dram data pin in kHz */
501 u32 sclk; /* engine clock in kHz */
502 u32 disp_clk; /* display clock in kHz */
503 u32 src_width; /* viewport width */
504 u32 active_time; /* active display time in ns */
505 u32 blank_time; /* blank time in ns */
506 bool interlaced; /* mode is interlaced */
507 fixed20_12 vsc; /* vertical scale ratio */
508 u32 num_heads; /* number of active crtcs */
509 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
510 u32 lb_size; /* line buffer allocated to pipe */
511 u32 vtaps; /* vertical scaler taps */
512 };
513
514 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
515 {
516 /* Calculate DRAM Bandwidth and the part allocated to display. */
517 fixed20_12 dram_efficiency; /* 0.7 */
518 fixed20_12 yclk, dram_channels, bandwidth;
519 fixed20_12 a;
520
521 a.full = dfixed_const(1000);
522 yclk.full = dfixed_const(wm->yclk);
523 yclk.full = dfixed_div(yclk, a);
524 dram_channels.full = dfixed_const(wm->dram_channels * 4);
525 a.full = dfixed_const(10);
526 dram_efficiency.full = dfixed_const(7);
527 dram_efficiency.full = dfixed_div(dram_efficiency, a);
528 bandwidth.full = dfixed_mul(dram_channels, yclk);
529 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
530
531 return dfixed_trunc(bandwidth);
532 }
533
534 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
535 {
536 /* Calculate DRAM Bandwidth and the part allocated to display. */
537 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
538 fixed20_12 yclk, dram_channels, bandwidth;
539 fixed20_12 a;
540
541 a.full = dfixed_const(1000);
542 yclk.full = dfixed_const(wm->yclk);
543 yclk.full = dfixed_div(yclk, a);
544 dram_channels.full = dfixed_const(wm->dram_channels * 4);
545 a.full = dfixed_const(10);
546 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
547 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
548 bandwidth.full = dfixed_mul(dram_channels, yclk);
549 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
550
551 return dfixed_trunc(bandwidth);
552 }
553
554 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
555 {
556 /* Calculate the display Data return Bandwidth */
557 fixed20_12 return_efficiency; /* 0.8 */
558 fixed20_12 sclk, bandwidth;
559 fixed20_12 a;
560
561 a.full = dfixed_const(1000);
562 sclk.full = dfixed_const(wm->sclk);
563 sclk.full = dfixed_div(sclk, a);
564 a.full = dfixed_const(10);
565 return_efficiency.full = dfixed_const(8);
566 return_efficiency.full = dfixed_div(return_efficiency, a);
567 a.full = dfixed_const(32);
568 bandwidth.full = dfixed_mul(a, sclk);
569 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
570
571 return dfixed_trunc(bandwidth);
572 }
573
574 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
575 {
576 /* Calculate the DMIF Request Bandwidth */
577 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
578 fixed20_12 disp_clk, bandwidth;
579 fixed20_12 a;
580
581 a.full = dfixed_const(1000);
582 disp_clk.full = dfixed_const(wm->disp_clk);
583 disp_clk.full = dfixed_div(disp_clk, a);
584 a.full = dfixed_const(10);
585 disp_clk_request_efficiency.full = dfixed_const(8);
586 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
587 a.full = dfixed_const(32);
588 bandwidth.full = dfixed_mul(a, disp_clk);
589 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
590
591 return dfixed_trunc(bandwidth);
592 }
593
594 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
595 {
596 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
597 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
598 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
599 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
600
601 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
602 }
603
604 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
605 {
606 /* Calculate the display mode Average Bandwidth
607 * DisplayMode should contain the source and destination dimensions,
608 * timing, etc.
609 */
610 fixed20_12 bpp;
611 fixed20_12 line_time;
612 fixed20_12 src_width;
613 fixed20_12 bandwidth;
614 fixed20_12 a;
615
616 a.full = dfixed_const(1000);
617 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
618 line_time.full = dfixed_div(line_time, a);
619 bpp.full = dfixed_const(wm->bytes_per_pixel);
620 src_width.full = dfixed_const(wm->src_width);
621 bandwidth.full = dfixed_mul(src_width, bpp);
622 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
623 bandwidth.full = dfixed_div(bandwidth, line_time);
624
625 return dfixed_trunc(bandwidth);
626 }
627
628 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
629 {
630 /* First calcualte the latency in ns */
631 u32 mc_latency = 2000; /* 2000 ns. */
632 u32 available_bandwidth = evergreen_available_bandwidth(wm);
633 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
634 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
635 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
636 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
637 (wm->num_heads * cursor_line_pair_return_time);
638 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
639 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
640 fixed20_12 a, b, c;
641
642 if (wm->num_heads == 0)
643 return 0;
644
645 a.full = dfixed_const(2);
646 b.full = dfixed_const(1);
647 if ((wm->vsc.full > a.full) ||
648 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
649 (wm->vtaps >= 5) ||
650 ((wm->vsc.full >= a.full) && wm->interlaced))
651 max_src_lines_per_dst_line = 4;
652 else
653 max_src_lines_per_dst_line = 2;
654
655 a.full = dfixed_const(available_bandwidth);
656 b.full = dfixed_const(wm->num_heads);
657 a.full = dfixed_div(a, b);
658
659 b.full = dfixed_const(1000);
660 c.full = dfixed_const(wm->disp_clk);
661 b.full = dfixed_div(c, b);
662 c.full = dfixed_const(wm->bytes_per_pixel);
663 b.full = dfixed_mul(b, c);
664
665 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
666
667 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
668 b.full = dfixed_const(1000);
669 c.full = dfixed_const(lb_fill_bw);
670 b.full = dfixed_div(c, b);
671 a.full = dfixed_div(a, b);
672 line_fill_time = dfixed_trunc(a);
673
674 if (line_fill_time < wm->active_time)
675 return latency;
676 else
677 return latency + (line_fill_time - wm->active_time);
678
679 }
680
681 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
682 {
683 if (evergreen_average_bandwidth(wm) <=
684 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
685 return true;
686 else
687 return false;
688 };
689
690 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
691 {
692 if (evergreen_average_bandwidth(wm) <=
693 (evergreen_available_bandwidth(wm) / wm->num_heads))
694 return true;
695 else
696 return false;
697 };
698
699 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
700 {
701 u32 lb_partitions = wm->lb_size / wm->src_width;
702 u32 line_time = wm->active_time + wm->blank_time;
703 u32 latency_tolerant_lines;
704 u32 latency_hiding;
705 fixed20_12 a;
706
707 a.full = dfixed_const(1);
708 if (wm->vsc.full > a.full)
709 latency_tolerant_lines = 1;
710 else {
711 if (lb_partitions <= (wm->vtaps + 1))
712 latency_tolerant_lines = 1;
713 else
714 latency_tolerant_lines = 2;
715 }
716
717 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
718
719 if (evergreen_latency_watermark(wm) <= latency_hiding)
720 return true;
721 else
722 return false;
723 }
724
725 static void evergreen_program_watermarks(struct radeon_device *rdev,
726 struct radeon_crtc *radeon_crtc,
727 u32 lb_size, u32 num_heads)
728 {
729 struct drm_display_mode *mode = &radeon_crtc->base.mode;
730 struct evergreen_wm_params wm;
731 u32 pixel_period;
732 u32 line_time = 0;
733 u32 latency_watermark_a = 0, latency_watermark_b = 0;
734 u32 priority_a_mark = 0, priority_b_mark = 0;
735 u32 priority_a_cnt = PRIORITY_OFF;
736 u32 priority_b_cnt = PRIORITY_OFF;
737 u32 pipe_offset = radeon_crtc->crtc_id * 16;
738 u32 tmp, arb_control3;
739 fixed20_12 a, b, c;
740
741 if (radeon_crtc->base.enabled && num_heads && mode) {
742 pixel_period = 1000000 / (u32)mode->clock;
743 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
744 priority_a_cnt = 0;
745 priority_b_cnt = 0;
746
747 wm.yclk = rdev->pm.current_mclk * 10;
748 wm.sclk = rdev->pm.current_sclk * 10;
749 wm.disp_clk = mode->clock;
750 wm.src_width = mode->crtc_hdisplay;
751 wm.active_time = mode->crtc_hdisplay * pixel_period;
752 wm.blank_time = line_time - wm.active_time;
753 wm.interlaced = false;
754 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
755 wm.interlaced = true;
756 wm.vsc = radeon_crtc->vsc;
757 wm.vtaps = 1;
758 if (radeon_crtc->rmx_type != RMX_OFF)
759 wm.vtaps = 2;
760 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
761 wm.lb_size = lb_size;
762 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
763 wm.num_heads = num_heads;
764
765 /* set for high clocks */
766 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
767 /* set for low clocks */
768 /* wm.yclk = low clk; wm.sclk = low clk */
769 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
770
771 /* possibly force display priority to high */
772 /* should really do this at mode validation time... */
773 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
774 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
775 !evergreen_check_latency_hiding(&wm) ||
776 (rdev->disp_priority == 2)) {
777 DRM_DEBUG_KMS("force priority to high\n");
778 priority_a_cnt |= PRIORITY_ALWAYS_ON;
779 priority_b_cnt |= PRIORITY_ALWAYS_ON;
780 }
781
782 a.full = dfixed_const(1000);
783 b.full = dfixed_const(mode->clock);
784 b.full = dfixed_div(b, a);
785 c.full = dfixed_const(latency_watermark_a);
786 c.full = dfixed_mul(c, b);
787 c.full = dfixed_mul(c, radeon_crtc->hsc);
788 c.full = dfixed_div(c, a);
789 a.full = dfixed_const(16);
790 c.full = dfixed_div(c, a);
791 priority_a_mark = dfixed_trunc(c);
792 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
793
794 a.full = dfixed_const(1000);
795 b.full = dfixed_const(mode->clock);
796 b.full = dfixed_div(b, a);
797 c.full = dfixed_const(latency_watermark_b);
798 c.full = dfixed_mul(c, b);
799 c.full = dfixed_mul(c, radeon_crtc->hsc);
800 c.full = dfixed_div(c, a);
801 a.full = dfixed_const(16);
802 c.full = dfixed_div(c, a);
803 priority_b_mark = dfixed_trunc(c);
804 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
805 }
806
807 /* select wm A */
808 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
809 tmp = arb_control3;
810 tmp &= ~LATENCY_WATERMARK_MASK(3);
811 tmp |= LATENCY_WATERMARK_MASK(1);
812 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
813 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
814 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
815 LATENCY_HIGH_WATERMARK(line_time)));
816 /* select wm B */
817 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
818 tmp &= ~LATENCY_WATERMARK_MASK(3);
819 tmp |= LATENCY_WATERMARK_MASK(2);
820 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
821 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
822 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
823 LATENCY_HIGH_WATERMARK(line_time)));
824 /* restore original selection */
825 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
826
827 /* write the priority marks */
828 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
829 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
830
831 }
832
833 void evergreen_bandwidth_update(struct radeon_device *rdev)
834 {
835 struct drm_display_mode *mode0 = NULL;
836 struct drm_display_mode *mode1 = NULL;
837 u32 num_heads = 0, lb_size;
838 int i;
839
840 radeon_update_display_priority(rdev);
841
842 for (i = 0; i < rdev->num_crtc; i++) {
843 if (rdev->mode_info.crtcs[i]->base.enabled)
844 num_heads++;
845 }
846 for (i = 0; i < rdev->num_crtc; i += 2) {
847 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
848 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
849 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
850 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
851 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
852 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
853 }
854 }
855
856 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
857 {
858 unsigned i;
859 u32 tmp;
860
861 for (i = 0; i < rdev->usec_timeout; i++) {
862 /* read MC_STATUS */
863 tmp = RREG32(SRBM_STATUS) & 0x1F00;
864 if (!tmp)
865 return 0;
866 udelay(1);
867 }
868 return -1;
869 }
870
871 /*
872 * GART
873 */
874 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
875 {
876 unsigned i;
877 u32 tmp;
878
879 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
880
881 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
882 for (i = 0; i < rdev->usec_timeout; i++) {
883 /* read MC_STATUS */
884 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
885 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
886 if (tmp == 2) {
887 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
888 return;
889 }
890 if (tmp) {
891 return;
892 }
893 udelay(1);
894 }
895 }
896
897 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
898 {
899 u32 tmp;
900 int r;
901
902 if (rdev->gart.table.vram.robj == NULL) {
903 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
904 return -EINVAL;
905 }
906 r = radeon_gart_table_vram_pin(rdev);
907 if (r)
908 return r;
909 radeon_gart_restore(rdev);
910 /* Setup L2 cache */
911 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
912 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
913 EFFECTIVE_L2_QUEUE_SIZE(7));
914 WREG32(VM_L2_CNTL2, 0);
915 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
916 /* Setup TLB control */
917 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
918 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
919 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
920 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
921 if (rdev->flags & RADEON_IS_IGP) {
922 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
923 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
924 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
925 } else {
926 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
927 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
928 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
929 }
930 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
931 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
932 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
933 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
934 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
935 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
936 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
937 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
938 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
939 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
940 (u32)(rdev->dummy_page.addr >> 12));
941 WREG32(VM_CONTEXT1_CNTL, 0);
942
943 evergreen_pcie_gart_tlb_flush(rdev);
944 rdev->gart.ready = true;
945 return 0;
946 }
947
948 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
949 {
950 u32 tmp;
951 int r;
952
953 /* Disable all tables */
954 WREG32(VM_CONTEXT0_CNTL, 0);
955 WREG32(VM_CONTEXT1_CNTL, 0);
956
957 /* Setup L2 cache */
958 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
959 EFFECTIVE_L2_QUEUE_SIZE(7));
960 WREG32(VM_L2_CNTL2, 0);
961 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
962 /* Setup TLB control */
963 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
964 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
965 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
966 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
967 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
968 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
969 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
970 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
971 if (rdev->gart.table.vram.robj) {
972 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
973 if (likely(r == 0)) {
974 radeon_bo_kunmap(rdev->gart.table.vram.robj);
975 radeon_bo_unpin(rdev->gart.table.vram.robj);
976 radeon_bo_unreserve(rdev->gart.table.vram.robj);
977 }
978 }
979 }
980
981 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
982 {
983 evergreen_pcie_gart_disable(rdev);
984 radeon_gart_table_vram_free(rdev);
985 radeon_gart_fini(rdev);
986 }
987
988
989 void evergreen_agp_enable(struct radeon_device *rdev)
990 {
991 u32 tmp;
992
993 /* Setup L2 cache */
994 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
995 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
996 EFFECTIVE_L2_QUEUE_SIZE(7));
997 WREG32(VM_L2_CNTL2, 0);
998 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
999 /* Setup TLB control */
1000 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1001 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1002 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1003 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1004 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1005 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1006 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1007 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1008 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1009 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1010 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1011 WREG32(VM_CONTEXT0_CNTL, 0);
1012 WREG32(VM_CONTEXT1_CNTL, 0);
1013 }
1014
1015 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1016 {
1017 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1018 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1019 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1020 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1021 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1022 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1023 if (rdev->num_crtc >= 4) {
1024 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1025 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1026 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1027 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1028 }
1029 if (rdev->num_crtc >= 6) {
1030 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1031 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1032 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1033 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1034 }
1035
1036 /* Stop all video */
1037 WREG32(VGA_RENDER_CONTROL, 0);
1038 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1039 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1040 if (rdev->num_crtc >= 4) {
1041 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1042 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1043 }
1044 if (rdev->num_crtc >= 6) {
1045 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1046 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1047 }
1048 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1049 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1050 if (rdev->num_crtc >= 4) {
1051 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1052 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1053 }
1054 if (rdev->num_crtc >= 6) {
1055 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1056 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1057 }
1058 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1059 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1060 if (rdev->num_crtc >= 4) {
1061 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1062 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1063 }
1064 if (rdev->num_crtc >= 6) {
1065 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1066 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1067 }
1068
1069 WREG32(D1VGA_CONTROL, 0);
1070 WREG32(D2VGA_CONTROL, 0);
1071 if (rdev->num_crtc >= 4) {
1072 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1073 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1074 }
1075 if (rdev->num_crtc >= 6) {
1076 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1077 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1078 }
1079 }
1080
1081 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1082 {
1083 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1084 upper_32_bits(rdev->mc.vram_start));
1085 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1086 upper_32_bits(rdev->mc.vram_start));
1087 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1088 (u32)rdev->mc.vram_start);
1089 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1090 (u32)rdev->mc.vram_start);
1091
1092 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1093 upper_32_bits(rdev->mc.vram_start));
1094 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1095 upper_32_bits(rdev->mc.vram_start));
1096 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1097 (u32)rdev->mc.vram_start);
1098 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1099 (u32)rdev->mc.vram_start);
1100
1101 if (rdev->num_crtc >= 4) {
1102 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1103 upper_32_bits(rdev->mc.vram_start));
1104 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1105 upper_32_bits(rdev->mc.vram_start));
1106 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1107 (u32)rdev->mc.vram_start);
1108 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1109 (u32)rdev->mc.vram_start);
1110
1111 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1112 upper_32_bits(rdev->mc.vram_start));
1113 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1114 upper_32_bits(rdev->mc.vram_start));
1115 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1116 (u32)rdev->mc.vram_start);
1117 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1118 (u32)rdev->mc.vram_start);
1119 }
1120 if (rdev->num_crtc >= 6) {
1121 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1122 upper_32_bits(rdev->mc.vram_start));
1123 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1124 upper_32_bits(rdev->mc.vram_start));
1125 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1126 (u32)rdev->mc.vram_start);
1127 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1128 (u32)rdev->mc.vram_start);
1129
1130 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1131 upper_32_bits(rdev->mc.vram_start));
1132 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1133 upper_32_bits(rdev->mc.vram_start));
1134 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1135 (u32)rdev->mc.vram_start);
1136 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1137 (u32)rdev->mc.vram_start);
1138 }
1139
1140 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1141 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1142 /* Unlock host access */
1143 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1144 mdelay(1);
1145 /* Restore video state */
1146 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1147 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1148 if (rdev->num_crtc >= 4) {
1149 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1150 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1151 }
1152 if (rdev->num_crtc >= 6) {
1153 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1154 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1155 }
1156 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1158 if (rdev->num_crtc >= 4) {
1159 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1160 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1161 }
1162 if (rdev->num_crtc >= 6) {
1163 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1164 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1165 }
1166 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1167 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1168 if (rdev->num_crtc >= 4) {
1169 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1170 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1171 }
1172 if (rdev->num_crtc >= 6) {
1173 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1174 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1175 }
1176 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1177 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1178 if (rdev->num_crtc >= 4) {
1179 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1180 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1181 }
1182 if (rdev->num_crtc >= 6) {
1183 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1184 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1185 }
1186 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1187 }
1188
1189 void evergreen_mc_program(struct radeon_device *rdev)
1190 {
1191 struct evergreen_mc_save save;
1192 u32 tmp;
1193 int i, j;
1194
1195 /* Initialize HDP */
1196 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1197 WREG32((0x2c14 + j), 0x00000000);
1198 WREG32((0x2c18 + j), 0x00000000);
1199 WREG32((0x2c1c + j), 0x00000000);
1200 WREG32((0x2c20 + j), 0x00000000);
1201 WREG32((0x2c24 + j), 0x00000000);
1202 }
1203 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1204
1205 evergreen_mc_stop(rdev, &save);
1206 if (evergreen_mc_wait_for_idle(rdev)) {
1207 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1208 }
1209 /* Lockout access through VGA aperture*/
1210 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1211 /* Update configuration */
1212 if (rdev->flags & RADEON_IS_AGP) {
1213 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1214 /* VRAM before AGP */
1215 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1216 rdev->mc.vram_start >> 12);
1217 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1218 rdev->mc.gtt_end >> 12);
1219 } else {
1220 /* VRAM after AGP */
1221 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1222 rdev->mc.gtt_start >> 12);
1223 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1224 rdev->mc.vram_end >> 12);
1225 }
1226 } else {
1227 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1228 rdev->mc.vram_start >> 12);
1229 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1230 rdev->mc.vram_end >> 12);
1231 }
1232 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1233 if (rdev->flags & RADEON_IS_IGP) {
1234 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1235 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1236 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1237 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1238 }
1239 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1240 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1241 WREG32(MC_VM_FB_LOCATION, tmp);
1242 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1243 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1244 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1245 if (rdev->flags & RADEON_IS_AGP) {
1246 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1247 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1248 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1249 } else {
1250 WREG32(MC_VM_AGP_BASE, 0);
1251 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1252 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1253 }
1254 if (evergreen_mc_wait_for_idle(rdev)) {
1255 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1256 }
1257 evergreen_mc_resume(rdev, &save);
1258 /* we need to own VRAM, so turn off the VGA renderer here
1259 * to stop it overwriting our objects */
1260 rv515_vga_render_disable(rdev);
1261 }
1262
1263 /*
1264 * CP.
1265 */
1266 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1267 {
1268 /* set to DX10/11 mode */
1269 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1270 radeon_ring_write(rdev, 1);
1271 /* FIXME: implement */
1272 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1273 radeon_ring_write(rdev,
1274 #ifdef __BIG_ENDIAN
1275 (2 << 0) |
1276 #endif
1277 (ib->gpu_addr & 0xFFFFFFFC));
1278 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1279 radeon_ring_write(rdev, ib->length_dw);
1280 }
1281
1282
1283 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1284 {
1285 const __be32 *fw_data;
1286 int i;
1287
1288 if (!rdev->me_fw || !rdev->pfp_fw)
1289 return -EINVAL;
1290
1291 r700_cp_stop(rdev);
1292 WREG32(CP_RB_CNTL,
1293 #ifdef __BIG_ENDIAN
1294 BUF_SWAP_32BIT |
1295 #endif
1296 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1297
1298 fw_data = (const __be32 *)rdev->pfp_fw->data;
1299 WREG32(CP_PFP_UCODE_ADDR, 0);
1300 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1301 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1302 WREG32(CP_PFP_UCODE_ADDR, 0);
1303
1304 fw_data = (const __be32 *)rdev->me_fw->data;
1305 WREG32(CP_ME_RAM_WADDR, 0);
1306 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1307 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1308
1309 WREG32(CP_PFP_UCODE_ADDR, 0);
1310 WREG32(CP_ME_RAM_WADDR, 0);
1311 WREG32(CP_ME_RAM_RADDR, 0);
1312 return 0;
1313 }
1314
1315 static int evergreen_cp_start(struct radeon_device *rdev)
1316 {
1317 int r, i;
1318 uint32_t cp_me;
1319
1320 r = radeon_ring_lock(rdev, 7);
1321 if (r) {
1322 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1323 return r;
1324 }
1325 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1326 radeon_ring_write(rdev, 0x1);
1327 radeon_ring_write(rdev, 0x0);
1328 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1329 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1330 radeon_ring_write(rdev, 0);
1331 radeon_ring_write(rdev, 0);
1332 radeon_ring_unlock_commit(rdev);
1333
1334 cp_me = 0xff;
1335 WREG32(CP_ME_CNTL, cp_me);
1336
1337 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1338 if (r) {
1339 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1340 return r;
1341 }
1342
1343 /* setup clear context state */
1344 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1345 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1346
1347 for (i = 0; i < evergreen_default_size; i++)
1348 radeon_ring_write(rdev, evergreen_default_state[i]);
1349
1350 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1351 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1352
1353 /* set clear context state */
1354 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1355 radeon_ring_write(rdev, 0);
1356
1357 /* SQ_VTX_BASE_VTX_LOC */
1358 radeon_ring_write(rdev, 0xc0026f00);
1359 radeon_ring_write(rdev, 0x00000000);
1360 radeon_ring_write(rdev, 0x00000000);
1361 radeon_ring_write(rdev, 0x00000000);
1362
1363 /* Clear consts */
1364 radeon_ring_write(rdev, 0xc0036f00);
1365 radeon_ring_write(rdev, 0x00000bc4);
1366 radeon_ring_write(rdev, 0xffffffff);
1367 radeon_ring_write(rdev, 0xffffffff);
1368 radeon_ring_write(rdev, 0xffffffff);
1369
1370 radeon_ring_write(rdev, 0xc0026900);
1371 radeon_ring_write(rdev, 0x00000316);
1372 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1373 radeon_ring_write(rdev, 0x00000010); /* */
1374
1375 radeon_ring_unlock_commit(rdev);
1376
1377 return 0;
1378 }
1379
1380 int evergreen_cp_resume(struct radeon_device *rdev)
1381 {
1382 u32 tmp;
1383 u32 rb_bufsz;
1384 int r;
1385
1386 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1387 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1388 SOFT_RESET_PA |
1389 SOFT_RESET_SH |
1390 SOFT_RESET_VGT |
1391 SOFT_RESET_SPI |
1392 SOFT_RESET_SX));
1393 RREG32(GRBM_SOFT_RESET);
1394 mdelay(15);
1395 WREG32(GRBM_SOFT_RESET, 0);
1396 RREG32(GRBM_SOFT_RESET);
1397
1398 /* Set ring buffer size */
1399 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1400 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1401 #ifdef __BIG_ENDIAN
1402 tmp |= BUF_SWAP_32BIT;
1403 #endif
1404 WREG32(CP_RB_CNTL, tmp);
1405 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1406
1407 /* Set the write pointer delay */
1408 WREG32(CP_RB_WPTR_DELAY, 0);
1409
1410 /* Initialize the ring buffer's read and write pointers */
1411 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1412 WREG32(CP_RB_RPTR_WR, 0);
1413 rdev->cp.wptr = 0;
1414 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1415
1416 /* set the wb address wether it's enabled or not */
1417 WREG32(CP_RB_RPTR_ADDR,
1418 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1419 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1420 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1421
1422 if (rdev->wb.enabled)
1423 WREG32(SCRATCH_UMSK, 0xff);
1424 else {
1425 tmp |= RB_NO_UPDATE;
1426 WREG32(SCRATCH_UMSK, 0);
1427 }
1428
1429 mdelay(1);
1430 WREG32(CP_RB_CNTL, tmp);
1431
1432 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1433 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1434
1435 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1436
1437 evergreen_cp_start(rdev);
1438 rdev->cp.ready = true;
1439 r = radeon_ring_test(rdev);
1440 if (r) {
1441 rdev->cp.ready = false;
1442 return r;
1443 }
1444 return 0;
1445 }
1446
1447 /*
1448 * Core functions
1449 */
1450 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1451 u32 num_tile_pipes,
1452 u32 num_backends,
1453 u32 backend_disable_mask)
1454 {
1455 u32 backend_map = 0;
1456 u32 enabled_backends_mask = 0;
1457 u32 enabled_backends_count = 0;
1458 u32 cur_pipe;
1459 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1460 u32 cur_backend = 0;
1461 u32 i;
1462 bool force_no_swizzle;
1463
1464 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1465 num_tile_pipes = EVERGREEN_MAX_PIPES;
1466 if (num_tile_pipes < 1)
1467 num_tile_pipes = 1;
1468 if (num_backends > EVERGREEN_MAX_BACKENDS)
1469 num_backends = EVERGREEN_MAX_BACKENDS;
1470 if (num_backends < 1)
1471 num_backends = 1;
1472
1473 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1474 if (((backend_disable_mask >> i) & 1) == 0) {
1475 enabled_backends_mask |= (1 << i);
1476 ++enabled_backends_count;
1477 }
1478 if (enabled_backends_count == num_backends)
1479 break;
1480 }
1481
1482 if (enabled_backends_count == 0) {
1483 enabled_backends_mask = 1;
1484 enabled_backends_count = 1;
1485 }
1486
1487 if (enabled_backends_count != num_backends)
1488 num_backends = enabled_backends_count;
1489
1490 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1491 switch (rdev->family) {
1492 case CHIP_CEDAR:
1493 case CHIP_REDWOOD:
1494 case CHIP_PALM:
1495 case CHIP_SUMO:
1496 case CHIP_SUMO2:
1497 case CHIP_TURKS:
1498 case CHIP_CAICOS:
1499 force_no_swizzle = false;
1500 break;
1501 case CHIP_CYPRESS:
1502 case CHIP_HEMLOCK:
1503 case CHIP_JUNIPER:
1504 case CHIP_BARTS:
1505 default:
1506 force_no_swizzle = true;
1507 break;
1508 }
1509 if (force_no_swizzle) {
1510 bool last_backend_enabled = false;
1511
1512 force_no_swizzle = false;
1513 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1514 if (((enabled_backends_mask >> i) & 1) == 1) {
1515 if (last_backend_enabled)
1516 force_no_swizzle = true;
1517 last_backend_enabled = true;
1518 } else
1519 last_backend_enabled = false;
1520 }
1521 }
1522
1523 switch (num_tile_pipes) {
1524 case 1:
1525 case 3:
1526 case 5:
1527 case 7:
1528 DRM_ERROR("odd number of pipes!\n");
1529 break;
1530 case 2:
1531 swizzle_pipe[0] = 0;
1532 swizzle_pipe[1] = 1;
1533 break;
1534 case 4:
1535 if (force_no_swizzle) {
1536 swizzle_pipe[0] = 0;
1537 swizzle_pipe[1] = 1;
1538 swizzle_pipe[2] = 2;
1539 swizzle_pipe[3] = 3;
1540 } else {
1541 swizzle_pipe[0] = 0;
1542 swizzle_pipe[1] = 2;
1543 swizzle_pipe[2] = 1;
1544 swizzle_pipe[3] = 3;
1545 }
1546 break;
1547 case 6:
1548 if (force_no_swizzle) {
1549 swizzle_pipe[0] = 0;
1550 swizzle_pipe[1] = 1;
1551 swizzle_pipe[2] = 2;
1552 swizzle_pipe[3] = 3;
1553 swizzle_pipe[4] = 4;
1554 swizzle_pipe[5] = 5;
1555 } else {
1556 swizzle_pipe[0] = 0;
1557 swizzle_pipe[1] = 2;
1558 swizzle_pipe[2] = 4;
1559 swizzle_pipe[3] = 1;
1560 swizzle_pipe[4] = 3;
1561 swizzle_pipe[5] = 5;
1562 }
1563 break;
1564 case 8:
1565 if (force_no_swizzle) {
1566 swizzle_pipe[0] = 0;
1567 swizzle_pipe[1] = 1;
1568 swizzle_pipe[2] = 2;
1569 swizzle_pipe[3] = 3;
1570 swizzle_pipe[4] = 4;
1571 swizzle_pipe[5] = 5;
1572 swizzle_pipe[6] = 6;
1573 swizzle_pipe[7] = 7;
1574 } else {
1575 swizzle_pipe[0] = 0;
1576 swizzle_pipe[1] = 2;
1577 swizzle_pipe[2] = 4;
1578 swizzle_pipe[3] = 6;
1579 swizzle_pipe[4] = 1;
1580 swizzle_pipe[5] = 3;
1581 swizzle_pipe[6] = 5;
1582 swizzle_pipe[7] = 7;
1583 }
1584 break;
1585 }
1586
1587 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1588 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1589 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1590
1591 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1592
1593 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1594 }
1595
1596 return backend_map;
1597 }
1598
1599 static void evergreen_gpu_init(struct radeon_device *rdev)
1600 {
1601 u32 cc_rb_backend_disable = 0;
1602 u32 cc_gc_shader_pipe_config;
1603 u32 gb_addr_config = 0;
1604 u32 mc_shared_chmap, mc_arb_ramcfg;
1605 u32 gb_backend_map;
1606 u32 grbm_gfx_index;
1607 u32 sx_debug_1;
1608 u32 smx_dc_ctl0;
1609 u32 sq_config;
1610 u32 sq_lds_resource_mgmt;
1611 u32 sq_gpr_resource_mgmt_1;
1612 u32 sq_gpr_resource_mgmt_2;
1613 u32 sq_gpr_resource_mgmt_3;
1614 u32 sq_thread_resource_mgmt;
1615 u32 sq_thread_resource_mgmt_2;
1616 u32 sq_stack_resource_mgmt_1;
1617 u32 sq_stack_resource_mgmt_2;
1618 u32 sq_stack_resource_mgmt_3;
1619 u32 vgt_cache_invalidation;
1620 u32 hdp_host_path_cntl, tmp;
1621 int i, j, num_shader_engines, ps_thread_count;
1622
1623 switch (rdev->family) {
1624 case CHIP_CYPRESS:
1625 case CHIP_HEMLOCK:
1626 rdev->config.evergreen.num_ses = 2;
1627 rdev->config.evergreen.max_pipes = 4;
1628 rdev->config.evergreen.max_tile_pipes = 8;
1629 rdev->config.evergreen.max_simds = 10;
1630 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1631 rdev->config.evergreen.max_gprs = 256;
1632 rdev->config.evergreen.max_threads = 248;
1633 rdev->config.evergreen.max_gs_threads = 32;
1634 rdev->config.evergreen.max_stack_entries = 512;
1635 rdev->config.evergreen.sx_num_of_sets = 4;
1636 rdev->config.evergreen.sx_max_export_size = 256;
1637 rdev->config.evergreen.sx_max_export_pos_size = 64;
1638 rdev->config.evergreen.sx_max_export_smx_size = 192;
1639 rdev->config.evergreen.max_hw_contexts = 8;
1640 rdev->config.evergreen.sq_num_cf_insts = 2;
1641
1642 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1643 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1644 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1645 break;
1646 case CHIP_JUNIPER:
1647 rdev->config.evergreen.num_ses = 1;
1648 rdev->config.evergreen.max_pipes = 4;
1649 rdev->config.evergreen.max_tile_pipes = 4;
1650 rdev->config.evergreen.max_simds = 10;
1651 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1652 rdev->config.evergreen.max_gprs = 256;
1653 rdev->config.evergreen.max_threads = 248;
1654 rdev->config.evergreen.max_gs_threads = 32;
1655 rdev->config.evergreen.max_stack_entries = 512;
1656 rdev->config.evergreen.sx_num_of_sets = 4;
1657 rdev->config.evergreen.sx_max_export_size = 256;
1658 rdev->config.evergreen.sx_max_export_pos_size = 64;
1659 rdev->config.evergreen.sx_max_export_smx_size = 192;
1660 rdev->config.evergreen.max_hw_contexts = 8;
1661 rdev->config.evergreen.sq_num_cf_insts = 2;
1662
1663 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1664 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1665 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1666 break;
1667 case CHIP_REDWOOD:
1668 rdev->config.evergreen.num_ses = 1;
1669 rdev->config.evergreen.max_pipes = 4;
1670 rdev->config.evergreen.max_tile_pipes = 4;
1671 rdev->config.evergreen.max_simds = 5;
1672 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1673 rdev->config.evergreen.max_gprs = 256;
1674 rdev->config.evergreen.max_threads = 248;
1675 rdev->config.evergreen.max_gs_threads = 32;
1676 rdev->config.evergreen.max_stack_entries = 256;
1677 rdev->config.evergreen.sx_num_of_sets = 4;
1678 rdev->config.evergreen.sx_max_export_size = 256;
1679 rdev->config.evergreen.sx_max_export_pos_size = 64;
1680 rdev->config.evergreen.sx_max_export_smx_size = 192;
1681 rdev->config.evergreen.max_hw_contexts = 8;
1682 rdev->config.evergreen.sq_num_cf_insts = 2;
1683
1684 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1685 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1686 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1687 break;
1688 case CHIP_CEDAR:
1689 default:
1690 rdev->config.evergreen.num_ses = 1;
1691 rdev->config.evergreen.max_pipes = 2;
1692 rdev->config.evergreen.max_tile_pipes = 2;
1693 rdev->config.evergreen.max_simds = 2;
1694 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1695 rdev->config.evergreen.max_gprs = 256;
1696 rdev->config.evergreen.max_threads = 192;
1697 rdev->config.evergreen.max_gs_threads = 16;
1698 rdev->config.evergreen.max_stack_entries = 256;
1699 rdev->config.evergreen.sx_num_of_sets = 4;
1700 rdev->config.evergreen.sx_max_export_size = 128;
1701 rdev->config.evergreen.sx_max_export_pos_size = 32;
1702 rdev->config.evergreen.sx_max_export_smx_size = 96;
1703 rdev->config.evergreen.max_hw_contexts = 4;
1704 rdev->config.evergreen.sq_num_cf_insts = 1;
1705
1706 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1707 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1708 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1709 break;
1710 case CHIP_PALM:
1711 rdev->config.evergreen.num_ses = 1;
1712 rdev->config.evergreen.max_pipes = 2;
1713 rdev->config.evergreen.max_tile_pipes = 2;
1714 rdev->config.evergreen.max_simds = 2;
1715 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1716 rdev->config.evergreen.max_gprs = 256;
1717 rdev->config.evergreen.max_threads = 192;
1718 rdev->config.evergreen.max_gs_threads = 16;
1719 rdev->config.evergreen.max_stack_entries = 256;
1720 rdev->config.evergreen.sx_num_of_sets = 4;
1721 rdev->config.evergreen.sx_max_export_size = 128;
1722 rdev->config.evergreen.sx_max_export_pos_size = 32;
1723 rdev->config.evergreen.sx_max_export_smx_size = 96;
1724 rdev->config.evergreen.max_hw_contexts = 4;
1725 rdev->config.evergreen.sq_num_cf_insts = 1;
1726
1727 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1728 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1729 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1730 break;
1731 case CHIP_SUMO:
1732 rdev->config.evergreen.num_ses = 1;
1733 rdev->config.evergreen.max_pipes = 4;
1734 rdev->config.evergreen.max_tile_pipes = 2;
1735 if (rdev->pdev->device == 0x9648)
1736 rdev->config.evergreen.max_simds = 3;
1737 else if ((rdev->pdev->device == 0x9647) ||
1738 (rdev->pdev->device == 0x964a))
1739 rdev->config.evergreen.max_simds = 4;
1740 else
1741 rdev->config.evergreen.max_simds = 5;
1742 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1743 rdev->config.evergreen.max_gprs = 256;
1744 rdev->config.evergreen.max_threads = 248;
1745 rdev->config.evergreen.max_gs_threads = 32;
1746 rdev->config.evergreen.max_stack_entries = 256;
1747 rdev->config.evergreen.sx_num_of_sets = 4;
1748 rdev->config.evergreen.sx_max_export_size = 256;
1749 rdev->config.evergreen.sx_max_export_pos_size = 64;
1750 rdev->config.evergreen.sx_max_export_smx_size = 192;
1751 rdev->config.evergreen.max_hw_contexts = 8;
1752 rdev->config.evergreen.sq_num_cf_insts = 2;
1753
1754 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1755 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1756 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1757 break;
1758 case CHIP_SUMO2:
1759 rdev->config.evergreen.num_ses = 1;
1760 rdev->config.evergreen.max_pipes = 4;
1761 rdev->config.evergreen.max_tile_pipes = 4;
1762 rdev->config.evergreen.max_simds = 2;
1763 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1764 rdev->config.evergreen.max_gprs = 256;
1765 rdev->config.evergreen.max_threads = 248;
1766 rdev->config.evergreen.max_gs_threads = 32;
1767 rdev->config.evergreen.max_stack_entries = 512;
1768 rdev->config.evergreen.sx_num_of_sets = 4;
1769 rdev->config.evergreen.sx_max_export_size = 256;
1770 rdev->config.evergreen.sx_max_export_pos_size = 64;
1771 rdev->config.evergreen.sx_max_export_smx_size = 192;
1772 rdev->config.evergreen.max_hw_contexts = 8;
1773 rdev->config.evergreen.sq_num_cf_insts = 2;
1774
1775 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1776 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1777 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1778 break;
1779 case CHIP_BARTS:
1780 rdev->config.evergreen.num_ses = 2;
1781 rdev->config.evergreen.max_pipes = 4;
1782 rdev->config.evergreen.max_tile_pipes = 8;
1783 rdev->config.evergreen.max_simds = 7;
1784 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1785 rdev->config.evergreen.max_gprs = 256;
1786 rdev->config.evergreen.max_threads = 248;
1787 rdev->config.evergreen.max_gs_threads = 32;
1788 rdev->config.evergreen.max_stack_entries = 512;
1789 rdev->config.evergreen.sx_num_of_sets = 4;
1790 rdev->config.evergreen.sx_max_export_size = 256;
1791 rdev->config.evergreen.sx_max_export_pos_size = 64;
1792 rdev->config.evergreen.sx_max_export_smx_size = 192;
1793 rdev->config.evergreen.max_hw_contexts = 8;
1794 rdev->config.evergreen.sq_num_cf_insts = 2;
1795
1796 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1797 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1798 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1799 break;
1800 case CHIP_TURKS:
1801 rdev->config.evergreen.num_ses = 1;
1802 rdev->config.evergreen.max_pipes = 4;
1803 rdev->config.evergreen.max_tile_pipes = 4;
1804 rdev->config.evergreen.max_simds = 6;
1805 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1806 rdev->config.evergreen.max_gprs = 256;
1807 rdev->config.evergreen.max_threads = 248;
1808 rdev->config.evergreen.max_gs_threads = 32;
1809 rdev->config.evergreen.max_stack_entries = 256;
1810 rdev->config.evergreen.sx_num_of_sets = 4;
1811 rdev->config.evergreen.sx_max_export_size = 256;
1812 rdev->config.evergreen.sx_max_export_pos_size = 64;
1813 rdev->config.evergreen.sx_max_export_smx_size = 192;
1814 rdev->config.evergreen.max_hw_contexts = 8;
1815 rdev->config.evergreen.sq_num_cf_insts = 2;
1816
1817 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1818 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1819 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1820 break;
1821 case CHIP_CAICOS:
1822 rdev->config.evergreen.num_ses = 1;
1823 rdev->config.evergreen.max_pipes = 4;
1824 rdev->config.evergreen.max_tile_pipes = 2;
1825 rdev->config.evergreen.max_simds = 2;
1826 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1827 rdev->config.evergreen.max_gprs = 256;
1828 rdev->config.evergreen.max_threads = 192;
1829 rdev->config.evergreen.max_gs_threads = 16;
1830 rdev->config.evergreen.max_stack_entries = 256;
1831 rdev->config.evergreen.sx_num_of_sets = 4;
1832 rdev->config.evergreen.sx_max_export_size = 128;
1833 rdev->config.evergreen.sx_max_export_pos_size = 32;
1834 rdev->config.evergreen.sx_max_export_smx_size = 96;
1835 rdev->config.evergreen.max_hw_contexts = 4;
1836 rdev->config.evergreen.sq_num_cf_insts = 1;
1837
1838 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1839 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1840 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1841 break;
1842 }
1843
1844 /* Initialize HDP */
1845 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1846 WREG32((0x2c14 + j), 0x00000000);
1847 WREG32((0x2c18 + j), 0x00000000);
1848 WREG32((0x2c1c + j), 0x00000000);
1849 WREG32((0x2c20 + j), 0x00000000);
1850 WREG32((0x2c24 + j), 0x00000000);
1851 }
1852
1853 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1854
1855 evergreen_fix_pci_max_read_req_size(rdev);
1856
1857 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1858
1859 cc_gc_shader_pipe_config |=
1860 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1861 & EVERGREEN_MAX_PIPES_MASK);
1862 cc_gc_shader_pipe_config |=
1863 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1864 & EVERGREEN_MAX_SIMDS_MASK);
1865
1866 cc_rb_backend_disable =
1867 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1868 & EVERGREEN_MAX_BACKENDS_MASK);
1869
1870
1871 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1872 if (rdev->flags & RADEON_IS_IGP)
1873 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1874 else
1875 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1876
1877 switch (rdev->config.evergreen.max_tile_pipes) {
1878 case 1:
1879 default:
1880 gb_addr_config |= NUM_PIPES(0);
1881 break;
1882 case 2:
1883 gb_addr_config |= NUM_PIPES(1);
1884 break;
1885 case 4:
1886 gb_addr_config |= NUM_PIPES(2);
1887 break;
1888 case 8:
1889 gb_addr_config |= NUM_PIPES(3);
1890 break;
1891 }
1892
1893 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1894 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1895 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1896 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1897 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1898 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1899
1900 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1901 gb_addr_config |= ROW_SIZE(2);
1902 else
1903 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1904
1905 if (rdev->ddev->pdev->device == 0x689e) {
1906 u32 efuse_straps_4;
1907 u32 efuse_straps_3;
1908 u8 efuse_box_bit_131_124;
1909
1910 WREG32(RCU_IND_INDEX, 0x204);
1911 efuse_straps_4 = RREG32(RCU_IND_DATA);
1912 WREG32(RCU_IND_INDEX, 0x203);
1913 efuse_straps_3 = RREG32(RCU_IND_DATA);
1914 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1915
1916 switch(efuse_box_bit_131_124) {
1917 case 0x00:
1918 gb_backend_map = 0x76543210;
1919 break;
1920 case 0x55:
1921 gb_backend_map = 0x77553311;
1922 break;
1923 case 0x56:
1924 gb_backend_map = 0x77553300;
1925 break;
1926 case 0x59:
1927 gb_backend_map = 0x77552211;
1928 break;
1929 case 0x66:
1930 gb_backend_map = 0x77443300;
1931 break;
1932 case 0x99:
1933 gb_backend_map = 0x66552211;
1934 break;
1935 case 0x5a:
1936 gb_backend_map = 0x77552200;
1937 break;
1938 case 0xaa:
1939 gb_backend_map = 0x66442200;
1940 break;
1941 case 0x95:
1942 gb_backend_map = 0x66553311;
1943 break;
1944 default:
1945 DRM_ERROR("bad backend map, using default\n");
1946 gb_backend_map =
1947 evergreen_get_tile_pipe_to_backend_map(rdev,
1948 rdev->config.evergreen.max_tile_pipes,
1949 rdev->config.evergreen.max_backends,
1950 ((EVERGREEN_MAX_BACKENDS_MASK <<
1951 rdev->config.evergreen.max_backends) &
1952 EVERGREEN_MAX_BACKENDS_MASK));
1953 break;
1954 }
1955 } else if (rdev->ddev->pdev->device == 0x68b9) {
1956 u32 efuse_straps_3;
1957 u8 efuse_box_bit_127_124;
1958
1959 WREG32(RCU_IND_INDEX, 0x203);
1960 efuse_straps_3 = RREG32(RCU_IND_DATA);
1961 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1962
1963 switch(efuse_box_bit_127_124) {
1964 case 0x0:
1965 gb_backend_map = 0x00003210;
1966 break;
1967 case 0x5:
1968 case 0x6:
1969 case 0x9:
1970 case 0xa:
1971 gb_backend_map = 0x00003311;
1972 break;
1973 default:
1974 DRM_ERROR("bad backend map, using default\n");
1975 gb_backend_map =
1976 evergreen_get_tile_pipe_to_backend_map(rdev,
1977 rdev->config.evergreen.max_tile_pipes,
1978 rdev->config.evergreen.max_backends,
1979 ((EVERGREEN_MAX_BACKENDS_MASK <<
1980 rdev->config.evergreen.max_backends) &
1981 EVERGREEN_MAX_BACKENDS_MASK));
1982 break;
1983 }
1984 } else {
1985 switch (rdev->family) {
1986 case CHIP_CYPRESS:
1987 case CHIP_HEMLOCK:
1988 case CHIP_BARTS:
1989 gb_backend_map = 0x66442200;
1990 break;
1991 case CHIP_JUNIPER:
1992 gb_backend_map = 0x00002200;
1993 break;
1994 default:
1995 gb_backend_map =
1996 evergreen_get_tile_pipe_to_backend_map(rdev,
1997 rdev->config.evergreen.max_tile_pipes,
1998 rdev->config.evergreen.max_backends,
1999 ((EVERGREEN_MAX_BACKENDS_MASK <<
2000 rdev->config.evergreen.max_backends) &
2001 EVERGREEN_MAX_BACKENDS_MASK));
2002 }
2003 }
2004
2005 /* setup tiling info dword. gb_addr_config is not adequate since it does
2006 * not have bank info, so create a custom tiling dword.
2007 * bits 3:0 num_pipes
2008 * bits 7:4 num_banks
2009 * bits 11:8 group_size
2010 * bits 15:12 row_size
2011 */
2012 rdev->config.evergreen.tile_config = 0;
2013 switch (rdev->config.evergreen.max_tile_pipes) {
2014 case 1:
2015 default:
2016 rdev->config.evergreen.tile_config |= (0 << 0);
2017 break;
2018 case 2:
2019 rdev->config.evergreen.tile_config |= (1 << 0);
2020 break;
2021 case 4:
2022 rdev->config.evergreen.tile_config |= (2 << 0);
2023 break;
2024 case 8:
2025 rdev->config.evergreen.tile_config |= (3 << 0);
2026 break;
2027 }
2028 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2029 if (rdev->flags & RADEON_IS_IGP)
2030 rdev->config.evergreen.tile_config |= 1 << 4;
2031 else
2032 rdev->config.evergreen.tile_config |=
2033 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2034 rdev->config.evergreen.tile_config |=
2035 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2036 rdev->config.evergreen.tile_config |=
2037 ((gb_addr_config & 0x30000000) >> 28) << 12;
2038
2039 rdev->config.evergreen.backend_map = gb_backend_map;
2040 WREG32(GB_BACKEND_MAP, gb_backend_map);
2041 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2042 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2043 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2044
2045 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2046 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2047
2048 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2049 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2050 u32 sp = cc_gc_shader_pipe_config;
2051 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2052
2053 if (i == num_shader_engines) {
2054 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2055 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2056 }
2057
2058 WREG32(GRBM_GFX_INDEX, gfx);
2059 WREG32(RLC_GFX_INDEX, gfx);
2060
2061 WREG32(CC_RB_BACKEND_DISABLE, rb);
2062 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2063 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2064 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2065 }
2066
2067 grbm_gfx_index |= SE_BROADCAST_WRITES;
2068 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2069 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2070
2071 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2072 WREG32(CGTS_TCC_DISABLE, 0);
2073 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2074 WREG32(CGTS_USER_TCC_DISABLE, 0);
2075
2076 /* set HW defaults for 3D engine */
2077 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2078 ROQ_IB2_START(0x2b)));
2079
2080 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2081
2082 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2083 SYNC_GRADIENT |
2084 SYNC_WALKER |
2085 SYNC_ALIGNER));
2086
2087 sx_debug_1 = RREG32(SX_DEBUG_1);
2088 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2089 WREG32(SX_DEBUG_1, sx_debug_1);
2090
2091
2092 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2093 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2094 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2095 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2096
2097 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2098 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2099 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2100
2101 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2102 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2103 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2104
2105 WREG32(VGT_NUM_INSTANCES, 1);
2106 WREG32(SPI_CONFIG_CNTL, 0);
2107 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2108 WREG32(CP_PERFMON_CNTL, 0);
2109
2110 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2111 FETCH_FIFO_HIWATER(0x4) |
2112 DONE_FIFO_HIWATER(0xe0) |
2113 ALU_UPDATE_FIFO_HIWATER(0x8)));
2114
2115 sq_config = RREG32(SQ_CONFIG);
2116 sq_config &= ~(PS_PRIO(3) |
2117 VS_PRIO(3) |
2118 GS_PRIO(3) |
2119 ES_PRIO(3));
2120 sq_config |= (VC_ENABLE |
2121 EXPORT_SRC_C |
2122 PS_PRIO(0) |
2123 VS_PRIO(1) |
2124 GS_PRIO(2) |
2125 ES_PRIO(3));
2126
2127 switch (rdev->family) {
2128 case CHIP_CEDAR:
2129 case CHIP_PALM:
2130 case CHIP_SUMO:
2131 case CHIP_SUMO2:
2132 case CHIP_CAICOS:
2133 /* no vertex cache */
2134 sq_config &= ~VC_ENABLE;
2135 break;
2136 default:
2137 break;
2138 }
2139
2140 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2141
2142 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2143 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2144 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2145 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2146 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2147 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2148 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2149
2150 switch (rdev->family) {
2151 case CHIP_CEDAR:
2152 case CHIP_PALM:
2153 case CHIP_SUMO:
2154 case CHIP_SUMO2:
2155 ps_thread_count = 96;
2156 break;
2157 default:
2158 ps_thread_count = 128;
2159 break;
2160 }
2161
2162 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2163 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2165 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2166 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2167 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2168
2169 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2173 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2174 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2175
2176 WREG32(SQ_CONFIG, sq_config);
2177 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2178 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2179 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2180 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2181 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2182 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2183 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2184 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2185 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2186 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2187
2188 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2189 FORCE_EOV_MAX_REZ_CNT(255)));
2190
2191 switch (rdev->family) {
2192 case CHIP_CEDAR:
2193 case CHIP_PALM:
2194 case CHIP_SUMO:
2195 case CHIP_SUMO2:
2196 case CHIP_CAICOS:
2197 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2198 break;
2199 default:
2200 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2201 break;
2202 }
2203 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2204 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2205
2206 WREG32(VGT_GS_VERTEX_REUSE, 16);
2207 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2208 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2209
2210 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2211 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2212
2213 WREG32(CB_PERF_CTR0_SEL_0, 0);
2214 WREG32(CB_PERF_CTR0_SEL_1, 0);
2215 WREG32(CB_PERF_CTR1_SEL_0, 0);
2216 WREG32(CB_PERF_CTR1_SEL_1, 0);
2217 WREG32(CB_PERF_CTR2_SEL_0, 0);
2218 WREG32(CB_PERF_CTR2_SEL_1, 0);
2219 WREG32(CB_PERF_CTR3_SEL_0, 0);
2220 WREG32(CB_PERF_CTR3_SEL_1, 0);
2221
2222 /* clear render buffer base addresses */
2223 WREG32(CB_COLOR0_BASE, 0);
2224 WREG32(CB_COLOR1_BASE, 0);
2225 WREG32(CB_COLOR2_BASE, 0);
2226 WREG32(CB_COLOR3_BASE, 0);
2227 WREG32(CB_COLOR4_BASE, 0);
2228 WREG32(CB_COLOR5_BASE, 0);
2229 WREG32(CB_COLOR6_BASE, 0);
2230 WREG32(CB_COLOR7_BASE, 0);
2231 WREG32(CB_COLOR8_BASE, 0);
2232 WREG32(CB_COLOR9_BASE, 0);
2233 WREG32(CB_COLOR10_BASE, 0);
2234 WREG32(CB_COLOR11_BASE, 0);
2235
2236 /* set the shader const cache sizes to 0 */
2237 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2238 WREG32(i, 0);
2239 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2240 WREG32(i, 0);
2241
2242 tmp = RREG32(HDP_MISC_CNTL);
2243 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2244 WREG32(HDP_MISC_CNTL, tmp);
2245
2246 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2247 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2248
2249 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2250
2251 udelay(50);
2252
2253 }
2254
2255 int evergreen_mc_init(struct radeon_device *rdev)
2256 {
2257 u32 tmp;
2258 int chansize, numchan;
2259
2260 /* Get VRAM informations */
2261 rdev->mc.vram_is_ddr = true;
2262 if (rdev->flags & RADEON_IS_IGP)
2263 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2264 else
2265 tmp = RREG32(MC_ARB_RAMCFG);
2266 if (tmp & CHANSIZE_OVERRIDE) {
2267 chansize = 16;
2268 } else if (tmp & CHANSIZE_MASK) {
2269 chansize = 64;
2270 } else {
2271 chansize = 32;
2272 }
2273 tmp = RREG32(MC_SHARED_CHMAP);
2274 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2275 case 0:
2276 default:
2277 numchan = 1;
2278 break;
2279 case 1:
2280 numchan = 2;
2281 break;
2282 case 2:
2283 numchan = 4;
2284 break;
2285 case 3:
2286 numchan = 8;
2287 break;
2288 }
2289 rdev->mc.vram_width = numchan * chansize;
2290 /* Could aper size report 0 ? */
2291 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2292 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2293 /* Setup GPU memory space */
2294 if (rdev->flags & RADEON_IS_IGP) {
2295 /* size in bytes on fusion */
2296 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2297 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2298 } else {
2299 /* size in MB on evergreen */
2300 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2301 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2302 }
2303 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2304 r700_vram_gtt_location(rdev, &rdev->mc);
2305 radeon_update_bandwidth_info(rdev);
2306
2307 return 0;
2308 }
2309
2310 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2311 {
2312 u32 srbm_status;
2313 u32 grbm_status;
2314 u32 grbm_status_se0, grbm_status_se1;
2315 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2316 int r;
2317
2318 srbm_status = RREG32(SRBM_STATUS);
2319 grbm_status = RREG32(GRBM_STATUS);
2320 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2321 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2322 if (!(grbm_status & GUI_ACTIVE)) {
2323 r100_gpu_lockup_update(lockup, &rdev->cp);
2324 return false;
2325 }
2326 /* force CP activities */
2327 r = radeon_ring_lock(rdev, 2);
2328 if (!r) {
2329 /* PACKET2 NOP */
2330 radeon_ring_write(rdev, 0x80000000);
2331 radeon_ring_write(rdev, 0x80000000);
2332 radeon_ring_unlock_commit(rdev);
2333 }
2334 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2335 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2336 }
2337
2338 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2339 {
2340 struct evergreen_mc_save save;
2341 u32 grbm_reset = 0;
2342
2343 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2344 return 0;
2345
2346 dev_info(rdev->dev, "GPU softreset \n");
2347 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2348 RREG32(GRBM_STATUS));
2349 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2350 RREG32(GRBM_STATUS_SE0));
2351 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2352 RREG32(GRBM_STATUS_SE1));
2353 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2354 RREG32(SRBM_STATUS));
2355 evergreen_mc_stop(rdev, &save);
2356 if (evergreen_mc_wait_for_idle(rdev)) {
2357 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2358 }
2359 /* Disable CP parsing/prefetching */
2360 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2361
2362 /* reset all the gfx blocks */
2363 grbm_reset = (SOFT_RESET_CP |
2364 SOFT_RESET_CB |
2365 SOFT_RESET_DB |
2366 SOFT_RESET_PA |
2367 SOFT_RESET_SC |
2368 SOFT_RESET_SPI |
2369 SOFT_RESET_SH |
2370 SOFT_RESET_SX |
2371 SOFT_RESET_TC |
2372 SOFT_RESET_TA |
2373 SOFT_RESET_VC |
2374 SOFT_RESET_VGT);
2375
2376 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2377 WREG32(GRBM_SOFT_RESET, grbm_reset);
2378 (void)RREG32(GRBM_SOFT_RESET);
2379 udelay(50);
2380 WREG32(GRBM_SOFT_RESET, 0);
2381 (void)RREG32(GRBM_SOFT_RESET);
2382 /* Wait a little for things to settle down */
2383 udelay(50);
2384 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2385 RREG32(GRBM_STATUS));
2386 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2387 RREG32(GRBM_STATUS_SE0));
2388 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2389 RREG32(GRBM_STATUS_SE1));
2390 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2391 RREG32(SRBM_STATUS));
2392 evergreen_mc_resume(rdev, &save);
2393 return 0;
2394 }
2395
2396 int evergreen_asic_reset(struct radeon_device *rdev)
2397 {
2398 return evergreen_gpu_soft_reset(rdev);
2399 }
2400
2401 /* Interrupts */
2402
2403 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2404 {
2405 switch (crtc) {
2406 case 0:
2407 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2408 case 1:
2409 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2410 case 2:
2411 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2412 case 3:
2413 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2414 case 4:
2415 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2416 case 5:
2417 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2418 default:
2419 return 0;
2420 }
2421 }
2422
2423 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2424 {
2425 u32 tmp;
2426
2427 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2428 WREG32(GRBM_INT_CNTL, 0);
2429 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2430 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2431 if (rdev->num_crtc >= 4) {
2432 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2433 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2434 }
2435 if (rdev->num_crtc >= 6) {
2436 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2437 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2438 }
2439
2440 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2441 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2442 if (rdev->num_crtc >= 4) {
2443 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2444 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2445 }
2446 if (rdev->num_crtc >= 6) {
2447 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2448 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2449 }
2450
2451 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2452 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2453
2454 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2455 WREG32(DC_HPD1_INT_CONTROL, tmp);
2456 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2457 WREG32(DC_HPD2_INT_CONTROL, tmp);
2458 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2459 WREG32(DC_HPD3_INT_CONTROL, tmp);
2460 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2461 WREG32(DC_HPD4_INT_CONTROL, tmp);
2462 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2463 WREG32(DC_HPD5_INT_CONTROL, tmp);
2464 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2465 WREG32(DC_HPD6_INT_CONTROL, tmp);
2466
2467 }
2468
2469 int evergreen_irq_set(struct radeon_device *rdev)
2470 {
2471 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2472 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2473 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2474 u32 grbm_int_cntl = 0;
2475 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2476
2477 if (!rdev->irq.installed) {
2478 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2479 return -EINVAL;
2480 }
2481 /* don't enable anything if the ih is disabled */
2482 if (!rdev->ih.enabled) {
2483 r600_disable_interrupts(rdev);
2484 /* force the active interrupt state to all disabled */
2485 evergreen_disable_interrupt_state(rdev);
2486 return 0;
2487 }
2488
2489 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2490 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2491 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2492 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2493 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2494 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2495
2496 if (rdev->irq.sw_int) {
2497 DRM_DEBUG("evergreen_irq_set: sw int\n");
2498 cp_int_cntl |= RB_INT_ENABLE;
2499 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2500 }
2501 if (rdev->irq.crtc_vblank_int[0] ||
2502 rdev->irq.pflip[0]) {
2503 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2504 crtc1 |= VBLANK_INT_MASK;
2505 }
2506 if (rdev->irq.crtc_vblank_int[1] ||
2507 rdev->irq.pflip[1]) {
2508 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2509 crtc2 |= VBLANK_INT_MASK;
2510 }
2511 if (rdev->irq.crtc_vblank_int[2] ||
2512 rdev->irq.pflip[2]) {
2513 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2514 crtc3 |= VBLANK_INT_MASK;
2515 }
2516 if (rdev->irq.crtc_vblank_int[3] ||
2517 rdev->irq.pflip[3]) {
2518 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2519 crtc4 |= VBLANK_INT_MASK;
2520 }
2521 if (rdev->irq.crtc_vblank_int[4] ||
2522 rdev->irq.pflip[4]) {
2523 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2524 crtc5 |= VBLANK_INT_MASK;
2525 }
2526 if (rdev->irq.crtc_vblank_int[5] ||
2527 rdev->irq.pflip[5]) {
2528 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2529 crtc6 |= VBLANK_INT_MASK;
2530 }
2531 if (rdev->irq.hpd[0]) {
2532 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2533 hpd1 |= DC_HPDx_INT_EN;
2534 }
2535 if (rdev->irq.hpd[1]) {
2536 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2537 hpd2 |= DC_HPDx_INT_EN;
2538 }
2539 if (rdev->irq.hpd[2]) {
2540 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2541 hpd3 |= DC_HPDx_INT_EN;
2542 }
2543 if (rdev->irq.hpd[3]) {
2544 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2545 hpd4 |= DC_HPDx_INT_EN;
2546 }
2547 if (rdev->irq.hpd[4]) {
2548 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2549 hpd5 |= DC_HPDx_INT_EN;
2550 }
2551 if (rdev->irq.hpd[5]) {
2552 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2553 hpd6 |= DC_HPDx_INT_EN;
2554 }
2555 if (rdev->irq.gui_idle) {
2556 DRM_DEBUG("gui idle\n");
2557 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2558 }
2559
2560 WREG32(CP_INT_CNTL, cp_int_cntl);
2561 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2562
2563 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2564 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2565 if (rdev->num_crtc >= 4) {
2566 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2567 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2568 }
2569 if (rdev->num_crtc >= 6) {
2570 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2571 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2572 }
2573
2574 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2575 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2576 if (rdev->num_crtc >= 4) {
2577 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2578 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2579 }
2580 if (rdev->num_crtc >= 6) {
2581 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2582 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2583 }
2584
2585 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2586 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2587 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2588 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2589 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2590 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2591
2592 return 0;
2593 }
2594
2595 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2596 {
2597 u32 tmp;
2598
2599 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2600 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2601 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2602 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2603 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2604 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2605 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2606 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2607 if (rdev->num_crtc >= 4) {
2608 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2609 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2610 }
2611 if (rdev->num_crtc >= 6) {
2612 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2613 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2614 }
2615
2616 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2617 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2618 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2619 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2620 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2621 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2622 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2623 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2624 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2625 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2626 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2627 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2628
2629 if (rdev->num_crtc >= 4) {
2630 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2632 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2633 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2634 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2635 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2637 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2639 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2640 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2641 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2642 }
2643
2644 if (rdev->num_crtc >= 6) {
2645 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2646 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2647 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2648 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2649 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2650 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2651 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2652 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2653 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2654 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2655 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2656 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2657 }
2658
2659 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2660 tmp = RREG32(DC_HPD1_INT_CONTROL);
2661 tmp |= DC_HPDx_INT_ACK;
2662 WREG32(DC_HPD1_INT_CONTROL, tmp);
2663 }
2664 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2665 tmp = RREG32(DC_HPD2_INT_CONTROL);
2666 tmp |= DC_HPDx_INT_ACK;
2667 WREG32(DC_HPD2_INT_CONTROL, tmp);
2668 }
2669 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2670 tmp = RREG32(DC_HPD3_INT_CONTROL);
2671 tmp |= DC_HPDx_INT_ACK;
2672 WREG32(DC_HPD3_INT_CONTROL, tmp);
2673 }
2674 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2675 tmp = RREG32(DC_HPD4_INT_CONTROL);
2676 tmp |= DC_HPDx_INT_ACK;
2677 WREG32(DC_HPD4_INT_CONTROL, tmp);
2678 }
2679 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2680 tmp = RREG32(DC_HPD5_INT_CONTROL);
2681 tmp |= DC_HPDx_INT_ACK;
2682 WREG32(DC_HPD5_INT_CONTROL, tmp);
2683 }
2684 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2685 tmp = RREG32(DC_HPD5_INT_CONTROL);
2686 tmp |= DC_HPDx_INT_ACK;
2687 WREG32(DC_HPD6_INT_CONTROL, tmp);
2688 }
2689 }
2690
2691 void evergreen_irq_disable(struct radeon_device *rdev)
2692 {
2693 r600_disable_interrupts(rdev);
2694 /* Wait and acknowledge irq */
2695 mdelay(1);
2696 evergreen_irq_ack(rdev);
2697 evergreen_disable_interrupt_state(rdev);
2698 }
2699
2700 void evergreen_irq_suspend(struct radeon_device *rdev)
2701 {
2702 evergreen_irq_disable(rdev);
2703 r600_rlc_stop(rdev);
2704 }
2705
2706 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2707 {
2708 u32 wptr, tmp;
2709
2710 if (rdev->wb.enabled)
2711 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2712 else
2713 wptr = RREG32(IH_RB_WPTR);
2714
2715 if (wptr & RB_OVERFLOW) {
2716 /* When a ring buffer overflow happen start parsing interrupt
2717 * from the last not overwritten vector (wptr + 16). Hopefully
2718 * this should allow us to catchup.
2719 */
2720 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2721 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2722 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2723 tmp = RREG32(IH_RB_CNTL);
2724 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2725 WREG32(IH_RB_CNTL, tmp);
2726 }
2727 return (wptr & rdev->ih.ptr_mask);
2728 }
2729
2730 int evergreen_irq_process(struct radeon_device *rdev)
2731 {
2732 u32 wptr;
2733 u32 rptr;
2734 u32 src_id, src_data;
2735 u32 ring_index;
2736 unsigned long flags;
2737 bool queue_hotplug = false;
2738
2739 if (!rdev->ih.enabled || rdev->shutdown)
2740 return IRQ_NONE;
2741
2742 wptr = evergreen_get_ih_wptr(rdev);
2743 rptr = rdev->ih.rptr;
2744 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2745
2746 spin_lock_irqsave(&rdev->ih.lock, flags);
2747 if (rptr == wptr) {
2748 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2749 return IRQ_NONE;
2750 }
2751 restart_ih:
2752 /* Order reading of wptr vs. reading of IH ring data */
2753 rmb();
2754
2755 /* display interrupts */
2756 evergreen_irq_ack(rdev);
2757
2758 rdev->ih.wptr = wptr;
2759 while (rptr != wptr) {
2760 /* wptr/rptr are in bytes! */
2761 ring_index = rptr / 4;
2762 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2763 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2764
2765 switch (src_id) {
2766 case 1: /* D1 vblank/vline */
2767 switch (src_data) {
2768 case 0: /* D1 vblank */
2769 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2770 if (rdev->irq.crtc_vblank_int[0]) {
2771 drm_handle_vblank(rdev->ddev, 0);
2772 rdev->pm.vblank_sync = true;
2773 wake_up(&rdev->irq.vblank_queue);
2774 }
2775 if (rdev->irq.pflip[0])
2776 radeon_crtc_handle_flip(rdev, 0);
2777 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2778 DRM_DEBUG("IH: D1 vblank\n");
2779 }
2780 break;
2781 case 1: /* D1 vline */
2782 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2783 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2784 DRM_DEBUG("IH: D1 vline\n");
2785 }
2786 break;
2787 default:
2788 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2789 break;
2790 }
2791 break;
2792 case 2: /* D2 vblank/vline */
2793 switch (src_data) {
2794 case 0: /* D2 vblank */
2795 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2796 if (rdev->irq.crtc_vblank_int[1]) {
2797 drm_handle_vblank(rdev->ddev, 1);
2798 rdev->pm.vblank_sync = true;
2799 wake_up(&rdev->irq.vblank_queue);
2800 }
2801 if (rdev->irq.pflip[1])
2802 radeon_crtc_handle_flip(rdev, 1);
2803 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2804 DRM_DEBUG("IH: D2 vblank\n");
2805 }
2806 break;
2807 case 1: /* D2 vline */
2808 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2809 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2810 DRM_DEBUG("IH: D2 vline\n");
2811 }
2812 break;
2813 default:
2814 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2815 break;
2816 }
2817 break;
2818 case 3: /* D3 vblank/vline */
2819 switch (src_data) {
2820 case 0: /* D3 vblank */
2821 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2822 if (rdev->irq.crtc_vblank_int[2]) {
2823 drm_handle_vblank(rdev->ddev, 2);
2824 rdev->pm.vblank_sync = true;
2825 wake_up(&rdev->irq.vblank_queue);
2826 }
2827 if (rdev->irq.pflip[2])
2828 radeon_crtc_handle_flip(rdev, 2);
2829 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2830 DRM_DEBUG("IH: D3 vblank\n");
2831 }
2832 break;
2833 case 1: /* D3 vline */
2834 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2835 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2836 DRM_DEBUG("IH: D3 vline\n");
2837 }
2838 break;
2839 default:
2840 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2841 break;
2842 }
2843 break;
2844 case 4: /* D4 vblank/vline */
2845 switch (src_data) {
2846 case 0: /* D4 vblank */
2847 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2848 if (rdev->irq.crtc_vblank_int[3]) {
2849 drm_handle_vblank(rdev->ddev, 3);
2850 rdev->pm.vblank_sync = true;
2851 wake_up(&rdev->irq.vblank_queue);
2852 }
2853 if (rdev->irq.pflip[3])
2854 radeon_crtc_handle_flip(rdev, 3);
2855 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2856 DRM_DEBUG("IH: D4 vblank\n");
2857 }
2858 break;
2859 case 1: /* D4 vline */
2860 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2861 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2862 DRM_DEBUG("IH: D4 vline\n");
2863 }
2864 break;
2865 default:
2866 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2867 break;
2868 }
2869 break;
2870 case 5: /* D5 vblank/vline */
2871 switch (src_data) {
2872 case 0: /* D5 vblank */
2873 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2874 if (rdev->irq.crtc_vblank_int[4]) {
2875 drm_handle_vblank(rdev->ddev, 4);
2876 rdev->pm.vblank_sync = true;
2877 wake_up(&rdev->irq.vblank_queue);
2878 }
2879 if (rdev->irq.pflip[4])
2880 radeon_crtc_handle_flip(rdev, 4);
2881 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2882 DRM_DEBUG("IH: D5 vblank\n");
2883 }
2884 break;
2885 case 1: /* D5 vline */
2886 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2887 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2888 DRM_DEBUG("IH: D5 vline\n");
2889 }
2890 break;
2891 default:
2892 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2893 break;
2894 }
2895 break;
2896 case 6: /* D6 vblank/vline */
2897 switch (src_data) {
2898 case 0: /* D6 vblank */
2899 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2900 if (rdev->irq.crtc_vblank_int[5]) {
2901 drm_handle_vblank(rdev->ddev, 5);
2902 rdev->pm.vblank_sync = true;
2903 wake_up(&rdev->irq.vblank_queue);
2904 }
2905 if (rdev->irq.pflip[5])
2906 radeon_crtc_handle_flip(rdev, 5);
2907 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2908 DRM_DEBUG("IH: D6 vblank\n");
2909 }
2910 break;
2911 case 1: /* D6 vline */
2912 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2913 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2914 DRM_DEBUG("IH: D6 vline\n");
2915 }
2916 break;
2917 default:
2918 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2919 break;
2920 }
2921 break;
2922 case 42: /* HPD hotplug */
2923 switch (src_data) {
2924 case 0:
2925 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2926 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2927 queue_hotplug = true;
2928 DRM_DEBUG("IH: HPD1\n");
2929 }
2930 break;
2931 case 1:
2932 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2933 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2934 queue_hotplug = true;
2935 DRM_DEBUG("IH: HPD2\n");
2936 }
2937 break;
2938 case 2:
2939 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2940 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2941 queue_hotplug = true;
2942 DRM_DEBUG("IH: HPD3\n");
2943 }
2944 break;
2945 case 3:
2946 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2947 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2948 queue_hotplug = true;
2949 DRM_DEBUG("IH: HPD4\n");
2950 }
2951 break;
2952 case 4:
2953 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2954 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2955 queue_hotplug = true;
2956 DRM_DEBUG("IH: HPD5\n");
2957 }
2958 break;
2959 case 5:
2960 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2961 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2962 queue_hotplug = true;
2963 DRM_DEBUG("IH: HPD6\n");
2964 }
2965 break;
2966 default:
2967 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2968 break;
2969 }
2970 break;
2971 case 176: /* CP_INT in ring buffer */
2972 case 177: /* CP_INT in IB1 */
2973 case 178: /* CP_INT in IB2 */
2974 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2975 radeon_fence_process(rdev);
2976 break;
2977 case 181: /* CP EOP event */
2978 DRM_DEBUG("IH: CP EOP\n");
2979 radeon_fence_process(rdev);
2980 break;
2981 case 233: /* GUI IDLE */
2982 DRM_DEBUG("IH: GUI idle\n");
2983 rdev->pm.gui_idle = true;
2984 wake_up(&rdev->irq.idle_queue);
2985 break;
2986 default:
2987 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2988 break;
2989 }
2990
2991 /* wptr/rptr are in bytes! */
2992 rptr += 16;
2993 rptr &= rdev->ih.ptr_mask;
2994 }
2995 /* make sure wptr hasn't changed while processing */
2996 wptr = evergreen_get_ih_wptr(rdev);
2997 if (wptr != rdev->ih.wptr)
2998 goto restart_ih;
2999 if (queue_hotplug)
3000 schedule_work(&rdev->hotplug_work);
3001 rdev->ih.rptr = rptr;
3002 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3003 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3004 return IRQ_HANDLED;
3005 }
3006
3007 static int evergreen_startup(struct radeon_device *rdev)
3008 {
3009 int r;
3010
3011 /* enable pcie gen2 link */
3012 if (!ASIC_IS_DCE5(rdev))
3013 evergreen_pcie_gen2_enable(rdev);
3014
3015 if (ASIC_IS_DCE5(rdev)) {
3016 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3017 r = ni_init_microcode(rdev);
3018 if (r) {
3019 DRM_ERROR("Failed to load firmware!\n");
3020 return r;
3021 }
3022 }
3023 r = ni_mc_load_microcode(rdev);
3024 if (r) {
3025 DRM_ERROR("Failed to load MC firmware!\n");
3026 return r;
3027 }
3028 } else {
3029 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3030 r = r600_init_microcode(rdev);
3031 if (r) {
3032 DRM_ERROR("Failed to load firmware!\n");
3033 return r;
3034 }
3035 }
3036 }
3037
3038 evergreen_mc_program(rdev);
3039 if (rdev->flags & RADEON_IS_AGP) {
3040 evergreen_agp_enable(rdev);
3041 } else {
3042 r = evergreen_pcie_gart_enable(rdev);
3043 if (r)
3044 return r;
3045 }
3046 evergreen_gpu_init(rdev);
3047
3048 r = evergreen_blit_init(rdev);
3049 if (r) {
3050 evergreen_blit_fini(rdev);
3051 rdev->asic->copy = NULL;
3052 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3053 }
3054
3055 /* allocate wb buffer */
3056 r = radeon_wb_init(rdev);
3057 if (r)
3058 return r;
3059
3060 /* Enable IRQ */
3061 r = r600_irq_init(rdev);
3062 if (r) {
3063 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3064 radeon_irq_kms_fini(rdev);
3065 return r;
3066 }
3067 evergreen_irq_set(rdev);
3068
3069 r = radeon_ring_init(rdev, rdev->cp.ring_size);
3070 if (r)
3071 return r;
3072 r = evergreen_cp_load_microcode(rdev);
3073 if (r)
3074 return r;
3075 r = evergreen_cp_resume(rdev);
3076 if (r)
3077 return r;
3078
3079 return 0;
3080 }
3081
3082 int evergreen_resume(struct radeon_device *rdev)
3083 {
3084 int r;
3085
3086 /* reset the asic, the gfx blocks are often in a bad state
3087 * after the driver is unloaded or after a resume
3088 */
3089 if (radeon_asic_reset(rdev))
3090 dev_warn(rdev->dev, "GPU reset failed !\n");
3091 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3092 * posting will perform necessary task to bring back GPU into good
3093 * shape.
3094 */
3095 /* post card */
3096 atom_asic_init(rdev->mode_info.atom_context);
3097
3098 r = evergreen_startup(rdev);
3099 if (r) {
3100 DRM_ERROR("evergreen startup failed on resume\n");
3101 return r;
3102 }
3103
3104 r = r600_ib_test(rdev);
3105 if (r) {
3106 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3107 return r;
3108 }
3109
3110 return r;
3111
3112 }
3113
3114 int evergreen_suspend(struct radeon_device *rdev)
3115 {
3116 int r;
3117
3118 /* FIXME: we should wait for ring to be empty */
3119 r700_cp_stop(rdev);
3120 rdev->cp.ready = false;
3121 evergreen_irq_suspend(rdev);
3122 radeon_wb_disable(rdev);
3123 evergreen_pcie_gart_disable(rdev);
3124
3125 /* unpin shaders bo */
3126 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3127 if (likely(r == 0)) {
3128 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3129 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3130 }
3131
3132 return 0;
3133 }
3134
3135 int evergreen_copy_blit(struct radeon_device *rdev,
3136 uint64_t src_offset,
3137 uint64_t dst_offset,
3138 unsigned num_gpu_pages,
3139 struct radeon_fence *fence)
3140 {
3141 int r;
3142
3143 mutex_lock(&rdev->r600_blit.mutex);
3144 rdev->r600_blit.vb_ib = NULL;
3145 r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3146 if (r) {
3147 if (rdev->r600_blit.vb_ib)
3148 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3149 mutex_unlock(&rdev->r600_blit.mutex);
3150 return r;
3151 }
3152 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3153 evergreen_blit_done_copy(rdev, fence);
3154 mutex_unlock(&rdev->r600_blit.mutex);
3155 return 0;
3156 }
3157
3158 /* Plan is to move initialization in that function and use
3159 * helper function so that radeon_device_init pretty much
3160 * do nothing more than calling asic specific function. This
3161 * should also allow to remove a bunch of callback function
3162 * like vram_info.
3163 */
3164 int evergreen_init(struct radeon_device *rdev)
3165 {
3166 int r;
3167
3168 /* This don't do much */
3169 r = radeon_gem_init(rdev);
3170 if (r)
3171 return r;
3172 /* Read BIOS */
3173 if (!radeon_get_bios(rdev)) {
3174 if (ASIC_IS_AVIVO(rdev))
3175 return -EINVAL;
3176 }
3177 /* Must be an ATOMBIOS */
3178 if (!rdev->is_atom_bios) {
3179 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3180 return -EINVAL;
3181 }
3182 r = radeon_atombios_init(rdev);
3183 if (r)
3184 return r;
3185 /* reset the asic, the gfx blocks are often in a bad state
3186 * after the driver is unloaded or after a resume
3187 */
3188 if (radeon_asic_reset(rdev))
3189 dev_warn(rdev->dev, "GPU reset failed !\n");
3190 /* Post card if necessary */
3191 if (!radeon_card_posted(rdev)) {
3192 if (!rdev->bios) {
3193 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3194 return -EINVAL;
3195 }
3196 DRM_INFO("GPU not posted. posting now...\n");
3197 atom_asic_init(rdev->mode_info.atom_context);
3198 }
3199 /* Initialize scratch registers */
3200 r600_scratch_init(rdev);
3201 /* Initialize surface registers */
3202 radeon_surface_init(rdev);
3203 /* Initialize clocks */
3204 radeon_get_clock_info(rdev->ddev);
3205 /* Fence driver */
3206 r = radeon_fence_driver_init(rdev);
3207 if (r)
3208 return r;
3209 /* initialize AGP */
3210 if (rdev->flags & RADEON_IS_AGP) {
3211 r = radeon_agp_init(rdev);
3212 if (r)
3213 radeon_agp_disable(rdev);
3214 }
3215 /* initialize memory controller */
3216 r = evergreen_mc_init(rdev);
3217 if (r)
3218 return r;
3219 /* Memory manager */
3220 r = radeon_bo_init(rdev);
3221 if (r)
3222 return r;
3223
3224 r = radeon_irq_kms_init(rdev);
3225 if (r)
3226 return r;
3227
3228 rdev->cp.ring_obj = NULL;
3229 r600_ring_init(rdev, 1024 * 1024);
3230
3231 rdev->ih.ring_obj = NULL;
3232 r600_ih_ring_init(rdev, 64 * 1024);
3233
3234 r = r600_pcie_gart_init(rdev);
3235 if (r)
3236 return r;
3237
3238 rdev->accel_working = true;
3239 r = evergreen_startup(rdev);
3240 if (r) {
3241 dev_err(rdev->dev, "disabling GPU acceleration\n");
3242 r700_cp_fini(rdev);
3243 r600_irq_fini(rdev);
3244 radeon_wb_fini(rdev);
3245 radeon_irq_kms_fini(rdev);
3246 evergreen_pcie_gart_fini(rdev);
3247 rdev->accel_working = false;
3248 }
3249 if (rdev->accel_working) {
3250 r = radeon_ib_pool_init(rdev);
3251 if (r) {
3252 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3253 rdev->accel_working = false;
3254 }
3255 r = r600_ib_test(rdev);
3256 if (r) {
3257 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3258 rdev->accel_working = false;
3259 }
3260 }
3261
3262 /* Don't start up if the MC ucode is missing on BTC parts.
3263 * The default clocks and voltages before the MC ucode
3264 * is loaded are not suffient for advanced operations.
3265 */
3266 if (ASIC_IS_DCE5(rdev)) {
3267 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3268 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3269 return -EINVAL;
3270 }
3271 }
3272
3273 return 0;
3274 }
3275
3276 void evergreen_fini(struct radeon_device *rdev)
3277 {
3278 evergreen_blit_fini(rdev);
3279 r700_cp_fini(rdev);
3280 r600_irq_fini(rdev);
3281 radeon_wb_fini(rdev);
3282 radeon_ib_pool_fini(rdev);
3283 radeon_irq_kms_fini(rdev);
3284 evergreen_pcie_gart_fini(rdev);
3285 radeon_gem_fini(rdev);
3286 radeon_fence_driver_fini(rdev);
3287 radeon_agp_fini(rdev);
3288 radeon_bo_fini(rdev);
3289 radeon_atombios_fini(rdev);
3290 kfree(rdev->bios);
3291 rdev->bios = NULL;
3292 }
3293
3294 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3295 {
3296 u32 link_width_cntl, speed_cntl;
3297
3298 if (radeon_pcie_gen2 == 0)
3299 return;
3300
3301 if (rdev->flags & RADEON_IS_IGP)
3302 return;
3303
3304 if (!(rdev->flags & RADEON_IS_PCIE))
3305 return;
3306
3307 /* x2 cards have a special sequence */
3308 if (ASIC_IS_X2(rdev))
3309 return;
3310
3311 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3312 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3313 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3314
3315 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3316 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3317 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3318
3319 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3320 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3321 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3322
3323 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3324 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3325 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3326
3327 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3328 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3329 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3330
3331 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3332 speed_cntl |= LC_GEN2_EN_STRAP;
3333 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3334
3335 } else {
3336 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3337 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3338 if (1)
3339 link_width_cntl |= LC_UPCONFIGURE_DIS;
3340 else
3341 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3342 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3343 }
3344 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree