arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c

   1 /*
   2  * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
   3  *
   4  * Toshiba RBTX4927 specific interrupt handlers
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         source@mvista.com
   8  *
   9  * Copyright 2001-2002 MontaVista Software Inc.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the
  13  *  Free Software Foundation; either version 2 of the License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  22  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  24  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  25  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the GNU General Public License along
  28  *  with this program; if not, write to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32
  33 /*
  34 IRQ  Device
  35 00   RBTX4927-ISA/00
  36 01   RBTX4927-ISA/01 PS2/Keyboard
  37 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
  38 03   RBTX4927-ISA/03
  39 04   RBTX4927-ISA/04
  40 05   RBTX4927-ISA/05
  41 06   RBTX4927-ISA/06
  42 07   RBTX4927-ISA/07
  43 08   RBTX4927-ISA/08
  44 09   RBTX4927-ISA/09
  45 10   RBTX4927-ISA/10
  46 11   RBTX4927-ISA/11
  47 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
  48 13   RBTX4927-ISA/13
  49 14   RBTX4927-ISA/14 IDE
  50 15   RBTX4927-ISA/15
  51
  52 16   TX4927-CP0/00 Software 0
  53 17   TX4927-CP0/01 Software 1
  54 18   TX4927-CP0/02 Cascade TX4927-CP0
  55 19   TX4927-CP0/03 Multiplexed -- do not use
  56 20   TX4927-CP0/04 Multiplexed -- do not use
  57 21   TX4927-CP0/05 Multiplexed -- do not use
  58 22   TX4927-CP0/06 Multiplexed -- do not use
  59 23   TX4927-CP0/07 CPU TIMER
  60
  61 24   TX4927-PIC/00
  62 25   TX4927-PIC/01
  63 26   TX4927-PIC/02
  64 27   TX4927-PIC/03 Cascade RBTX4927-IOC
  65 28   TX4927-PIC/04
  66 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
  67 30   TX4927-PIC/06
  68 31   TX4927-PIC/07
  69 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
  70 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
  71 34   TX4927-PIC/10
  72 35   TX4927-PIC/11
  73 36   TX4927-PIC/12
  74 37   TX4927-PIC/13
  75 38   TX4927-PIC/14
  76 39   TX4927-PIC/15
  77 40   TX4927-PIC/16 TX4927 PCI PCI-C
  78 41   TX4927-PIC/17
  79 42   TX4927-PIC/18
  80 43   TX4927-PIC/19
  81 44   TX4927-PIC/20
  82 45   TX4927-PIC/21
  83 46   TX4927-PIC/22 TX4927 PCI PCI-ERR
  84 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
  85 48   TX4927-PIC/24
  86 49   TX4927-PIC/25
  87 50   TX4927-PIC/26
  88 51   TX4927-PIC/27
  89 52   TX4927-PIC/28
  90 53   TX4927-PIC/29
  91 54   TX4927-PIC/30
  92 55   TX4927-PIC/31
  93
  94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
  95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
  96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
  97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
  98 60 RBTX4927-IOC/04
  99 61 RBTX4927-IOC/05
 100 62 RBTX4927-IOC/06
 101 63 RBTX4927-IOC/07
 102
 103 NOTES:
 104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
 105 SouthBridge/ISA/pin=0 no pci irq used by this device
 106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
 107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
 108 SouthBridge/PMC/pin=0 no pci irq used by this device
 109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
 110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
 111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
 112 */
 113
 114 #include <linux/init.h>
 115 #include <linux/kernel.h>
 116 #include <linux/types.h>
 117 #include <linux/mm.h>
 118 #include <linux/swap.h>
 119 #include <linux/ioport.h>
 120 #include <linux/sched.h>
 121 #include <linux/interrupt.h>
 122 #include <linux/pci.h>
 123 #include <linux/timex.h>
 124 #include <asm/bootinfo.h>
 125 #include <asm/page.h>
 126 #include <asm/io.h>
 127 #include <asm/irq.h>
 128 #include <asm/pci.h>
 129 #include <asm/processor.h>
 130 #include <asm/ptrace.h>
 131 #include <asm/reboot.h>
 132 #include <asm/time.h>
 133 #include <linux/bootmem.h>
 134 #include <linux/blkdev.h>
 135 #ifdef CONFIG_RTC_DS1742
 136 #include <linux/ds1742rtc.h>
 137 #endif
 138 #ifdef CONFIG_TOSHIBA_FPCIB0
 139 #include <asm/tx4927/smsc_fdc37m81x.h>
 140 #endif
 141 #include <asm/tx4927/toshiba_rbtx4927.h>
 142
 143
 144 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
 145
 146 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 147 #define TOSHIBA_RBTX4927_IRQ_NONE        0x00000000
 148
 149 #define TOSHIBA_RBTX4927_IRQ_INFO          ( 1 <<  0 )
 150 #define TOSHIBA_RBTX4927_IRQ_WARN          ( 1 <<  1 )
 151 #define TOSHIBA_RBTX4927_IRQ_EROR          ( 1 <<  2 )
 152
 153 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT      ( 1 << 10 )
 154 #define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP   ( 1 << 11 )
 155 #define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN  ( 1 << 12 )
 156 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
 157 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
 158 #define TOSHIBA_RBTX4927_IRQ_IOC_MASK      ( 1 << 15 )
 159 #define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ    ( 1 << 16 )
 160
 161 #define TOSHIBA_RBTX4927_IRQ_ISA_INIT      ( 1 << 20 )
 162 #define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP   ( 1 << 21 )
 163 #define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN  ( 1 << 22 )
 164 #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE    ( 1 << 23 )
 165 #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE   ( 1 << 24 )
 166 #define TOSHIBA_RBTX4927_IRQ_ISA_MASK      ( 1 << 25 )
 167 #define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ    ( 1 << 26 )
 168
 169 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 170 #endif
 171
 172
 173 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 174 static const u32 toshiba_rbtx4927_irq_debug_flag =
 175     (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
 176      TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
 177 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT
 178 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
 179 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
 180 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
 181 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
 182 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_MASK
 183 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
 184 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_INIT
 185 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
 186 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
 187 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
 188 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
 189 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_MASK
 190 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
 191     );
 192 #endif
 193
 194
 195 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 196 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
 197         if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
 198         { \
 199            char tmp[100]; \
 200            sprintf( tmp, str ); \
 201            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 202         }
 203 #else
 204 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
 205 #endif
 206
 207
 208
 209
 210 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG   0
 211 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END   7
 212
 213 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
 214 #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
 215
 216
 217 #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
 218 #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
 219 #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
 220
 221
 222 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
 223 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
 224 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
 225
 226 extern int tx4927_using_backplane;
 227
 228 #ifdef CONFIG_TOSHIBA_FPCIB0
 229 extern void enable_8259A_irq(unsigned int irq);
 230 extern void disable_8259A_irq(unsigned int irq);
 231 extern void mask_and_ack_8259A(unsigned int irq);
 232 #endif
 233
 234 static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
 235 static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
 236 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
 237 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
 238 static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
 239 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
 240
 241 #ifdef CONFIG_TOSHIBA_FPCIB0
 242 static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
 243 static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
 244 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
 245 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
 246 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
 247 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
 248 #endif
 249
 250 static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
 251
 252
 253 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
 254 static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = {
 255         .typename = TOSHIBA_RBTX4927_IOC_NAME,
 256         .startup = toshiba_rbtx4927_irq_ioc_startup,
 257         .shutdown = toshiba_rbtx4927_irq_ioc_shutdown,
 258         .enable = toshiba_rbtx4927_irq_ioc_enable,
 259         .disable = toshiba_rbtx4927_irq_ioc_disable,
 260         .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
 261         .end = toshiba_rbtx4927_irq_ioc_end,
 262         .set_affinity = NULL
 263 };
 264 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
 265 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
 266
 267
 268 #ifdef CONFIG_TOSHIBA_FPCIB0
 269 #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
 270 static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = {
 271         .typename = TOSHIBA_RBTX4927_ISA_NAME,
 272         .startup = toshiba_rbtx4927_irq_isa_startup,
 273         .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
 274         .enable = toshiba_rbtx4927_irq_isa_enable,
 275         .disable = toshiba_rbtx4927_irq_isa_disable,
 276         .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
 277         .end = toshiba_rbtx4927_irq_isa_end,
 278         .set_affinity = NULL
 279 };
 280 #endif
 281
 282
 283 u32 bit2num(u32 num)
 284 {
 285         u32 i;
 286
 287         for (i = 0; i < (sizeof(num) * 8); i++) {
 288                 if (num & (1 << i)) {
 289                         return (i);
 290                 }
 291         }
 292         return (0);
 293 }
 294
 295 int toshiba_rbtx4927_irq_nested(int sw_irq)
 296 {
 297         u32 level3;
 298         u32 level4;
 299         u32 level5;
 300
 301         level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
 302         if (level3) {
 303                 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
 304                 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
 305                         goto RETURN;
 306                 }
 307         }
 308 #ifdef CONFIG_TOSHIBA_FPCIB0
 309         {
 310                 if (tx4927_using_backplane) {
 311                         outb(0x0A, 0x20);
 312                         level4 = inb(0x20) & 0xff;
 313                         if (level4) {
 314                                 sw_irq =
 315                                     TOSHIBA_RBTX4927_IRQ_ISA_BEG +
 316                                     bit2num(level4);
 317                                 if (sw_irq !=
 318                                     TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
 319                                         goto RETURN;
 320                                 }
 321                         }
 322
 323                         outb(0x0A, 0xA0);
 324                         level5 = inb(0xA0) & 0xff;
 325                         if (level5) {
 326                                 sw_irq =
 327                                     TOSHIBA_RBTX4927_IRQ_ISA_MID +
 328                                     bit2num(level5);
 329                                 goto RETURN;
 330                         }
 331                 }
 332         }
 333 #endif
 334
 335       RETURN:
 336         return (sw_irq);
 337 }
 338
 339 //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
 340 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
 341 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
 342 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
 343 #ifdef CONFIG_TOSHIBA_FPCIB0
 344 static struct irqaction toshiba_rbtx4927_irq_isa_master =
 345 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
 346 static struct irqaction toshiba_rbtx4927_irq_isa_slave =
 347 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
 348 #endif
 349
 350
 351 /**********************************************************************************/
 352 /* Functions for ioc                                                              */
 353 /**********************************************************************************/
 354
 355
 356 static void __init toshiba_rbtx4927_irq_ioc_init(void)
 357 {
 358         int i;
 359
 360         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
 361                                      "beg=%d end=%d\n",
 362                                      TOSHIBA_RBTX4927_IRQ_IOC_BEG,
 363                                      TOSHIBA_RBTX4927_IRQ_IOC_END);
 364
 365         for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
 366              i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) {
 367                 irq_desc[i].status = IRQ_DISABLED;
 368                 irq_desc[i].action = 0;
 369                 irq_desc[i].depth = 3;
 370                 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
 371         }
 372
 373         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
 374                   &toshiba_rbtx4927_irq_ioc_action);
 375
 376         return;
 377 }
 378
 379 static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
 380 {
 381         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
 382                                      "irq=%d\n", irq);
 383
 384         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 385             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 386                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 387                                              "bad irq=%d\n", irq);
 388                 panic("\n");
 389         }
 390
 391         toshiba_rbtx4927_irq_ioc_enable(irq);
 392
 393         return (0);
 394 }
 395
 396
 397 static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
 398 {
 399         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
 400                                      "irq=%d\n", irq);
 401
 402         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 403             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 404                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 405                                              "bad irq=%d\n", irq);
 406                 panic("\n");
 407         }
 408
 409         toshiba_rbtx4927_irq_ioc_disable(irq);
 410
 411         return;
 412 }
 413
 414
 415 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
 416 {
 417         unsigned long flags;
 418         volatile unsigned char v;
 419
 420         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
 421                                      "irq=%d\n", irq);
 422
 423         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 424             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 425                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 426                                              "bad irq=%d\n", irq);
 427                 panic("\n");
 428         }
 429
 430         spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
 431
 432         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 433         v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
 434         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
 435
 436         spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
 437
 438         return;
 439 }
 440
 441
 442 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
 443 {
 444         unsigned long flags;
 445         volatile unsigned char v;
 446
 447         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
 448                                      "irq=%d\n", irq);
 449
 450         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 451             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 452                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 453                                              "bad irq=%d\n", irq);
 454                 panic("\n");
 455         }
 456
 457         spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
 458
 459         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 460         v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
 461         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
 462
 463         spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
 464
 465         return;
 466 }
 467
 468
 469 static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
 470 {
 471         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
 472                                      "irq=%d\n", irq);
 473
 474         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 475             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 476                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 477                                              "bad irq=%d\n", irq);
 478                 panic("\n");
 479         }
 480
 481         toshiba_rbtx4927_irq_ioc_disable(irq);
 482
 483         return;
 484 }
 485
 486
 487 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
 488 {
 489         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
 490                                      "irq=%d\n", irq);
 491
 492         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 493             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 494                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 495                                              "bad irq=%d\n", irq);
 496                 panic("\n");
 497         }
 498
 499         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 500                 toshiba_rbtx4927_irq_ioc_enable(irq);
 501         }
 502
 503         return;
 504 }
 505
 506
 507 /**********************************************************************************/
 508 /* Functions for isa                                                              */
 509 /**********************************************************************************/
 510
 511
 512 #ifdef CONFIG_TOSHIBA_FPCIB0
 513 static void __init toshiba_rbtx4927_irq_isa_init(void)
 514 {
 515         int i;
 516
 517         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
 518                                      "beg=%d end=%d\n",
 519                                      TOSHIBA_RBTX4927_IRQ_ISA_BEG,
 520                                      TOSHIBA_RBTX4927_IRQ_ISA_END);
 521
 522         for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
 523              i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) {
 524                 irq_desc[i].status = IRQ_DISABLED;
 525                 irq_desc[i].action = 0;
 526                 irq_desc[i].depth =
 527                     ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
 528                 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
 529         }
 530
 531         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
 532                   &toshiba_rbtx4927_irq_isa_master);
 533         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
 534                   &toshiba_rbtx4927_irq_isa_slave);
 535
 536         /* make sure we are looking at IRR (not ISR) */
 537         outb(0x0A, 0x20);
 538         outb(0x0A, 0xA0);
 539
 540         return;
 541 }
 542 #endif
 543
 544
 545 #ifdef CONFIG_TOSHIBA_FPCIB0
 546 static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
 547 {
 548         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
 549                                      "irq=%d\n", irq);
 550
 551         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 552             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 553                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 554                                              "bad irq=%d\n", irq);
 555                 panic("\n");
 556         }
 557
 558         toshiba_rbtx4927_irq_isa_enable(irq);
 559
 560         return (0);
 561 }
 562 #endif
 563
 564
 565 #ifdef CONFIG_TOSHIBA_FPCIB0
 566 static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
 567 {
 568         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
 569                                      "irq=%d\n", irq);
 570
 571         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 572             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 573                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 574                                              "bad irq=%d\n", irq);
 575                 panic("\n");
 576         }
 577
 578         toshiba_rbtx4927_irq_isa_disable(irq);
 579
 580         return;
 581 }
 582 #endif
 583
 584
 585 #ifdef CONFIG_TOSHIBA_FPCIB0
 586 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
 587 {
 588         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
 589                                      "irq=%d\n", irq);
 590
 591         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 592             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 593                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 594                                              "bad irq=%d\n", irq);
 595                 panic("\n");
 596         }
 597
 598         enable_8259A_irq(irq);
 599
 600         return;
 601 }
 602 #endif
 603
 604
 605 #ifdef CONFIG_TOSHIBA_FPCIB0
 606 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
 607 {
 608         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
 609                                      "irq=%d\n", irq);
 610
 611         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 612             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 613                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 614                                              "bad irq=%d\n", irq);
 615                 panic("\n");
 616         }
 617
 618         disable_8259A_irq(irq);
 619
 620         return;
 621 }
 622 #endif
 623
 624
 625 #ifdef CONFIG_TOSHIBA_FPCIB0
 626 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
 627 {
 628         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
 629                                      "irq=%d\n", irq);
 630
 631         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 632             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 633                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 634                                              "bad irq=%d\n", irq);
 635                 panic("\n");
 636         }
 637
 638         mask_and_ack_8259A(irq);
 639
 640         return;
 641 }
 642 #endif
 643
 644
 645 #ifdef CONFIG_TOSHIBA_FPCIB0
 646 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
 647 {
 648         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
 649                                      "irq=%d\n", irq);
 650
 651         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
 652             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
 653                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 654                                              "bad irq=%d\n", irq);
 655                 panic("\n");
 656         }
 657
 658         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 659                 toshiba_rbtx4927_irq_isa_enable(irq);
 660         }
 661
 662         return;
 663 }
 664 #endif
 665
 666
 667 void __init arch_init_irq(void)
 668 {
 669         extern void tx4927_irq_init(void);
 670
 671         local_irq_disable();
 672
 673         tx4927_irq_init();
 674         toshiba_rbtx4927_irq_ioc_init();
 675 #ifdef CONFIG_TOSHIBA_FPCIB0
 676         {
 677                 if (tx4927_using_backplane) {
 678                         toshiba_rbtx4927_irq_isa_init();
 679                 }
 680         }
 681 #endif
 682
 683         wbflush();
 684
 685         return;
 686 }
 687
 688 void toshiba_rbtx4927_irq_dump(char *key)
 689 {
 690 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 691         {
 692                 u32 i, j = 0;
 693                 for (i = 0; i < NR_IRQS; i++) {
 694                         if (strcmp(irq_desc[i].chip->typename, "none")
 695                             == 0)
 696                                 continue;
 697
 698                         if ((i >= 1)
 699                             && (irq_desc[i - 1].chip->typename ==
 700                                 irq_desc[i].chip->typename)) {
 701                                 j++;
 702                         } else {
 703                                 j = 0;
 704                         }
 705                         TOSHIBA_RBTX4927_IRQ_DPRINTK
 706                             (TOSHIBA_RBTX4927_IRQ_INFO,
 707                              "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
 708                              key, i, i, irq_desc[i].status,
 709                              (u32) irq_desc[i].chip,
 710                              (u32) irq_desc[i].action,
 711                              (u32) (irq_desc[i].action ? irq_desc[i].
 712                                     action->handler : 0),
 713                              irq_desc[i].depth,
 714                              irq_desc[i].chip->typename, j);
 715                 }
 716         }
 717 #endif
 718         return;
 719 }
 720
 721 void toshiba_rbtx4927_irq_dump_pics(char *s)
 722 {
 723         u32 level0_m;
 724         u32 level0_s;
 725         u32 level1_m;
 726         u32 level1_s;
 727         u32 level2;
 728         u32 level2_p;
 729         u32 level2_s;
 730         u32 level3_m;
 731         u32 level3_s;
 732         u32 level4_m;
 733         u32 level4_s;
 734         u32 level5_m;
 735         u32 level5_s;
 736
 737         if (s == NULL)
 738                 s = "null";
 739
 740         level0_m = (read_c0_status() & 0x0000ff00) >> 8;
 741         level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
 742
 743         level1_m = level0_m;
 744         level1_s = level0_s & 0x87;
 745
 746         level2 = TX4927_RD(0xff1ff6a0);
 747         level2_p = (((level2 & 0x10000)) ? 0 : 1);
 748         level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
 749
 750         level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
 751         level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
 752
 753         level4_m = inb(0x21);
 754         outb(0x0A, 0x20);
 755         level4_s = inb(0x20);
 756
 757         level5_m = inb(0xa1);
 758         outb(0x0A, 0xa0);
 759         level5_s = inb(0xa0);
 760
 761         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 762                                      "dump_raw_pic() ");
 763         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 764                                      "cp0:m=0x%02x/s=0x%02x ", level0_m,
 765                                      level0_s);
 766         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 767                                      "cp0:m=0x%02x/s=0x%02x ", level1_m,
 768                                      level1_s);
 769         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 770                                      "pic:e=0x%02x/s=0x%02x ", level2_p,
 771                                      level2_s);
 772         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 773                                      "ioc:m=0x%02x/s=0x%02x ", level3_m,
 774                                      level3_s);
 775         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 776                                      "sbm:m=0x%02x/s=0x%02x ", level4_m,
 777                                      level4_s);
 778         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 779                                      "sbs:m=0x%02x/s=0x%02x ", level5_m,
 780                                      level5_s);
 781         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
 782                                      s);
 783
 784         return;
 785 }