arch/mips/momentum/ocelot_g/gt-irq.c

   1 /*
   2  *
   3  * Copyright 2002 Momentum Computer
   4  * Author: mdharm@momenco.com
   5  *
   6  * arch/mips/momentum/ocelot_g/gt_irq.c
   7  *     Interrupt routines for gt64240.  Currently it only handles timer irq.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <asm/ptrace.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel_stat.h>
  20 #include <asm/gt64240.h>
  21 #include <asm/io.h>
  22
  23 unsigned long bus_clock;
  24
  25 /*
  26  * These are interrupt handlers for the GT on-chip interrupts.  They
  27  * all come in to the MIPS on a single interrupt line, and have to
  28  * be handled and ack'ed differently than other MIPS interrupts.
  29  */
  30
  31 #if CURRENTLY_UNUSED
  32
  33 struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
  34 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
  35
  36 /*
  37  * Hooks IRQ handler to the system. When the system is interrupted
  38  * the interrupt service routine is called.
  39  *
  40  * Inputs :
  41  * int_cause - The interrupt cause number. In EVB64120 two parameters
  42  *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
  43  * bit_num   - Indicates which bit number in the cause register
  44  * isr_ptr   - Pointer to the interrupt service routine
  45  */
  46 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
  47 {
  48         irq_handlers[int_cause][bit_num].routine = isr_ptr;
  49 }
  50
  51
  52 /*
  53  * Enables the IRQ on Galileo Chip
  54  *
  55  * Inputs :
  56  * int_cause - The interrupt cause number. In EVB64120 two parameters
  57  *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
  58  * bit_num   - Indicates which bit number in the cause register
  59  *
  60  * Outputs :
  61  * 1 if successful, 0 if failure
  62  */
  63 int enable_galileo_irq(int int_cause, int bit_num)
  64 {
  65         if (int_cause == INT_CAUSE_MAIN)
  66                 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
  67         else if (int_cause == INT_CAUSE_HIGH)
  68                 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
  69                              (1 << bit_num));
  70         else
  71                 return 0;
  72
  73         return 1;
  74 }
  75
  76 /*
  77  * Disables the IRQ on Galileo Chip
  78  *
  79  * Inputs :
  80  * int_cause - The interrupt cause number. In EVB64120 two parameters
  81  *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
  82  * bit_num   - Indicates which bit number in the cause register
  83  *
  84  * Outputs :
  85  * 1 if successful, 0 if failure
  86  */
  87 int disable_galileo_irq(int int_cause, int bit_num)
  88 {
  89         if (int_cause == INT_CAUSE_MAIN)
  90                 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
  91                                (1 << bit_num));
  92         else if (int_cause == INT_CAUSE_HIGH)
  93                 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
  94                                (1 << bit_num));
  95         else
  96                 return 0;
  97         return 1;
  98 }
  99 #endif                          /*  UNUSED  */
 100
 101 /*
 102  * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
 103  *
 104  * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
 105  * routine can handle, for now.
 106  *
 107  * In the future, we'll route more interrupts to this pin, and that's why
 108  * we keep this particular structure in the function.
 109  */
 110
 111 static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs)
 112 {
 113         uint32_t irq_src, irq_src_mask;
 114         int handled;
 115
 116         /* get the low interrupt cause register */
 117         irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
 118
 119         /* get the mask register for this pin */
 120         irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
 121
 122         /* mask off only the interrupts we're interested in */
 123         irq_src = irq_src & irq_src_mask;
 124
 125         handled = IRQ_NONE;
 126
 127         /* Check for timer interrupt */
 128         if (irq_src & 0x00000100) {
 129                 handled = IRQ_HANDLED;
 130                 irq_src &= ~0x00000100;
 131
 132                 /* Clear any pending cause bits */
 133                 MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
 134
 135                 /* handle the timer call */
 136                 do_timer(regs);
 137 #ifndef CONFIG_SMP
 138                 update_process_times(user_mode(regs));
 139 #endif
 140         }
 141
 142         if (irq_src) {
 143                 printk(KERN_INFO
 144                        "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
 145                        irq_src);
 146         }
 147
 148         return handled;
 149 }
 150
 151 /*
 152  * Initializes timer using galileo's built in timer.
 153  */
 154
 155 /*
 156  * This will ignore the standard MIPS timer interrupt handler
 157  * that is passed in as *irq (=irq0 in ../kernel/time.c).
 158  * We will do our own timer interrupt handling.
 159  */
 160 void gt64240_time_init(void)
 161 {
 162         static struct irqaction timer;
 163
 164         /* Stop the timer -- we'll use timer #0 */
 165         MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
 166
 167         /* Load timer value for 100 Hz */
 168         MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
 169
 170         /*
 171          * Create the IRQ structure entry for the timer.  Since we're too early
 172          * in the boot process to use the "request_irq()" call, we'll hard-code
 173          * the values to the correct interrupt line.
 174          */
 175         timer.handler = &gt64240_p0int_irq;
 176         timer.flags = IRQF_SHARED | IRQF_DISABLED;
 177         timer.name = "timer";
 178         timer.dev_id = NULL;
 179         timer.next = NULL;
 180         timer.mask = CPU_MASK_NONE;
 181         irq_desc[6].action = &timer;
 182
 183         enable_irq(6);
 184
 185         /* Clear any pending cause bits */
 186         MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
 187
 188         /* Enable the interrupt for timer 0 */
 189         MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
 190
 191         /* Enable the timer interrupt for GT-64240 pin P0_INT# */
 192         MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
 193
 194         /* Configure and start the timer */
 195         MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
 196 }
 197
 198 void gt64240_irq_init(void)
 199 {
 200 #if CURRENTLY_UNUSED
 201         int i, j;
 202
 203         /* Reset irq handlers pointers to NULL */
 204         for (i = 0; i < MAX_CAUSE_REGS; i++) {
 205                 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
 206                         irq_handlers[i][j].next = NULL;
 207                         irq_handlers[i][j].sync = 0;
 208                         irq_handlers[i][j].routine = NULL;
 209                         irq_handlers[i][j].data = NULL;
 210                 }
 211         }
 212 #endif
 213 }