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mac80211: fix ampdu_action tx_start ssn
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e100.c
blob929701ca07d31bf1aedbcb7e54a9ba93bc6db654
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/sched.h>
155 #include <linux/slab.h>
156 #include <linux/delay.h>
157 #include <linux/init.h>
158 #include <linux/pci.h>
159 #include <linux/dma-mapping.h>
160 #include <linux/dmapool.h>
161 #include <linux/netdevice.h>
162 #include <linux/etherdevice.h>
163 #include <linux/mii.h>
164 #include <linux/if_vlan.h>
165 #include <linux/skbuff.h>
166 #include <linux/ethtool.h>
167 #include <linux/string.h>
168 #include <linux/firmware.h>
169 #include <asm/unaligned.h>
170
171
172 #define DRV_NAME "e100"
173 #define DRV_EXT "-NAPI"
174 #define DRV_VERSION "3.5.24-k2"DRV_EXT
175 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
176 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
177 #define PFX DRV_NAME ": "
178
179 #define E100_WATCHDOG_PERIOD (2 * HZ)
180 #define E100_NAPI_WEIGHT 16
181
182 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
183 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
184 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
185
186 MODULE_DESCRIPTION(DRV_DESCRIPTION);
187 MODULE_AUTHOR(DRV_COPYRIGHT);
188 MODULE_LICENSE("GPL");
189 MODULE_VERSION(DRV_VERSION);
190 MODULE_FIRMWARE(FIRMWARE_D101M);
191 MODULE_FIRMWARE(FIRMWARE_D101S);
192 MODULE_FIRMWARE(FIRMWARE_D102E);
193
194 static int debug = 3;
195 static int eeprom_bad_csum_allow = 0;
196 static int use_io = 0;
197 module_param(debug, int, 0);
198 module_param(eeprom_bad_csum_allow, int, 0);
199 module_param(use_io, int, 0);
200 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
201 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
202 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
203 #define DPRINTK(nlevel, klevel, fmt, args...) \
204 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
205 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
206 __func__ , ## args))
207
208 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
209 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
210 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
211 static struct pci_device_id e100_id_table[] = {
212 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
219 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
225 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
233 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
234 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
242 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
247 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
248 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
249 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
250 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
253 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
254 { 0, }
255 };
256 MODULE_DEVICE_TABLE(pci, e100_id_table);
257
258 enum mac {
259 mac_82557_D100_A = 0,
260 mac_82557_D100_B = 1,
261 mac_82557_D100_C = 2,
262 mac_82558_D101_A4 = 4,
263 mac_82558_D101_B0 = 5,
264 mac_82559_D101M = 8,
265 mac_82559_D101S = 9,
266 mac_82550_D102 = 12,
267 mac_82550_D102_C = 13,
268 mac_82551_E = 14,
269 mac_82551_F = 15,
270 mac_82551_10 = 16,
271 mac_unknown = 0xFF,
272 };
273
274 enum phy {
275 phy_100a = 0x000003E0,
276 phy_100c = 0x035002A8,
277 phy_82555_tx = 0x015002A8,
278 phy_nsc_tx = 0x5C002000,
279 phy_82562_et = 0x033002A8,
280 phy_82562_em = 0x032002A8,
281 phy_82562_ek = 0x031002A8,
282 phy_82562_eh = 0x017002A8,
283 phy_82552_v = 0xd061004d,
284 phy_unknown = 0xFFFFFFFF,
285 };
286
287 /* CSR (Control/Status Registers) */
288 struct csr {
289 struct {
290 u8 status;
291 u8 stat_ack;
292 u8 cmd_lo;
293 u8 cmd_hi;
294 u32 gen_ptr;
295 } scb;
296 u32 port;
297 u16 flash_ctrl;
298 u8 eeprom_ctrl_lo;
299 u8 eeprom_ctrl_hi;
300 u32 mdi_ctrl;
301 u32 rx_dma_count;
302 };
303
304 enum scb_status {
305 rus_no_res = 0x08,
306 rus_ready = 0x10,
307 rus_mask = 0x3C,
308 };
309
310 enum ru_state {
311 RU_SUSPENDED = 0,
312 RU_RUNNING = 1,
313 RU_UNINITIALIZED = -1,
314 };
315
316 enum scb_stat_ack {
317 stat_ack_not_ours = 0x00,
318 stat_ack_sw_gen = 0x04,
319 stat_ack_rnr = 0x10,
320 stat_ack_cu_idle = 0x20,
321 stat_ack_frame_rx = 0x40,
322 stat_ack_cu_cmd_done = 0x80,
323 stat_ack_not_present = 0xFF,
324 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
325 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
326 };
327
328 enum scb_cmd_hi {
329 irq_mask_none = 0x00,
330 irq_mask_all = 0x01,
331 irq_sw_gen = 0x02,
332 };
333
334 enum scb_cmd_lo {
335 cuc_nop = 0x00,
336 ruc_start = 0x01,
337 ruc_load_base = 0x06,
338 cuc_start = 0x10,
339 cuc_resume = 0x20,
340 cuc_dump_addr = 0x40,
341 cuc_dump_stats = 0x50,
342 cuc_load_base = 0x60,
343 cuc_dump_reset = 0x70,
344 };
345
346 enum cuc_dump {
347 cuc_dump_complete = 0x0000A005,
348 cuc_dump_reset_complete = 0x0000A007,
349 };
350
351 enum port {
352 software_reset = 0x0000,
353 selftest = 0x0001,
354 selective_reset = 0x0002,
355 };
356
357 enum eeprom_ctrl_lo {
358 eesk = 0x01,
359 eecs = 0x02,
360 eedi = 0x04,
361 eedo = 0x08,
362 };
363
364 enum mdi_ctrl {
365 mdi_write = 0x04000000,
366 mdi_read = 0x08000000,
367 mdi_ready = 0x10000000,
368 };
369
370 enum eeprom_op {
371 op_write = 0x05,
372 op_read = 0x06,
373 op_ewds = 0x10,
374 op_ewen = 0x13,
375 };
376
377 enum eeprom_offsets {
378 eeprom_cnfg_mdix = 0x03,
379 eeprom_phy_iface = 0x06,
380 eeprom_id = 0x0A,
381 eeprom_config_asf = 0x0D,
382 eeprom_smbus_addr = 0x90,
383 };
384
385 enum eeprom_cnfg_mdix {
386 eeprom_mdix_enabled = 0x0080,
387 };
388
389 enum eeprom_phy_iface {
390 NoSuchPhy = 0,
391 I82553AB,
392 I82553C,
393 I82503,
394 DP83840,
395 S80C240,
396 S80C24,
397 I82555,
398 DP83840A = 10,
399 };
400
401 enum eeprom_id {
402 eeprom_id_wol = 0x0020,
403 };
404
405 enum eeprom_config_asf {
406 eeprom_asf = 0x8000,
407 eeprom_gcl = 0x4000,
408 };
409
410 enum cb_status {
411 cb_complete = 0x8000,
412 cb_ok = 0x2000,
413 };
414
415 enum cb_command {
416 cb_nop = 0x0000,
417 cb_iaaddr = 0x0001,
418 cb_config = 0x0002,
419 cb_multi = 0x0003,
420 cb_tx = 0x0004,
421 cb_ucode = 0x0005,
422 cb_dump = 0x0006,
423 cb_tx_sf = 0x0008,
424 cb_cid = 0x1f00,
425 cb_i = 0x2000,
426 cb_s = 0x4000,
427 cb_el = 0x8000,
428 };
429
430 struct rfd {
431 __le16 status;
432 __le16 command;
433 __le32 link;
434 __le32 rbd;
435 __le16 actual_size;
436 __le16 size;
437 };
438
439 struct rx {
440 struct rx *next, *prev;
441 struct sk_buff *skb;
442 dma_addr_t dma_addr;
443 };
444
445 #if defined(__BIG_ENDIAN_BITFIELD)
446 #define X(a,b) b,a
447 #else
448 #define X(a,b) a,b
449 #endif
450 struct config {
451 /*0*/ u8 X(byte_count:6, pad0:2);
452 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
453 /*2*/ u8 adaptive_ifs;
454 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
455 term_write_cache_line:1), pad3:4);
456 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
457 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
458 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
459 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
460 rx_discard_overruns:1), rx_save_bad_frames:1);
461 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
462 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
463 tx_dynamic_tbd:1);
464 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
465 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
466 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
467 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
468 loopback:2);
469 /*11*/ u8 X(linear_priority:3, pad11:5);
470 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
471 /*13*/ u8 ip_addr_lo;
472 /*14*/ u8 ip_addr_hi;
473 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
474 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
475 pad15_2:1), crs_or_cdt:1);
476 /*16*/ u8 fc_delay_lo;
477 /*17*/ u8 fc_delay_hi;
478 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
479 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
480 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
481 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
482 full_duplex_force:1), full_duplex_pin:1);
483 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
484 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
485 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
486 u8 pad_d102[9];
487 };
488
489 #define E100_MAX_MULTICAST_ADDRS 64
490 struct multi {
491 __le16 count;
492 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
493 };
494
495 /* Important: keep total struct u32-aligned */
496 #define UCODE_SIZE 134
497 struct cb {
498 __le16 status;
499 __le16 command;
500 __le32 link;
501 union {
502 u8 iaaddr[ETH_ALEN];
503 __le32 ucode[UCODE_SIZE];
504 struct config config;
505 struct multi multi;
506 struct {
507 u32 tbd_array;
508 u16 tcb_byte_count;
509 u8 threshold;
510 u8 tbd_count;
511 struct {
512 __le32 buf_addr;
513 __le16 size;
514 u16 eol;
515 } tbd;
516 } tcb;
517 __le32 dump_buffer_addr;
518 } u;
519 struct cb *next, *prev;
520 dma_addr_t dma_addr;
521 struct sk_buff *skb;
522 };
523
524 enum loopback {
525 lb_none = 0, lb_mac = 1, lb_phy = 3,
526 };
527
528 struct stats {
529 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
530 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
531 tx_multiple_collisions, tx_total_collisions;
532 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
533 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
534 rx_short_frame_errors;
535 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
536 __le16 xmt_tco_frames, rcv_tco_frames;
537 __le32 complete;
538 };
539
540 struct mem {
541 struct {
542 u32 signature;
543 u32 result;
544 } selftest;
545 struct stats stats;
546 u8 dump_buf[596];
547 };
548
549 struct param_range {
550 u32 min;
551 u32 max;
552 u32 count;
553 };
554
555 struct params {
556 struct param_range rfds;
557 struct param_range cbs;
558 };
559
560 struct nic {
561 /* Begin: frequently used values: keep adjacent for cache effect */
562 u32 msg_enable ____cacheline_aligned;
563 struct net_device *netdev;
564 struct pci_dev *pdev;
565 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
566
567 struct rx *rxs ____cacheline_aligned;
568 struct rx *rx_to_use;
569 struct rx *rx_to_clean;
570 struct rfd blank_rfd;
571 enum ru_state ru_running;
572
573 spinlock_t cb_lock ____cacheline_aligned;
574 spinlock_t cmd_lock;
575 struct csr __iomem *csr;
576 enum scb_cmd_lo cuc_cmd;
577 unsigned int cbs_avail;
578 struct napi_struct napi;
579 struct cb *cbs;
580 struct cb *cb_to_use;
581 struct cb *cb_to_send;
582 struct cb *cb_to_clean;
583 __le16 tx_command;
584 /* End: frequently used values: keep adjacent for cache effect */
585
586 enum {
587 ich = (1 << 0),
588 promiscuous = (1 << 1),
589 multicast_all = (1 << 2),
590 wol_magic = (1 << 3),
591 ich_10h_workaround = (1 << 4),
592 } flags ____cacheline_aligned;
593
594 enum mac mac;
595 enum phy phy;
596 struct params params;
597 struct timer_list watchdog;
598 struct timer_list blink_timer;
599 struct mii_if_info mii;
600 struct work_struct tx_timeout_task;
601 enum loopback loopback;
602
603 struct mem *mem;
604 dma_addr_t dma_addr;
605
606 struct pci_pool *cbs_pool;
607 dma_addr_t cbs_dma_addr;
608 u8 adaptive_ifs;
609 u8 tx_threshold;
610 u32 tx_frames;
611 u32 tx_collisions;
612 u32 tx_deferred;
613 u32 tx_single_collisions;
614 u32 tx_multiple_collisions;
615 u32 tx_fc_pause;
616 u32 tx_tco_frames;
617
618 u32 rx_fc_pause;
619 u32 rx_fc_unsupported;
620 u32 rx_tco_frames;
621 u32 rx_over_length_errors;
622
623 u16 leds;
624 u16 eeprom_wc;
625 __le16 eeprom[256];
626 spinlock_t mdio_lock;
627 const struct firmware *fw;
628 };
629
630 static inline void e100_write_flush(struct nic *nic)
631 {
632 /* Flush previous PCI writes through intermediate bridges
633 * by doing a benign read */
634 (void)ioread8(&nic->csr->scb.status);
635 }
636
637 static void e100_enable_irq(struct nic *nic)
638 {
639 unsigned long flags;
640
641 spin_lock_irqsave(&nic->cmd_lock, flags);
642 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
643 e100_write_flush(nic);
644 spin_unlock_irqrestore(&nic->cmd_lock, flags);
645 }
646
647 static void e100_disable_irq(struct nic *nic)
648 {
649 unsigned long flags;
650
651 spin_lock_irqsave(&nic->cmd_lock, flags);
652 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
653 e100_write_flush(nic);
654 spin_unlock_irqrestore(&nic->cmd_lock, flags);
655 }
656
657 static void e100_hw_reset(struct nic *nic)
658 {
659 /* Put CU and RU into idle with a selective reset to get
660 * device off of PCI bus */
661 iowrite32(selective_reset, &nic->csr->port);
662 e100_write_flush(nic); udelay(20);
663
664 /* Now fully reset device */
665 iowrite32(software_reset, &nic->csr->port);
666 e100_write_flush(nic); udelay(20);
667
668 /* Mask off our interrupt line - it's unmasked after reset */
669 e100_disable_irq(nic);
670 }
671
672 static int e100_self_test(struct nic *nic)
673 {
674 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
675
676 /* Passing the self-test is a pretty good indication
677 * that the device can DMA to/from host memory */
678
679 nic->mem->selftest.signature = 0;
680 nic->mem->selftest.result = 0xFFFFFFFF;
681
682 iowrite32(selftest | dma_addr, &nic->csr->port);
683 e100_write_flush(nic);
684 /* Wait 10 msec for self-test to complete */
685 msleep(10);
686
687 /* Interrupts are enabled after self-test */
688 e100_disable_irq(nic);
689
690 /* Check results of self-test */
691 if (nic->mem->selftest.result != 0) {
692 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
693 nic->mem->selftest.result);
694 return -ETIMEDOUT;
695 }
696 if (nic->mem->selftest.signature == 0) {
697 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
698 return -ETIMEDOUT;
699 }
700
701 return 0;
702 }
703
704 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
705 {
706 u32 cmd_addr_data[3];
707 u8 ctrl;
708 int i, j;
709
710 /* Three cmds: write/erase enable, write data, write/erase disable */
711 cmd_addr_data[0] = op_ewen << (addr_len - 2);
712 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
713 le16_to_cpu(data);
714 cmd_addr_data[2] = op_ewds << (addr_len - 2);
715
716 /* Bit-bang cmds to write word to eeprom */
717 for (j = 0; j < 3; j++) {
718
719 /* Chip select */
720 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
721 e100_write_flush(nic); udelay(4);
722
723 for (i = 31; i >= 0; i--) {
724 ctrl = (cmd_addr_data[j] & (1 << i)) ?
725 eecs | eedi : eecs;
726 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
727 e100_write_flush(nic); udelay(4);
728
729 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
730 e100_write_flush(nic); udelay(4);
731 }
732 /* Wait 10 msec for cmd to complete */
733 msleep(10);
734
735 /* Chip deselect */
736 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
737 e100_write_flush(nic); udelay(4);
738 }
739 };
740
741 /* General technique stolen from the eepro100 driver - very clever */
742 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
743 {
744 u32 cmd_addr_data;
745 u16 data = 0;
746 u8 ctrl;
747 int i;
748
749 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
750
751 /* Chip select */
752 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
753 e100_write_flush(nic); udelay(4);
754
755 /* Bit-bang to read word from eeprom */
756 for (i = 31; i >= 0; i--) {
757 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
758 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
759 e100_write_flush(nic); udelay(4);
760
761 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
762 e100_write_flush(nic); udelay(4);
763
764 /* Eeprom drives a dummy zero to EEDO after receiving
765 * complete address. Use this to adjust addr_len. */
766 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
767 if (!(ctrl & eedo) && i > 16) {
768 *addr_len -= (i - 16);
769 i = 17;
770 }
771
772 data = (data << 1) | (ctrl & eedo ? 1 : 0);
773 }
774
775 /* Chip deselect */
776 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
777 e100_write_flush(nic); udelay(4);
778
779 return cpu_to_le16(data);
780 };
781
782 /* Load entire EEPROM image into driver cache and validate checksum */
783 static int e100_eeprom_load(struct nic *nic)
784 {
785 u16 addr, addr_len = 8, checksum = 0;
786
787 /* Try reading with an 8-bit addr len to discover actual addr len */
788 e100_eeprom_read(nic, &addr_len, 0);
789 nic->eeprom_wc = 1 << addr_len;
790
791 for (addr = 0; addr < nic->eeprom_wc; addr++) {
792 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
793 if (addr < nic->eeprom_wc - 1)
794 checksum += le16_to_cpu(nic->eeprom[addr]);
795 }
796
797 /* The checksum, stored in the last word, is calculated such that
798 * the sum of words should be 0xBABA */
799 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
800 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
801 if (!eeprom_bad_csum_allow)
802 return -EAGAIN;
803 }
804
805 return 0;
806 }
807
808 /* Save (portion of) driver EEPROM cache to device and update checksum */
809 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
810 {
811 u16 addr, addr_len = 8, checksum = 0;
812
813 /* Try reading with an 8-bit addr len to discover actual addr len */
814 e100_eeprom_read(nic, &addr_len, 0);
815 nic->eeprom_wc = 1 << addr_len;
816
817 if (start + count >= nic->eeprom_wc)
818 return -EINVAL;
819
820 for (addr = start; addr < start + count; addr++)
821 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
822
823 /* The checksum, stored in the last word, is calculated such that
824 * the sum of words should be 0xBABA */
825 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
826 checksum += le16_to_cpu(nic->eeprom[addr]);
827 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
828 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
829 nic->eeprom[nic->eeprom_wc - 1]);
830
831 return 0;
832 }
833
834 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
835 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
836 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
837 {
838 unsigned long flags;
839 unsigned int i;
840 int err = 0;
841
842 spin_lock_irqsave(&nic->cmd_lock, flags);
843
844 /* Previous command is accepted when SCB clears */
845 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
846 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
847 break;
848 cpu_relax();
849 if (unlikely(i > E100_WAIT_SCB_FAST))
850 udelay(5);
851 }
852 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
853 err = -EAGAIN;
854 goto err_unlock;
855 }
856
857 if (unlikely(cmd != cuc_resume))
858 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
859 iowrite8(cmd, &nic->csr->scb.cmd_lo);
860
861 err_unlock:
862 spin_unlock_irqrestore(&nic->cmd_lock, flags);
863
864 return err;
865 }
866
867 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
868 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
869 {
870 struct cb *cb;
871 unsigned long flags;
872 int err = 0;
873
874 spin_lock_irqsave(&nic->cb_lock, flags);
875
876 if (unlikely(!nic->cbs_avail)) {
877 err = -ENOMEM;
878 goto err_unlock;
879 }
880
881 cb = nic->cb_to_use;
882 nic->cb_to_use = cb->next;
883 nic->cbs_avail--;
884 cb->skb = skb;
885
886 if (unlikely(!nic->cbs_avail))
887 err = -ENOSPC;
888
889 cb_prepare(nic, cb, skb);
890
891 /* Order is important otherwise we'll be in a race with h/w:
892 * set S-bit in current first, then clear S-bit in previous. */
893 cb->command |= cpu_to_le16(cb_s);
894 wmb();
895 cb->prev->command &= cpu_to_le16(~cb_s);
896
897 while (nic->cb_to_send != nic->cb_to_use) {
898 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
899 nic->cb_to_send->dma_addr))) {
900 /* Ok, here's where things get sticky. It's
901 * possible that we can't schedule the command
902 * because the controller is too busy, so
903 * let's just queue the command and try again
904 * when another command is scheduled. */
905 if (err == -ENOSPC) {
906 //request a reset
907 schedule_work(&nic->tx_timeout_task);
908 }
909 break;
910 } else {
911 nic->cuc_cmd = cuc_resume;
912 nic->cb_to_send = nic->cb_to_send->next;
913 }
914 }
915
916 err_unlock:
917 spin_unlock_irqrestore(&nic->cb_lock, flags);
918
919 return err;
920 }
921
922 static int mdio_read(struct net_device *netdev, int addr, int reg)
923 {
924 struct nic *nic = netdev_priv(netdev);
925 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
926 }
927
928 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
929 {
930 struct nic *nic = netdev_priv(netdev);
931
932 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
933 }
934
935 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
936 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
937 {
938 u32 data_out = 0;
939 unsigned int i;
940 unsigned long flags;
941
942
943 /*
944 * Stratus87247: we shouldn't be writing the MDI control
945 * register until the Ready bit shows True. Also, since
946 * manipulation of the MDI control registers is a multi-step
947 * procedure it should be done under lock.
948 */
949 spin_lock_irqsave(&nic->mdio_lock, flags);
950 for (i = 100; i; --i) {
951 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
952 break;
953 udelay(20);
954 }
955 if (unlikely(!i)) {
956 printk("e100.mdio_ctrl(%s) won't go Ready\n",
957 nic->netdev->name );
958 spin_unlock_irqrestore(&nic->mdio_lock, flags);
959 return 0; /* No way to indicate timeout error */
960 }
961 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
962
963 for (i = 0; i < 100; i++) {
964 udelay(20);
965 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
966 break;
967 }
968 spin_unlock_irqrestore(&nic->mdio_lock, flags);
969 DPRINTK(HW, DEBUG,
970 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
971 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
972 return (u16)data_out;
973 }
974
975 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
976 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
977 u32 addr,
978 u32 dir,
979 u32 reg,
980 u16 data)
981 {
982 if ((reg == MII_BMCR) && (dir == mdi_write)) {
983 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
984 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
985 MII_ADVERTISE);
986
987 /*
988 * Workaround Si issue where sometimes the part will not
989 * autoneg to 100Mbps even when advertised.
990 */
991 if (advert & ADVERTISE_100FULL)
992 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
993 else if (advert & ADVERTISE_100HALF)
994 data |= BMCR_SPEED100;
995 }
996 }
997 return mdio_ctrl_hw(nic, addr, dir, reg, data);
998 }
999
1000 /* Fully software-emulated mdio_ctrl() function for cards without
1001 * MII-compliant PHYs.
1002 * For now, this is mainly geared towards 80c24 support; in case of further
1003 * requirements for other types (i82503, ...?) either extend this mechanism
1004 * or split it, whichever is cleaner.
1005 */
1006 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1007 u32 addr,
1008 u32 dir,
1009 u32 reg,
1010 u16 data)
1011 {
1012 /* might need to allocate a netdev_priv'ed register array eventually
1013 * to be able to record state changes, but for now
1014 * some fully hardcoded register handling ought to be ok I guess. */
1015
1016 if (dir == mdi_read) {
1017 switch (reg) {
1018 case MII_BMCR:
1019 /* Auto-negotiation, right? */
1020 return BMCR_ANENABLE |
1021 BMCR_FULLDPLX;
1022 case MII_BMSR:
1023 return BMSR_LSTATUS /* for mii_link_ok() */ |
1024 BMSR_ANEGCAPABLE |
1025 BMSR_10FULL;
1026 case MII_ADVERTISE:
1027 /* 80c24 is a "combo card" PHY, right? */
1028 return ADVERTISE_10HALF |
1029 ADVERTISE_10FULL;
1030 default:
1031 DPRINTK(HW, DEBUG,
1032 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1033 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1034 return 0xFFFF;
1035 }
1036 } else {
1037 switch (reg) {
1038 default:
1039 DPRINTK(HW, DEBUG,
1040 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1041 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1042 return 0xFFFF;
1043 }
1044 }
1045 }
1046 static inline int e100_phy_supports_mii(struct nic *nic)
1047 {
1048 /* for now, just check it by comparing whether we
1049 are using MII software emulation.
1050 */
1051 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1052 }
1053
1054 static void e100_get_defaults(struct nic *nic)
1055 {
1056 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1057 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1058
1059 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1060 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1061 if (nic->mac == mac_unknown)
1062 nic->mac = mac_82557_D100_A;
1063
1064 nic->params.rfds = rfds;
1065 nic->params.cbs = cbs;
1066
1067 /* Quadwords to DMA into FIFO before starting frame transmit */
1068 nic->tx_threshold = 0xE0;
1069
1070 /* no interrupt for every tx completion, delay = 256us if not 557 */
1071 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1072 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1073
1074 /* Template for a freshly allocated RFD */
1075 nic->blank_rfd.command = 0;
1076 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1077 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1078
1079 /* MII setup */
1080 nic->mii.phy_id_mask = 0x1F;
1081 nic->mii.reg_num_mask = 0x1F;
1082 nic->mii.dev = nic->netdev;
1083 nic->mii.mdio_read = mdio_read;
1084 nic->mii.mdio_write = mdio_write;
1085 }
1086
1087 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1088 {
1089 struct config *config = &cb->u.config;
1090 u8 *c = (u8 *)config;
1091
1092 cb->command = cpu_to_le16(cb_config);
1093
1094 memset(config, 0, sizeof(struct config));
1095
1096 config->byte_count = 0x16; /* bytes in this struct */
1097 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1098 config->direct_rx_dma = 0x1; /* reserved */
1099 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1100 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1101 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1102 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1103 if (e100_phy_supports_mii(nic))
1104 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1105 config->pad10 = 0x6;
1106 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1107 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1108 config->ifs = 0x6; /* x16 = inter frame spacing */
1109 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1110 config->pad15_1 = 0x1;
1111 config->pad15_2 = 0x1;
1112 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1113 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1114 config->tx_padding = 0x1; /* 1=pad short frames */
1115 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1116 config->pad18 = 0x1;
1117 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1118 config->pad20_1 = 0x1F;
1119 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1120 config->pad21_1 = 0x5;
1121
1122 config->adaptive_ifs = nic->adaptive_ifs;
1123 config->loopback = nic->loopback;
1124
1125 if (nic->mii.force_media && nic->mii.full_duplex)
1126 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1127
1128 if (nic->flags & promiscuous || nic->loopback) {
1129 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1130 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1131 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1132 }
1133
1134 if (nic->flags & multicast_all)
1135 config->multicast_all = 0x1; /* 1=accept, 0=no */
1136
1137 /* disable WoL when up */
1138 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1139 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1140
1141 if (nic->mac >= mac_82558_D101_A4) {
1142 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1143 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1144 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1145 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1146 if (nic->mac >= mac_82559_D101M) {
1147 config->tno_intr = 0x1; /* TCO stats enable */
1148 /* Enable TCO in extended config */
1149 if (nic->mac >= mac_82551_10) {
1150 config->byte_count = 0x20; /* extended bytes */
1151 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1152 }
1153 } else {
1154 config->standard_stat_counter = 0x0;
1155 }
1156 }
1157
1158 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1160 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1161 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1162 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1163 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1164 }
1165
1166 /*************************************************************************
1167 * CPUSaver parameters
1168 *
1169 * All CPUSaver parameters are 16-bit literals that are part of a
1170 * "move immediate value" instruction. By changing the value of
1171 * the literal in the instruction before the code is loaded, the
1172 * driver can change the algorithm.
1173 *
1174 * INTDELAY - This loads the dead-man timer with its initial value.
1175 * When this timer expires the interrupt is asserted, and the
1176 * timer is reset each time a new packet is received. (see
1177 * BUNDLEMAX below to set the limit on number of chained packets)
1178 * The current default is 0x600 or 1536. Experiments show that
1179 * the value should probably stay within the 0x200 - 0x1000.
1180 *
1181 * BUNDLEMAX -
1182 * This sets the maximum number of frames that will be bundled. In
1183 * some situations, such as the TCP windowing algorithm, it may be
1184 * better to limit the growth of the bundle size than let it go as
1185 * high as it can, because that could cause too much added latency.
1186 * The default is six, because this is the number of packets in the
1187 * default TCP window size. A value of 1 would make CPUSaver indicate
1188 * an interrupt for every frame received. If you do not want to put
1189 * a limit on the bundle size, set this value to xFFFF.
1190 *
1191 * BUNDLESMALL -
1192 * This contains a bit-mask describing the minimum size frame that
1193 * will be bundled. The default masks the lower 7 bits, which means
1194 * that any frame less than 128 bytes in length will not be bundled,
1195 * but will instead immediately generate an interrupt. This does
1196 * not affect the current bundle in any way. Any frame that is 128
1197 * bytes or large will be bundled normally. This feature is meant
1198 * to provide immediate indication of ACK frames in a TCP environment.
1199 * Customers were seeing poor performance when a machine with CPUSaver
1200 * enabled was sending but not receiving. The delay introduced when
1201 * the ACKs were received was enough to reduce total throughput, because
1202 * the sender would sit idle until the ACK was finally seen.
1203 *
1204 * The current default is 0xFF80, which masks out the lower 7 bits.
1205 * This means that any frame which is x7F (127) bytes or smaller
1206 * will cause an immediate interrupt. Because this value must be a
1207 * bit mask, there are only a few valid values that can be used. To
1208 * turn this feature off, the driver can write the value xFFFF to the
1209 * lower word of this instruction (in the same way that the other
1210 * parameters are used). Likewise, a value of 0xF800 (2047) would
1211 * cause an interrupt to be generated for every frame, because all
1212 * standard Ethernet frames are <= 2047 bytes in length.
1213 *************************************************************************/
1214
1215 /* if you wish to disable the ucode functionality, while maintaining the
1216 * workarounds it provides, set the following defines to:
1217 * BUNDLESMALL 0
1218 * BUNDLEMAX 1
1219 * INTDELAY 1
1220 */
1221 #define BUNDLESMALL 1
1222 #define BUNDLEMAX (u16)6
1223 #define INTDELAY (u16)1536 /* 0x600 */
1224
1225 /* Initialize firmware */
1226 static const struct firmware *e100_request_firmware(struct nic *nic)
1227 {
1228 const char *fw_name;
1229 const struct firmware *fw = nic->fw;
1230 u8 timer, bundle, min_size;
1231 int err = 0;
1232
1233 /* do not load u-code for ICH devices */
1234 if (nic->flags & ich)
1235 return NULL;
1236
1237 /* Search for ucode match against h/w revision */
1238 if (nic->mac == mac_82559_D101M)
1239 fw_name = FIRMWARE_D101M;
1240 else if (nic->mac == mac_82559_D101S)
1241 fw_name = FIRMWARE_D101S;
1242 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1243 fw_name = FIRMWARE_D102E;
1244 else /* No ucode on other devices */
1245 return NULL;
1246
1247 /* If the firmware has not previously been loaded, request a pointer
1248 * to it. If it was previously loaded, we are reinitializing the
1249 * adapter, possibly in a resume from hibernate, in which case
1250 * request_firmware() cannot be used.
1251 */
1252 if (!fw)
1253 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1254
1255 if (err) {
1256 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1257 fw_name, err);
1258 return ERR_PTR(err);
1259 }
1260
1261 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1262 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1263 if (fw->size != UCODE_SIZE * 4 + 3) {
1264 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1265 fw_name, fw->size);
1266 release_firmware(fw);
1267 return ERR_PTR(-EINVAL);
1268 }
1269
1270 /* Read timer, bundle and min_size from end of firmware blob */
1271 timer = fw->data[UCODE_SIZE * 4];
1272 bundle = fw->data[UCODE_SIZE * 4 + 1];
1273 min_size = fw->data[UCODE_SIZE * 4 + 2];
1274
1275 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1276 min_size >= UCODE_SIZE) {
1277 DPRINTK(PROBE, ERR,
1278 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1279 fw_name, timer, bundle, min_size);
1280 release_firmware(fw);
1281 return ERR_PTR(-EINVAL);
1282 }
1283
1284 /* OK, firmware is validated and ready to use. Save a pointer
1285 * to it in the nic */
1286 nic->fw = fw;
1287 return fw;
1288 }
1289
1290 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1291 struct sk_buff *skb)
1292 {
1293 const struct firmware *fw = (void *)skb;
1294 u8 timer, bundle, min_size;
1295
1296 /* It's not a real skb; we just abused the fact that e100_exec_cb
1297 will pass it through to here... */
1298 cb->skb = NULL;
1299
1300 /* firmware is stored as little endian already */
1301 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1302
1303 /* Read timer, bundle and min_size from end of firmware blob */
1304 timer = fw->data[UCODE_SIZE * 4];
1305 bundle = fw->data[UCODE_SIZE * 4 + 1];
1306 min_size = fw->data[UCODE_SIZE * 4 + 2];
1307
1308 /* Insert user-tunable settings in cb->u.ucode */
1309 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1310 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1311 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1312 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1313 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1314 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1315
1316 cb->command = cpu_to_le16(cb_ucode | cb_el);
1317 }
1318
1319 static inline int e100_load_ucode_wait(struct nic *nic)
1320 {
1321 const struct firmware *fw;
1322 int err = 0, counter = 50;
1323 struct cb *cb = nic->cb_to_clean;
1324
1325 fw = e100_request_firmware(nic);
1326 /* If it's NULL, then no ucode is required */
1327 if (!fw || IS_ERR(fw))
1328 return PTR_ERR(fw);
1329
1330 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1331 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1332
1333 /* must restart cuc */
1334 nic->cuc_cmd = cuc_start;
1335
1336 /* wait for completion */
1337 e100_write_flush(nic);
1338 udelay(10);
1339
1340 /* wait for possibly (ouch) 500ms */
1341 while (!(cb->status & cpu_to_le16(cb_complete))) {
1342 msleep(10);
1343 if (!--counter) break;
1344 }
1345
1346 /* ack any interrupts, something could have been set */
1347 iowrite8(~0, &nic->csr->scb.stat_ack);
1348
1349 /* if the command failed, or is not OK, notify and return */
1350 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1351 DPRINTK(PROBE,ERR, "ucode load failed\n");
1352 err = -EPERM;
1353 }
1354
1355 return err;
1356 }
1357
1358 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1359 struct sk_buff *skb)
1360 {
1361 cb->command = cpu_to_le16(cb_iaaddr);
1362 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1363 }
1364
1365 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1366 {
1367 cb->command = cpu_to_le16(cb_dump);
1368 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1369 offsetof(struct mem, dump_buf));
1370 }
1371
1372 static int e100_phy_check_without_mii(struct nic *nic)
1373 {
1374 u8 phy_type;
1375 int without_mii;
1376
1377 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1378
1379 switch (phy_type) {
1380 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1381 case I82503: /* Non-MII PHY; UNTESTED! */
1382 case S80C24: /* Non-MII PHY; tested and working */
1383 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1384 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1385 * doesn't have a programming interface of any sort. The
1386 * media is sensed automatically based on how the link partner
1387 * is configured. This is, in essence, manual configuration.
1388 */
1389 DPRINTK(PROBE, INFO,
1390 "found MII-less i82503 or 80c24 or other PHY\n");
1391
1392 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1393 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1394
1395 /* these might be needed for certain MII-less cards...
1396 * nic->flags |= ich;
1397 * nic->flags |= ich_10h_workaround; */
1398
1399 without_mii = 1;
1400 break;
1401 default:
1402 without_mii = 0;
1403 break;
1404 }
1405 return without_mii;
1406 }
1407
1408 #define NCONFIG_AUTO_SWITCH 0x0080
1409 #define MII_NSC_CONG MII_RESV1
1410 #define NSC_CONG_ENABLE 0x0100
1411 #define NSC_CONG_TXREADY 0x0400
1412 #define ADVERTISE_FC_SUPPORTED 0x0400
1413 static int e100_phy_init(struct nic *nic)
1414 {
1415 struct net_device *netdev = nic->netdev;
1416 u32 addr;
1417 u16 bmcr, stat, id_lo, id_hi, cong;
1418
1419 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1420 for (addr = 0; addr < 32; addr++) {
1421 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1422 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1423 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1424 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1425 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1426 break;
1427 }
1428 if (addr == 32) {
1429 /* uhoh, no PHY detected: check whether we seem to be some
1430 * weird, rare variant which is *known* to not have any MII.
1431 * But do this AFTER MII checking only, since this does
1432 * lookup of EEPROM values which may easily be unreliable. */
1433 if (e100_phy_check_without_mii(nic))
1434 return 0; /* simply return and hope for the best */
1435 else {
1436 /* for unknown cases log a fatal error */
1437 DPRINTK(HW, ERR,
1438 "Failed to locate any known PHY, aborting.\n");
1439 return -EAGAIN;
1440 }
1441 } else
1442 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1443
1444 /* Get phy ID */
1445 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1446 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1447 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1448 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1449
1450 /* Select the phy and isolate the rest */
1451 for (addr = 0; addr < 32; addr++) {
1452 if (addr != nic->mii.phy_id) {
1453 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1454 } else if (nic->phy != phy_82552_v) {
1455 bmcr = mdio_read(netdev, addr, MII_BMCR);
1456 mdio_write(netdev, addr, MII_BMCR,
1457 bmcr & ~BMCR_ISOLATE);
1458 }
1459 }
1460 /*
1461 * Workaround for 82552:
1462 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1463 * other phy_id's) using bmcr value from addr discovery loop above.
1464 */
1465 if (nic->phy == phy_82552_v)
1466 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1467 bmcr & ~BMCR_ISOLATE);
1468
1469 /* Handle National tx phys */
1470 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1471 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1472 /* Disable congestion control */
1473 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1474 cong |= NSC_CONG_TXREADY;
1475 cong &= ~NSC_CONG_ENABLE;
1476 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1477 }
1478
1479 if (nic->phy == phy_82552_v) {
1480 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1481
1482 /* assign special tweaked mdio_ctrl() function */
1483 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1484
1485 /* Workaround Si not advertising flow-control during autoneg */
1486 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1488
1489 /* Reset for the above changes to take effect */
1490 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1491 bmcr |= BMCR_RESET;
1492 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1493 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1494 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1495 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1496 /* enable/disable MDI/MDI-X auto-switching. */
1497 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1498 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1499 }
1500
1501 return 0;
1502 }
1503
1504 static int e100_hw_init(struct nic *nic)
1505 {
1506 int err;
1507
1508 e100_hw_reset(nic);
1509
1510 DPRINTK(HW, ERR, "e100_hw_init\n");
1511 if (!in_interrupt() && (err = e100_self_test(nic)))
1512 return err;
1513
1514 if ((err = e100_phy_init(nic)))
1515 return err;
1516 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1517 return err;
1518 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1519 return err;
1520 if ((err = e100_load_ucode_wait(nic)))
1521 return err;
1522 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1523 return err;
1524 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1525 return err;
1526 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1527 nic->dma_addr + offsetof(struct mem, stats))))
1528 return err;
1529 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1530 return err;
1531
1532 e100_disable_irq(nic);
1533
1534 return 0;
1535 }
1536
1537 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1538 {
1539 struct net_device *netdev = nic->netdev;
1540 struct dev_mc_list *list = netdev->mc_list;
1541 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1542
1543 cb->command = cpu_to_le16(cb_multi);
1544 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1545 for (i = 0; list && i < count; i++, list = list->next)
1546 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1547 ETH_ALEN);
1548 }
1549
1550 static void e100_set_multicast_list(struct net_device *netdev)
1551 {
1552 struct nic *nic = netdev_priv(netdev);
1553
1554 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1555 netdev->mc_count, netdev->flags);
1556
1557 if (netdev->flags & IFF_PROMISC)
1558 nic->flags |= promiscuous;
1559 else
1560 nic->flags &= ~promiscuous;
1561
1562 if (netdev->flags & IFF_ALLMULTI ||
1563 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1564 nic->flags |= multicast_all;
1565 else
1566 nic->flags &= ~multicast_all;
1567
1568 e100_exec_cb(nic, NULL, e100_configure);
1569 e100_exec_cb(nic, NULL, e100_multi);
1570 }
1571
1572 static void e100_update_stats(struct nic *nic)
1573 {
1574 struct net_device *dev = nic->netdev;
1575 struct net_device_stats *ns = &dev->stats;
1576 struct stats *s = &nic->mem->stats;
1577 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1578 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1579 &s->complete;
1580
1581 /* Device's stats reporting may take several microseconds to
1582 * complete, so we're always waiting for results of the
1583 * previous command. */
1584
1585 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1586 *complete = 0;
1587 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1588 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1589 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1590 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1591 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1592 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1593 ns->collisions += nic->tx_collisions;
1594 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1595 le32_to_cpu(s->tx_lost_crs);
1596 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1597 nic->rx_over_length_errors;
1598 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1599 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1600 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1601 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1602 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1603 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1604 le32_to_cpu(s->rx_alignment_errors) +
1605 le32_to_cpu(s->rx_short_frame_errors) +
1606 le32_to_cpu(s->rx_cdt_errors);
1607 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1608 nic->tx_single_collisions +=
1609 le32_to_cpu(s->tx_single_collisions);
1610 nic->tx_multiple_collisions +=
1611 le32_to_cpu(s->tx_multiple_collisions);
1612 if (nic->mac >= mac_82558_D101_A4) {
1613 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1614 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1615 nic->rx_fc_unsupported +=
1616 le32_to_cpu(s->fc_rcv_unsupported);
1617 if (nic->mac >= mac_82559_D101M) {
1618 nic->tx_tco_frames +=
1619 le16_to_cpu(s->xmt_tco_frames);
1620 nic->rx_tco_frames +=
1621 le16_to_cpu(s->rcv_tco_frames);
1622 }
1623 }
1624 }
1625
1626
1627 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1628 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1629 }
1630
1631 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1632 {
1633 /* Adjust inter-frame-spacing (IFS) between two transmits if
1634 * we're getting collisions on a half-duplex connection. */
1635
1636 if (duplex == DUPLEX_HALF) {
1637 u32 prev = nic->adaptive_ifs;
1638 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1639
1640 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1641 (nic->tx_frames > min_frames)) {
1642 if (nic->adaptive_ifs < 60)
1643 nic->adaptive_ifs += 5;
1644 } else if (nic->tx_frames < min_frames) {
1645 if (nic->adaptive_ifs >= 5)
1646 nic->adaptive_ifs -= 5;
1647 }
1648 if (nic->adaptive_ifs != prev)
1649 e100_exec_cb(nic, NULL, e100_configure);
1650 }
1651 }
1652
1653 static void e100_watchdog(unsigned long data)
1654 {
1655 struct nic *nic = (struct nic *)data;
1656 struct ethtool_cmd cmd;
1657
1658 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1659
1660 /* mii library handles link maintenance tasks */
1661
1662 mii_ethtool_gset(&nic->mii, &cmd);
1663
1664 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1665 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1666 nic->netdev->name,
1667 cmd.speed == SPEED_100 ? "100" : "10",
1668 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1669 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1670 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1671 nic->netdev->name);
1672 }
1673
1674 mii_check_link(&nic->mii);
1675
1676 /* Software generated interrupt to recover from (rare) Rx
1677 * allocation failure.
1678 * Unfortunately have to use a spinlock to not re-enable interrupts
1679 * accidentally, due to hardware that shares a register between the
1680 * interrupt mask bit and the SW Interrupt generation bit */
1681 spin_lock_irq(&nic->cmd_lock);
1682 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1683 e100_write_flush(nic);
1684 spin_unlock_irq(&nic->cmd_lock);
1685
1686 e100_update_stats(nic);
1687 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1688
1689 if (nic->mac <= mac_82557_D100_C)
1690 /* Issue a multicast command to workaround a 557 lock up */
1691 e100_set_multicast_list(nic->netdev);
1692
1693 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1694 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1695 nic->flags |= ich_10h_workaround;
1696 else
1697 nic->flags &= ~ich_10h_workaround;
1698
1699 mod_timer(&nic->watchdog,
1700 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1701 }
1702
1703 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1704 struct sk_buff *skb)
1705 {
1706 cb->command = nic->tx_command;
1707 /* interrupt every 16 packets regardless of delay */
1708 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1709 cb->command |= cpu_to_le16(cb_i);
1710 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1711 cb->u.tcb.tcb_byte_count = 0;
1712 cb->u.tcb.threshold = nic->tx_threshold;
1713 cb->u.tcb.tbd_count = 1;
1714 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1715 skb->data, skb->len, PCI_DMA_TODEVICE));
1716 /* check for mapping failure? */
1717 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1718 }
1719
1720 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1721 struct net_device *netdev)
1722 {
1723 struct nic *nic = netdev_priv(netdev);
1724 int err;
1725
1726 if (nic->flags & ich_10h_workaround) {
1727 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1728 Issue a NOP command followed by a 1us delay before
1729 issuing the Tx command. */
1730 if (e100_exec_cmd(nic, cuc_nop, 0))
1731 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1732 udelay(1);
1733 }
1734
1735 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1736
1737 switch (err) {
1738 case -ENOSPC:
1739 /* We queued the skb, but now we're out of space. */
1740 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1741 netif_stop_queue(netdev);
1742 break;
1743 case -ENOMEM:
1744 /* This is a hard error - log it. */
1745 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1746 netif_stop_queue(netdev);
1747 return NETDEV_TX_BUSY;
1748 }
1749
1750 netdev->trans_start = jiffies;
1751 return NETDEV_TX_OK;
1752 }
1753
1754 static int e100_tx_clean(struct nic *nic)
1755 {
1756 struct net_device *dev = nic->netdev;
1757 struct cb *cb;
1758 int tx_cleaned = 0;
1759
1760 spin_lock(&nic->cb_lock);
1761
1762 /* Clean CBs marked complete */
1763 for (cb = nic->cb_to_clean;
1764 cb->status & cpu_to_le16(cb_complete);
1765 cb = nic->cb_to_clean = cb->next) {
1766 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1767 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1768 cb->status);
1769
1770 if (likely(cb->skb != NULL)) {
1771 dev->stats.tx_packets++;
1772 dev->stats.tx_bytes += cb->skb->len;
1773
1774 pci_unmap_single(nic->pdev,
1775 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1776 le16_to_cpu(cb->u.tcb.tbd.size),
1777 PCI_DMA_TODEVICE);
1778 dev_kfree_skb_any(cb->skb);
1779 cb->skb = NULL;
1780 tx_cleaned = 1;
1781 }
1782 cb->status = 0;
1783 nic->cbs_avail++;
1784 }
1785
1786 spin_unlock(&nic->cb_lock);
1787
1788 /* Recover from running out of Tx resources in xmit_frame */
1789 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1790 netif_wake_queue(nic->netdev);
1791
1792 return tx_cleaned;
1793 }
1794
1795 static void e100_clean_cbs(struct nic *nic)
1796 {
1797 if (nic->cbs) {
1798 while (nic->cbs_avail != nic->params.cbs.count) {
1799 struct cb *cb = nic->cb_to_clean;
1800 if (cb->skb) {
1801 pci_unmap_single(nic->pdev,
1802 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1803 le16_to_cpu(cb->u.tcb.tbd.size),
1804 PCI_DMA_TODEVICE);
1805 dev_kfree_skb(cb->skb);
1806 }
1807 nic->cb_to_clean = nic->cb_to_clean->next;
1808 nic->cbs_avail++;
1809 }
1810 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1811 nic->cbs = NULL;
1812 nic->cbs_avail = 0;
1813 }
1814 nic->cuc_cmd = cuc_start;
1815 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1816 nic->cbs;
1817 }
1818
1819 static int e100_alloc_cbs(struct nic *nic)
1820 {
1821 struct cb *cb;
1822 unsigned int i, count = nic->params.cbs.count;
1823
1824 nic->cuc_cmd = cuc_start;
1825 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1826 nic->cbs_avail = 0;
1827
1828 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1829 &nic->cbs_dma_addr);
1830 if (!nic->cbs)
1831 return -ENOMEM;
1832
1833 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1834 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1835 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1836
1837 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1838 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1839 ((i+1) % count) * sizeof(struct cb));
1840 cb->skb = NULL;
1841 }
1842
1843 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1844 nic->cbs_avail = count;
1845
1846 return 0;
1847 }
1848
1849 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1850 {
1851 if (!nic->rxs) return;
1852 if (RU_SUSPENDED != nic->ru_running) return;
1853
1854 /* handle init time starts */
1855 if (!rx) rx = nic->rxs;
1856
1857 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1858 if (rx->skb) {
1859 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1860 nic->ru_running = RU_RUNNING;
1861 }
1862 }
1863
1864 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1865 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1866 {
1867 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1868 return -ENOMEM;
1869
1870 /* Init, and map the RFD. */
1871 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1872 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1873 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1874
1875 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1876 dev_kfree_skb_any(rx->skb);
1877 rx->skb = NULL;
1878 rx->dma_addr = 0;
1879 return -ENOMEM;
1880 }
1881
1882 /* Link the RFD to end of RFA by linking previous RFD to
1883 * this one. We are safe to touch the previous RFD because
1884 * it is protected by the before last buffer's el bit being set */
1885 if (rx->prev->skb) {
1886 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1887 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1888 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1889 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1890 }
1891
1892 return 0;
1893 }
1894
1895 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1896 unsigned int *work_done, unsigned int work_to_do)
1897 {
1898 struct net_device *dev = nic->netdev;
1899 struct sk_buff *skb = rx->skb;
1900 struct rfd *rfd = (struct rfd *)skb->data;
1901 u16 rfd_status, actual_size;
1902
1903 if (unlikely(work_done && *work_done >= work_to_do))
1904 return -EAGAIN;
1905
1906 /* Need to sync before taking a peek at cb_complete bit */
1907 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1908 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1909 rfd_status = le16_to_cpu(rfd->status);
1910
1911 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1912
1913 /* If data isn't ready, nothing to indicate */
1914 if (unlikely(!(rfd_status & cb_complete))) {
1915 /* If the next buffer has the el bit, but we think the receiver
1916 * is still running, check to see if it really stopped while
1917 * we had interrupts off.
1918 * This allows for a fast restart without re-enabling
1919 * interrupts */
1920 if ((le16_to_cpu(rfd->command) & cb_el) &&
1921 (RU_RUNNING == nic->ru_running))
1922
1923 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1924 nic->ru_running = RU_SUSPENDED;
1925 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1926 sizeof(struct rfd),
1927 PCI_DMA_FROMDEVICE);
1928 return -ENODATA;
1929 }
1930
1931 /* Get actual data size */
1932 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1933 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1934 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1935
1936 /* Get data */
1937 pci_unmap_single(nic->pdev, rx->dma_addr,
1938 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1939
1940 /* If this buffer has the el bit, but we think the receiver
1941 * is still running, check to see if it really stopped while
1942 * we had interrupts off.
1943 * This allows for a fast restart without re-enabling interrupts.
1944 * This can happen when the RU sees the size change but also sees
1945 * the el bit set. */
1946 if ((le16_to_cpu(rfd->command) & cb_el) &&
1947 (RU_RUNNING == nic->ru_running)) {
1948
1949 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1950 nic->ru_running = RU_SUSPENDED;
1951 }
1952
1953 /* Pull off the RFD and put the actual data (minus eth hdr) */
1954 skb_reserve(skb, sizeof(struct rfd));
1955 skb_put(skb, actual_size);
1956 skb->protocol = eth_type_trans(skb, nic->netdev);
1957
1958 if (unlikely(!(rfd_status & cb_ok))) {
1959 /* Don't indicate if hardware indicates errors */
1960 dev_kfree_skb_any(skb);
1961 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1962 /* Don't indicate oversized frames */
1963 nic->rx_over_length_errors++;
1964 dev_kfree_skb_any(skb);
1965 } else {
1966 dev->stats.rx_packets++;
1967 dev->stats.rx_bytes += actual_size;
1968 netif_receive_skb(skb);
1969 if (work_done)
1970 (*work_done)++;
1971 }
1972
1973 rx->skb = NULL;
1974
1975 return 0;
1976 }
1977
1978 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1979 unsigned int work_to_do)
1980 {
1981 struct rx *rx;
1982 int restart_required = 0, err = 0;
1983 struct rx *old_before_last_rx, *new_before_last_rx;
1984 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1985
1986 /* Indicate newly arrived packets */
1987 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1988 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1989 /* Hit quota or no more to clean */
1990 if (-EAGAIN == err || -ENODATA == err)
1991 break;
1992 }
1993
1994
1995 /* On EAGAIN, hit quota so have more work to do, restart once
1996 * cleanup is complete.
1997 * Else, are we already rnr? then pay attention!!! this ensures that
1998 * the state machine progression never allows a start with a
1999 * partially cleaned list, avoiding a race between hardware
2000 * and rx_to_clean when in NAPI mode */
2001 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2002 restart_required = 1;
2003
2004 old_before_last_rx = nic->rx_to_use->prev->prev;
2005 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2006
2007 /* Alloc new skbs to refill list */
2008 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2009 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2010 break; /* Better luck next time (see watchdog) */
2011 }
2012
2013 new_before_last_rx = nic->rx_to_use->prev->prev;
2014 if (new_before_last_rx != old_before_last_rx) {
2015 /* Set the el-bit on the buffer that is before the last buffer.
2016 * This lets us update the next pointer on the last buffer
2017 * without worrying about hardware touching it.
2018 * We set the size to 0 to prevent hardware from touching this
2019 * buffer.
2020 * When the hardware hits the before last buffer with el-bit
2021 * and size of 0, it will RNR interrupt, the RUS will go into
2022 * the No Resources state. It will not complete nor write to
2023 * this buffer. */
2024 new_before_last_rfd =
2025 (struct rfd *)new_before_last_rx->skb->data;
2026 new_before_last_rfd->size = 0;
2027 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2028 pci_dma_sync_single_for_device(nic->pdev,
2029 new_before_last_rx->dma_addr, sizeof(struct rfd),
2030 PCI_DMA_BIDIRECTIONAL);
2031
2032 /* Now that we have a new stopping point, we can clear the old
2033 * stopping point. We must sync twice to get the proper
2034 * ordering on the hardware side of things. */
2035 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2036 pci_dma_sync_single_for_device(nic->pdev,
2037 old_before_last_rx->dma_addr, sizeof(struct rfd),
2038 PCI_DMA_BIDIRECTIONAL);
2039 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2040 pci_dma_sync_single_for_device(nic->pdev,
2041 old_before_last_rx->dma_addr, sizeof(struct rfd),
2042 PCI_DMA_BIDIRECTIONAL);
2043 }
2044
2045 if (restart_required) {
2046 // ack the rnr?
2047 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2048 e100_start_receiver(nic, nic->rx_to_clean);
2049 if (work_done)
2050 (*work_done)++;
2051 }
2052 }
2053
2054 static void e100_rx_clean_list(struct nic *nic)
2055 {
2056 struct rx *rx;
2057 unsigned int i, count = nic->params.rfds.count;
2058
2059 nic->ru_running = RU_UNINITIALIZED;
2060
2061 if (nic->rxs) {
2062 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2063 if (rx->skb) {
2064 pci_unmap_single(nic->pdev, rx->dma_addr,
2065 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2066 dev_kfree_skb(rx->skb);
2067 }
2068 }
2069 kfree(nic->rxs);
2070 nic->rxs = NULL;
2071 }
2072
2073 nic->rx_to_use = nic->rx_to_clean = NULL;
2074 }
2075
2076 static int e100_rx_alloc_list(struct nic *nic)
2077 {
2078 struct rx *rx;
2079 unsigned int i, count = nic->params.rfds.count;
2080 struct rfd *before_last;
2081
2082 nic->rx_to_use = nic->rx_to_clean = NULL;
2083 nic->ru_running = RU_UNINITIALIZED;
2084
2085 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2086 return -ENOMEM;
2087
2088 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2089 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2090 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2091 if (e100_rx_alloc_skb(nic, rx)) {
2092 e100_rx_clean_list(nic);
2093 return -ENOMEM;
2094 }
2095 }
2096 /* Set the el-bit on the buffer that is before the last buffer.
2097 * This lets us update the next pointer on the last buffer without
2098 * worrying about hardware touching it.
2099 * We set the size to 0 to prevent hardware from touching this buffer.
2100 * When the hardware hits the before last buffer with el-bit and size
2101 * of 0, it will RNR interrupt, the RU will go into the No Resources
2102 * state. It will not complete nor write to this buffer. */
2103 rx = nic->rxs->prev->prev;
2104 before_last = (struct rfd *)rx->skb->data;
2105 before_last->command |= cpu_to_le16(cb_el);
2106 before_last->size = 0;
2107 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2108 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2109
2110 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2111 nic->ru_running = RU_SUSPENDED;
2112
2113 return 0;
2114 }
2115
2116 static irqreturn_t e100_intr(int irq, void *dev_id)
2117 {
2118 struct net_device *netdev = dev_id;
2119 struct nic *nic = netdev_priv(netdev);
2120 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2121
2122 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2123
2124 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2125 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2126 return IRQ_NONE;
2127
2128 /* Ack interrupt(s) */
2129 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2130
2131 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2132 if (stat_ack & stat_ack_rnr)
2133 nic->ru_running = RU_SUSPENDED;
2134
2135 if (likely(napi_schedule_prep(&nic->napi))) {
2136 e100_disable_irq(nic);
2137 __napi_schedule(&nic->napi);
2138 }
2139
2140 return IRQ_HANDLED;
2141 }
2142
2143 static int e100_poll(struct napi_struct *napi, int budget)
2144 {
2145 struct nic *nic = container_of(napi, struct nic, napi);
2146 unsigned int work_done = 0;
2147
2148 e100_rx_clean(nic, &work_done, budget);
2149 e100_tx_clean(nic);
2150
2151 /* If budget not fully consumed, exit the polling mode */
2152 if (work_done < budget) {
2153 napi_complete(napi);
2154 e100_enable_irq(nic);
2155 }
2156
2157 return work_done;
2158 }
2159
2160 #ifdef CONFIG_NET_POLL_CONTROLLER
2161 static void e100_netpoll(struct net_device *netdev)
2162 {
2163 struct nic *nic = netdev_priv(netdev);
2164
2165 e100_disable_irq(nic);
2166 e100_intr(nic->pdev->irq, netdev);
2167 e100_tx_clean(nic);
2168 e100_enable_irq(nic);
2169 }
2170 #endif
2171
2172 static int e100_set_mac_address(struct net_device *netdev, void *p)
2173 {
2174 struct nic *nic = netdev_priv(netdev);
2175 struct sockaddr *addr = p;
2176
2177 if (!is_valid_ether_addr(addr->sa_data))
2178 return -EADDRNOTAVAIL;
2179
2180 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2181 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2182
2183 return 0;
2184 }
2185
2186 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2187 {
2188 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2189 return -EINVAL;
2190 netdev->mtu = new_mtu;
2191 return 0;
2192 }
2193
2194 static int e100_asf(struct nic *nic)
2195 {
2196 /* ASF can be enabled from eeprom */
2197 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2198 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2199 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2200 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2201 }
2202
2203 static int e100_up(struct nic *nic)
2204 {
2205 int err;
2206
2207 if ((err = e100_rx_alloc_list(nic)))
2208 return err;
2209 if ((err = e100_alloc_cbs(nic)))
2210 goto err_rx_clean_list;
2211 if ((err = e100_hw_init(nic)))
2212 goto err_clean_cbs;
2213 e100_set_multicast_list(nic->netdev);
2214 e100_start_receiver(nic, NULL);
2215 mod_timer(&nic->watchdog, jiffies);
2216 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2217 nic->netdev->name, nic->netdev)))
2218 goto err_no_irq;
2219 netif_wake_queue(nic->netdev);
2220 napi_enable(&nic->napi);
2221 /* enable ints _after_ enabling poll, preventing a race between
2222 * disable ints+schedule */
2223 e100_enable_irq(nic);
2224 return 0;
2225
2226 err_no_irq:
2227 del_timer_sync(&nic->watchdog);
2228 err_clean_cbs:
2229 e100_clean_cbs(nic);
2230 err_rx_clean_list:
2231 e100_rx_clean_list(nic);
2232 return err;
2233 }
2234
2235 static void e100_down(struct nic *nic)
2236 {
2237 /* wait here for poll to complete */
2238 napi_disable(&nic->napi);
2239 netif_stop_queue(nic->netdev);
2240 e100_hw_reset(nic);
2241 free_irq(nic->pdev->irq, nic->netdev);
2242 del_timer_sync(&nic->watchdog);
2243 netif_carrier_off(nic->netdev);
2244 e100_clean_cbs(nic);
2245 e100_rx_clean_list(nic);
2246 }
2247
2248 static void e100_tx_timeout(struct net_device *netdev)
2249 {
2250 struct nic *nic = netdev_priv(netdev);
2251
2252 /* Reset outside of interrupt context, to avoid request_irq
2253 * in interrupt context */
2254 schedule_work(&nic->tx_timeout_task);
2255 }
2256
2257 static void e100_tx_timeout_task(struct work_struct *work)
2258 {
2259 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2260 struct net_device *netdev = nic->netdev;
2261
2262 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2263 ioread8(&nic->csr->scb.status));
2264 e100_down(netdev_priv(netdev));
2265 e100_up(netdev_priv(netdev));
2266 }
2267
2268 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2269 {
2270 int err;
2271 struct sk_buff *skb;
2272
2273 /* Use driver resources to perform internal MAC or PHY
2274 * loopback test. A single packet is prepared and transmitted
2275 * in loopback mode, and the test passes if the received
2276 * packet compares byte-for-byte to the transmitted packet. */
2277
2278 if ((err = e100_rx_alloc_list(nic)))
2279 return err;
2280 if ((err = e100_alloc_cbs(nic)))
2281 goto err_clean_rx;
2282
2283 /* ICH PHY loopback is broken so do MAC loopback instead */
2284 if (nic->flags & ich && loopback_mode == lb_phy)
2285 loopback_mode = lb_mac;
2286
2287 nic->loopback = loopback_mode;
2288 if ((err = e100_hw_init(nic)))
2289 goto err_loopback_none;
2290
2291 if (loopback_mode == lb_phy)
2292 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2293 BMCR_LOOPBACK);
2294
2295 e100_start_receiver(nic, NULL);
2296
2297 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2298 err = -ENOMEM;
2299 goto err_loopback_none;
2300 }
2301 skb_put(skb, ETH_DATA_LEN);
2302 memset(skb->data, 0xFF, ETH_DATA_LEN);
2303 e100_xmit_frame(skb, nic->netdev);
2304
2305 msleep(10);
2306
2307 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2308 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2309
2310 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2311 skb->data, ETH_DATA_LEN))
2312 err = -EAGAIN;
2313
2314 err_loopback_none:
2315 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2316 nic->loopback = lb_none;
2317 e100_clean_cbs(nic);
2318 e100_hw_reset(nic);
2319 err_clean_rx:
2320 e100_rx_clean_list(nic);
2321 return err;
2322 }
2323
2324 #define MII_LED_CONTROL 0x1B
2325 #define E100_82552_LED_OVERRIDE 0x19
2326 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2327 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2328 static void e100_blink_led(unsigned long data)
2329 {
2330 struct nic *nic = (struct nic *)data;
2331 enum led_state {
2332 led_on = 0x01,
2333 led_off = 0x04,
2334 led_on_559 = 0x05,
2335 led_on_557 = 0x07,
2336 };
2337 u16 led_reg = MII_LED_CONTROL;
2338
2339 if (nic->phy == phy_82552_v) {
2340 led_reg = E100_82552_LED_OVERRIDE;
2341
2342 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2343 E100_82552_LED_OFF : E100_82552_LED_ON;
2344 } else {
2345 nic->leds = (nic->leds & led_on) ? led_off :
2346 (nic->mac < mac_82559_D101M) ? led_on_557 :
2347 led_on_559;
2348 }
2349 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2350 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2351 }
2352
2353 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2354 {
2355 struct nic *nic = netdev_priv(netdev);
2356 return mii_ethtool_gset(&nic->mii, cmd);
2357 }
2358
2359 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2360 {
2361 struct nic *nic = netdev_priv(netdev);
2362 int err;
2363
2364 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2365 err = mii_ethtool_sset(&nic->mii, cmd);
2366 e100_exec_cb(nic, NULL, e100_configure);
2367
2368 return err;
2369 }
2370
2371 static void e100_get_drvinfo(struct net_device *netdev,
2372 struct ethtool_drvinfo *info)
2373 {
2374 struct nic *nic = netdev_priv(netdev);
2375 strcpy(info->driver, DRV_NAME);
2376 strcpy(info->version, DRV_VERSION);
2377 strcpy(info->fw_version, "N/A");
2378 strcpy(info->bus_info, pci_name(nic->pdev));
2379 }
2380
2381 #define E100_PHY_REGS 0x1C
2382 static int e100_get_regs_len(struct net_device *netdev)
2383 {
2384 struct nic *nic = netdev_priv(netdev);
2385 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2386 }
2387
2388 static void e100_get_regs(struct net_device *netdev,
2389 struct ethtool_regs *regs, void *p)
2390 {
2391 struct nic *nic = netdev_priv(netdev);
2392 u32 *buff = p;
2393 int i;
2394
2395 regs->version = (1 << 24) | nic->pdev->revision;
2396 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2397 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2398 ioread16(&nic->csr->scb.status);
2399 for (i = E100_PHY_REGS; i >= 0; i--)
2400 buff[1 + E100_PHY_REGS - i] =
2401 mdio_read(netdev, nic->mii.phy_id, i);
2402 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2403 e100_exec_cb(nic, NULL, e100_dump);
2404 msleep(10);
2405 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2406 sizeof(nic->mem->dump_buf));
2407 }
2408
2409 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2410 {
2411 struct nic *nic = netdev_priv(netdev);
2412 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2413 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2414 }
2415
2416 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2417 {
2418 struct nic *nic = netdev_priv(netdev);
2419
2420 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2421 !device_can_wakeup(&nic->pdev->dev))
2422 return -EOPNOTSUPP;
2423
2424 if (wol->wolopts)
2425 nic->flags |= wol_magic;
2426 else
2427 nic->flags &= ~wol_magic;
2428
2429 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2430
2431 e100_exec_cb(nic, NULL, e100_configure);
2432
2433 return 0;
2434 }
2435
2436 static u32 e100_get_msglevel(struct net_device *netdev)
2437 {
2438 struct nic *nic = netdev_priv(netdev);
2439 return nic->msg_enable;
2440 }
2441
2442 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2443 {
2444 struct nic *nic = netdev_priv(netdev);
2445 nic->msg_enable = value;
2446 }
2447
2448 static int e100_nway_reset(struct net_device *netdev)
2449 {
2450 struct nic *nic = netdev_priv(netdev);
2451 return mii_nway_restart(&nic->mii);
2452 }
2453
2454 static u32 e100_get_link(struct net_device *netdev)
2455 {
2456 struct nic *nic = netdev_priv(netdev);
2457 return mii_link_ok(&nic->mii);
2458 }
2459
2460 static int e100_get_eeprom_len(struct net_device *netdev)
2461 {
2462 struct nic *nic = netdev_priv(netdev);
2463 return nic->eeprom_wc << 1;
2464 }
2465
2466 #define E100_EEPROM_MAGIC 0x1234
2467 static int e100_get_eeprom(struct net_device *netdev,
2468 struct ethtool_eeprom *eeprom, u8 *bytes)
2469 {
2470 struct nic *nic = netdev_priv(netdev);
2471
2472 eeprom->magic = E100_EEPROM_MAGIC;
2473 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2474
2475 return 0;
2476 }
2477
2478 static int e100_set_eeprom(struct net_device *netdev,
2479 struct ethtool_eeprom *eeprom, u8 *bytes)
2480 {
2481 struct nic *nic = netdev_priv(netdev);
2482
2483 if (eeprom->magic != E100_EEPROM_MAGIC)
2484 return -EINVAL;
2485
2486 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2487
2488 return e100_eeprom_save(nic, eeprom->offset >> 1,
2489 (eeprom->len >> 1) + 1);
2490 }
2491
2492 static void e100_get_ringparam(struct net_device *netdev,
2493 struct ethtool_ringparam *ring)
2494 {
2495 struct nic *nic = netdev_priv(netdev);
2496 struct param_range *rfds = &nic->params.rfds;
2497 struct param_range *cbs = &nic->params.cbs;
2498
2499 ring->rx_max_pending = rfds->max;
2500 ring->tx_max_pending = cbs->max;
2501 ring->rx_mini_max_pending = 0;
2502 ring->rx_jumbo_max_pending = 0;
2503 ring->rx_pending = rfds->count;
2504 ring->tx_pending = cbs->count;
2505 ring->rx_mini_pending = 0;
2506 ring->rx_jumbo_pending = 0;
2507 }
2508
2509 static int e100_set_ringparam(struct net_device *netdev,
2510 struct ethtool_ringparam *ring)
2511 {
2512 struct nic *nic = netdev_priv(netdev);
2513 struct param_range *rfds = &nic->params.rfds;
2514 struct param_range *cbs = &nic->params.cbs;
2515
2516 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2517 return -EINVAL;
2518
2519 if (netif_running(netdev))
2520 e100_down(nic);
2521 rfds->count = max(ring->rx_pending, rfds->min);
2522 rfds->count = min(rfds->count, rfds->max);
2523 cbs->count = max(ring->tx_pending, cbs->min);
2524 cbs->count = min(cbs->count, cbs->max);
2525 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2526 rfds->count, cbs->count);
2527 if (netif_running(netdev))
2528 e100_up(nic);
2529
2530 return 0;
2531 }
2532
2533 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2534 "Link test (on/offline)",
2535 "Eeprom test (on/offline)",
2536 "Self test (offline)",
2537 "Mac loopback (offline)",
2538 "Phy loopback (offline)",
2539 };
2540 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2541
2542 static void e100_diag_test(struct net_device *netdev,
2543 struct ethtool_test *test, u64 *data)
2544 {
2545 struct ethtool_cmd cmd;
2546 struct nic *nic = netdev_priv(netdev);
2547 int i, err;
2548
2549 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2550 data[0] = !mii_link_ok(&nic->mii);
2551 data[1] = e100_eeprom_load(nic);
2552 if (test->flags & ETH_TEST_FL_OFFLINE) {
2553
2554 /* save speed, duplex & autoneg settings */
2555 err = mii_ethtool_gset(&nic->mii, &cmd);
2556
2557 if (netif_running(netdev))
2558 e100_down(nic);
2559 data[2] = e100_self_test(nic);
2560 data[3] = e100_loopback_test(nic, lb_mac);
2561 data[4] = e100_loopback_test(nic, lb_phy);
2562
2563 /* restore speed, duplex & autoneg settings */
2564 err = mii_ethtool_sset(&nic->mii, &cmd);
2565
2566 if (netif_running(netdev))
2567 e100_up(nic);
2568 }
2569 for (i = 0; i < E100_TEST_LEN; i++)
2570 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2571
2572 msleep_interruptible(4 * 1000);
2573 }
2574
2575 static int e100_phys_id(struct net_device *netdev, u32 data)
2576 {
2577 struct nic *nic = netdev_priv(netdev);
2578 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2579 MII_LED_CONTROL;
2580
2581 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2582 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2583 mod_timer(&nic->blink_timer, jiffies);
2584 msleep_interruptible(data * 1000);
2585 del_timer_sync(&nic->blink_timer);
2586 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2587
2588 return 0;
2589 }
2590
2591 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2592 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2593 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2594 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2595 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2596 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2597 "tx_heartbeat_errors", "tx_window_errors",
2598 /* device-specific stats */
2599 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2600 "tx_flow_control_pause", "rx_flow_control_pause",
2601 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2602 };
2603 #define E100_NET_STATS_LEN 21
2604 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2605
2606 static int e100_get_sset_count(struct net_device *netdev, int sset)
2607 {
2608 switch (sset) {
2609 case ETH_SS_TEST:
2610 return E100_TEST_LEN;
2611 case ETH_SS_STATS:
2612 return E100_STATS_LEN;
2613 default:
2614 return -EOPNOTSUPP;
2615 }
2616 }
2617
2618 static void e100_get_ethtool_stats(struct net_device *netdev,
2619 struct ethtool_stats *stats, u64 *data)
2620 {
2621 struct nic *nic = netdev_priv(netdev);
2622 int i;
2623
2624 for (i = 0; i < E100_NET_STATS_LEN; i++)
2625 data[i] = ((unsigned long *)&netdev->stats)[i];
2626
2627 data[i++] = nic->tx_deferred;
2628 data[i++] = nic->tx_single_collisions;
2629 data[i++] = nic->tx_multiple_collisions;
2630 data[i++] = nic->tx_fc_pause;
2631 data[i++] = nic->rx_fc_pause;
2632 data[i++] = nic->rx_fc_unsupported;
2633 data[i++] = nic->tx_tco_frames;
2634 data[i++] = nic->rx_tco_frames;
2635 }
2636
2637 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2638 {
2639 switch (stringset) {
2640 case ETH_SS_TEST:
2641 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2642 break;
2643 case ETH_SS_STATS:
2644 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2645 break;
2646 }
2647 }
2648
2649 static const struct ethtool_ops e100_ethtool_ops = {
2650 .get_settings = e100_get_settings,
2651 .set_settings = e100_set_settings,
2652 .get_drvinfo = e100_get_drvinfo,
2653 .get_regs_len = e100_get_regs_len,
2654 .get_regs = e100_get_regs,
2655 .get_wol = e100_get_wol,
2656 .set_wol = e100_set_wol,
2657 .get_msglevel = e100_get_msglevel,
2658 .set_msglevel = e100_set_msglevel,
2659 .nway_reset = e100_nway_reset,
2660 .get_link = e100_get_link,
2661 .get_eeprom_len = e100_get_eeprom_len,
2662 .get_eeprom = e100_get_eeprom,
2663 .set_eeprom = e100_set_eeprom,
2664 .get_ringparam = e100_get_ringparam,
2665 .set_ringparam = e100_set_ringparam,
2666 .self_test = e100_diag_test,
2667 .get_strings = e100_get_strings,
2668 .phys_id = e100_phys_id,
2669 .get_ethtool_stats = e100_get_ethtool_stats,
2670 .get_sset_count = e100_get_sset_count,
2671 };
2672
2673 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2674 {
2675 struct nic *nic = netdev_priv(netdev);
2676
2677 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2678 }
2679
2680 static int e100_alloc(struct nic *nic)
2681 {
2682 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2683 &nic->dma_addr);
2684 return nic->mem ? 0 : -ENOMEM;
2685 }
2686
2687 static void e100_free(struct nic *nic)
2688 {
2689 if (nic->mem) {
2690 pci_free_consistent(nic->pdev, sizeof(struct mem),
2691 nic->mem, nic->dma_addr);
2692 nic->mem = NULL;
2693 }
2694 }
2695
2696 static int e100_open(struct net_device *netdev)
2697 {
2698 struct nic *nic = netdev_priv(netdev);
2699 int err = 0;
2700
2701 netif_carrier_off(netdev);
2702 if ((err = e100_up(nic)))
2703 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2704 return err;
2705 }
2706
2707 static int e100_close(struct net_device *netdev)
2708 {
2709 e100_down(netdev_priv(netdev));
2710 return 0;
2711 }
2712
2713 static const struct net_device_ops e100_netdev_ops = {
2714 .ndo_open = e100_open,
2715 .ndo_stop = e100_close,
2716 .ndo_start_xmit = e100_xmit_frame,
2717 .ndo_validate_addr = eth_validate_addr,
2718 .ndo_set_multicast_list = e100_set_multicast_list,
2719 .ndo_set_mac_address = e100_set_mac_address,
2720 .ndo_change_mtu = e100_change_mtu,
2721 .ndo_do_ioctl = e100_do_ioctl,
2722 .ndo_tx_timeout = e100_tx_timeout,
2723 #ifdef CONFIG_NET_POLL_CONTROLLER
2724 .ndo_poll_controller = e100_netpoll,
2725 #endif
2726 };
2727
2728 static int __devinit e100_probe(struct pci_dev *pdev,
2729 const struct pci_device_id *ent)
2730 {
2731 struct net_device *netdev;
2732 struct nic *nic;
2733 int err;
2734
2735 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2736 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2737 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2738 return -ENOMEM;
2739 }
2740
2741 netdev->netdev_ops = &e100_netdev_ops;
2742 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2743 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2744 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2745
2746 nic = netdev_priv(netdev);
2747 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2748 nic->netdev = netdev;
2749 nic->pdev = pdev;
2750 nic->msg_enable = (1 << debug) - 1;
2751 nic->mdio_ctrl = mdio_ctrl_hw;
2752 pci_set_drvdata(pdev, netdev);
2753
2754 if ((err = pci_enable_device(pdev))) {
2755 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2756 goto err_out_free_dev;
2757 }
2758
2759 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2760 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2761 "base address, aborting.\n");
2762 err = -ENODEV;
2763 goto err_out_disable_pdev;
2764 }
2765
2766 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2767 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2768 goto err_out_disable_pdev;
2769 }
2770
2771 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2772 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2773 goto err_out_free_res;
2774 }
2775
2776 SET_NETDEV_DEV(netdev, &pdev->dev);
2777
2778 if (use_io)
2779 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2780
2781 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2782 if (!nic->csr) {
2783 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2784 err = -ENOMEM;
2785 goto err_out_free_res;
2786 }
2787
2788 if (ent->driver_data)
2789 nic->flags |= ich;
2790 else
2791 nic->flags &= ~ich;
2792
2793 e100_get_defaults(nic);
2794
2795 /* locks must be initialized before calling hw_reset */
2796 spin_lock_init(&nic->cb_lock);
2797 spin_lock_init(&nic->cmd_lock);
2798 spin_lock_init(&nic->mdio_lock);
2799
2800 /* Reset the device before pci_set_master() in case device is in some
2801 * funky state and has an interrupt pending - hint: we don't have the
2802 * interrupt handler registered yet. */
2803 e100_hw_reset(nic);
2804
2805 pci_set_master(pdev);
2806
2807 init_timer(&nic->watchdog);
2808 nic->watchdog.function = e100_watchdog;
2809 nic->watchdog.data = (unsigned long)nic;
2810 init_timer(&nic->blink_timer);
2811 nic->blink_timer.function = e100_blink_led;
2812 nic->blink_timer.data = (unsigned long)nic;
2813
2814 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2815
2816 if ((err = e100_alloc(nic))) {
2817 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2818 goto err_out_iounmap;
2819 }
2820
2821 if ((err = e100_eeprom_load(nic)))
2822 goto err_out_free;
2823
2824 e100_phy_init(nic);
2825
2826 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2827 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2828 if (!is_valid_ether_addr(netdev->perm_addr)) {
2829 if (!eeprom_bad_csum_allow) {
2830 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2831 "EEPROM, aborting.\n");
2832 err = -EAGAIN;
2833 goto err_out_free;
2834 } else {
2835 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2836 "you MUST configure one.\n");
2837 }
2838 }
2839
2840 /* Wol magic packet can be enabled from eeprom */
2841 if ((nic->mac >= mac_82558_D101_A4) &&
2842 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2843 nic->flags |= wol_magic;
2844 device_set_wakeup_enable(&pdev->dev, true);
2845 }
2846
2847 /* ack any pending wake events, disable PME */
2848 pci_pme_active(pdev, false);
2849
2850 strcpy(netdev->name, "eth%d");
2851 if ((err = register_netdev(netdev))) {
2852 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2853 goto err_out_free;
2854 }
2855 nic->cbs_pool = pci_pool_create(netdev->name,
2856 nic->pdev,
2857 nic->params.cbs.count * sizeof(struct cb),
2858 sizeof(u32),
2859 0);
2860 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2861 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2862 pdev->irq, netdev->dev_addr);
2863
2864 return 0;
2865
2866 err_out_free:
2867 e100_free(nic);
2868 err_out_iounmap:
2869 pci_iounmap(pdev, nic->csr);
2870 err_out_free_res:
2871 pci_release_regions(pdev);
2872 err_out_disable_pdev:
2873 pci_disable_device(pdev);
2874 err_out_free_dev:
2875 pci_set_drvdata(pdev, NULL);
2876 free_netdev(netdev);
2877 return err;
2878 }
2879
2880 static void __devexit e100_remove(struct pci_dev *pdev)
2881 {
2882 struct net_device *netdev = pci_get_drvdata(pdev);
2883
2884 if (netdev) {
2885 struct nic *nic = netdev_priv(netdev);
2886 unregister_netdev(netdev);
2887 e100_free(nic);
2888 pci_iounmap(pdev, nic->csr);
2889 pci_pool_destroy(nic->cbs_pool);
2890 free_netdev(netdev);
2891 pci_release_regions(pdev);
2892 pci_disable_device(pdev);
2893 pci_set_drvdata(pdev, NULL);
2894 }
2895 }
2896
2897 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2898 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2899 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2900 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2901 {
2902 struct net_device *netdev = pci_get_drvdata(pdev);
2903 struct nic *nic = netdev_priv(netdev);
2904
2905 if (netif_running(netdev))
2906 e100_down(nic);
2907 netif_device_detach(netdev);
2908
2909 pci_save_state(pdev);
2910
2911 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2912 /* enable reverse auto-negotiation */
2913 if (nic->phy == phy_82552_v) {
2914 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2915 E100_82552_SMARTSPEED);
2916
2917 mdio_write(netdev, nic->mii.phy_id,
2918 E100_82552_SMARTSPEED, smartspeed |
2919 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2920 }
2921 *enable_wake = true;
2922 } else {
2923 *enable_wake = false;
2924 }
2925
2926 pci_disable_device(pdev);
2927 }
2928
2929 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2930 {
2931 if (wake)
2932 return pci_prepare_to_sleep(pdev);
2933
2934 pci_wake_from_d3(pdev, false);
2935 pci_set_power_state(pdev, PCI_D3hot);
2936
2937 return 0;
2938 }
2939
2940 #ifdef CONFIG_PM
2941 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2942 {
2943 bool wake;
2944 __e100_shutdown(pdev, &wake);
2945 return __e100_power_off(pdev, wake);
2946 }
2947
2948 static int e100_resume(struct pci_dev *pdev)
2949 {
2950 struct net_device *netdev = pci_get_drvdata(pdev);
2951 struct nic *nic = netdev_priv(netdev);
2952
2953 pci_set_power_state(pdev, PCI_D0);
2954 pci_restore_state(pdev);
2955 /* ack any pending wake events, disable PME */
2956 pci_enable_wake(pdev, 0, 0);
2957
2958 /* disable reverse auto-negotiation */
2959 if (nic->phy == phy_82552_v) {
2960 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2961 E100_82552_SMARTSPEED);
2962
2963 mdio_write(netdev, nic->mii.phy_id,
2964 E100_82552_SMARTSPEED,
2965 smartspeed & ~(E100_82552_REV_ANEG));
2966 }
2967
2968 netif_device_attach(netdev);
2969 if (netif_running(netdev))
2970 e100_up(nic);
2971
2972 return 0;
2973 }
2974 #endif /* CONFIG_PM */
2975
2976 static void e100_shutdown(struct pci_dev *pdev)
2977 {
2978 bool wake;
2979 __e100_shutdown(pdev, &wake);
2980 if (system_state == SYSTEM_POWER_OFF)
2981 __e100_power_off(pdev, wake);
2982 }
2983
2984 /* ------------------ PCI Error Recovery infrastructure -------------- */
2985 /**
2986 * e100_io_error_detected - called when PCI error is detected.
2987 * @pdev: Pointer to PCI device
2988 * @state: The current pci connection state
2989 */
2990 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2991 {
2992 struct net_device *netdev = pci_get_drvdata(pdev);
2993 struct nic *nic = netdev_priv(netdev);
2994
2995 netif_device_detach(netdev);
2996
2997 if (state == pci_channel_io_perm_failure)
2998 return PCI_ERS_RESULT_DISCONNECT;
2999
3000 if (netif_running(netdev))
3001 e100_down(nic);
3002 pci_disable_device(pdev);
3003
3004 /* Request a slot reset. */
3005 return PCI_ERS_RESULT_NEED_RESET;
3006 }
3007
3008 /**
3009 * e100_io_slot_reset - called after the pci bus has been reset.
3010 * @pdev: Pointer to PCI device
3011 *
3012 * Restart the card from scratch.
3013 */
3014 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3015 {
3016 struct net_device *netdev = pci_get_drvdata(pdev);
3017 struct nic *nic = netdev_priv(netdev);
3018
3019 if (pci_enable_device(pdev)) {
3020 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
3021 return PCI_ERS_RESULT_DISCONNECT;
3022 }
3023 pci_set_master(pdev);
3024
3025 /* Only one device per card can do a reset */
3026 if (0 != PCI_FUNC(pdev->devfn))
3027 return PCI_ERS_RESULT_RECOVERED;
3028 e100_hw_reset(nic);
3029 e100_phy_init(nic);
3030
3031 return PCI_ERS_RESULT_RECOVERED;
3032 }
3033
3034 /**
3035 * e100_io_resume - resume normal operations
3036 * @pdev: Pointer to PCI device
3037 *
3038 * Resume normal operations after an error recovery
3039 * sequence has been completed.
3040 */
3041 static void e100_io_resume(struct pci_dev *pdev)
3042 {
3043 struct net_device *netdev = pci_get_drvdata(pdev);
3044 struct nic *nic = netdev_priv(netdev);
3045
3046 /* ack any pending wake events, disable PME */
3047 pci_enable_wake(pdev, 0, 0);
3048
3049 netif_device_attach(netdev);
3050 if (netif_running(netdev)) {
3051 e100_open(netdev);
3052 mod_timer(&nic->watchdog, jiffies);
3053 }
3054 }
3055
3056 static struct pci_error_handlers e100_err_handler = {
3057 .error_detected = e100_io_error_detected,
3058 .slot_reset = e100_io_slot_reset,
3059 .resume = e100_io_resume,
3060 };
3061
3062 static struct pci_driver e100_driver = {
3063 .name = DRV_NAME,
3064 .id_table = e100_id_table,
3065 .probe = e100_probe,
3066 .remove = __devexit_p(e100_remove),
3067 #ifdef CONFIG_PM
3068 /* Power Management hooks */
3069 .suspend = e100_suspend,
3070 .resume = e100_resume,
3071 #endif
3072 .shutdown = e100_shutdown,
3073 .err_handler = &e100_err_handler,
3074 };
3075
3076 static int __init e100_init_module(void)
3077 {
3078 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3079 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3080 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3081 }
3082 return pci_register_driver(&e100_driver);
3083 }
3084
3085 static void __exit e100_cleanup_module(void)
3086 {
3087 pci_unregister_driver(&e100_driver);
3088 }
3089
3090 module_init(e100_init_module);
3091 module_exit(e100_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree