| blob | c929fba7f39941661dda561c9d74191604f35bf6 |
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
13 /*
14 /memreserve/ 00000000 1000000;
15 */
17 / {
18 model = "MPC8568EMDS";
19 compatible = "MPC8568EMDS", "MPC85xxMDS";
20 #address-cells = <1>;
21 #size-cells = <1>;
23 aliases {
24 ethernet0 = &enet0;
25 ethernet1 = &enet1;
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28 serial0 = &serial0;
29 serial1 = &serial1;
30 pci0 = &pci0;
31 pci1 = &pci1;
32 };
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
38 PowerPC,8568@0 {
39 device_type = "cpu";
40 reg = <0>;
41 d-cache-line-size = <20>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K
45 timebase-frequency = <0>;
46 bus-frequency = <0>;
47 clock-frequency = <0>;
48 };
49 };
51 memory {
52 device_type = "memory";
53 reg = <00000000 10000000>;
54 };
56 bcsr@f8000000 {
57 device_type = "board-control";
58 reg = <f8000000 8000>;
59 };
61 soc8568@e0000000 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 device_type = "soc";
65 ranges = <0 e0000000 00100000>;
66 reg = <e0000000 00001000>;
67 bus-frequency = <0>;
69 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <12 2>;
74 };
76 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>;
79 cache-line-size = <20>; // 32 bytes
80 cache-size = <80000>; // L2, 512K
81 interrupt-parent = <&mpic>;
82 interrupts = <10 2>;
83 };
85 i2c@3000 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <0>;
89 compatible = "fsl-i2c";
90 reg = <3000 100>;
91 interrupts = <2b 2>;
92 interrupt-parent = <&mpic>;
93 dfsrr;
95 rtc@68 {
96 compatible = "dallas,ds1374";
97 reg = <68>;
98 };
99 };
101 i2c@3100 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 cell-index = <1>;
105 compatible = "fsl-i2c";
106 reg = <3100 100>;
107 interrupts = <2b 2>;
108 interrupt-parent = <&mpic>;
109 dfsrr;
110 };
112 mdio@24520 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>;
118 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>;
120 interrupts = <1 1>;
121 reg = <7>;
122 device_type = "ethernet-phy";
123 };
124 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>;
126 interrupts = <2 1>;
127 reg = <1>;
128 device_type = "ethernet-phy";
129 };
130 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>;
132 interrupts = <1 1>;
133 reg = <2>;
134 device_type = "ethernet-phy";
135 };
136 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>;
138 interrupts = <2 1>;
139 reg = <3>;
140 device_type = "ethernet-phy";
141 };
142 };
144 enet0: ethernet@24000 {
145 cell-index = <0>;
146 device_type = "network";
147 model = "eTSEC";
148 compatible = "gianfar";
149 reg = <24000 1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>;
152 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>;
154 };
156 enet1: ethernet@25000 {
157 cell-index = <1>;
158 device_type = "network";
159 model = "eTSEC";
160 compatible = "gianfar";
161 reg = <25000 1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>;
164 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>;
166 };
168 serial0: serial@4500 {
169 cell-index = <0>;
170 device_type = "serial";
171 compatible = "ns16550";
172 reg = <4500 100>;
173 clock-frequency = <0>;
174 interrupts = <2a 2>;
175 interrupt-parent = <&mpic>;
176 };
178 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>;
181 fsl,has-rstcr;
182 };
184 serial1: serial@4600 {
185 cell-index = <1>;
186 device_type = "serial";
187 compatible = "ns16550";
188 reg = <4600 100>;
189 clock-frequency = <0>;
190 interrupts = <2a 2>;
191 interrupt-parent = <&mpic>;
192 };
194 crypto@30000 {
195 device_type = "crypto";
196 model = "SEC2";
197 compatible = "talitos";
198 reg = <30000 f000>;
199 interrupts = <2d 2>;
200 interrupt-parent = <&mpic>;
201 num-channels = <4>;
202 channel-fifo-len = <18>;
203 exec-units-mask = <000000fe>;
204 descriptor-types-mask = <012b0ebf>;
205 };
207 mpic: pic@40000 {
208 clock-frequency = <0>;
209 interrupt-controller;
210 #address-cells = <0>;
211 #interrupt-cells = <2>;
212 reg = <40000 40000>;
213 compatible = "chrp,open-pic";
214 device_type = "open-pic";
215 big-endian;
216 };
218 par_io@e0100 {
219 reg = <e0100 100>;
220 device_type = "par_io";
221 num-ports = <7>;
223 pio1: ucc_pin@01 {
224 pio-map = <
225 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */
249 };
251 pio2: ucc_pin@02 {
252 pio-map = <
253 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */
279 };
280 };
281 };
283 qe@e0080000 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 device_type = "qe";
287 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>;
289 reg = <e0080000 480>;
290 brg-frequency = <0>;
291 bus-frequency = <179A7B00>;
293 muram@10000 {
294 compatible = "fsl,qe-muram", "fsl,cpm-muram";
295 ranges = <0 00010000 0000c000>;
297 data-only@0{
298 compatible = "fsl,qe-muram-data",
299 "fsl,cpm-muram-data";
300 reg = <0 c000>;
301 };
302 };
304 spi@4c0 {
305 cell-index = <0>;
306 compatible = "fsl,spi";
307 reg = <4c0 40>;
308 interrupts = <2>;
309 interrupt-parent = <&qeic>;
310 mode = "cpu";
311 };
313 spi@500 {
314 cell-index = <1>;
315 compatible = "fsl,spi";
316 reg = <500 40>;
317 interrupts = <1>;
318 interrupt-parent = <&qeic>;
319 mode = "cpu";
320 };
322 enet2: ucc@2000 {
323 device_type = "network";
324 compatible = "ucc_geth";
325 model = "UCC";
326 cell-index = <1>;
327 device-id = <1>;
328 reg = <2000 200>;
329 interrupts = <20>;
330 interrupt-parent = <&qeic>;
331 local-mac-address = [ 00 00 00 00 00 00 ];
332 rx-clock-name = "none";
333 tx-clock-name = "clk16";
334 pio-handle = <&pio1>;
335 phy-handle = <&phy0>;
336 phy-connection-type = "rgmii-id";
337 };
339 enet3: ucc@3000 {
340 device_type = "network";
341 compatible = "ucc_geth";
342 model = "UCC";
343 cell-index = <2>;
344 device-id = <2>;
345 reg = <3000 200>;
346 interrupts = <21>;
347 interrupt-parent = <&qeic>;
348 local-mac-address = [ 00 00 00 00 00 00 ];
349 rx-clock-name = "none";
350 tx-clock-name = "clk16";
351 pio-handle = <&pio2>;
352 phy-handle = <&phy1>;
353 phy-connection-type = "rgmii-id";
354 };
356 mdio@2120 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 reg = <2120 18>;
360 compatible = "fsl,ucc-mdio";
362 /* These are the same PHYs as on
363 * gianfar's MDIO bus */
364 qe_phy0: ethernet-phy@07 {
365 interrupt-parent = <&mpic>;
366 interrupts = <1 1>;
367 reg = <7>;
368 device_type = "ethernet-phy";
369 };
370 qe_phy1: ethernet-phy@01 {
371 interrupt-parent = <&mpic>;
372 interrupts = <2 1>;
373 reg = <1>;
374 device_type = "ethernet-phy";
375 };
376 qe_phy2: ethernet-phy@02 {
377 interrupt-parent = <&mpic>;
378 interrupts = <1 1>;
379 reg = <2>;
380 device_type = "ethernet-phy";
381 };
382 qe_phy3: ethernet-phy@03 {
383 interrupt-parent = <&mpic>;
384 interrupts = <2 1>;
385 reg = <3>;
386 device_type = "ethernet-phy";
387 };
388 };
390 qeic: interrupt-controller@80 {
391 interrupt-controller;
392 compatible = "fsl,qe-ic";
393 #address-cells = <0>;
394 #interrupt-cells = <1>;
395 reg = <80 80>;
396 big-endian;
397 interrupts = <2e 2 2e 2>; //high:30 low:30
398 interrupt-parent = <&mpic>;
399 };
401 };
403 pci0: pci@e0008000 {
404 cell-index = <0>;
405 interrupt-map-mask = <f800 0 0 7>;
406 interrupt-map = <
407 /* IDSEL 0x12 AD18 */
408 9000 0 0 1 &mpic 5 1
409 9000 0 0 2 &mpic 6 1
410 9000 0 0 3 &mpic 7 1
411 9000 0 0 4 &mpic 4 1
413 /* IDSEL 0x13 AD19 */
414 9800 0 0 1 &mpic 6 1
415 9800 0 0 2 &mpic 7 1
416 9800 0 0 3 &mpic 4 1
417 9800 0 0 4 &mpic 5 1>;
419 interrupt-parent = <&mpic>;
420 interrupts = <18 2>;
421 bus-range = <0 ff>;
422 ranges = <02000000 0 80000000 80000000 0 20000000
423 01000000 0 00000000 e2000000 0 00800000>;
424 clock-frequency = <3f940aa>;
425 #interrupt-cells = <1>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 reg = <e0008000 1000>;
429 compatible = "fsl,mpc8540-pci";
430 device_type = "pci";
431 };
433 /* PCI Express */
434 pci1: pcie@e000a000 {
435 cell-index = <2>;
436 interrupt-map-mask = <f800 0 0 7>;
437 interrupt-map = <
439 /* IDSEL 0x0 (PEX) */
440 00000 0 0 1 &mpic 0 1
441 00000 0 0 2 &mpic 1 1
442 00000 0 0 3 &mpic 2 1
443 00000 0 0 4 &mpic 3 1>;
445 interrupt-parent = <&mpic>;
446 interrupts = <1a 2>;
447 bus-range = <0 ff>;
448 ranges = <02000000 0 a0000000 a0000000 0 10000000
449 01000000 0 00000000 e2800000 0 00800000>;
450 clock-frequency = <1fca055>;
451 #interrupt-cells = <1>;
452 #size-cells = <2>;
453 #address-cells = <3>;
454 reg = <e000a000 1000>;
455 compatible = "fsl,mpc8548-pcie";
456 device_type = "pci";
457 pcie@0 {
458 reg = <0 0 0 0 0>;
459 #size-cells = <2>;
460 #address-cells = <3>;
461 device_type = "pci";
462 ranges = <02000000 0 a0000000
463 02000000 0 a0000000
464 0 10000000
466 01000000 0 00000000
467 01000000 0 00000000
468 0 00800000>;
469 };
470 };
471 };