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drm/radeon/kms: unify i2c handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
bloba841adead1a1afd2e08840273899463df855b512
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
52
53 /* from radeon_legacy_encoder.c */
54 extern void
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62 };
63
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
66 {
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset, size;
73 int i, num_indices;
74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
83
84 for (i = 0; i < num_indices; i++) {
85 gpio = &i2c_info->asGPIO_Info[i];
86
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
107 else
108 i2c.hw_capable = false;
109
110 if (gpio->sucI2cId.ucAccess == 0xa0)
111 i2c.mm_i2c = true;
112 else
113 i2c.mm_i2c = false;
114
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116
117 if (i2c.mask_clk_reg)
118 i2c.valid = true;
119 break;
120 }
121 }
122 }
123
124 return i2c;
125 }
126
127 void radeon_atombios_i2c_init(struct radeon_device *rdev)
128 {
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 ATOM_GPIO_I2C_ASSIGMENT *gpio;
131 struct radeon_i2c_bus_rec i2c;
132 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
133 struct _ATOM_GPIO_I2C_INFO *i2c_info;
134 uint16_t data_offset, size;
135 int i, num_indices;
136 char stmp[32];
137
138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
139
140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
142
143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
145
146 for (i = 0; i < num_indices; i++) {
147 gpio = &i2c_info->asGPIO_Info[i];
148 i2c.valid = false;
149 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
150 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
151 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
152 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
153 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
154 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
155 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
156 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
157 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
158 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
159 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
160 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
161 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
162 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
163 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
164 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
165
166 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
167 i2c.hw_capable = true;
168 else
169 i2c.hw_capable = false;
170
171 if (gpio->sucI2cId.ucAccess == 0xa0)
172 i2c.mm_i2c = true;
173 else
174 i2c.mm_i2c = false;
175
176 i2c.i2c_id = gpio->sucI2cId.ucAccess;
177
178 if (i2c.mask_clk_reg) {
179 i2c.valid = true;
180 sprintf(stmp, "0x%x", i2c.i2c_id);
181 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
182 }
183 }
184 }
185 }
186
187 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
188 u8 id)
189 {
190 struct atom_context *ctx = rdev->mode_info.atom_context;
191 struct radeon_gpio_rec gpio;
192 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
193 struct _ATOM_GPIO_PIN_LUT *gpio_info;
194 ATOM_GPIO_PIN_ASSIGNMENT *pin;
195 u16 data_offset, size;
196 int i, num_indices;
197
198 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
199 gpio.valid = false;
200
201 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
202 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
203
204 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
205 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
206
207 for (i = 0; i < num_indices; i++) {
208 pin = &gpio_info->asGPIO_Pin[i];
209 if (id == pin->ucGPIO_ID) {
210 gpio.id = pin->ucGPIO_ID;
211 gpio.reg = pin->usGpioPin_AIndex * 4;
212 gpio.mask = (1 << pin->ucGpioPinBitShift);
213 gpio.valid = true;
214 break;
215 }
216 }
217 }
218
219 return gpio;
220 }
221
222 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
223 struct radeon_gpio_rec *gpio)
224 {
225 struct radeon_hpd hpd;
226 u32 reg;
227
228 if (ASIC_IS_DCE4(rdev))
229 reg = EVERGREEN_DC_GPIO_HPD_A;
230 else
231 reg = AVIVO_DC_GPIO_HPD_A;
232
233 hpd.gpio = *gpio;
234 if (gpio->reg == reg) {
235 switch(gpio->mask) {
236 case (1 << 0):
237 hpd.hpd = RADEON_HPD_1;
238 break;
239 case (1 << 8):
240 hpd.hpd = RADEON_HPD_2;
241 break;
242 case (1 << 16):
243 hpd.hpd = RADEON_HPD_3;
244 break;
245 case (1 << 24):
246 hpd.hpd = RADEON_HPD_4;
247 break;
248 case (1 << 26):
249 hpd.hpd = RADEON_HPD_5;
250 break;
251 case (1 << 28):
252 hpd.hpd = RADEON_HPD_6;
253 break;
254 default:
255 hpd.hpd = RADEON_HPD_NONE;
256 break;
257 }
258 } else
259 hpd.hpd = RADEON_HPD_NONE;
260 return hpd;
261 }
262
263 static bool radeon_atom_apply_quirks(struct drm_device *dev,
264 uint32_t supported_device,
265 int *connector_type,
266 struct radeon_i2c_bus_rec *i2c_bus,
267 uint16_t *line_mux,
268 struct radeon_hpd *hpd)
269 {
270
271 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
272 if ((dev->pdev->device == 0x791e) &&
273 (dev->pdev->subsystem_vendor == 0x1043) &&
274 (dev->pdev->subsystem_device == 0x826d)) {
275 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
276 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
277 *connector_type = DRM_MODE_CONNECTOR_DVID;
278 }
279
280 /* Asrock RS600 board lists the DVI port as HDMI */
281 if ((dev->pdev->device == 0x7941) &&
282 (dev->pdev->subsystem_vendor == 0x1849) &&
283 (dev->pdev->subsystem_device == 0x7941)) {
284 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
285 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
286 *connector_type = DRM_MODE_CONNECTOR_DVID;
287 }
288
289 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
290 if ((dev->pdev->device == 0x7941) &&
291 (dev->pdev->subsystem_vendor == 0x147b) &&
292 (dev->pdev->subsystem_device == 0x2412)) {
293 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
294 return false;
295 }
296
297 /* Falcon NW laptop lists vga ddc line for LVDS */
298 if ((dev->pdev->device == 0x5653) &&
299 (dev->pdev->subsystem_vendor == 0x1462) &&
300 (dev->pdev->subsystem_device == 0x0291)) {
301 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
302 i2c_bus->valid = false;
303 *line_mux = 53;
304 }
305 }
306
307 /* HIS X1300 is DVI+VGA, not DVI+DVI */
308 if ((dev->pdev->device == 0x7146) &&
309 (dev->pdev->subsystem_vendor == 0x17af) &&
310 (dev->pdev->subsystem_device == 0x2058)) {
311 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
312 return false;
313 }
314
315 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
316 if ((dev->pdev->device == 0x7142) &&
317 (dev->pdev->subsystem_vendor == 0x1458) &&
318 (dev->pdev->subsystem_device == 0x2134)) {
319 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
320 return false;
321 }
322
323
324 /* Funky macbooks */
325 if ((dev->pdev->device == 0x71C5) &&
326 (dev->pdev->subsystem_vendor == 0x106b) &&
327 (dev->pdev->subsystem_device == 0x0080)) {
328 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
329 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
330 return false;
331 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
332 *line_mux = 0x90;
333 }
334
335 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
336 if ((dev->pdev->device == 0x9598) &&
337 (dev->pdev->subsystem_vendor == 0x1043) &&
338 (dev->pdev->subsystem_device == 0x01da)) {
339 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
340 *connector_type = DRM_MODE_CONNECTOR_DVII;
341 }
342 }
343
344 /* ASUS HD 3600 board lists the DVI port as HDMI */
345 if ((dev->pdev->device == 0x9598) &&
346 (dev->pdev->subsystem_vendor == 0x1043) &&
347 (dev->pdev->subsystem_device == 0x01e4)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
349 *connector_type = DRM_MODE_CONNECTOR_DVII;
350 }
351 }
352
353 /* ASUS HD 3450 board lists the DVI port as HDMI */
354 if ((dev->pdev->device == 0x95C5) &&
355 (dev->pdev->subsystem_vendor == 0x1043) &&
356 (dev->pdev->subsystem_device == 0x01e2)) {
357 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
358 *connector_type = DRM_MODE_CONNECTOR_DVII;
359 }
360 }
361
362 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
363 * HDMI + VGA reporting as HDMI
364 */
365 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
366 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
367 *connector_type = DRM_MODE_CONNECTOR_VGA;
368 *line_mux = 0;
369 }
370 }
371
372 /* Acer laptop reports DVI-D as DVI-I */
373 if ((dev->pdev->device == 0x95c4) &&
374 (dev->pdev->subsystem_vendor == 0x1025) &&
375 (dev->pdev->subsystem_device == 0x013c)) {
376 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
377 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
378 *connector_type = DRM_MODE_CONNECTOR_DVID;
379 }
380
381 /* XFX Pine Group device rv730 reports no VGA DDC lines
382 * even though they are wired up to record 0x93
383 */
384 if ((dev->pdev->device == 0x9498) &&
385 (dev->pdev->subsystem_vendor == 0x1682) &&
386 (dev->pdev->subsystem_device == 0x2452)) {
387 struct radeon_device *rdev = dev->dev_private;
388 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
389 }
390 return true;
391 }
392
393 const int supported_devices_connector_convert[] = {
394 DRM_MODE_CONNECTOR_Unknown,
395 DRM_MODE_CONNECTOR_VGA,
396 DRM_MODE_CONNECTOR_DVII,
397 DRM_MODE_CONNECTOR_DVID,
398 DRM_MODE_CONNECTOR_DVIA,
399 DRM_MODE_CONNECTOR_SVIDEO,
400 DRM_MODE_CONNECTOR_Composite,
401 DRM_MODE_CONNECTOR_LVDS,
402 DRM_MODE_CONNECTOR_Unknown,
403 DRM_MODE_CONNECTOR_Unknown,
404 DRM_MODE_CONNECTOR_HDMIA,
405 DRM_MODE_CONNECTOR_HDMIB,
406 DRM_MODE_CONNECTOR_Unknown,
407 DRM_MODE_CONNECTOR_Unknown,
408 DRM_MODE_CONNECTOR_9PinDIN,
409 DRM_MODE_CONNECTOR_DisplayPort
410 };
411
412 const uint16_t supported_devices_connector_object_id_convert[] = {
413 CONNECTOR_OBJECT_ID_NONE,
414 CONNECTOR_OBJECT_ID_VGA,
415 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
416 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
417 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
418 CONNECTOR_OBJECT_ID_COMPOSITE,
419 CONNECTOR_OBJECT_ID_SVIDEO,
420 CONNECTOR_OBJECT_ID_LVDS,
421 CONNECTOR_OBJECT_ID_9PIN_DIN,
422 CONNECTOR_OBJECT_ID_9PIN_DIN,
423 CONNECTOR_OBJECT_ID_DISPLAYPORT,
424 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
425 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
426 CONNECTOR_OBJECT_ID_SVIDEO
427 };
428
429 const int object_connector_convert[] = {
430 DRM_MODE_CONNECTOR_Unknown,
431 DRM_MODE_CONNECTOR_DVII,
432 DRM_MODE_CONNECTOR_DVII,
433 DRM_MODE_CONNECTOR_DVID,
434 DRM_MODE_CONNECTOR_DVID,
435 DRM_MODE_CONNECTOR_VGA,
436 DRM_MODE_CONNECTOR_Composite,
437 DRM_MODE_CONNECTOR_SVIDEO,
438 DRM_MODE_CONNECTOR_Unknown,
439 DRM_MODE_CONNECTOR_Unknown,
440 DRM_MODE_CONNECTOR_9PinDIN,
441 DRM_MODE_CONNECTOR_Unknown,
442 DRM_MODE_CONNECTOR_HDMIA,
443 DRM_MODE_CONNECTOR_HDMIB,
444 DRM_MODE_CONNECTOR_LVDS,
445 DRM_MODE_CONNECTOR_9PinDIN,
446 DRM_MODE_CONNECTOR_Unknown,
447 DRM_MODE_CONNECTOR_Unknown,
448 DRM_MODE_CONNECTOR_Unknown,
449 DRM_MODE_CONNECTOR_DisplayPort,
450 DRM_MODE_CONNECTOR_eDP,
451 DRM_MODE_CONNECTOR_Unknown
452 };
453
454 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
455 {
456 struct radeon_device *rdev = dev->dev_private;
457 struct radeon_mode_info *mode_info = &rdev->mode_info;
458 struct atom_context *ctx = mode_info->atom_context;
459 int index = GetIndexIntoMasterTable(DATA, Object_Header);
460 u16 size, data_offset;
461 u8 frev, crev;
462 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
463 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
464 ATOM_OBJECT_HEADER *obj_header;
465 int i, j, path_size, device_support;
466 int connector_type;
467 u16 igp_lane_info, conn_id, connector_object_id;
468 bool linkb;
469 struct radeon_i2c_bus_rec ddc_bus;
470 struct radeon_gpio_rec gpio;
471 struct radeon_hpd hpd;
472
473 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
474 return false;
475
476 if (crev < 2)
477 return false;
478
479 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
480 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
481 (ctx->bios + data_offset +
482 le16_to_cpu(obj_header->usDisplayPathTableOffset));
483 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
484 (ctx->bios + data_offset +
485 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
486 device_support = le16_to_cpu(obj_header->usDeviceSupport);
487
488 path_size = 0;
489 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
490 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
491 ATOM_DISPLAY_OBJECT_PATH *path;
492 addr += path_size;
493 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
494 path_size += le16_to_cpu(path->usSize);
495 linkb = false;
496 if (device_support & le16_to_cpu(path->usDeviceTag)) {
497 uint8_t con_obj_id, con_obj_num, con_obj_type;
498
499 con_obj_id =
500 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
501 >> OBJECT_ID_SHIFT;
502 con_obj_num =
503 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
504 >> ENUM_ID_SHIFT;
505 con_obj_type =
506 (le16_to_cpu(path->usConnObjectId) &
507 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
508
509 /* TODO CV support */
510 if (le16_to_cpu(path->usDeviceTag) ==
511 ATOM_DEVICE_CV_SUPPORT)
512 continue;
513
514 /* IGP chips */
515 if ((rdev->flags & RADEON_IS_IGP) &&
516 (con_obj_id ==
517 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
518 uint16_t igp_offset = 0;
519 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
520
521 index =
522 GetIndexIntoMasterTable(DATA,
523 IntegratedSystemInfo);
524
525 if (atom_parse_data_header(ctx, index, &size, &frev,
526 &crev, &igp_offset)) {
527
528 if (crev >= 2) {
529 igp_obj =
530 (ATOM_INTEGRATED_SYSTEM_INFO_V2
531 *) (ctx->bios + igp_offset);
532
533 if (igp_obj) {
534 uint32_t slot_config, ct;
535
536 if (con_obj_num == 1)
537 slot_config =
538 igp_obj->
539 ulDDISlot1Config;
540 else
541 slot_config =
542 igp_obj->
543 ulDDISlot2Config;
544
545 ct = (slot_config >> 16) & 0xff;
546 connector_type =
547 object_connector_convert
548 [ct];
549 connector_object_id = ct;
550 igp_lane_info =
551 slot_config & 0xffff;
552 } else
553 continue;
554 } else
555 continue;
556 } else {
557 igp_lane_info = 0;
558 connector_type =
559 object_connector_convert[con_obj_id];
560 connector_object_id = con_obj_id;
561 }
562 } else {
563 igp_lane_info = 0;
564 connector_type =
565 object_connector_convert[con_obj_id];
566 connector_object_id = con_obj_id;
567 }
568
569 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
570 continue;
571
572 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
573 j++) {
574 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
575
576 enc_obj_id =
577 (le16_to_cpu(path->usGraphicObjIds[j]) &
578 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
579 enc_obj_num =
580 (le16_to_cpu(path->usGraphicObjIds[j]) &
581 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
582 enc_obj_type =
583 (le16_to_cpu(path->usGraphicObjIds[j]) &
584 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
585
586 /* FIXME: add support for router objects */
587 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
588 if (enc_obj_num == 2)
589 linkb = true;
590 else
591 linkb = false;
592
593 radeon_add_atom_encoder(dev,
594 enc_obj_id,
595 le16_to_cpu
596 (path->
597 usDeviceTag));
598
599 }
600 }
601
602 /* look up gpio for ddc, hpd */
603 ddc_bus.valid = false;
604 hpd.hpd = RADEON_HPD_NONE;
605 if ((le16_to_cpu(path->usDeviceTag) &
606 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
607 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
608 if (le16_to_cpu(path->usConnObjectId) ==
609 le16_to_cpu(con_obj->asObjects[j].
610 usObjectID)) {
611 ATOM_COMMON_RECORD_HEADER
612 *record =
613 (ATOM_COMMON_RECORD_HEADER
614 *)
615 (ctx->bios + data_offset +
616 le16_to_cpu(con_obj->
617 asObjects[j].
618 usRecordOffset));
619 ATOM_I2C_RECORD *i2c_record;
620 ATOM_HPD_INT_RECORD *hpd_record;
621 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
622
623 while (record->ucRecordType > 0
624 && record->
625 ucRecordType <=
626 ATOM_MAX_OBJECT_RECORD_NUMBER) {
627 switch (record->ucRecordType) {
628 case ATOM_I2C_RECORD_TYPE:
629 i2c_record =
630 (ATOM_I2C_RECORD *)
631 record;
632 i2c_config =
633 (ATOM_I2C_ID_CONFIG_ACCESS *)
634 &i2c_record->sucI2cId;
635 ddc_bus = radeon_lookup_i2c_gpio(rdev,
636 i2c_config->
637 ucAccess);
638 break;
639 case ATOM_HPD_INT_RECORD_TYPE:
640 hpd_record =
641 (ATOM_HPD_INT_RECORD *)
642 record;
643 gpio = radeon_lookup_gpio(rdev,
644 hpd_record->ucHPDIntGPIOID);
645 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
646 hpd.plugged_state = hpd_record->ucPlugged_PinState;
647 break;
648 }
649 record =
650 (ATOM_COMMON_RECORD_HEADER
651 *) ((char *)record
652 +
653 record->
654 ucRecordSize);
655 }
656 break;
657 }
658 }
659 }
660
661 /* needed for aux chan transactions */
662 ddc_bus.hpd = hpd.hpd;
663
664 conn_id = le16_to_cpu(path->usConnObjectId);
665
666 if (!radeon_atom_apply_quirks
667 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
668 &ddc_bus, &conn_id, &hpd))
669 continue;
670
671 radeon_add_atom_connector(dev,
672 conn_id,
673 le16_to_cpu(path->
674 usDeviceTag),
675 connector_type, &ddc_bus,
676 linkb, igp_lane_info,
677 connector_object_id,
678 &hpd);
679
680 }
681 }
682
683 radeon_link_encoder_connector(dev);
684
685 return true;
686 }
687
688 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
689 int connector_type,
690 uint16_t devices)
691 {
692 struct radeon_device *rdev = dev->dev_private;
693
694 if (rdev->flags & RADEON_IS_IGP) {
695 return supported_devices_connector_object_id_convert
696 [connector_type];
697 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
698 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
699 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
700 struct radeon_mode_info *mode_info = &rdev->mode_info;
701 struct atom_context *ctx = mode_info->atom_context;
702 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
703 uint16_t size, data_offset;
704 uint8_t frev, crev;
705 ATOM_XTMDS_INFO *xtmds;
706
707 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
708 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
709
710 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
711 if (connector_type == DRM_MODE_CONNECTOR_DVII)
712 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
713 else
714 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
715 } else {
716 if (connector_type == DRM_MODE_CONNECTOR_DVII)
717 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
718 else
719 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
720 }
721 } else
722 return supported_devices_connector_object_id_convert
723 [connector_type];
724 } else {
725 return supported_devices_connector_object_id_convert
726 [connector_type];
727 }
728 }
729
730 struct bios_connector {
731 bool valid;
732 uint16_t line_mux;
733 uint16_t devices;
734 int connector_type;
735 struct radeon_i2c_bus_rec ddc_bus;
736 struct radeon_hpd hpd;
737 };
738
739 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
740 drm_device
741 *dev)
742 {
743 struct radeon_device *rdev = dev->dev_private;
744 struct radeon_mode_info *mode_info = &rdev->mode_info;
745 struct atom_context *ctx = mode_info->atom_context;
746 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
747 uint16_t size, data_offset;
748 uint8_t frev, crev;
749 uint16_t device_support;
750 uint8_t dac;
751 union atom_supported_devices *supported_devices;
752 int i, j, max_device;
753 struct bios_connector *bios_connectors;
754 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
755
756 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
757 if (!bios_connectors)
758 return false;
759
760 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
761 &data_offset)) {
762 kfree(bios_connectors);
763 return false;
764 }
765
766 supported_devices =
767 (union atom_supported_devices *)(ctx->bios + data_offset);
768
769 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
770
771 if (frev > 1)
772 max_device = ATOM_MAX_SUPPORTED_DEVICE;
773 else
774 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
775
776 for (i = 0; i < max_device; i++) {
777 ATOM_CONNECTOR_INFO_I2C ci =
778 supported_devices->info.asConnInfo[i];
779
780 bios_connectors[i].valid = false;
781
782 if (!(device_support & (1 << i))) {
783 continue;
784 }
785
786 if (i == ATOM_DEVICE_CV_INDEX) {
787 DRM_DEBUG_KMS("Skipping Component Video\n");
788 continue;
789 }
790
791 bios_connectors[i].connector_type =
792 supported_devices_connector_convert[ci.sucConnectorInfo.
793 sbfAccess.
794 bfConnectorType];
795
796 if (bios_connectors[i].connector_type ==
797 DRM_MODE_CONNECTOR_Unknown)
798 continue;
799
800 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
801
802 bios_connectors[i].line_mux =
803 ci.sucI2cId.ucAccess;
804
805 /* give tv unique connector ids */
806 if (i == ATOM_DEVICE_TV1_INDEX) {
807 bios_connectors[i].ddc_bus.valid = false;
808 bios_connectors[i].line_mux = 50;
809 } else if (i == ATOM_DEVICE_TV2_INDEX) {
810 bios_connectors[i].ddc_bus.valid = false;
811 bios_connectors[i].line_mux = 51;
812 } else if (i == ATOM_DEVICE_CV_INDEX) {
813 bios_connectors[i].ddc_bus.valid = false;
814 bios_connectors[i].line_mux = 52;
815 } else
816 bios_connectors[i].ddc_bus =
817 radeon_lookup_i2c_gpio(rdev,
818 bios_connectors[i].line_mux);
819
820 if ((crev > 1) && (frev > 1)) {
821 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
822 switch (isb) {
823 case 0x4:
824 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
825 break;
826 case 0xa:
827 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
828 break;
829 default:
830 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
831 break;
832 }
833 } else {
834 if (i == ATOM_DEVICE_DFP1_INDEX)
835 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
836 else if (i == ATOM_DEVICE_DFP2_INDEX)
837 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
838 else
839 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
840 }
841
842 /* Always set the connector type to VGA for CRT1/CRT2. if they are
843 * shared with a DVI port, we'll pick up the DVI connector when we
844 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
845 */
846 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
847 bios_connectors[i].connector_type =
848 DRM_MODE_CONNECTOR_VGA;
849
850 if (!radeon_atom_apply_quirks
851 (dev, (1 << i), &bios_connectors[i].connector_type,
852 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
853 &bios_connectors[i].hpd))
854 continue;
855
856 bios_connectors[i].valid = true;
857 bios_connectors[i].devices = (1 << i);
858
859 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
860 radeon_add_atom_encoder(dev,
861 radeon_get_encoder_id(dev,
862 (1 << i),
863 dac),
864 (1 << i));
865 else
866 radeon_add_legacy_encoder(dev,
867 radeon_get_encoder_id(dev,
868 (1 << i),
869 dac),
870 (1 << i));
871 }
872
873 /* combine shared connectors */
874 for (i = 0; i < max_device; i++) {
875 if (bios_connectors[i].valid) {
876 for (j = 0; j < max_device; j++) {
877 if (bios_connectors[j].valid && (i != j)) {
878 if (bios_connectors[i].line_mux ==
879 bios_connectors[j].line_mux) {
880 /* make sure not to combine LVDS */
881 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
882 bios_connectors[i].line_mux = 53;
883 bios_connectors[i].ddc_bus.valid = false;
884 continue;
885 }
886 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
887 bios_connectors[j].line_mux = 53;
888 bios_connectors[j].ddc_bus.valid = false;
889 continue;
890 }
891 /* combine analog and digital for DVI-I */
892 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
893 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
894 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
895 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
896 bios_connectors[i].devices |=
897 bios_connectors[j].devices;
898 bios_connectors[i].connector_type =
899 DRM_MODE_CONNECTOR_DVII;
900 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
901 bios_connectors[i].hpd =
902 bios_connectors[j].hpd;
903 bios_connectors[j].valid = false;
904 }
905 }
906 }
907 }
908 }
909 }
910
911 /* add the connectors */
912 for (i = 0; i < max_device; i++) {
913 if (bios_connectors[i].valid) {
914 uint16_t connector_object_id =
915 atombios_get_connector_object_id(dev,
916 bios_connectors[i].connector_type,
917 bios_connectors[i].devices);
918 radeon_add_atom_connector(dev,
919 bios_connectors[i].line_mux,
920 bios_connectors[i].devices,
921 bios_connectors[i].
922 connector_type,
923 &bios_connectors[i].ddc_bus,
924 false, 0,
925 connector_object_id,
926 &bios_connectors[i].hpd);
927 }
928 }
929
930 radeon_link_encoder_connector(dev);
931
932 kfree(bios_connectors);
933 return true;
934 }
935
936 union firmware_info {
937 ATOM_FIRMWARE_INFO info;
938 ATOM_FIRMWARE_INFO_V1_2 info_12;
939 ATOM_FIRMWARE_INFO_V1_3 info_13;
940 ATOM_FIRMWARE_INFO_V1_4 info_14;
941 ATOM_FIRMWARE_INFO_V2_1 info_21;
942 };
943
944 bool radeon_atom_get_clock_info(struct drm_device *dev)
945 {
946 struct radeon_device *rdev = dev->dev_private;
947 struct radeon_mode_info *mode_info = &rdev->mode_info;
948 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
949 union firmware_info *firmware_info;
950 uint8_t frev, crev;
951 struct radeon_pll *p1pll = &rdev->clock.p1pll;
952 struct radeon_pll *p2pll = &rdev->clock.p2pll;
953 struct radeon_pll *dcpll = &rdev->clock.dcpll;
954 struct radeon_pll *spll = &rdev->clock.spll;
955 struct radeon_pll *mpll = &rdev->clock.mpll;
956 uint16_t data_offset;
957
958 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
959 &frev, &crev, &data_offset)) {
960 firmware_info =
961 (union firmware_info *)(mode_info->atom_context->bios +
962 data_offset);
963 /* pixel clocks */
964 p1pll->reference_freq =
965 le16_to_cpu(firmware_info->info.usReferenceClock);
966 p1pll->reference_div = 0;
967
968 if (crev < 2)
969 p1pll->pll_out_min =
970 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
971 else
972 p1pll->pll_out_min =
973 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
974 p1pll->pll_out_max =
975 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
976
977 if (crev >= 4) {
978 p1pll->lcd_pll_out_min =
979 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
980 if (p1pll->lcd_pll_out_min == 0)
981 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
982 p1pll->lcd_pll_out_max =
983 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
984 if (p1pll->lcd_pll_out_max == 0)
985 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
986 } else {
987 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
988 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
989 }
990
991 if (p1pll->pll_out_min == 0) {
992 if (ASIC_IS_AVIVO(rdev))
993 p1pll->pll_out_min = 64800;
994 else
995 p1pll->pll_out_min = 20000;
996 } else if (p1pll->pll_out_min > 64800) {
997 /* Limiting the pll output range is a good thing generally as
998 * it limits the number of possible pll combinations for a given
999 * frequency presumably to the ones that work best on each card.
1000 * However, certain duallink DVI monitors seem to like
1001 * pll combinations that would be limited by this at least on
1002 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1003 * family.
1004 */
1005 if (!radeon_new_pll)
1006 p1pll->pll_out_min = 64800;
1007 }
1008
1009 p1pll->pll_in_min =
1010 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1011 p1pll->pll_in_max =
1012 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1013
1014 *p2pll = *p1pll;
1015
1016 /* system clock */
1017 spll->reference_freq =
1018 le16_to_cpu(firmware_info->info.usReferenceClock);
1019 spll->reference_div = 0;
1020
1021 spll->pll_out_min =
1022 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1023 spll->pll_out_max =
1024 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1025
1026 /* ??? */
1027 if (spll->pll_out_min == 0) {
1028 if (ASIC_IS_AVIVO(rdev))
1029 spll->pll_out_min = 64800;
1030 else
1031 spll->pll_out_min = 20000;
1032 }
1033
1034 spll->pll_in_min =
1035 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1036 spll->pll_in_max =
1037 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1038
1039 /* memory clock */
1040 mpll->reference_freq =
1041 le16_to_cpu(firmware_info->info.usReferenceClock);
1042 mpll->reference_div = 0;
1043
1044 mpll->pll_out_min =
1045 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1046 mpll->pll_out_max =
1047 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1048
1049 /* ??? */
1050 if (mpll->pll_out_min == 0) {
1051 if (ASIC_IS_AVIVO(rdev))
1052 mpll->pll_out_min = 64800;
1053 else
1054 mpll->pll_out_min = 20000;
1055 }
1056
1057 mpll->pll_in_min =
1058 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1059 mpll->pll_in_max =
1060 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1061
1062 rdev->clock.default_sclk =
1063 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1064 rdev->clock.default_mclk =
1065 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1066
1067 if (ASIC_IS_DCE4(rdev)) {
1068 rdev->clock.default_dispclk =
1069 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1070 if (rdev->clock.default_dispclk == 0)
1071 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1072 rdev->clock.dp_extclk =
1073 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1074 }
1075 *dcpll = *p1pll;
1076
1077 return true;
1078 }
1079
1080 return false;
1081 }
1082
1083 union igp_info {
1084 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1085 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1086 };
1087
1088 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1089 {
1090 struct radeon_mode_info *mode_info = &rdev->mode_info;
1091 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1092 union igp_info *igp_info;
1093 u8 frev, crev;
1094 u16 data_offset;
1095
1096 /* sideport is AMD only */
1097 if (rdev->family == CHIP_RS600)
1098 return false;
1099
1100 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1101 &frev, &crev, &data_offset)) {
1102 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1103 data_offset);
1104 switch (crev) {
1105 case 1:
1106 if (igp_info->info.ulBootUpMemoryClock)
1107 return true;
1108 break;
1109 case 2:
1110 if (igp_info->info_2.ucMemoryType & 0x0f)
1111 return true;
1112 break;
1113 default:
1114 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1115 break;
1116 }
1117 }
1118 return false;
1119 }
1120
1121 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1122 struct radeon_encoder_int_tmds *tmds)
1123 {
1124 struct drm_device *dev = encoder->base.dev;
1125 struct radeon_device *rdev = dev->dev_private;
1126 struct radeon_mode_info *mode_info = &rdev->mode_info;
1127 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1128 uint16_t data_offset;
1129 struct _ATOM_TMDS_INFO *tmds_info;
1130 uint8_t frev, crev;
1131 uint16_t maxfreq;
1132 int i;
1133
1134 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1135 &frev, &crev, &data_offset)) {
1136 tmds_info =
1137 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1138 data_offset);
1139
1140 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1141 for (i = 0; i < 4; i++) {
1142 tmds->tmds_pll[i].freq =
1143 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1144 tmds->tmds_pll[i].value =
1145 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1146 tmds->tmds_pll[i].value |=
1147 (tmds_info->asMiscInfo[i].
1148 ucPLL_VCO_Gain & 0x3f) << 6;
1149 tmds->tmds_pll[i].value |=
1150 (tmds_info->asMiscInfo[i].
1151 ucPLL_DutyCycle & 0xf) << 12;
1152 tmds->tmds_pll[i].value |=
1153 (tmds_info->asMiscInfo[i].
1154 ucPLL_VoltageSwing & 0xf) << 16;
1155
1156 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1157 tmds->tmds_pll[i].freq,
1158 tmds->tmds_pll[i].value);
1159
1160 if (maxfreq == tmds->tmds_pll[i].freq) {
1161 tmds->tmds_pll[i].freq = 0xffffffff;
1162 break;
1163 }
1164 }
1165 return true;
1166 }
1167 return false;
1168 }
1169
1170 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1171 radeon_encoder
1172 *encoder,
1173 int id)
1174 {
1175 struct drm_device *dev = encoder->base.dev;
1176 struct radeon_device *rdev = dev->dev_private;
1177 struct radeon_mode_info *mode_info = &rdev->mode_info;
1178 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1179 uint16_t data_offset;
1180 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1181 uint8_t frev, crev;
1182 struct radeon_atom_ss *ss = NULL;
1183 int i;
1184
1185 if (id > ATOM_MAX_SS_ENTRY)
1186 return NULL;
1187
1188 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1189 &frev, &crev, &data_offset)) {
1190 ss_info =
1191 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1192
1193 ss =
1194 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1195
1196 if (!ss)
1197 return NULL;
1198
1199 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1200 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1201 ss->percentage =
1202 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1203 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1204 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1205 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1206 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1207 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1208 break;
1209 }
1210 }
1211 }
1212 return ss;
1213 }
1214
1215 union lvds_info {
1216 struct _ATOM_LVDS_INFO info;
1217 struct _ATOM_LVDS_INFO_V12 info_12;
1218 };
1219
1220 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1221 radeon_encoder
1222 *encoder)
1223 {
1224 struct drm_device *dev = encoder->base.dev;
1225 struct radeon_device *rdev = dev->dev_private;
1226 struct radeon_mode_info *mode_info = &rdev->mode_info;
1227 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1228 uint16_t data_offset, misc;
1229 union lvds_info *lvds_info;
1230 uint8_t frev, crev;
1231 struct radeon_encoder_atom_dig *lvds = NULL;
1232
1233 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1234 &frev, &crev, &data_offset)) {
1235 lvds_info =
1236 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1237 lvds =
1238 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1239
1240 if (!lvds)
1241 return NULL;
1242
1243 lvds->native_mode.clock =
1244 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1245 lvds->native_mode.hdisplay =
1246 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1247 lvds->native_mode.vdisplay =
1248 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1249 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1250 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1251 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1252 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1253 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1254 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1255 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1256 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1257 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1258 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1259 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1260 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1261 lvds->panel_pwr_delay =
1262 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1263 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1264
1265 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1266 if (misc & ATOM_VSYNC_POLARITY)
1267 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1268 if (misc & ATOM_HSYNC_POLARITY)
1269 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1270 if (misc & ATOM_COMPOSITESYNC)
1271 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1272 if (misc & ATOM_INTERLACE)
1273 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1274 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1275 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1276
1277 /* set crtc values */
1278 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1279
1280 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1281
1282 if (ASIC_IS_AVIVO(rdev)) {
1283 if (radeon_new_pll == 0)
1284 lvds->pll_algo = PLL_ALGO_LEGACY;
1285 else
1286 lvds->pll_algo = PLL_ALGO_NEW;
1287 } else {
1288 if (radeon_new_pll == 1)
1289 lvds->pll_algo = PLL_ALGO_NEW;
1290 else
1291 lvds->pll_algo = PLL_ALGO_LEGACY;
1292 }
1293
1294 encoder->native_mode = lvds->native_mode;
1295 }
1296 return lvds;
1297 }
1298
1299 struct radeon_encoder_primary_dac *
1300 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1301 {
1302 struct drm_device *dev = encoder->base.dev;
1303 struct radeon_device *rdev = dev->dev_private;
1304 struct radeon_mode_info *mode_info = &rdev->mode_info;
1305 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1306 uint16_t data_offset;
1307 struct _COMPASSIONATE_DATA *dac_info;
1308 uint8_t frev, crev;
1309 uint8_t bg, dac;
1310 struct radeon_encoder_primary_dac *p_dac = NULL;
1311
1312 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1313 &frev, &crev, &data_offset)) {
1314 dac_info = (struct _COMPASSIONATE_DATA *)
1315 (mode_info->atom_context->bios + data_offset);
1316
1317 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1318
1319 if (!p_dac)
1320 return NULL;
1321
1322 bg = dac_info->ucDAC1_BG_Adjustment;
1323 dac = dac_info->ucDAC1_DAC_Adjustment;
1324 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1325
1326 }
1327 return p_dac;
1328 }
1329
1330 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1331 struct drm_display_mode *mode)
1332 {
1333 struct radeon_mode_info *mode_info = &rdev->mode_info;
1334 ATOM_ANALOG_TV_INFO *tv_info;
1335 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1336 ATOM_DTD_FORMAT *dtd_timings;
1337 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1338 u8 frev, crev;
1339 u16 data_offset, misc;
1340
1341 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1342 &frev, &crev, &data_offset))
1343 return false;
1344
1345 switch (crev) {
1346 case 1:
1347 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1348 if (index >= MAX_SUPPORTED_TV_TIMING)
1349 return false;
1350
1351 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1352 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1353 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1354 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1355 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1356
1357 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1358 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1359 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1360 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1361 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1362
1363 mode->flags = 0;
1364 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1365 if (misc & ATOM_VSYNC_POLARITY)
1366 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1367 if (misc & ATOM_HSYNC_POLARITY)
1368 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1369 if (misc & ATOM_COMPOSITESYNC)
1370 mode->flags |= DRM_MODE_FLAG_CSYNC;
1371 if (misc & ATOM_INTERLACE)
1372 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1373 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1374 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1375
1376 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1377
1378 if (index == 1) {
1379 /* PAL timings appear to have wrong values for totals */
1380 mode->crtc_htotal -= 1;
1381 mode->crtc_vtotal -= 1;
1382 }
1383 break;
1384 case 2:
1385 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1386 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1387 return false;
1388
1389 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1390 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1391 le16_to_cpu(dtd_timings->usHBlanking_Time);
1392 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1393 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1394 le16_to_cpu(dtd_timings->usHSyncOffset);
1395 mode->crtc_hsync_end = mode->crtc_hsync_start +
1396 le16_to_cpu(dtd_timings->usHSyncWidth);
1397
1398 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1399 le16_to_cpu(dtd_timings->usVBlanking_Time);
1400 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1401 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1402 le16_to_cpu(dtd_timings->usVSyncOffset);
1403 mode->crtc_vsync_end = mode->crtc_vsync_start +
1404 le16_to_cpu(dtd_timings->usVSyncWidth);
1405
1406 mode->flags = 0;
1407 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1408 if (misc & ATOM_VSYNC_POLARITY)
1409 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1410 if (misc & ATOM_HSYNC_POLARITY)
1411 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1412 if (misc & ATOM_COMPOSITESYNC)
1413 mode->flags |= DRM_MODE_FLAG_CSYNC;
1414 if (misc & ATOM_INTERLACE)
1415 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1416 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1417 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1418
1419 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1420 break;
1421 }
1422 return true;
1423 }
1424
1425 enum radeon_tv_std
1426 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1427 {
1428 struct radeon_mode_info *mode_info = &rdev->mode_info;
1429 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1430 uint16_t data_offset;
1431 uint8_t frev, crev;
1432 struct _ATOM_ANALOG_TV_INFO *tv_info;
1433 enum radeon_tv_std tv_std = TV_STD_NTSC;
1434
1435 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1436 &frev, &crev, &data_offset)) {
1437
1438 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1439 (mode_info->atom_context->bios + data_offset);
1440
1441 switch (tv_info->ucTV_BootUpDefaultStandard) {
1442 case ATOM_TV_NTSC:
1443 tv_std = TV_STD_NTSC;
1444 DRM_INFO("Default TV standard: NTSC\n");
1445 break;
1446 case ATOM_TV_NTSCJ:
1447 tv_std = TV_STD_NTSC_J;
1448 DRM_INFO("Default TV standard: NTSC-J\n");
1449 break;
1450 case ATOM_TV_PAL:
1451 tv_std = TV_STD_PAL;
1452 DRM_INFO("Default TV standard: PAL\n");
1453 break;
1454 case ATOM_TV_PALM:
1455 tv_std = TV_STD_PAL_M;
1456 DRM_INFO("Default TV standard: PAL-M\n");
1457 break;
1458 case ATOM_TV_PALN:
1459 tv_std = TV_STD_PAL_N;
1460 DRM_INFO("Default TV standard: PAL-N\n");
1461 break;
1462 case ATOM_TV_PALCN:
1463 tv_std = TV_STD_PAL_CN;
1464 DRM_INFO("Default TV standard: PAL-CN\n");
1465 break;
1466 case ATOM_TV_PAL60:
1467 tv_std = TV_STD_PAL_60;
1468 DRM_INFO("Default TV standard: PAL-60\n");
1469 break;
1470 case ATOM_TV_SECAM:
1471 tv_std = TV_STD_SECAM;
1472 DRM_INFO("Default TV standard: SECAM\n");
1473 break;
1474 default:
1475 tv_std = TV_STD_NTSC;
1476 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1477 break;
1478 }
1479 }
1480 return tv_std;
1481 }
1482
1483 struct radeon_encoder_tv_dac *
1484 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1485 {
1486 struct drm_device *dev = encoder->base.dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct radeon_mode_info *mode_info = &rdev->mode_info;
1489 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1490 uint16_t data_offset;
1491 struct _COMPASSIONATE_DATA *dac_info;
1492 uint8_t frev, crev;
1493 uint8_t bg, dac;
1494 struct radeon_encoder_tv_dac *tv_dac = NULL;
1495
1496 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1497 &frev, &crev, &data_offset)) {
1498
1499 dac_info = (struct _COMPASSIONATE_DATA *)
1500 (mode_info->atom_context->bios + data_offset);
1501
1502 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1503
1504 if (!tv_dac)
1505 return NULL;
1506
1507 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1508 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1509 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1510
1511 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1512 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1513 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1514
1515 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1516 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1517 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1518
1519 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1520 }
1521 return tv_dac;
1522 }
1523
1524 static const char *thermal_controller_names[] = {
1525 "NONE",
1526 "lm63",
1527 "adm1032",
1528 "adm1030",
1529 "max6649",
1530 "lm64",
1531 "f75375",
1532 "asc7xxx",
1533 };
1534
1535 static const char *pp_lib_thermal_controller_names[] = {
1536 "NONE",
1537 "lm63",
1538 "adm1032",
1539 "adm1030",
1540 "max6649",
1541 "lm64",
1542 "f75375",
1543 "RV6xx",
1544 "RV770",
1545 "adt7473",
1546 "External GPIO",
1547 "Evergreen",
1548 "adt7473 with internal",
1549
1550 };
1551
1552 union power_info {
1553 struct _ATOM_POWERPLAY_INFO info;
1554 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1555 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1556 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1557 };
1558
1559 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1560 {
1561 struct radeon_mode_info *mode_info = &rdev->mode_info;
1562 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1563 u16 data_offset;
1564 u8 frev, crev;
1565 u32 misc, misc2 = 0, sclk, mclk;
1566 union power_info *power_info;
1567 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1568 struct _ATOM_PPLIB_STATE *power_state;
1569 int num_modes = 0, i, j;
1570 int state_index = 0, mode_index = 0;
1571 struct radeon_i2c_bus_rec i2c_bus;
1572
1573 rdev->pm.default_power_state_index = -1;
1574
1575 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1576 &frev, &crev, &data_offset)) {
1577 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1578 if (frev < 4) {
1579 /* add the i2c bus for thermal/fan chip */
1580 if (power_info->info.ucOverdriveThermalController > 0) {
1581 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1582 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1583 power_info->info.ucOverdriveControllerAddress >> 1);
1584 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1585 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1586 if (rdev->pm.i2c_bus) {
1587 struct i2c_board_info info = { };
1588 const char *name = thermal_controller_names[power_info->info.
1589 ucOverdriveThermalController];
1590 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1591 strlcpy(info.type, name, sizeof(info.type));
1592 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1593 }
1594 }
1595 num_modes = power_info->info.ucNumOfPowerModeEntries;
1596 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1597 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1598 /* last mode is usually default, array is low to high */
1599 for (i = 0; i < num_modes; i++) {
1600 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1601 switch (frev) {
1602 case 1:
1603 rdev->pm.power_state[state_index].num_clock_modes = 1;
1604 rdev->pm.power_state[state_index].clock_info[0].mclk =
1605 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1606 rdev->pm.power_state[state_index].clock_info[0].sclk =
1607 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1608 /* skip invalid modes */
1609 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1610 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1611 continue;
1612 rdev->pm.power_state[state_index].pcie_lanes =
1613 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1614 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1615 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1616 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1617 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1618 VOLTAGE_GPIO;
1619 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1620 radeon_lookup_gpio(rdev,
1621 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1622 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1623 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1624 true;
1625 else
1626 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1627 false;
1628 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1629 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1630 VOLTAGE_VDDC;
1631 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1632 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1633 }
1634 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1635 rdev->pm.power_state[state_index].misc = misc;
1636 /* order matters! */
1637 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1638 rdev->pm.power_state[state_index].type =
1639 POWER_STATE_TYPE_POWERSAVE;
1640 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1641 rdev->pm.power_state[state_index].type =
1642 POWER_STATE_TYPE_BATTERY;
1643 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1644 rdev->pm.power_state[state_index].type =
1645 POWER_STATE_TYPE_BATTERY;
1646 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1647 rdev->pm.power_state[state_index].type =
1648 POWER_STATE_TYPE_BALANCED;
1649 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1650 rdev->pm.power_state[state_index].type =
1651 POWER_STATE_TYPE_PERFORMANCE;
1652 rdev->pm.power_state[state_index].flags &=
1653 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1654 }
1655 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1656 rdev->pm.power_state[state_index].type =
1657 POWER_STATE_TYPE_DEFAULT;
1658 rdev->pm.default_power_state_index = state_index;
1659 rdev->pm.power_state[state_index].default_clock_mode =
1660 &rdev->pm.power_state[state_index].clock_info[0];
1661 rdev->pm.power_state[state_index].flags &=
1662 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1663 } else if (state_index == 0) {
1664 rdev->pm.power_state[state_index].clock_info[0].flags |=
1665 RADEON_PM_MODE_NO_DISPLAY;
1666 }
1667 state_index++;
1668 break;
1669 case 2:
1670 rdev->pm.power_state[state_index].num_clock_modes = 1;
1671 rdev->pm.power_state[state_index].clock_info[0].mclk =
1672 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1673 rdev->pm.power_state[state_index].clock_info[0].sclk =
1674 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1675 /* skip invalid modes */
1676 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1677 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1678 continue;
1679 rdev->pm.power_state[state_index].pcie_lanes =
1680 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1681 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1682 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1683 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1684 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1685 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1686 VOLTAGE_GPIO;
1687 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1688 radeon_lookup_gpio(rdev,
1689 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1690 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1691 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1692 true;
1693 else
1694 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1695 false;
1696 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1697 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1698 VOLTAGE_VDDC;
1699 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1700 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1701 }
1702 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1703 rdev->pm.power_state[state_index].misc = misc;
1704 rdev->pm.power_state[state_index].misc2 = misc2;
1705 /* order matters! */
1706 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1707 rdev->pm.power_state[state_index].type =
1708 POWER_STATE_TYPE_POWERSAVE;
1709 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1710 rdev->pm.power_state[state_index].type =
1711 POWER_STATE_TYPE_BATTERY;
1712 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1713 rdev->pm.power_state[state_index].type =
1714 POWER_STATE_TYPE_BATTERY;
1715 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1716 rdev->pm.power_state[state_index].type =
1717 POWER_STATE_TYPE_BALANCED;
1718 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1719 rdev->pm.power_state[state_index].type =
1720 POWER_STATE_TYPE_PERFORMANCE;
1721 rdev->pm.power_state[state_index].flags &=
1722 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1723 }
1724 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1725 rdev->pm.power_state[state_index].type =
1726 POWER_STATE_TYPE_BALANCED;
1727 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1728 rdev->pm.power_state[state_index].flags &=
1729 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1730 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1731 rdev->pm.power_state[state_index].type =
1732 POWER_STATE_TYPE_DEFAULT;
1733 rdev->pm.default_power_state_index = state_index;
1734 rdev->pm.power_state[state_index].default_clock_mode =
1735 &rdev->pm.power_state[state_index].clock_info[0];
1736 rdev->pm.power_state[state_index].flags &=
1737 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1738 } else if (state_index == 0) {
1739 rdev->pm.power_state[state_index].clock_info[0].flags |=
1740 RADEON_PM_MODE_NO_DISPLAY;
1741 }
1742 state_index++;
1743 break;
1744 case 3:
1745 rdev->pm.power_state[state_index].num_clock_modes = 1;
1746 rdev->pm.power_state[state_index].clock_info[0].mclk =
1747 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1748 rdev->pm.power_state[state_index].clock_info[0].sclk =
1749 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1750 /* skip invalid modes */
1751 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1752 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1753 continue;
1754 rdev->pm.power_state[state_index].pcie_lanes =
1755 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1756 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1757 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1758 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1759 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1760 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1761 VOLTAGE_GPIO;
1762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1763 radeon_lookup_gpio(rdev,
1764 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1765 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1766 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1767 true;
1768 else
1769 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1770 false;
1771 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1772 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1773 VOLTAGE_VDDC;
1774 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1775 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1776 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1777 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1778 true;
1779 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1780 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1781 }
1782 }
1783 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1784 rdev->pm.power_state[state_index].misc = misc;
1785 rdev->pm.power_state[state_index].misc2 = misc2;
1786 /* order matters! */
1787 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1788 rdev->pm.power_state[state_index].type =
1789 POWER_STATE_TYPE_POWERSAVE;
1790 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1791 rdev->pm.power_state[state_index].type =
1792 POWER_STATE_TYPE_BATTERY;
1793 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1794 rdev->pm.power_state[state_index].type =
1795 POWER_STATE_TYPE_BATTERY;
1796 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1797 rdev->pm.power_state[state_index].type =
1798 POWER_STATE_TYPE_BALANCED;
1799 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1800 rdev->pm.power_state[state_index].type =
1801 POWER_STATE_TYPE_PERFORMANCE;
1802 rdev->pm.power_state[state_index].flags &=
1803 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1804 }
1805 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1806 rdev->pm.power_state[state_index].type =
1807 POWER_STATE_TYPE_BALANCED;
1808 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1809 rdev->pm.power_state[state_index].type =
1810 POWER_STATE_TYPE_DEFAULT;
1811 rdev->pm.default_power_state_index = state_index;
1812 rdev->pm.power_state[state_index].default_clock_mode =
1813 &rdev->pm.power_state[state_index].clock_info[0];
1814 } else if (state_index == 0) {
1815 rdev->pm.power_state[state_index].clock_info[0].flags |=
1816 RADEON_PM_MODE_NO_DISPLAY;
1817 }
1818 state_index++;
1819 break;
1820 }
1821 }
1822 /* last mode is usually default */
1823 if (rdev->pm.default_power_state_index == -1) {
1824 rdev->pm.power_state[state_index - 1].type =
1825 POWER_STATE_TYPE_DEFAULT;
1826 rdev->pm.default_power_state_index = state_index - 1;
1827 rdev->pm.power_state[state_index - 1].default_clock_mode =
1828 &rdev->pm.power_state[state_index - 1].clock_info[0];
1829 rdev->pm.power_state[state_index].flags &=
1830 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1831 rdev->pm.power_state[state_index].misc = 0;
1832 rdev->pm.power_state[state_index].misc2 = 0;
1833 }
1834 } else {
1835 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1836 uint8_t fw_frev, fw_crev;
1837 uint16_t fw_data_offset, vddc = 0;
1838 union firmware_info *firmware_info;
1839 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1840
1841 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1842 &fw_frev, &fw_crev, &fw_data_offset)) {
1843 firmware_info =
1844 (union firmware_info *)(mode_info->atom_context->bios +
1845 fw_data_offset);
1846 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1847 }
1848
1849 /* add the i2c bus for thermal/fan chip */
1850 if (controller->ucType > 0) {
1851 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
1852 DRM_INFO("Internal thermal controller %s fan control\n",
1853 (controller->ucFanParameters &
1854 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1855 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1856 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1857 DRM_INFO("Internal thermal controller %s fan control\n",
1858 (controller->ucFanParameters &
1859 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1860 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1861 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1862 DRM_INFO("Internal thermal controller %s fan control\n",
1863 (controller->ucFanParameters &
1864 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1865 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
1866 } else if ((controller->ucType ==
1867 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1868 (controller->ucType ==
1869 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1870 DRM_INFO("Special thermal controller config\n");
1871 } else {
1872 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1873 pp_lib_thermal_controller_names[controller->ucType],
1874 controller->ucI2cAddress >> 1,
1875 (controller->ucFanParameters &
1876 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1877 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1878 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1879 if (rdev->pm.i2c_bus) {
1880 struct i2c_board_info info = { };
1881 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1882 info.addr = controller->ucI2cAddress >> 1;
1883 strlcpy(info.type, name, sizeof(info.type));
1884 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1885 }
1886
1887 }
1888 }
1889 /* first mode is usually default, followed by low to high */
1890 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1891 mode_index = 0;
1892 power_state = (struct _ATOM_PPLIB_STATE *)
1893 (mode_info->atom_context->bios +
1894 data_offset +
1895 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1896 i * power_info->info_4.ucStateEntrySize);
1897 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1898 (mode_info->atom_context->bios +
1899 data_offset +
1900 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1901 (power_state->ucNonClockStateIndex *
1902 power_info->info_4.ucNonClockSize));
1903 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1904 if (rdev->flags & RADEON_IS_IGP) {
1905 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1906 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1907 (mode_info->atom_context->bios +
1908 data_offset +
1909 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1910 (power_state->ucClockStateIndices[j] *
1911 power_info->info_4.ucClockInfoSize));
1912 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1913 sclk |= clock_info->ucLowEngineClockHigh << 16;
1914 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1915 /* skip invalid modes */
1916 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1917 continue;
1918 /* voltage works differently on IGPs */
1919 mode_index++;
1920 } else if (ASIC_IS_DCE4(rdev)) {
1921 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1922 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1923 (mode_info->atom_context->bios +
1924 data_offset +
1925 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1926 (power_state->ucClockStateIndices[j] *
1927 power_info->info_4.ucClockInfoSize));
1928 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1929 sclk |= clock_info->ucEngineClockHigh << 16;
1930 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1931 mclk |= clock_info->ucMemoryClockHigh << 16;
1932 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1933 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1934 /* skip invalid modes */
1935 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1936 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1937 continue;
1938 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1939 VOLTAGE_SW;
1940 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1941 clock_info->usVDDC;
1942 /* XXX usVDDCI */
1943 mode_index++;
1944 } else {
1945 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1946 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1947 (mode_info->atom_context->bios +
1948 data_offset +
1949 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1950 (power_state->ucClockStateIndices[j] *
1951 power_info->info_4.ucClockInfoSize));
1952 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1953 sclk |= clock_info->ucEngineClockHigh << 16;
1954 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1955 mclk |= clock_info->ucMemoryClockHigh << 16;
1956 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1957 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1958 /* skip invalid modes */
1959 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1960 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1961 continue;
1962 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1963 VOLTAGE_SW;
1964 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1965 clock_info->usVDDC;
1966 mode_index++;
1967 }
1968 }
1969 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1970 if (mode_index) {
1971 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1972 misc2 = le16_to_cpu(non_clock_info->usClassification);
1973 rdev->pm.power_state[state_index].misc = misc;
1974 rdev->pm.power_state[state_index].misc2 = misc2;
1975 rdev->pm.power_state[state_index].pcie_lanes =
1976 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1977 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1978 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1979 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1980 rdev->pm.power_state[state_index].type =
1981 POWER_STATE_TYPE_BATTERY;
1982 break;
1983 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1984 rdev->pm.power_state[state_index].type =
1985 POWER_STATE_TYPE_BALANCED;
1986 break;
1987 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1988 rdev->pm.power_state[state_index].type =
1989 POWER_STATE_TYPE_PERFORMANCE;
1990 break;
1991 }
1992 rdev->pm.power_state[state_index].flags = 0;
1993 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1994 rdev->pm.power_state[state_index].flags |=
1995 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1996 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1997 rdev->pm.power_state[state_index].type =
1998 POWER_STATE_TYPE_DEFAULT;
1999 rdev->pm.default_power_state_index = state_index;
2000 rdev->pm.power_state[state_index].default_clock_mode =
2001 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2002 /* patch the table values with the default slck/mclk from firmware info */
2003 for (j = 0; j < mode_index; j++) {
2004 rdev->pm.power_state[state_index].clock_info[j].mclk =
2005 rdev->clock.default_mclk;
2006 rdev->pm.power_state[state_index].clock_info[j].sclk =
2007 rdev->clock.default_sclk;
2008 if (vddc)
2009 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2010 vddc;
2011 }
2012 }
2013 state_index++;
2014 }
2015 }
2016 /* if multiple clock modes, mark the lowest as no display */
2017 for (i = 0; i < state_index; i++) {
2018 if (rdev->pm.power_state[i].num_clock_modes > 1)
2019 rdev->pm.power_state[i].clock_info[0].flags |=
2020 RADEON_PM_MODE_NO_DISPLAY;
2021 }
2022 /* first mode is usually default */
2023 if (rdev->pm.default_power_state_index == -1) {
2024 rdev->pm.power_state[0].type =
2025 POWER_STATE_TYPE_DEFAULT;
2026 rdev->pm.default_power_state_index = 0;
2027 rdev->pm.power_state[0].default_clock_mode =
2028 &rdev->pm.power_state[0].clock_info[0];
2029 }
2030 }
2031 } else {
2032 /* add the default mode */
2033 rdev->pm.power_state[state_index].type =
2034 POWER_STATE_TYPE_DEFAULT;
2035 rdev->pm.power_state[state_index].num_clock_modes = 1;
2036 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2037 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2038 rdev->pm.power_state[state_index].default_clock_mode =
2039 &rdev->pm.power_state[state_index].clock_info[0];
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2041 rdev->pm.power_state[state_index].pcie_lanes = 16;
2042 rdev->pm.default_power_state_index = state_index;
2043 rdev->pm.power_state[state_index].flags = 0;
2044 state_index++;
2045 }
2046
2047 rdev->pm.num_power_states = state_index;
2048
2049 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2050 rdev->pm.current_clock_mode_index = 0;
2051 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2052 }
2053
2054 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2055 {
2056 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2057 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2058
2059 args.ucEnable = enable;
2060
2061 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2062 }
2063
2064 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2065 {
2066 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2067 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2068
2069 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2070 return args.ulReturnEngineClock;
2071 }
2072
2073 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2074 {
2075 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2076 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2077
2078 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2079 return args.ulReturnMemoryClock;
2080 }
2081
2082 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2083 uint32_t eng_clock)
2084 {
2085 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2086 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2087
2088 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2089
2090 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2091 }
2092
2093 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2094 uint32_t mem_clock)
2095 {
2096 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2097 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2098
2099 if (rdev->flags & RADEON_IS_IGP)
2100 return;
2101
2102 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2103
2104 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2105 }
2106
2107 union set_voltage {
2108 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2109 struct _SET_VOLTAGE_PARAMETERS v1;
2110 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2111 };
2112
2113 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2114 {
2115 union set_voltage args;
2116 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2117 u8 frev, crev, volt_index = level;
2118
2119 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2120 return;
2121
2122 switch (crev) {
2123 case 1:
2124 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2125 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2126 args.v1.ucVoltageIndex = volt_index;
2127 break;
2128 case 2:
2129 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2130 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2131 args.v2.usVoltageLevel = cpu_to_le16(level);
2132 break;
2133 default:
2134 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2135 return;
2136 }
2137
2138 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2139 }
2140
2141
2142
2143 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2144 {
2145 struct radeon_device *rdev = dev->dev_private;
2146 uint32_t bios_2_scratch, bios_6_scratch;
2147
2148 if (rdev->family >= CHIP_R600) {
2149 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2150 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2151 } else {
2152 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2153 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2154 }
2155
2156 /* let the bios control the backlight */
2157 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2158
2159 /* tell the bios not to handle mode switching */
2160 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2161
2162 if (rdev->family >= CHIP_R600) {
2163 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2164 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2165 } else {
2166 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2167 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2168 }
2169
2170 }
2171
2172 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2173 {
2174 uint32_t scratch_reg;
2175 int i;
2176
2177 if (rdev->family >= CHIP_R600)
2178 scratch_reg = R600_BIOS_0_SCRATCH;
2179 else
2180 scratch_reg = RADEON_BIOS_0_SCRATCH;
2181
2182 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2183 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2184 }
2185
2186 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2187 {
2188 uint32_t scratch_reg;
2189 int i;
2190
2191 if (rdev->family >= CHIP_R600)
2192 scratch_reg = R600_BIOS_0_SCRATCH;
2193 else
2194 scratch_reg = RADEON_BIOS_0_SCRATCH;
2195
2196 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2197 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2198 }
2199
2200 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2201 {
2202 struct drm_device *dev = encoder->dev;
2203 struct radeon_device *rdev = dev->dev_private;
2204 uint32_t bios_6_scratch;
2205
2206 if (rdev->family >= CHIP_R600)
2207 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2208 else
2209 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2210
2211 if (lock)
2212 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2213 else
2214 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2215
2216 if (rdev->family >= CHIP_R600)
2217 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2218 else
2219 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2220 }
2221
2222 /* at some point we may want to break this out into individual functions */
2223 void
2224 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2225 struct drm_encoder *encoder,
2226 bool connected)
2227 {
2228 struct drm_device *dev = connector->dev;
2229 struct radeon_device *rdev = dev->dev_private;
2230 struct radeon_connector *radeon_connector =
2231 to_radeon_connector(connector);
2232 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2233 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2234
2235 if (rdev->family >= CHIP_R600) {
2236 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2237 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2238 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2239 } else {
2240 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2241 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2242 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2243 }
2244
2245 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2246 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2247 if (connected) {
2248 DRM_DEBUG_KMS("TV1 connected\n");
2249 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2250 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2251 } else {
2252 DRM_DEBUG_KMS("TV1 disconnected\n");
2253 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2254 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2255 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2256 }
2257 }
2258 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2259 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2260 if (connected) {
2261 DRM_DEBUG_KMS("CV connected\n");
2262 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2263 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2264 } else {
2265 DRM_DEBUG_KMS("CV disconnected\n");
2266 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2267 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2268 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2269 }
2270 }
2271 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2272 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2273 if (connected) {
2274 DRM_DEBUG_KMS("LCD1 connected\n");
2275 bios_0_scratch |= ATOM_S0_LCD1;
2276 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2277 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2278 } else {
2279 DRM_DEBUG_KMS("LCD1 disconnected\n");
2280 bios_0_scratch &= ~ATOM_S0_LCD1;
2281 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2282 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2283 }
2284 }
2285 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2286 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2287 if (connected) {
2288 DRM_DEBUG_KMS("CRT1 connected\n");
2289 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2290 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2291 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2292 } else {
2293 DRM_DEBUG_KMS("CRT1 disconnected\n");
2294 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2295 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2296 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2297 }
2298 }
2299 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2300 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2301 if (connected) {
2302 DRM_DEBUG_KMS("CRT2 connected\n");
2303 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2304 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2305 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2306 } else {
2307 DRM_DEBUG_KMS("CRT2 disconnected\n");
2308 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2309 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2310 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2311 }
2312 }
2313 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2314 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2315 if (connected) {
2316 DRM_DEBUG_KMS("DFP1 connected\n");
2317 bios_0_scratch |= ATOM_S0_DFP1;
2318 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2319 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2320 } else {
2321 DRM_DEBUG_KMS("DFP1 disconnected\n");
2322 bios_0_scratch &= ~ATOM_S0_DFP1;
2323 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2324 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2325 }
2326 }
2327 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2328 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2329 if (connected) {
2330 DRM_DEBUG_KMS("DFP2 connected\n");
2331 bios_0_scratch |= ATOM_S0_DFP2;
2332 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2333 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2334 } else {
2335 DRM_DEBUG_KMS("DFP2 disconnected\n");
2336 bios_0_scratch &= ~ATOM_S0_DFP2;
2337 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2338 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2339 }
2340 }
2341 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2342 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2343 if (connected) {
2344 DRM_DEBUG_KMS("DFP3 connected\n");
2345 bios_0_scratch |= ATOM_S0_DFP3;
2346 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2347 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2348 } else {
2349 DRM_DEBUG_KMS("DFP3 disconnected\n");
2350 bios_0_scratch &= ~ATOM_S0_DFP3;
2351 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2352 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2353 }
2354 }
2355 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2356 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2357 if (connected) {
2358 DRM_DEBUG_KMS("DFP4 connected\n");
2359 bios_0_scratch |= ATOM_S0_DFP4;
2360 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2361 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2362 } else {
2363 DRM_DEBUG_KMS("DFP4 disconnected\n");
2364 bios_0_scratch &= ~ATOM_S0_DFP4;
2365 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2366 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2367 }
2368 }
2369 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2370 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2371 if (connected) {
2372 DRM_DEBUG_KMS("DFP5 connected\n");
2373 bios_0_scratch |= ATOM_S0_DFP5;
2374 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2375 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2376 } else {
2377 DRM_DEBUG_KMS("DFP5 disconnected\n");
2378 bios_0_scratch &= ~ATOM_S0_DFP5;
2379 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2380 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2381 }
2382 }
2383
2384 if (rdev->family >= CHIP_R600) {
2385 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2386 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2387 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2388 } else {
2389 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2390 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2391 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2392 }
2393 }
2394
2395 void
2396 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2397 {
2398 struct drm_device *dev = encoder->dev;
2399 struct radeon_device *rdev = dev->dev_private;
2400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2401 uint32_t bios_3_scratch;
2402
2403 if (rdev->family >= CHIP_R600)
2404 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2405 else
2406 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2407
2408 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2409 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2410 bios_3_scratch |= (crtc << 18);
2411 }
2412 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2413 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2414 bios_3_scratch |= (crtc << 24);
2415 }
2416 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2417 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2418 bios_3_scratch |= (crtc << 16);
2419 }
2420 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2421 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2422 bios_3_scratch |= (crtc << 20);
2423 }
2424 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2425 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2426 bios_3_scratch |= (crtc << 17);
2427 }
2428 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2429 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2430 bios_3_scratch |= (crtc << 19);
2431 }
2432 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2433 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2434 bios_3_scratch |= (crtc << 23);
2435 }
2436 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2437 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2438 bios_3_scratch |= (crtc << 25);
2439 }
2440
2441 if (rdev->family >= CHIP_R600)
2442 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2443 else
2444 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2445 }
2446
2447 void
2448 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2449 {
2450 struct drm_device *dev = encoder->dev;
2451 struct radeon_device *rdev = dev->dev_private;
2452 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2453 uint32_t bios_2_scratch;
2454
2455 if (rdev->family >= CHIP_R600)
2456 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2457 else
2458 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2459
2460 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2461 if (on)
2462 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2463 else
2464 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2465 }
2466 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2467 if (on)
2468 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2469 else
2470 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2471 }
2472 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2473 if (on)
2474 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2475 else
2476 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2477 }
2478 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2479 if (on)
2480 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2481 else
2482 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2483 }
2484 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2485 if (on)
2486 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2487 else
2488 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2489 }
2490 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2491 if (on)
2492 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2493 else
2494 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2495 }
2496 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2497 if (on)
2498 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2499 else
2500 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2501 }
2502 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2503 if (on)
2504 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2505 else
2506 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2507 }
2508 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2509 if (on)
2510 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2511 else
2512 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2513 }
2514 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2515 if (on)
2516 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2517 else
2518 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2519 }
2520
2521 if (rdev->family >= CHIP_R600)
2522 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2523 else
2524 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2525 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree