2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/errno.h>
30 #include <linux/delay.h>
34 #include <asm/hardware.h>
35 #include <asm/delay.h>
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/pxa-regs.h>
40 #include <asm/arch/pxa2xx_spi.h>
42 MODULE_AUTHOR("Stephen Street");
43 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
44 MODULE_LICENSE("GPL");
48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
52 #define DEFINE_SSP_REG(reg, off) \
53 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
54 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
56 DEFINE_SSP_REG(SSCR0
, 0x00)
57 DEFINE_SSP_REG(SSCR1
, 0x04)
58 DEFINE_SSP_REG(SSSR
, 0x08)
59 DEFINE_SSP_REG(SSITR
, 0x0c)
60 DEFINE_SSP_REG(SSDR
, 0x10)
61 DEFINE_SSP_REG(SSTO
, 0x28)
62 DEFINE_SSP_REG(SSPSP
, 0x2c)
64 #define START_STATE ((void*)0)
65 #define RUNNING_STATE ((void*)1)
66 #define DONE_STATE ((void*)2)
67 #define ERROR_STATE ((void*)-1)
69 #define QUEUE_RUNNING 0
70 #define QUEUE_STOPPED 1
73 /* Driver model hookup */
74 struct platform_device
*pdev
;
76 /* SPI framework hookup */
77 enum pxa_ssp_type ssp_type
;
78 struct spi_master
*master
;
81 struct pxa2xx_spi_master
*master_info
;
88 /* SSP register addresses */
98 /* Driver message queue */
99 struct workqueue_struct
*workqueue
;
100 struct work_struct pump_messages
;
102 struct list_head queue
;
106 /* Message Transfer pump */
107 struct tasklet_struct pump_transfers
;
109 /* Current message transfer state info */
110 struct spi_message
* cur_msg
;
111 struct spi_transfer
* cur_transfer
;
112 struct chip_data
*cur_chip
;
126 void (*write
)(struct driver_data
*drv_data
);
127 void (*read
)(struct driver_data
*drv_data
);
128 irqreturn_t (*transfer_handler
)(struct driver_data
*drv_data
);
129 void (*cs_control
)(u32 command
);
146 void (*write
)(struct driver_data
*drv_data
);
147 void (*read
)(struct driver_data
*drv_data
);
148 void (*cs_control
)(u32 command
);
151 static void pump_messages(struct work_struct
*work
);
153 static int flush(struct driver_data
*drv_data
)
155 unsigned long limit
= loops_per_jiffy
<< 1;
157 void *reg
= drv_data
->ioaddr
;
160 while (read_SSSR(reg
) & SSSR_RNE
) {
163 } while ((read_SSSR(reg
) & SSSR_BSY
) && limit
--);
164 write_SSSR(SSSR_ROR
, reg
);
169 static void restore_state(struct driver_data
*drv_data
)
171 void *reg
= drv_data
->ioaddr
;
173 /* Clear status and disable clock */
174 write_SSSR(drv_data
->clear_sr
, reg
);
175 write_SSCR0(drv_data
->cur_chip
->cr0
& ~SSCR0_SSE
, reg
);
177 /* Load the registers */
178 write_SSCR1(drv_data
->cur_chip
->cr1
, reg
);
179 write_SSCR0(drv_data
->cur_chip
->cr0
, reg
);
180 if (drv_data
->ssp_type
!= PXA25x_SSP
) {
182 write_SSPSP(drv_data
->cur_chip
->psp
, reg
);
186 static void null_cs_control(u32 command
)
190 static void null_writer(struct driver_data
*drv_data
)
192 void *reg
= drv_data
->ioaddr
;
193 u8 n_bytes
= drv_data
->n_bytes
;
195 while ((read_SSSR(reg
) & SSSR_TNF
)
196 && (drv_data
->tx
< drv_data
->tx_end
)) {
198 drv_data
->tx
+= n_bytes
;
202 static void null_reader(struct driver_data
*drv_data
)
204 void *reg
= drv_data
->ioaddr
;
205 u8 n_bytes
= drv_data
->n_bytes
;
207 while ((read_SSSR(reg
) & SSSR_RNE
)
208 && (drv_data
->rx
< drv_data
->rx_end
)) {
210 drv_data
->rx
+= n_bytes
;
214 static void u8_writer(struct driver_data
*drv_data
)
216 void *reg
= drv_data
->ioaddr
;
218 while ((read_SSSR(reg
) & SSSR_TNF
)
219 && (drv_data
->tx
< drv_data
->tx_end
)) {
220 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
225 static void u8_reader(struct driver_data
*drv_data
)
227 void *reg
= drv_data
->ioaddr
;
229 while ((read_SSSR(reg
) & SSSR_RNE
)
230 && (drv_data
->rx
< drv_data
->rx_end
)) {
231 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
236 static void u16_writer(struct driver_data
*drv_data
)
238 void *reg
= drv_data
->ioaddr
;
240 while ((read_SSSR(reg
) & SSSR_TNF
)
241 && (drv_data
->tx
< drv_data
->tx_end
)) {
242 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
247 static void u16_reader(struct driver_data
*drv_data
)
249 void *reg
= drv_data
->ioaddr
;
251 while ((read_SSSR(reg
) & SSSR_RNE
)
252 && (drv_data
->rx
< drv_data
->rx_end
)) {
253 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
257 static void u32_writer(struct driver_data
*drv_data
)
259 void *reg
= drv_data
->ioaddr
;
261 while ((read_SSSR(reg
) & SSSR_TNF
)
262 && (drv_data
->tx
< drv_data
->tx_end
)) {
263 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
268 static void u32_reader(struct driver_data
*drv_data
)
270 void *reg
= drv_data
->ioaddr
;
272 while ((read_SSSR(reg
) & SSSR_RNE
)
273 && (drv_data
->rx
< drv_data
->rx_end
)) {
274 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
279 static void *next_transfer(struct driver_data
*drv_data
)
281 struct spi_message
*msg
= drv_data
->cur_msg
;
282 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
284 /* Move to next transfer */
285 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
286 drv_data
->cur_transfer
=
287 list_entry(trans
->transfer_list
.next
,
290 return RUNNING_STATE
;
295 static int map_dma_buffers(struct driver_data
*drv_data
)
297 struct spi_message
*msg
= drv_data
->cur_msg
;
298 struct device
*dev
= &msg
->spi
->dev
;
300 if (!drv_data
->cur_chip
->enable_dma
)
303 if (msg
->is_dma_mapped
)
304 return drv_data
->rx_dma
&& drv_data
->tx_dma
;
306 if (!IS_DMA_ALIGNED(drv_data
->rx
) || !IS_DMA_ALIGNED(drv_data
->tx
))
309 /* Modify setup if rx buffer is null */
310 if (drv_data
->rx
== NULL
) {
311 *drv_data
->null_dma_buf
= 0;
312 drv_data
->rx
= drv_data
->null_dma_buf
;
313 drv_data
->rx_map_len
= 4;
315 drv_data
->rx_map_len
= drv_data
->len
;
318 /* Modify setup if tx buffer is null */
319 if (drv_data
->tx
== NULL
) {
320 *drv_data
->null_dma_buf
= 0;
321 drv_data
->tx
= drv_data
->null_dma_buf
;
322 drv_data
->tx_map_len
= 4;
324 drv_data
->tx_map_len
= drv_data
->len
;
326 /* Stream map the rx buffer */
327 drv_data
->rx_dma
= dma_map_single(dev
, drv_data
->rx
,
328 drv_data
->rx_map_len
,
330 if (dma_mapping_error(drv_data
->rx_dma
))
333 /* Stream map the tx buffer */
334 drv_data
->tx_dma
= dma_map_single(dev
, drv_data
->tx
,
335 drv_data
->tx_map_len
,
338 if (dma_mapping_error(drv_data
->tx_dma
)) {
339 dma_unmap_single(dev
, drv_data
->rx_dma
,
340 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
347 static void unmap_dma_buffers(struct driver_data
*drv_data
)
351 if (!drv_data
->dma_mapped
)
354 if (!drv_data
->cur_msg
->is_dma_mapped
) {
355 dev
= &drv_data
->cur_msg
->spi
->dev
;
356 dma_unmap_single(dev
, drv_data
->rx_dma
,
357 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
358 dma_unmap_single(dev
, drv_data
->tx_dma
,
359 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
362 drv_data
->dma_mapped
= 0;
365 /* caller already set message->status; dma and pio irqs are blocked */
366 static void giveback(struct driver_data
*drv_data
)
368 struct spi_transfer
* last_transfer
;
370 struct spi_message
*msg
;
372 spin_lock_irqsave(&drv_data
->lock
, flags
);
373 msg
= drv_data
->cur_msg
;
374 drv_data
->cur_msg
= NULL
;
375 drv_data
->cur_transfer
= NULL
;
376 drv_data
->cur_chip
= NULL
;
377 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
378 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
380 last_transfer
= list_entry(msg
->transfers
.prev
,
384 if (!last_transfer
->cs_change
)
385 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
389 msg
->complete(msg
->context
);
392 static int wait_ssp_rx_stall(void *ioaddr
)
394 unsigned long limit
= loops_per_jiffy
<< 1;
396 while ((read_SSSR(ioaddr
) & SSSR_BSY
) && limit
--)
402 static int wait_dma_channel_stop(int channel
)
404 unsigned long limit
= loops_per_jiffy
<< 1;
406 while (!(DCSR(channel
) & DCSR_STOPSTATE
) && limit
--)
412 static void dma_handler(int channel
, void *data
)
414 struct driver_data
*drv_data
= data
;
415 struct spi_message
*msg
= drv_data
->cur_msg
;
416 void *reg
= drv_data
->ioaddr
;
417 u32 irq_status
= DCSR(channel
) & DMA_INT_MASK
;
418 u32 trailing_sssr
= 0;
420 if (irq_status
& DCSR_BUSERR
) {
422 /* Disable interrupts, clear status and reset DMA */
423 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
424 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
425 if (drv_data
->ssp_type
!= PXA25x_SSP
)
427 write_SSSR(drv_data
->clear_sr
, reg
);
428 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
429 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
431 if (flush(drv_data
) == 0)
432 dev_err(&drv_data
->pdev
->dev
,
433 "dma_handler: flush fail\n");
435 unmap_dma_buffers(drv_data
);
437 if (channel
== drv_data
->tx_channel
)
438 dev_err(&drv_data
->pdev
->dev
,
439 "dma_handler: bad bus address on "
440 "tx channel %d, source %x target = %x\n",
441 channel
, DSADR(channel
), DTADR(channel
));
443 dev_err(&drv_data
->pdev
->dev
,
444 "dma_handler: bad bus address on "
445 "rx channel %d, source %x target = %x\n",
446 channel
, DSADR(channel
), DTADR(channel
));
448 msg
->state
= ERROR_STATE
;
449 tasklet_schedule(&drv_data
->pump_transfers
);
452 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
453 if ((drv_data
->ssp_type
== PXA25x_SSP
)
454 && (channel
== drv_data
->tx_channel
)
455 && (irq_status
& DCSR_ENDINTR
)) {
457 /* Wait for rx to stall */
458 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
459 dev_err(&drv_data
->pdev
->dev
,
460 "dma_handler: ssp rx stall failed\n");
462 /* Clear and disable interrupts on SSP and DMA channels*/
463 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
464 write_SSSR(drv_data
->clear_sr
, reg
);
465 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
466 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
467 if (wait_dma_channel_stop(drv_data
->rx_channel
) == 0)
468 dev_err(&drv_data
->pdev
->dev
,
469 "dma_handler: dma rx channel stop failed\n");
471 unmap_dma_buffers(drv_data
);
473 /* Read trailing bytes */
474 /* Calculate number of trailing bytes, read them */
475 trailing_sssr
= read_SSSR(reg
);
476 if ((trailing_sssr
& 0xf008) != 0xf000) {
477 drv_data
->rx
= drv_data
->rx_end
-
478 (((trailing_sssr
>> 12) & 0x0f) + 1);
479 drv_data
->read(drv_data
);
481 msg
->actual_length
+= drv_data
->len
;
483 /* Release chip select if requested, transfer delays are
484 * handled in pump_transfers */
485 if (drv_data
->cs_change
)
486 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
488 /* Move to next transfer */
489 msg
->state
= next_transfer(drv_data
);
491 /* Schedule transfer tasklet */
492 tasklet_schedule(&drv_data
->pump_transfers
);
496 static irqreturn_t
dma_transfer(struct driver_data
*drv_data
)
499 u32 trailing_sssr
= 0;
500 struct spi_message
*msg
= drv_data
->cur_msg
;
501 void *reg
= drv_data
->ioaddr
;
503 irq_status
= read_SSSR(reg
) & drv_data
->mask_sr
;
504 if (irq_status
& SSSR_ROR
) {
505 /* Clear and disable interrupts on SSP and DMA channels*/
506 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
507 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
508 if (drv_data
->ssp_type
!= PXA25x_SSP
)
510 write_SSSR(drv_data
->clear_sr
, reg
);
511 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
512 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
513 unmap_dma_buffers(drv_data
);
515 if (flush(drv_data
) == 0)
516 dev_err(&drv_data
->pdev
->dev
,
517 "dma_transfer: flush fail\n");
519 dev_warn(&drv_data
->pdev
->dev
, "dma_transfer: fifo overun\n");
521 drv_data
->cur_msg
->state
= ERROR_STATE
;
522 tasklet_schedule(&drv_data
->pump_transfers
);
527 /* Check for false positive timeout */
528 if ((irq_status
& SSSR_TINT
) && DCSR(drv_data
->tx_channel
) & DCSR_RUN
) {
529 write_SSSR(SSSR_TINT
, reg
);
533 if (irq_status
& SSSR_TINT
|| drv_data
->rx
== drv_data
->rx_end
) {
535 /* Clear and disable interrupts on SSP and DMA channels*/
536 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
537 if (drv_data
->ssp_type
!= PXA25x_SSP
)
539 write_SSSR(drv_data
->clear_sr
, reg
);
540 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
541 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
543 if (wait_dma_channel_stop(drv_data
->rx_channel
) == 0)
544 dev_err(&drv_data
->pdev
->dev
,
545 "dma_transfer: dma rx channel stop failed\n");
547 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
548 dev_err(&drv_data
->pdev
->dev
,
549 "dma_transfer: ssp rx stall failed\n");
551 unmap_dma_buffers(drv_data
);
553 /* Calculate number of trailing bytes, read them */
554 trailing_sssr
= read_SSSR(reg
);
555 if ((trailing_sssr
& 0xf008) != 0xf000) {
556 drv_data
->rx
= drv_data
->rx_end
-
557 (((trailing_sssr
>> 12) & 0x0f) + 1);
558 drv_data
->read(drv_data
);
560 msg
->actual_length
+= drv_data
->len
;
562 /* Release chip select if requested, transfer delays are
563 * handled in pump_transfers */
564 if (drv_data
->cs_change
)
565 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
567 /* Move to next transfer */
568 msg
->state
= next_transfer(drv_data
);
570 /* Schedule transfer tasklet */
571 tasklet_schedule(&drv_data
->pump_transfers
);
576 /* Opps problem detected */
580 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
582 struct spi_message
*msg
= drv_data
->cur_msg
;
583 void *reg
= drv_data
->ioaddr
;
584 unsigned long limit
= loops_per_jiffy
<< 1;
586 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
587 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
589 while ((irq_status
= read_SSSR(reg
) & irq_mask
)) {
591 if (irq_status
& SSSR_ROR
) {
593 /* Clear and disable interrupts */
594 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
595 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
596 if (drv_data
->ssp_type
!= PXA25x_SSP
)
598 write_SSSR(drv_data
->clear_sr
, reg
);
600 if (flush(drv_data
) == 0)
601 dev_err(&drv_data
->pdev
->dev
,
602 "interrupt_transfer: flush fail\n");
606 dev_warn(&drv_data
->pdev
->dev
,
607 "interrupt_transfer: fifo overun\n");
609 msg
->state
= ERROR_STATE
;
610 tasklet_schedule(&drv_data
->pump_transfers
);
615 /* Look for false positive timeout */
616 if ((irq_status
& SSSR_TINT
)
617 && (drv_data
->rx
< drv_data
->rx_end
))
618 write_SSSR(SSSR_TINT
, reg
);
621 drv_data
->read(drv_data
);
622 drv_data
->write(drv_data
);
624 if (drv_data
->tx
== drv_data
->tx_end
) {
625 /* Disable tx interrupt */
626 write_SSCR1(read_SSCR1(reg
) & ~SSCR1_TIE
, reg
);
627 irq_mask
= drv_data
->mask_sr
& ~SSSR_TFS
;
629 /* PXA25x_SSP has no timeout, read trailing bytes */
630 if (drv_data
->ssp_type
== PXA25x_SSP
) {
631 while ((read_SSSR(reg
) & SSSR_BSY
) && limit
--)
632 drv_data
->read(drv_data
);
635 dev_err(&drv_data
->pdev
->dev
,
636 "interrupt_transfer: "
637 "trailing byte read failed\n");
641 if ((irq_status
& SSSR_TINT
)
642 || (drv_data
->rx
== drv_data
->rx_end
)) {
645 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
646 if (drv_data
->ssp_type
!= PXA25x_SSP
)
648 write_SSSR(drv_data
->clear_sr
, reg
);
650 /* Update total byte transfered */
651 msg
->actual_length
+= drv_data
->len
;
653 /* Release chip select if requested, transfer delays are
654 * handled in pump_transfers */
655 if (drv_data
->cs_change
)
656 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
658 /* Move to next transfer */
659 msg
->state
= next_transfer(drv_data
);
661 /* Schedule transfer tasklet */
662 tasklet_schedule(&drv_data
->pump_transfers
);
666 /* We did something */
670 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
672 struct driver_data
*drv_data
= dev_id
;
673 void *reg
= drv_data
->ioaddr
;
675 if (!drv_data
->cur_msg
) {
677 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
678 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
679 if (drv_data
->ssp_type
!= PXA25x_SSP
)
681 write_SSSR(drv_data
->clear_sr
, reg
);
683 dev_err(&drv_data
->pdev
->dev
, "bad message state "
684 "in interrupt handler");
690 return drv_data
->transfer_handler(drv_data
);
693 static void pump_transfers(unsigned long data
)
695 struct driver_data
*drv_data
= (struct driver_data
*)data
;
696 struct spi_message
*message
= NULL
;
697 struct spi_transfer
*transfer
= NULL
;
698 struct spi_transfer
*previous
= NULL
;
699 struct chip_data
*chip
= NULL
;
700 void *reg
= drv_data
->ioaddr
;
706 /* Get current state information */
707 message
= drv_data
->cur_msg
;
708 transfer
= drv_data
->cur_transfer
;
709 chip
= drv_data
->cur_chip
;
711 /* Handle for abort */
712 if (message
->state
== ERROR_STATE
) {
713 message
->status
= -EIO
;
718 /* Handle end of message */
719 if (message
->state
== DONE_STATE
) {
725 /* Delay if requested at end of transfer*/
726 if (message
->state
== RUNNING_STATE
) {
727 previous
= list_entry(transfer
->transfer_list
.prev
,
730 if (previous
->delay_usecs
)
731 udelay(previous
->delay_usecs
);
734 /* Setup the transfer state based on the type of transfer */
735 if (flush(drv_data
) == 0) {
736 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
737 message
->status
= -EIO
;
741 drv_data
->n_bytes
= chip
->n_bytes
;
742 drv_data
->dma_width
= chip
->dma_width
;
743 drv_data
->cs_control
= chip
->cs_control
;
744 drv_data
->tx
= (void *)transfer
->tx_buf
;
745 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
746 drv_data
->rx
= transfer
->rx_buf
;
747 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
748 drv_data
->rx_dma
= transfer
->rx_dma
;
749 drv_data
->tx_dma
= transfer
->tx_dma
;
750 drv_data
->len
= transfer
->len
;
751 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
752 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
753 drv_data
->cs_change
= transfer
->cs_change
;
755 /* Change speed and bit per word on a per transfer */
756 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
759 write_SSCR0(chip
->cr0
& ~SSCR0_SSE
, reg
);
761 bits
= chip
->bits_per_word
;
762 speed
= chip
->speed_hz
;
764 if (transfer
->speed_hz
)
765 speed
= transfer
->speed_hz
;
767 if (transfer
->bits_per_word
)
768 bits
= transfer
->bits_per_word
;
770 if (reg
== SSP1_VIRT
)
771 clk_div
= SSP1_SerClkDiv(speed
);
772 else if (reg
== SSP2_VIRT
)
773 clk_div
= SSP2_SerClkDiv(speed
);
774 else if (reg
== SSP3_VIRT
)
775 clk_div
= SSP3_SerClkDiv(speed
);
778 drv_data
->n_bytes
= 1;
779 drv_data
->dma_width
= DCMD_WIDTH1
;
780 drv_data
->read
= drv_data
->read
!= null_reader
?
781 u8_reader
: null_reader
;
782 drv_data
->write
= drv_data
->write
!= null_writer
?
783 u8_writer
: null_writer
;
784 } else if (bits
<= 16) {
785 drv_data
->n_bytes
= 2;
786 drv_data
->dma_width
= DCMD_WIDTH2
;
787 drv_data
->read
= drv_data
->read
!= null_reader
?
788 u16_reader
: null_reader
;
789 drv_data
->write
= drv_data
->write
!= null_writer
?
790 u16_writer
: null_writer
;
791 } else if (bits
<= 32) {
792 drv_data
->n_bytes
= 4;
793 drv_data
->dma_width
= DCMD_WIDTH4
;
794 drv_data
->read
= drv_data
->read
!= null_reader
?
795 u32_reader
: null_reader
;
796 drv_data
->write
= drv_data
->write
!= null_writer
?
797 u32_writer
: null_writer
;
802 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
804 | (bits
> 16 ? SSCR0_EDSS
: 0);
806 /* Start it back up */
807 write_SSCR0(cr0
, reg
);
810 message
->state
= RUNNING_STATE
;
812 /* Try to map dma buffer and do a dma transfer if successful */
813 if ((drv_data
->dma_mapped
= map_dma_buffers(drv_data
))) {
815 /* Ensure we have the correct interrupt handler */
816 drv_data
->transfer_handler
= dma_transfer
;
818 /* Setup rx DMA Channel */
819 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
820 DSADR(drv_data
->rx_channel
) = drv_data
->ssdr_physical
;
821 DTADR(drv_data
->rx_channel
) = drv_data
->rx_dma
;
822 if (drv_data
->rx
== drv_data
->null_dma_buf
)
823 /* No target address increment */
824 DCMD(drv_data
->rx_channel
) = DCMD_FLOWSRC
825 | drv_data
->dma_width
826 | chip
->dma_burst_size
829 DCMD(drv_data
->rx_channel
) = DCMD_INCTRGADDR
831 | drv_data
->dma_width
832 | chip
->dma_burst_size
835 /* Setup tx DMA Channel */
836 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
837 DSADR(drv_data
->tx_channel
) = drv_data
->tx_dma
;
838 DTADR(drv_data
->tx_channel
) = drv_data
->ssdr_physical
;
839 if (drv_data
->tx
== drv_data
->null_dma_buf
)
840 /* No source address increment */
841 DCMD(drv_data
->tx_channel
) = DCMD_FLOWTRG
842 | drv_data
->dma_width
843 | chip
->dma_burst_size
846 DCMD(drv_data
->tx_channel
) = DCMD_INCSRCADDR
848 | drv_data
->dma_width
849 | chip
->dma_burst_size
852 /* Enable dma end irqs on SSP to detect end of transfer */
853 if (drv_data
->ssp_type
== PXA25x_SSP
)
854 DCMD(drv_data
->tx_channel
) |= DCMD_ENDIRQEN
;
856 /* Fix me, need to handle cs polarity */
857 drv_data
->cs_control(PXA2XX_CS_ASSERT
);
860 write_SSSR(drv_data
->clear_sr
, reg
);
861 DCSR(drv_data
->rx_channel
) |= DCSR_RUN
;
862 DCSR(drv_data
->tx_channel
) |= DCSR_RUN
;
863 if (drv_data
->ssp_type
!= PXA25x_SSP
)
864 write_SSTO(chip
->timeout
, reg
);
865 write_SSCR1(chip
->cr1
866 | chip
->dma_threshold
870 /* Ensure we have the correct interrupt handler */
871 drv_data
->transfer_handler
= interrupt_transfer
;
873 /* Fix me, need to handle cs polarity */
874 drv_data
->cs_control(PXA2XX_CS_ASSERT
);
877 write_SSSR(drv_data
->clear_sr
, reg
);
878 if (drv_data
->ssp_type
!= PXA25x_SSP
)
879 write_SSTO(chip
->timeout
, reg
);
880 write_SSCR1(chip
->cr1
887 static void pump_messages(struct work_struct
*work
)
889 struct driver_data
*drv_data
=
890 container_of(work
, struct driver_data
, pump_messages
);
893 /* Lock queue and check for queue work */
894 spin_lock_irqsave(&drv_data
->lock
, flags
);
895 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
897 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
901 /* Make sure we are not already running a message */
902 if (drv_data
->cur_msg
) {
903 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
907 /* Extract head of queue */
908 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
909 struct spi_message
, queue
);
910 list_del_init(&drv_data
->cur_msg
->queue
);
912 /* Initial message state*/
913 drv_data
->cur_msg
->state
= START_STATE
;
914 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
918 /* Setup the SSP using the per chip configuration */
919 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
920 restore_state(drv_data
);
922 /* Mark as busy and launch transfers */
923 tasklet_schedule(&drv_data
->pump_transfers
);
926 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
929 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
931 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
934 spin_lock_irqsave(&drv_data
->lock
, flags
);
936 if (drv_data
->run
== QUEUE_STOPPED
) {
937 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
941 msg
->actual_length
= 0;
942 msg
->status
= -EINPROGRESS
;
943 msg
->state
= START_STATE
;
945 list_add_tail(&msg
->queue
, &drv_data
->queue
);
947 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
948 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
950 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
955 static int setup(struct spi_device
*spi
)
957 struct pxa2xx_spi_chip
*chip_info
= NULL
;
958 struct chip_data
*chip
;
959 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
960 unsigned int clk_div
;
962 if (!spi
->bits_per_word
)
963 spi
->bits_per_word
= 8;
965 if (drv_data
->ssp_type
!= PXA25x_SSP
966 && (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32))
968 else if (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 16)
971 /* Only alloc (or use chip_info) on first setup */
972 chip
= spi_get_ctldata(spi
);
974 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
978 chip
->cs_control
= null_cs_control
;
979 chip
->enable_dma
= 0;
980 chip
->timeout
= SSP_TIMEOUT(1000);
981 chip
->threshold
= SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
982 chip
->dma_burst_size
= drv_data
->master_info
->enable_dma
?
985 chip_info
= spi
->controller_data
;
988 /* chip_info isn't always needed */
990 if (chip_info
->cs_control
)
991 chip
->cs_control
= chip_info
->cs_control
;
993 chip
->timeout
= SSP_TIMEOUT(chip_info
->timeout_microsecs
);
995 chip
->threshold
= SSCR1_RxTresh(chip_info
->rx_threshold
)
996 | SSCR1_TxTresh(chip_info
->tx_threshold
);
998 chip
->enable_dma
= chip_info
->dma_burst_size
!= 0
999 && drv_data
->master_info
->enable_dma
;
1000 chip
->dma_threshold
= 0;
1002 if (chip
->enable_dma
) {
1003 if (chip_info
->dma_burst_size
<= 8) {
1004 chip
->dma_threshold
= SSCR1_RxTresh(8)
1006 chip
->dma_burst_size
= DCMD_BURST8
;
1007 } else if (chip_info
->dma_burst_size
<= 16) {
1008 chip
->dma_threshold
= SSCR1_RxTresh(16)
1009 | SSCR1_TxTresh(16);
1010 chip
->dma_burst_size
= DCMD_BURST16
;
1012 chip
->dma_threshold
= SSCR1_RxTresh(32)
1013 | SSCR1_TxTresh(32);
1014 chip
->dma_burst_size
= DCMD_BURST32
;
1019 if (chip_info
->enable_loopback
)
1020 chip
->cr1
= SSCR1_LBM
;
1023 if (drv_data
->ioaddr
== SSP1_VIRT
)
1024 clk_div
= SSP1_SerClkDiv(spi
->max_speed_hz
);
1025 else if (drv_data
->ioaddr
== SSP2_VIRT
)
1026 clk_div
= SSP2_SerClkDiv(spi
->max_speed_hz
);
1027 else if (drv_data
->ioaddr
== SSP3_VIRT
)
1028 clk_div
= SSP3_SerClkDiv(spi
->max_speed_hz
);
1031 chip
->speed_hz
= spi
->max_speed_hz
;
1035 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
1036 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
1038 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
1039 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) << 4)
1040 | (((spi
->mode
& SPI_CPOL
) != 0) << 3);
1042 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1043 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1044 dev_dbg(&spi
->dev
, "%d bits/word, %d Hz, mode %d\n",
1047 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1050 dev_dbg(&spi
->dev
, "%d bits/word, %d Hz, mode %d\n",
1053 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1056 if (spi
->bits_per_word
<= 8) {
1058 chip
->dma_width
= DCMD_WIDTH1
;
1059 chip
->read
= u8_reader
;
1060 chip
->write
= u8_writer
;
1061 } else if (spi
->bits_per_word
<= 16) {
1063 chip
->dma_width
= DCMD_WIDTH2
;
1064 chip
->read
= u16_reader
;
1065 chip
->write
= u16_writer
;
1066 } else if (spi
->bits_per_word
<= 32) {
1067 chip
->cr0
|= SSCR0_EDSS
;
1069 chip
->dma_width
= DCMD_WIDTH4
;
1070 chip
->read
= u32_reader
;
1071 chip
->write
= u32_writer
;
1073 dev_err(&spi
->dev
, "invalid wordsize\n");
1077 chip
->bits_per_word
= spi
->bits_per_word
;
1079 spi_set_ctldata(spi
, chip
);
1084 static void cleanup(const struct spi_device
*spi
)
1086 struct chip_data
*chip
= spi_get_ctldata((struct spi_device
*)spi
);
1091 static int init_queue(struct driver_data
*drv_data
)
1093 INIT_LIST_HEAD(&drv_data
->queue
);
1094 spin_lock_init(&drv_data
->lock
);
1096 drv_data
->run
= QUEUE_STOPPED
;
1099 tasklet_init(&drv_data
->pump_transfers
,
1100 pump_transfers
, (unsigned long)drv_data
);
1102 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1103 drv_data
->workqueue
= create_singlethread_workqueue(
1104 drv_data
->master
->cdev
.dev
->bus_id
);
1105 if (drv_data
->workqueue
== NULL
)
1111 static int start_queue(struct driver_data
*drv_data
)
1113 unsigned long flags
;
1115 spin_lock_irqsave(&drv_data
->lock
, flags
);
1117 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1118 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1122 drv_data
->run
= QUEUE_RUNNING
;
1123 drv_data
->cur_msg
= NULL
;
1124 drv_data
->cur_transfer
= NULL
;
1125 drv_data
->cur_chip
= NULL
;
1126 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1128 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1133 static int stop_queue(struct driver_data
*drv_data
)
1135 unsigned long flags
;
1136 unsigned limit
= 500;
1139 spin_lock_irqsave(&drv_data
->lock
, flags
);
1141 /* This is a bit lame, but is optimized for the common execution path.
1142 * A wait_queue on the drv_data->busy could be used, but then the common
1143 * execution path (pump_messages) would be required to call wake_up or
1144 * friends on every SPI message. Do this instead */
1145 drv_data
->run
= QUEUE_STOPPED
;
1146 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1147 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1149 spin_lock_irqsave(&drv_data
->lock
, flags
);
1152 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1155 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1160 static int destroy_queue(struct driver_data
*drv_data
)
1164 status
= stop_queue(drv_data
);
1168 destroy_workqueue(drv_data
->workqueue
);
1173 static int pxa2xx_spi_probe(struct platform_device
*pdev
)
1175 struct device
*dev
= &pdev
->dev
;
1176 struct pxa2xx_spi_master
*platform_info
;
1177 struct spi_master
*master
;
1178 struct driver_data
*drv_data
= 0;
1179 struct resource
*memory_resource
;
1183 platform_info
= dev
->platform_data
;
1185 if (platform_info
->ssp_type
== SSP_UNDEFINED
) {
1186 dev_err(&pdev
->dev
, "undefined SSP\n");
1190 /* Allocate master with space for drv_data and null dma buffer */
1191 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1193 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1196 drv_data
= spi_master_get_devdata(master
);
1197 drv_data
->master
= master
;
1198 drv_data
->master_info
= platform_info
;
1199 drv_data
->pdev
= pdev
;
1201 master
->bus_num
= pdev
->id
;
1202 master
->num_chipselect
= platform_info
->num_chipselect
;
1203 master
->cleanup
= cleanup
;
1204 master
->setup
= setup
;
1205 master
->transfer
= transfer
;
1207 drv_data
->ssp_type
= platform_info
->ssp_type
;
1208 drv_data
->null_dma_buf
= (u32
*)ALIGN((u32
)(drv_data
+
1209 sizeof(struct driver_data
)), 8);
1211 /* Setup register addresses */
1212 memory_resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1213 if (!memory_resource
) {
1214 dev_err(&pdev
->dev
, "memory resources not defined\n");
1216 goto out_error_master_alloc
;
1219 drv_data
->ioaddr
= (void *)io_p2v((unsigned long)(memory_resource
->start
));
1220 drv_data
->ssdr_physical
= memory_resource
->start
+ 0x00000010;
1221 if (platform_info
->ssp_type
== PXA25x_SSP
) {
1222 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1223 drv_data
->dma_cr1
= 0;
1224 drv_data
->clear_sr
= SSSR_ROR
;
1225 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1227 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1228 drv_data
->dma_cr1
= SSCR1_TSRE
| SSCR1_RSRE
| SSCR1_TINTE
;
1229 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1230 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1234 irq
= platform_get_irq(pdev
, 0);
1236 dev_err(&pdev
->dev
, "irq resource not defined\n");
1238 goto out_error_master_alloc
;
1241 status
= request_irq(irq
, ssp_int
, 0, dev
->bus_id
, drv_data
);
1243 dev_err(&pdev
->dev
, "can not get IRQ\n");
1244 goto out_error_master_alloc
;
1247 /* Setup DMA if requested */
1248 drv_data
->tx_channel
= -1;
1249 drv_data
->rx_channel
= -1;
1250 if (platform_info
->enable_dma
) {
1252 /* Get two DMA channels (rx and tx) */
1253 drv_data
->rx_channel
= pxa_request_dma("pxa2xx_spi_ssp_rx",
1257 if (drv_data
->rx_channel
< 0) {
1258 dev_err(dev
, "problem (%d) requesting rx channel\n",
1259 drv_data
->rx_channel
);
1261 goto out_error_irq_alloc
;
1263 drv_data
->tx_channel
= pxa_request_dma("pxa2xx_spi_ssp_tx",
1267 if (drv_data
->tx_channel
< 0) {
1268 dev_err(dev
, "problem (%d) requesting tx channel\n",
1269 drv_data
->tx_channel
);
1271 goto out_error_dma_alloc
;
1274 if (drv_data
->ioaddr
== SSP1_VIRT
) {
1275 DRCMRRXSSDR
= DRCMR_MAPVLD
1276 | drv_data
->rx_channel
;
1277 DRCMRTXSSDR
= DRCMR_MAPVLD
1278 | drv_data
->tx_channel
;
1279 } else if (drv_data
->ioaddr
== SSP2_VIRT
) {
1280 DRCMRRXSS2DR
= DRCMR_MAPVLD
1281 | drv_data
->rx_channel
;
1282 DRCMRTXSS2DR
= DRCMR_MAPVLD
1283 | drv_data
->tx_channel
;
1284 } else if (drv_data
->ioaddr
== SSP3_VIRT
) {
1285 DRCMRRXSS3DR
= DRCMR_MAPVLD
1286 | drv_data
->rx_channel
;
1287 DRCMRTXSS3DR
= DRCMR_MAPVLD
1288 | drv_data
->tx_channel
;
1290 dev_err(dev
, "bad SSP type\n");
1291 goto out_error_dma_alloc
;
1295 /* Enable SOC clock */
1296 pxa_set_cken(platform_info
->clock_enable
, 1);
1298 /* Load default SSP configuration */
1299 write_SSCR0(0, drv_data
->ioaddr
);
1300 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data
->ioaddr
);
1301 write_SSCR0(SSCR0_SerClkDiv(2)
1303 | SSCR0_DataSize(8),
1305 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1306 write_SSTO(0, drv_data
->ioaddr
);
1307 write_SSPSP(0, drv_data
->ioaddr
);
1309 /* Initial and start queue */
1310 status
= init_queue(drv_data
);
1312 dev_err(&pdev
->dev
, "problem initializing queue\n");
1313 goto out_error_clock_enabled
;
1315 status
= start_queue(drv_data
);
1317 dev_err(&pdev
->dev
, "problem starting queue\n");
1318 goto out_error_clock_enabled
;
1321 /* Register with the SPI framework */
1322 platform_set_drvdata(pdev
, drv_data
);
1323 status
= spi_register_master(master
);
1325 dev_err(&pdev
->dev
, "problem registering spi master\n");
1326 goto out_error_queue_alloc
;
1331 out_error_queue_alloc
:
1332 destroy_queue(drv_data
);
1334 out_error_clock_enabled
:
1335 pxa_set_cken(platform_info
->clock_enable
, 0);
1337 out_error_dma_alloc
:
1338 if (drv_data
->tx_channel
!= -1)
1339 pxa_free_dma(drv_data
->tx_channel
);
1340 if (drv_data
->rx_channel
!= -1)
1341 pxa_free_dma(drv_data
->rx_channel
);
1343 out_error_irq_alloc
:
1344 free_irq(irq
, drv_data
);
1346 out_error_master_alloc
:
1347 spi_master_put(master
);
1351 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1353 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1360 /* Remove the queue */
1361 status
= destroy_queue(drv_data
);
1365 /* Disable the SSP at the peripheral and SOC level */
1366 write_SSCR0(0, drv_data
->ioaddr
);
1367 pxa_set_cken(drv_data
->master_info
->clock_enable
, 0);
1370 if (drv_data
->master_info
->enable_dma
) {
1371 if (drv_data
->ioaddr
== SSP1_VIRT
) {
1374 } else if (drv_data
->ioaddr
== SSP2_VIRT
) {
1377 } else if (drv_data
->ioaddr
== SSP3_VIRT
) {
1381 pxa_free_dma(drv_data
->tx_channel
);
1382 pxa_free_dma(drv_data
->rx_channel
);
1386 irq
= platform_get_irq(pdev
, 0);
1388 free_irq(irq
, drv_data
);
1390 /* Disconnect from the SPI framework */
1391 spi_unregister_master(drv_data
->master
);
1393 /* Prevent double remove */
1394 platform_set_drvdata(pdev
, NULL
);
1399 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1403 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1404 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1408 static int suspend_devices(struct device
*dev
, void *pm_message
)
1410 pm_message_t
*state
= pm_message
;
1412 if (dev
->power
.power_state
.event
!= state
->event
) {
1413 dev_warn(dev
, "pm state does not match request\n");
1420 static int pxa2xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1422 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1425 /* Check all childern for current power state */
1426 if (device_for_each_child(&pdev
->dev
, &state
, suspend_devices
) != 0) {
1427 dev_warn(&pdev
->dev
, "suspend aborted\n");
1431 status
= stop_queue(drv_data
);
1434 write_SSCR0(0, drv_data
->ioaddr
);
1435 pxa_set_cken(drv_data
->master_info
->clock_enable
, 0);
1440 static int pxa2xx_spi_resume(struct platform_device
*pdev
)
1442 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1445 /* Enable the SSP clock */
1446 pxa_set_cken(drv_data
->master_info
->clock_enable
, 1);
1448 /* Start the queue running */
1449 status
= start_queue(drv_data
);
1451 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1458 #define pxa2xx_spi_suspend NULL
1459 #define pxa2xx_spi_resume NULL
1460 #endif /* CONFIG_PM */
1462 static struct platform_driver driver
= {
1464 .name
= "pxa2xx-spi",
1465 .bus
= &platform_bus_type
,
1466 .owner
= THIS_MODULE
,
1468 .probe
= pxa2xx_spi_probe
,
1469 .remove
= __devexit_p(pxa2xx_spi_remove
),
1470 .shutdown
= pxa2xx_spi_shutdown
,
1471 .suspend
= pxa2xx_spi_suspend
,
1472 .resume
= pxa2xx_spi_resume
,
1475 static int __init
pxa2xx_spi_init(void)
1477 platform_driver_register(&driver
);
1481 module_init(pxa2xx_spi_init
);
1483 static void __exit
pxa2xx_spi_exit(void)
1485 platform_driver_unregister(&driver
);
1487 module_exit(pxa2xx_spi_exit
);