?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / pci / es1968.c
blobdc84c189b05f25922e253c4418b71754fba4838d
1 /*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97 #include <sound/driver.h>
98 #include <asm/io.h>
99 #include <linux/delay.h>
100 #include <linux/interrupt.h>
101 #include <linux/init.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/slab.h>
105 #include <linux/gameport.h>
106 #include <linux/moduleparam.h>
107 #include <linux/mutex.h>
108
109 #include <sound/core.h>
110 #include <sound/pcm.h>
111 #include <sound/mpu401.h>
112 #include <sound/ac97_codec.h>
113 #include <sound/initval.h>
114
115 #define CARD_NAME "ESS Maestro1/2"
116 #define DRIVER_NAME "ES1968"
117
118 MODULE_DESCRIPTION("ESS Maestro");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
121 "{ESS,Maestro 2},"
122 "{ESS,Maestro 1},"
123 "{TerraTec,DMX}}");
124
125 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
126 #define SUPPORT_JOYSTICK 1
127 #endif
128
129 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
130 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
131 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
132 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
133 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
134 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
135 static int clock[SNDRV_CARDS];
136 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
138 #ifdef SUPPORT_JOYSTICK
139 static int joystick[SNDRV_CARDS];
140 #endif
141
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
148 module_param_array(total_bufsize, int, NULL, 0444);
149 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
150 module_param_array(pcm_substreams_p, int, NULL, 0444);
151 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
152 module_param_array(pcm_substreams_c, int, NULL, 0444);
153 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
154 module_param_array(clock, int, NULL, 0444);
155 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
156 module_param_array(use_pm, int, NULL, 0444);
157 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
158 module_param_array(enable_mpu, int, NULL, 0444);
159 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
160 #ifdef SUPPORT_JOYSTICK
161 module_param_array(joystick, bool, NULL, 0444);
162 MODULE_PARM_DESC(joystick, "Enable joystick.");
163 #endif
164
165
166 #define NR_APUS 64
167 #define NR_APU_REGS 16
168
169 /* NEC Versas ? */
170 #define NEC_VERSA_SUBID1 0x80581033
171 #define NEC_VERSA_SUBID2 0x803c1033
172
173 /* Mode Flags */
174 #define ESS_FMT_STEREO 0x01
175 #define ESS_FMT_16BIT 0x02
176
177 #define DAC_RUNNING 1
178 #define ADC_RUNNING 2
179
180 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
181
182 #define ESS_DISABLE_AUDIO 0x8000
183 #define ESS_ENABLE_SERIAL_IRQ 0x4000
184 #define IO_ADRESS_ALIAS 0x0020
185 #define MPU401_IRQ_ENABLE 0x0010
186 #define MPU401_IO_ENABLE 0x0008
187 #define GAME_IO_ENABLE 0x0004
188 #define FM_IO_ENABLE 0x0002
189 #define SB_IO_ENABLE 0x0001
190
191 /* Values for the ESM_CONFIG_A */
192
193 #define PIC_SNOOP1 0x4000
194 #define PIC_SNOOP2 0x2000
195 #define SAFEGUARD 0x0800
196 #define DMA_CLEAR 0x0700
197 #define DMA_DDMA 0x0000
198 #define DMA_TDMA 0x0100
199 #define DMA_PCPCI 0x0200
200 #define POST_WRITE 0x0080
201 #define PCI_TIMING 0x0040
202 #define SWAP_LR 0x0020
203 #define SUBTR_DECODE 0x0002
204
205 /* Values for the ESM_CONFIG_B */
206
207 #define SPDIF_CONFB 0x0100
208 #define HWV_CONFB 0x0080
209 #define DEBOUNCE 0x0040
210 #define GPIO_CONFB 0x0020
211 #define CHI_CONFB 0x0010
212 #define IDMA_CONFB 0x0008 /*undoc */
213 #define MIDI_FIX 0x0004 /*undoc */
214 #define IRQ_TO_ISA 0x0001 /*undoc */
215
216 /* Values for Ring Bus Control B */
217 #define RINGB_2CODEC_ID_MASK 0x0003
218 #define RINGB_DIS_VALIDATION 0x0008
219 #define RINGB_EN_SPDIF 0x0010
220 #define RINGB_EN_2CODEC 0x0020
221 #define RINGB_SING_BIT_DUAL 0x0040
222
223 /* ****Port Adresses**** */
224
225 /* Write & Read */
226 #define ESM_INDEX 0x02
227 #define ESM_DATA 0x00
228
229 /* AC97 + RingBus */
230 #define ESM_AC97_INDEX 0x30
231 #define ESM_AC97_DATA 0x32
232 #define ESM_RING_BUS_DEST 0x34
233 #define ESM_RING_BUS_CONTR_A 0x36
234 #define ESM_RING_BUS_CONTR_B 0x38
235 #define ESM_RING_BUS_SDO 0x3A
236
237 /* WaveCache*/
238 #define WC_INDEX 0x10
239 #define WC_DATA 0x12
240 #define WC_CONTROL 0x14
241
242 /* ASSP*/
243 #define ASSP_INDEX 0x80
244 #define ASSP_MEMORY 0x82
245 #define ASSP_DATA 0x84
246 #define ASSP_CONTROL_A 0xA2
247 #define ASSP_CONTROL_B 0xA4
248 #define ASSP_CONTROL_C 0xA6
249 #define ASSP_HOSTW_INDEX 0xA8
250 #define ASSP_HOSTW_DATA 0xAA
251 #define ASSP_HOSTW_IRQ 0xAC
252 /* Midi */
253 #define ESM_MPU401_PORT 0x98
254 /* Others */
255 #define ESM_PORT_HOST_IRQ 0x18
256
257 #define IDR0_DATA_PORT 0x00
258 #define IDR1_CRAM_POINTER 0x01
259 #define IDR2_CRAM_DATA 0x02
260 #define IDR3_WAVE_DATA 0x03
261 #define IDR4_WAVE_PTR_LOW 0x04
262 #define IDR5_WAVE_PTR_HI 0x05
263 #define IDR6_TIMER_CTRL 0x06
264 #define IDR7_WAVE_ROMRAM 0x07
265
266 #define WRITEABLE_MAP 0xEFFFFF
267 #define READABLE_MAP 0x64003F
268
269 /* PCI Register */
270
271 #define ESM_LEGACY_AUDIO_CONTROL 0x40
272 #define ESM_ACPI_COMMAND 0x54
273 #define ESM_CONFIG_A 0x50
274 #define ESM_CONFIG_B 0x52
275 #define ESM_DDMA 0x60
276
277 /* Bob Bits */
278 #define ESM_BOB_ENABLE 0x0001
279 #define ESM_BOB_START 0x0001
280
281 /* Host IRQ Control Bits */
282 #define ESM_RESET_MAESTRO 0x8000
283 #define ESM_RESET_DIRECTSOUND 0x4000
284 #define ESM_HIRQ_ClkRun 0x0100
285 #define ESM_HIRQ_HW_VOLUME 0x0040
286 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
287 #define ESM_HIRQ_ASSP 0x0010
288 #define ESM_HIRQ_DSIE 0x0004
289 #define ESM_HIRQ_MPU401 0x0002
290 #define ESM_HIRQ_SB 0x0001
291
292 /* Host IRQ Status Bits */
293 #define ESM_MPU401_IRQ 0x02
294 #define ESM_SB_IRQ 0x01
295 #define ESM_SOUND_IRQ 0x04
296 #define ESM_ASSP_IRQ 0x10
297 #define ESM_HWVOL_IRQ 0x40
298
299 #define ESS_SYSCLK 50000000
300 #define ESM_BOB_FREQ 200
301 #define ESM_BOB_FREQ_MAX 800
302
303 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
304 #define ESM_FREQ_ESM2 (50000000L / 1024L)
305
306 /* APU Modes: reg 0x00, bit 4-7 */
307 #define ESM_APU_MODE_SHIFT 4
308 #define ESM_APU_MODE_MASK (0xf << 4)
309 #define ESM_APU_OFF 0x00
310 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
311 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
312 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
313 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
314 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
315 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
316 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
317 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
318 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
319 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
320 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
321 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
322 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
323 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
324 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
325
326 /* reg 0x00 */
327 #define ESM_APU_FILTER_Q_SHIFT 0
328 #define ESM_APU_FILTER_Q_MASK (3 << 0)
329 /* APU Filtey Q Control */
330 #define ESM_APU_FILTER_LESSQ 0x00
331 #define ESM_APU_FILTER_MOREQ 0x03
332
333 #define ESM_APU_FILTER_TYPE_SHIFT 2
334 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
335 #define ESM_APU_ENV_TYPE_SHIFT 8
336 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
337 #define ESM_APU_ENV_STATE_SHIFT 10
338 #define ESM_APU_ENV_STATE_MASK (3 << 10)
339 #define ESM_APU_END_CURVE (1 << 12)
340 #define ESM_APU_INT_ON_LOOP (1 << 13)
341 #define ESM_APU_DMA_ENABLE (1 << 14)
342
343 /* reg 0x02 */
344 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
345 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
346 #define ESM_APU_SUBMIX_MODE (1 << 3)
347 #define ESM_APU_6dB (1 << 4)
348 #define ESM_APU_DUAL_EFFECT (1 << 5)
349 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
350 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
351
352 /* reg 0x03 */
353 #define ESM_APU_STEP_SIZE_MASK 0x0fff
354
355 /* reg 0x04 */
356 #define ESM_APU_PHASE_SHIFT 0
357 #define ESM_APU_PHASE_MASK (0xff << 0)
358 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
359 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
360
361 /* reg 0x05 - wave start offset */
362 /* reg 0x06 - wave end offset */
363 /* reg 0x07 - wave loop length */
364
365 /* reg 0x08 */
366 #define ESM_APU_EFFECT_GAIN_SHIFT 0
367 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
368 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
369 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
370 #define ESM_APU_TREMOLO_RATE_SHIFT 12
371 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
372
373 /* reg 0x09 */
374 /* bit 0-7 amplitude dest? */
375 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
376 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
377
378 /* reg 0x0a */
379 #define ESM_APU_POLAR_PAN_SHIFT 0
380 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
381 /* Polar Pan Control */
382 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
383 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
384 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
385
386 #define ESM_APU_FILTER_TUNING_SHIFT 8
387 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
388
389 /* reg 0x0b */
390 #define ESM_APU_DATA_SRC_A_SHIFT 0
391 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
392 #define ESM_APU_INV_POL_A (1 << 7)
393 #define ESM_APU_DATA_SRC_B_SHIFT 8
394 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
395 #define ESM_APU_INV_POL_B (1 << 15)
396
397 #define ESM_APU_VIBRATO_RATE_SHIFT 0
398 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
399 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
400 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
401 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
402 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
403
404 /* reg 0x0c */
405 #define ESM_APU_RADIUS_SELECT (1 << 6)
406
407 /* APU Filter Control */
408 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
409 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
410 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
411 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
412 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
413 #define ESM_APU_FILTER_OFF 0x05
414
415 /* APU ATFP Type */
416 #define ESM_APU_ATFP_AMPLITUDE 0x00
417 #define ESM_APU_ATFP_TREMELO 0x01
418 #define ESM_APU_ATFP_FILTER 0x02
419 #define ESM_APU_ATFP_PAN 0x03
420
421 /* APU ATFP Flags */
422 #define ESM_APU_ATFP_FLG_OFF 0x00
423 #define ESM_APU_ATFP_FLG_WAIT 0x01
424 #define ESM_APU_ATFP_FLG_DONE 0x02
425 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
426
427
428 /* capture mixing buffer size */
429 #define ESM_MEM_ALIGN 0x1000
430 #define ESM_MIXBUF_SIZE 0x400
431
432 #define ESM_MODE_PLAY 0
433 #define ESM_MODE_CAPTURE 1
434
435
436 /* APU use in the driver */
437 enum snd_enum_apu_type {
438 ESM_APU_PCM_PLAY,
439 ESM_APU_PCM_CAPTURE,
440 ESM_APU_PCM_RATECONV,
441 ESM_APU_FREE
442 };
443
444 /* chip type */
445 enum {
446 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
447 };
448
449 /* DMA Hack! */
450 struct esm_memory {
451 struct snd_dma_buffer buf;
452 int empty; /* status */
453 struct list_head list;
454 };
455
456 /* Playback Channel */
457 struct esschan {
458 int running;
459
460 u8 apu[4];
461 u8 apu_mode[4];
462
463 /* playback/capture pcm buffer */
464 struct esm_memory *memory;
465 /* capture mixer buffer */
466 struct esm_memory *mixbuf;
467
468 unsigned int hwptr; /* current hw pointer in bytes */
469 unsigned int count; /* sample counter in bytes */
470 unsigned int dma_size; /* total buffer size in bytes */
471 unsigned int frag_size; /* period size in bytes */
472 unsigned int wav_shift;
473 u16 base[4]; /* offset for ptr */
474
475 /* stereo/16bit flag */
476 unsigned char fmt;
477 int mode; /* playback / capture */
478
479 int bob_freq; /* required timer frequency */
480
481 struct snd_pcm_substream *substream;
482
483 /* linked list */
484 struct list_head list;
485
486 #ifdef CONFIG_PM
487 u16 wc_map[4];
488 #endif
489 };
490
491 struct es1968 {
492 /* Module Config */
493 int total_bufsize; /* in bytes */
494
495 int playback_streams, capture_streams;
496
497 unsigned int clock; /* clock */
498 /* for clock measurement */
499 unsigned int in_measurement: 1;
500 unsigned int measure_apu;
501 unsigned int measure_lastpos;
502 unsigned int measure_count;
503
504 /* buffer */
505 struct snd_dma_buffer dma;
506
507 /* Resources... */
508 int irq;
509 unsigned long io_port;
510 int type;
511 struct pci_dev *pci;
512 struct snd_card *card;
513 struct snd_pcm *pcm;
514 int do_pm; /* power-management enabled */
515
516 /* DMA memory block */
517 struct list_head buf_list;
518
519 /* ALSA Stuff */
520 struct snd_ac97 *ac97;
521 struct snd_kcontrol *master_switch; /* for h/w volume control */
522 struct snd_kcontrol *master_volume;
523
524 struct snd_rawmidi *rmidi;
525
526 spinlock_t reg_lock;
527 spinlock_t ac97_lock;
528 struct tasklet_struct hwvol_tq;
529 unsigned int in_suspend;
530
531 /* Maestro Stuff */
532 u16 maestro_map[32];
533 int bobclient; /* active timer instancs */
534 int bob_freq; /* timer frequency */
535 struct mutex memory_mutex; /* memory lock */
536
537 /* APU states */
538 unsigned char apu[NR_APUS];
539
540 /* active substreams */
541 struct list_head substream_list;
542 spinlock_t substream_lock;
543
544 #ifdef CONFIG_PM
545 u16 apu_map[NR_APUS][NR_APU_REGS];
546 #endif
547
548 #ifdef SUPPORT_JOYSTICK
549 struct gameport *gameport;
550 #endif
551 };
552
553 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
554
555 static struct pci_device_id snd_es1968_ids[] = {
556 /* Maestro 1 */
557 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
558 /* Maestro 2 */
559 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
560 /* Maestro 2E */
561 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
562 { 0, }
563 };
564
565 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
566
567 /* *********************
568 * Low Level Funcs! *
569 *********************/
570
571 /* no spinlock */
572 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
573 {
574 outw(reg, chip->io_port + ESM_INDEX);
575 outw(data, chip->io_port + ESM_DATA);
576 chip->maestro_map[reg] = data;
577 }
578
579 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
580 {
581 unsigned long flags;
582 spin_lock_irqsave(&chip->reg_lock, flags);
583 __maestro_write(chip, reg, data);
584 spin_unlock_irqrestore(&chip->reg_lock, flags);
585 }
586
587 /* no spinlock */
588 static u16 __maestro_read(struct es1968 *chip, u16 reg)
589 {
590 if (READABLE_MAP & (1 << reg)) {
591 outw(reg, chip->io_port + ESM_INDEX);
592 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
593 }
594 return chip->maestro_map[reg];
595 }
596
597 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
598 {
599 unsigned long flags;
600 u16 result;
601 spin_lock_irqsave(&chip->reg_lock, flags);
602 result = __maestro_read(chip, reg);
603 spin_unlock_irqrestore(&chip->reg_lock, flags);
604 return result;
605 }
606
607 /* Wait for the codec bus to be free */
608 static int snd_es1968_ac97_wait(struct es1968 *chip)
609 {
610 int timeout = 100000;
611
612 while (timeout-- > 0) {
613 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
614 return 0;
615 cond_resched();
616 }
617 snd_printd("es1968: ac97 timeout\n");
618 return 1; /* timeout */
619 }
620
621 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
622 {
623 struct es1968 *chip = ac97->private_data;
624 unsigned long flags;
625
626 snd_es1968_ac97_wait(chip);
627
628 /* Write the bus */
629 spin_lock_irqsave(&chip->ac97_lock, flags);
630 outw(val, chip->io_port + ESM_AC97_DATA);
631 /*msleep(1);*/
632 outb(reg, chip->io_port + ESM_AC97_INDEX);
633 /*msleep(1);*/
634 spin_unlock_irqrestore(&chip->ac97_lock, flags);
635 }
636
637 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
638 {
639 u16 data = 0;
640 struct es1968 *chip = ac97->private_data;
641 unsigned long flags;
642
643 snd_es1968_ac97_wait(chip);
644
645 spin_lock_irqsave(&chip->ac97_lock, flags);
646 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
647 /*msleep(1);*/
648
649 if (! snd_es1968_ac97_wait(chip)) {
650 data = inw(chip->io_port + ESM_AC97_DATA);
651 /*msleep(1);*/
652 }
653 spin_unlock_irqrestore(&chip->ac97_lock, flags);
654
655 return data;
656 }
657
658 /* no spinlock */
659 static void apu_index_set(struct es1968 *chip, u16 index)
660 {
661 int i;
662 __maestro_write(chip, IDR1_CRAM_POINTER, index);
663 for (i = 0; i < 1000; i++)
664 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
665 return;
666 snd_printd("es1968: APU register select failed. (Timeout)\n");
667 }
668
669 /* no spinlock */
670 static void apu_data_set(struct es1968 *chip, u16 data)
671 {
672 int i;
673 for (i = 0; i < 1000; i++) {
674 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
675 return;
676 __maestro_write(chip, IDR0_DATA_PORT, data);
677 }
678 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
679 }
680
681 /* no spinlock */
682 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
683 {
684 snd_assert(channel < NR_APUS, return);
685 #ifdef CONFIG_PM
686 chip->apu_map[channel][reg] = data;
687 #endif
688 reg |= (channel << 4);
689 apu_index_set(chip, reg);
690 apu_data_set(chip, data);
691 }
692
693 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
694 {
695 unsigned long flags;
696 spin_lock_irqsave(&chip->reg_lock, flags);
697 __apu_set_register(chip, channel, reg, data);
698 spin_unlock_irqrestore(&chip->reg_lock, flags);
699 }
700
701 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
702 {
703 snd_assert(channel < NR_APUS, return 0);
704 reg |= (channel << 4);
705 apu_index_set(chip, reg);
706 return __maestro_read(chip, IDR0_DATA_PORT);
707 }
708
709 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
710 {
711 unsigned long flags;
712 u16 v;
713 spin_lock_irqsave(&chip->reg_lock, flags);
714 v = __apu_get_register(chip, channel, reg);
715 spin_unlock_irqrestore(&chip->reg_lock, flags);
716 return v;
717 }
718
719 #if 0 /* ASSP is not supported */
720
721 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
722 {
723 unsigned long flags;
724
725 spin_lock_irqsave(&chip->reg_lock, flags);
726 outl(reg, chip->io_port + ASSP_INDEX);
727 outl(value, chip->io_port + ASSP_DATA);
728 spin_unlock_irqrestore(&chip->reg_lock, flags);
729 }
730
731 static u32 assp_get_register(struct es1968 *chip, u32 reg)
732 {
733 unsigned long flags;
734 u32 value;
735
736 spin_lock_irqsave(&chip->reg_lock, flags);
737 outl(reg, chip->io_port + ASSP_INDEX);
738 value = inl(chip->io_port + ASSP_DATA);
739 spin_unlock_irqrestore(&chip->reg_lock, flags);
740
741 return value;
742 }
743
744 #endif
745
746 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
747 {
748 unsigned long flags;
749
750 spin_lock_irqsave(&chip->reg_lock, flags);
751 outw(reg, chip->io_port + WC_INDEX);
752 outw(value, chip->io_port + WC_DATA);
753 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 }
755
756 static u16 wave_get_register(struct es1968 *chip, u16 reg)
757 {
758 unsigned long flags;
759 u16 value;
760
761 spin_lock_irqsave(&chip->reg_lock, flags);
762 outw(reg, chip->io_port + WC_INDEX);
763 value = inw(chip->io_port + WC_DATA);
764 spin_unlock_irqrestore(&chip->reg_lock, flags);
765
766 return value;
767 }
768
769 /* *******************
770 * Bob the Timer! *
771 *******************/
772
773 static void snd_es1968_bob_stop(struct es1968 *chip)
774 {
775 u16 reg;
776
777 reg = __maestro_read(chip, 0x11);
778 reg &= ~ESM_BOB_ENABLE;
779 __maestro_write(chip, 0x11, reg);
780 reg = __maestro_read(chip, 0x17);
781 reg &= ~ESM_BOB_START;
782 __maestro_write(chip, 0x17, reg);
783 }
784
785 static void snd_es1968_bob_start(struct es1968 *chip)
786 {
787 int prescale;
788 int divide;
789
790 /* compute ideal interrupt frequency for buffer size & play rate */
791 /* first, find best prescaler value to match freq */
792 for (prescale = 5; prescale < 12; prescale++)
793 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
794 break;
795
796 /* next, back off prescaler whilst getting divider into optimum range */
797 divide = 1;
798 while ((prescale > 5) && (divide < 32)) {
799 prescale--;
800 divide <<= 1;
801 }
802 divide >>= 1;
803
804 /* now fine-tune the divider for best match */
805 for (; divide < 31; divide++)
806 if (chip->bob_freq >
807 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
808
809 /* divide = 0 is illegal, but don't let prescale = 4! */
810 if (divide == 0) {
811 divide++;
812 if (prescale > 5)
813 prescale--;
814 } else if (divide > 1)
815 divide--;
816
817 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
818
819 /* Now set IDR 11/17 */
820 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
821 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
822 }
823
824 /* call with substream spinlock */
825 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
826 {
827 chip->bobclient++;
828 if (chip->bobclient == 1) {
829 chip->bob_freq = freq;
830 snd_es1968_bob_start(chip);
831 } else if (chip->bob_freq < freq) {
832 snd_es1968_bob_stop(chip);
833 chip->bob_freq = freq;
834 snd_es1968_bob_start(chip);
835 }
836 }
837
838 /* call with substream spinlock */
839 static void snd_es1968_bob_dec(struct es1968 *chip)
840 {
841 chip->bobclient--;
842 if (chip->bobclient <= 0)
843 snd_es1968_bob_stop(chip);
844 else if (chip->bob_freq > ESM_BOB_FREQ) {
845 /* check reduction of timer frequency */
846 struct list_head *p;
847 int max_freq = ESM_BOB_FREQ;
848 list_for_each(p, &chip->substream_list) {
849 struct esschan *es = list_entry(p, struct esschan, list);
850 if (max_freq < es->bob_freq)
851 max_freq = es->bob_freq;
852 }
853 if (max_freq != chip->bob_freq) {
854 snd_es1968_bob_stop(chip);
855 chip->bob_freq = max_freq;
856 snd_es1968_bob_start(chip);
857 }
858 }
859 }
860
861 static int
862 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
863 struct snd_pcm_runtime *runtime)
864 {
865 /* we acquire 4 interrupts per period for precise control.. */
866 int freq = runtime->rate * 4;
867 if (es->fmt & ESS_FMT_STEREO)
868 freq <<= 1;
869 if (es->fmt & ESS_FMT_16BIT)
870 freq <<= 1;
871 freq /= es->frag_size;
872 if (freq < ESM_BOB_FREQ)
873 freq = ESM_BOB_FREQ;
874 else if (freq > ESM_BOB_FREQ_MAX)
875 freq = ESM_BOB_FREQ_MAX;
876 return freq;
877 }
878
879
880 /*************
881 * PCM Part *
882 *************/
883
884 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
885 {
886 u32 rate = (freq << 16) / chip->clock;
887 #if 0 /* XXX: do we need this? */
888 if (rate > 0x10000)
889 rate = 0x10000;
890 #endif
891 return rate;
892 }
893
894 /* get current pointer */
895 static inline unsigned int
896 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
897 {
898 unsigned int offset;
899
900 offset = apu_get_register(chip, es->apu[0], 5);
901
902 offset -= es->base[0];
903
904 return (offset & 0xFFFE); /* hardware is in words */
905 }
906
907 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
908 {
909 apu_set_register(chip, apu, 2,
910 (apu_get_register(chip, apu, 2) & 0x00FF) |
911 ((freq & 0xff) << 8) | 0x10);
912 apu_set_register(chip, apu, 3, freq >> 8);
913 }
914
915 /* spin lock held */
916 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
917 {
918 /* set the APU mode */
919 __apu_set_register(esm, apu, 0,
920 (__apu_get_register(esm, apu, 0) & 0xff0f) |
921 (mode << 4));
922 }
923
924 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
925 {
926 spin_lock(&chip->reg_lock);
927 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
928 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
929 if (es->mode == ESM_MODE_CAPTURE) {
930 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
931 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
932 }
933 if (es->fmt & ESS_FMT_STEREO) {
934 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
935 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
936 if (es->mode == ESM_MODE_CAPTURE) {
937 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
938 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
939 }
940 }
941 spin_unlock(&chip->reg_lock);
942 }
943
944 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
945 {
946 spin_lock(&chip->reg_lock);
947 snd_es1968_trigger_apu(chip, es->apu[0], 0);
948 snd_es1968_trigger_apu(chip, es->apu[1], 0);
949 if (es->mode == ESM_MODE_CAPTURE) {
950 snd_es1968_trigger_apu(chip, es->apu[2], 0);
951 snd_es1968_trigger_apu(chip, es->apu[3], 0);
952 }
953 spin_unlock(&chip->reg_lock);
954 }
955
956 /* set the wavecache control reg */
957 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
958 int channel, u32 addr, int capture)
959 {
960 u32 tmpval = (addr - 0x10) & 0xFFF8;
961
962 if (! capture) {
963 if (!(es->fmt & ESS_FMT_16BIT))
964 tmpval |= 4; /* 8bit */
965 if (es->fmt & ESS_FMT_STEREO)
966 tmpval |= 2; /* stereo */
967 }
968
969 /* set the wavecache control reg */
970 wave_set_register(chip, es->apu[channel] << 3, tmpval);
971
972 #ifdef CONFIG_PM
973 es->wc_map[channel] = tmpval;
974 #endif
975 }
976
977
978 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
979 struct snd_pcm_runtime *runtime)
980 {
981 u32 pa;
982 int high_apu = 0;
983 int channel, apu;
984 int i, size;
985 unsigned long flags;
986 u32 freq;
987
988 size = es->dma_size >> es->wav_shift;
989
990 if (es->fmt & ESS_FMT_STEREO)
991 high_apu++;
992
993 for (channel = 0; channel <= high_apu; channel++) {
994 apu = es->apu[channel];
995
996 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
997
998 /* Offset to PCMBAR */
999 pa = es->memory->buf.addr;
1000 pa -= chip->dma.addr;
1001 pa >>= 1; /* words */
1002
1003 pa |= 0x00400000; /* System RAM (Bit 22) */
1004
1005 if (es->fmt & ESS_FMT_STEREO) {
1006 /* Enable stereo */
1007 if (channel)
1008 pa |= 0x00800000; /* (Bit 23) */
1009 if (es->fmt & ESS_FMT_16BIT)
1010 pa >>= 1;
1011 }
1012
1013 /* base offset of dma calcs when reading the pointer
1014 on this left one */
1015 es->base[channel] = pa & 0xFFFF;
1016
1017 for (i = 0; i < 16; i++)
1018 apu_set_register(chip, apu, i, 0x0000);
1019
1020 /* Load the buffer into the wave engine */
1021 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1022 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1023 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1024 /* setting loop == sample len */
1025 apu_set_register(chip, apu, 7, size);
1026
1027 /* clear effects/env.. */
1028 apu_set_register(chip, apu, 8, 0x0000);
1029 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1030 apu_set_register(chip, apu, 9, 0xD000);
1031
1032 /* clear routing stuff */
1033 apu_set_register(chip, apu, 11, 0x0000);
1034 /* dma on, no envelopes, filter to all 1s) */
1035 apu_set_register(chip, apu, 0, 0x400F);
1036
1037 if (es->fmt & ESS_FMT_16BIT)
1038 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1039 else
1040 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1041
1042 if (es->fmt & ESS_FMT_STEREO) {
1043 /* set panning: left or right */
1044 /* Check: different panning. On my Canyon 3D Chipset the
1045 Channels are swapped. I don't know, about the output
1046 to the SPDif Link. Perhaps you have to change this
1047 and not the APU Regs 4-5. */
1048 apu_set_register(chip, apu, 10,
1049 0x8F00 | (channel ? 0 : 0x10));
1050 es->apu_mode[channel] += 1; /* stereo */
1051 } else
1052 apu_set_register(chip, apu, 10, 0x8F08);
1053 }
1054
1055 spin_lock_irqsave(&chip->reg_lock, flags);
1056 /* clear WP interrupts */
1057 outw(1, chip->io_port + 0x04);
1058 /* enable WP ints */
1059 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1060 spin_unlock_irqrestore(&chip->reg_lock, flags);
1061
1062 freq = runtime->rate;
1063 /* set frequency */
1064 if (freq > 48000)
1065 freq = 48000;
1066 if (freq < 4000)
1067 freq = 4000;
1068
1069 /* hmmm.. */
1070 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1071 freq >>= 1;
1072
1073 freq = snd_es1968_compute_rate(chip, freq);
1074
1075 /* Load the frequency, turn on 6dB */
1076 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1077 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1078 }
1079
1080
1081 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1082 unsigned int pa, unsigned int bsize,
1083 int mode, int route)
1084 {
1085 int i, apu = es->apu[channel];
1086
1087 es->apu_mode[channel] = mode;
1088
1089 /* set the wavecache control reg */
1090 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1091
1092 /* Offset to PCMBAR */
1093 pa -= chip->dma.addr;
1094 pa >>= 1; /* words */
1095
1096 /* base offset of dma calcs when reading the pointer
1097 on this left one */
1098 es->base[channel] = pa & 0xFFFF;
1099 pa |= 0x00400000; /* bit 22 -> System RAM */
1100
1101 /* Begin loading the APU */
1102 for (i = 0; i < 16; i++)
1103 apu_set_register(chip, apu, i, 0x0000);
1104
1105 /* need to enable subgroups.. and we should probably
1106 have different groups for different /dev/dsps.. */
1107 apu_set_register(chip, apu, 2, 0x8);
1108
1109 /* Load the buffer into the wave engine */
1110 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1111 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1112 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1113 apu_set_register(chip, apu, 7, bsize);
1114 /* clear effects/env.. */
1115 apu_set_register(chip, apu, 8, 0x00F0);
1116 /* amplitude now? sure. why not. */
1117 apu_set_register(chip, apu, 9, 0x0000);
1118 /* set filter tune, radius, polar pan */
1119 apu_set_register(chip, apu, 10, 0x8F08);
1120 /* route input */
1121 apu_set_register(chip, apu, 11, route);
1122 /* dma on, no envelopes, filter to all 1s) */
1123 apu_set_register(chip, apu, 0, 0x400F);
1124 }
1125
1126 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1127 struct snd_pcm_runtime *runtime)
1128 {
1129 int size;
1130 u32 freq;
1131 unsigned long flags;
1132
1133 size = es->dma_size >> es->wav_shift;
1134
1135 /* APU assignments:
1136 0 = mono/left SRC
1137 1 = right SRC
1138 2 = mono/left Input Mixer
1139 3 = right Input Mixer
1140 */
1141 /* data seems to flow from the codec, through an apu into
1142 the 'mixbuf' bit of page, then through the SRC apu
1143 and out to the real 'buffer'. ok. sure. */
1144
1145 /* input mixer (left/mono) */
1146 /* parallel in crap, see maestro reg 0xC [8-11] */
1147 init_capture_apu(chip, es, 2,
1148 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1149 ESM_APU_INPUTMIXER, 0x14);
1150 /* SRC (left/mono); get input from inputing apu */
1151 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1152 ESM_APU_SRCONVERTOR, es->apu[2]);
1153 if (es->fmt & ESS_FMT_STEREO) {
1154 /* input mixer (right) */
1155 init_capture_apu(chip, es, 3,
1156 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1157 ESM_MIXBUF_SIZE/4, /* in words */
1158 ESM_APU_INPUTMIXER, 0x15);
1159 /* SRC (right) */
1160 init_capture_apu(chip, es, 1,
1161 es->memory->buf.addr + size*2, size,
1162 ESM_APU_SRCONVERTOR, es->apu[3]);
1163 }
1164
1165 freq = runtime->rate;
1166 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1167 if (freq > 47999)
1168 freq = 47999;
1169 if (freq < 4000)
1170 freq = 4000;
1171
1172 freq = snd_es1968_compute_rate(chip, freq);
1173
1174 /* Load the frequency, turn on 6dB */
1175 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1176 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1177
1178 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1179 freq = 0x10000;
1180 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1181 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1182
1183 spin_lock_irqsave(&chip->reg_lock, flags);
1184 /* clear WP interrupts */
1185 outw(1, chip->io_port + 0x04);
1186 /* enable WP ints */
1187 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1188 spin_unlock_irqrestore(&chip->reg_lock, flags);
1189 }
1190
1191 /*******************
1192 * ALSA Interface *
1193 *******************/
1194
1195 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1196 {
1197 struct es1968 *chip = snd_pcm_substream_chip(substream);
1198 struct snd_pcm_runtime *runtime = substream->runtime;
1199 struct esschan *es = runtime->private_data;
1200
1201 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1202 es->frag_size = snd_pcm_lib_period_bytes(substream);
1203
1204 es->wav_shift = 1; /* maestro handles always 16bit */
1205 es->fmt = 0;
1206 if (snd_pcm_format_width(runtime->format) == 16)
1207 es->fmt |= ESS_FMT_16BIT;
1208 if (runtime->channels > 1) {
1209 es->fmt |= ESS_FMT_STEREO;
1210 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1211 es->wav_shift++;
1212 }
1213 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1214
1215 switch (es->mode) {
1216 case ESM_MODE_PLAY:
1217 snd_es1968_playback_setup(chip, es, runtime);
1218 break;
1219 case ESM_MODE_CAPTURE:
1220 snd_es1968_capture_setup(chip, es, runtime);
1221 break;
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1228 {
1229 struct es1968 *chip = snd_pcm_substream_chip(substream);
1230 struct esschan *es = substream->runtime->private_data;
1231
1232 spin_lock(&chip->substream_lock);
1233 switch (cmd) {
1234 case SNDRV_PCM_TRIGGER_START:
1235 case SNDRV_PCM_TRIGGER_RESUME:
1236 if (es->running)
1237 break;
1238 snd_es1968_bob_inc(chip, es->bob_freq);
1239 es->count = 0;
1240 es->hwptr = 0;
1241 snd_es1968_pcm_start(chip, es);
1242 es->running = 1;
1243 break;
1244 case SNDRV_PCM_TRIGGER_STOP:
1245 case SNDRV_PCM_TRIGGER_SUSPEND:
1246 if (! es->running)
1247 break;
1248 snd_es1968_pcm_stop(chip, es);
1249 es->running = 0;
1250 snd_es1968_bob_dec(chip);
1251 break;
1252 }
1253 spin_unlock(&chip->substream_lock);
1254 return 0;
1255 }
1256
1257 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1258 {
1259 struct es1968 *chip = snd_pcm_substream_chip(substream);
1260 struct esschan *es = substream->runtime->private_data;
1261 unsigned int ptr;
1262
1263 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1264
1265 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1266 }
1267
1268 static struct snd_pcm_hardware snd_es1968_playback = {
1269 .info = (SNDRV_PCM_INFO_MMAP |
1270 SNDRV_PCM_INFO_MMAP_VALID |
1271 SNDRV_PCM_INFO_INTERLEAVED |
1272 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1273 /*SNDRV_PCM_INFO_PAUSE |*/
1274 SNDRV_PCM_INFO_RESUME),
1275 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1276 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1277 .rate_min = 4000,
1278 .rate_max = 48000,
1279 .channels_min = 1,
1280 .channels_max = 2,
1281 .buffer_bytes_max = 65536,
1282 .period_bytes_min = 256,
1283 .period_bytes_max = 65536,
1284 .periods_min = 1,
1285 .periods_max = 1024,
1286 .fifo_size = 0,
1287 };
1288
1289 static struct snd_pcm_hardware snd_es1968_capture = {
1290 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1291 SNDRV_PCM_INFO_MMAP |
1292 SNDRV_PCM_INFO_MMAP_VALID |
1293 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1294 /*SNDRV_PCM_INFO_PAUSE |*/
1295 SNDRV_PCM_INFO_RESUME),
1296 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1297 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1298 .rate_min = 4000,
1299 .rate_max = 48000,
1300 .channels_min = 1,
1301 .channels_max = 2,
1302 .buffer_bytes_max = 65536,
1303 .period_bytes_min = 256,
1304 .period_bytes_max = 65536,
1305 .periods_min = 1,
1306 .periods_max = 1024,
1307 .fifo_size = 0,
1308 };
1309
1310 /* *************************
1311 * DMA memory management *
1312 *************************/
1313
1314 /* Because the Maestro can only take addresses relative to the PCM base address
1315 register :( */
1316
1317 static int calc_available_memory_size(struct es1968 *chip)
1318 {
1319 struct list_head *p;
1320 int max_size = 0;
1321
1322 mutex_lock(&chip->memory_mutex);
1323 list_for_each(p, &chip->buf_list) {
1324 struct esm_memory *buf = list_entry(p, struct esm_memory, list);
1325 if (buf->empty && buf->buf.bytes > max_size)
1326 max_size = buf->buf.bytes;
1327 }
1328 mutex_unlock(&chip->memory_mutex);
1329 if (max_size >= 128*1024)
1330 max_size = 127*1024;
1331 return max_size;
1332 }
1333
1334 /* allocate a new memory chunk with the specified size */
1335 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1336 {
1337 struct esm_memory *buf;
1338 struct list_head *p;
1339
1340 size = ALIGN(size, ESM_MEM_ALIGN);
1341 mutex_lock(&chip->memory_mutex);
1342 list_for_each(p, &chip->buf_list) {
1343 buf = list_entry(p, struct esm_memory, list);
1344 if (buf->empty && buf->buf.bytes >= size)
1345 goto __found;
1346 }
1347 mutex_unlock(&chip->memory_mutex);
1348 return NULL;
1349
1350 __found:
1351 if (buf->buf.bytes > size) {
1352 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1353 if (chunk == NULL) {
1354 mutex_unlock(&chip->memory_mutex);
1355 return NULL;
1356 }
1357 chunk->buf = buf->buf;
1358 chunk->buf.bytes -= size;
1359 chunk->buf.area += size;
1360 chunk->buf.addr += size;
1361 chunk->empty = 1;
1362 buf->buf.bytes = size;
1363 list_add(&chunk->list, &buf->list);
1364 }
1365 buf->empty = 0;
1366 mutex_unlock(&chip->memory_mutex);
1367 return buf;
1368 }
1369
1370 /* free a memory chunk */
1371 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1372 {
1373 struct esm_memory *chunk;
1374
1375 mutex_lock(&chip->memory_mutex);
1376 buf->empty = 1;
1377 if (buf->list.prev != &chip->buf_list) {
1378 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1379 if (chunk->empty) {
1380 chunk->buf.bytes += buf->buf.bytes;
1381 list_del(&buf->list);
1382 kfree(buf);
1383 buf = chunk;
1384 }
1385 }
1386 if (buf->list.next != &chip->buf_list) {
1387 chunk = list_entry(buf->list.next, struct esm_memory, list);
1388 if (chunk->empty) {
1389 buf->buf.bytes += chunk->buf.bytes;
1390 list_del(&chunk->list);
1391 kfree(chunk);
1392 }
1393 }
1394 mutex_unlock(&chip->memory_mutex);
1395 }
1396
1397 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1398 {
1399 struct list_head *p;
1400
1401 if (! chip->dma.area)
1402 return;
1403 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1404 while ((p = chip->buf_list.next) != &chip->buf_list) {
1405 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1406 list_del(p);
1407 kfree(chunk);
1408 }
1409 }
1410
1411 static int __devinit
1412 snd_es1968_init_dmabuf(struct es1968 *chip)
1413 {
1414 int err;
1415 struct esm_memory *chunk;
1416
1417 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1418 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1419 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1420 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1421 snd_dma_pci_data(chip->pci),
1422 chip->total_bufsize, &chip->dma);
1423 if (err < 0 || ! chip->dma.area) {
1424 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1425 chip->total_bufsize);
1426 return -ENOMEM;
1427 }
1428 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1429 snd_dma_free_pages(&chip->dma);
1430 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1431 return -ENOMEM;
1432 }
1433 }
1434
1435 INIT_LIST_HEAD(&chip->buf_list);
1436 /* allocate an empty chunk */
1437 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1438 if (chunk == NULL) {
1439 snd_es1968_free_dmabuf(chip);
1440 return -ENOMEM;
1441 }
1442 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1443 chunk->buf = chip->dma;
1444 chunk->buf.area += ESM_MEM_ALIGN;
1445 chunk->buf.addr += ESM_MEM_ALIGN;
1446 chunk->buf.bytes -= ESM_MEM_ALIGN;
1447 chunk->empty = 1;
1448 list_add(&chunk->list, &chip->buf_list);
1449
1450 return 0;
1451 }
1452
1453 /* setup the dma_areas */
1454 /* buffer is extracted from the pre-allocated memory chunk */
1455 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1456 struct snd_pcm_hw_params *hw_params)
1457 {
1458 struct es1968 *chip = snd_pcm_substream_chip(substream);
1459 struct snd_pcm_runtime *runtime = substream->runtime;
1460 struct esschan *chan = runtime->private_data;
1461 int size = params_buffer_bytes(hw_params);
1462
1463 if (chan->memory) {
1464 if (chan->memory->buf.bytes >= size) {
1465 runtime->dma_bytes = size;
1466 return 0;
1467 }
1468 snd_es1968_free_memory(chip, chan->memory);
1469 }
1470 chan->memory = snd_es1968_new_memory(chip, size);
1471 if (chan->memory == NULL) {
1472 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1473 return -ENOMEM;
1474 }
1475 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1476 return 1; /* area was changed */
1477 }
1478
1479 /* remove dma areas if allocated */
1480 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1481 {
1482 struct es1968 *chip = snd_pcm_substream_chip(substream);
1483 struct snd_pcm_runtime *runtime = substream->runtime;
1484 struct esschan *chan;
1485
1486 if (runtime->private_data == NULL)
1487 return 0;
1488 chan = runtime->private_data;
1489 if (chan->memory) {
1490 snd_es1968_free_memory(chip, chan->memory);
1491 chan->memory = NULL;
1492 }
1493 return 0;
1494 }
1495
1496
1497 /*
1498 * allocate APU pair
1499 */
1500 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1501 {
1502 int apu;
1503
1504 for (apu = 0; apu < NR_APUS; apu += 2) {
1505 if (chip->apu[apu] == ESM_APU_FREE &&
1506 chip->apu[apu + 1] == ESM_APU_FREE) {
1507 chip->apu[apu] = chip->apu[apu + 1] = type;
1508 return apu;
1509 }
1510 }
1511 return -EBUSY;
1512 }
1513
1514 /*
1515 * release APU pair
1516 */
1517 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1518 {
1519 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1520 }
1521
1522
1523 /******************
1524 * PCM open/close *
1525 ******************/
1526
1527 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1528 {
1529 struct es1968 *chip = snd_pcm_substream_chip(substream);
1530 struct snd_pcm_runtime *runtime = substream->runtime;
1531 struct esschan *es;
1532 int apu1;
1533
1534 /* search 2 APUs */
1535 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1536 if (apu1 < 0)
1537 return apu1;
1538
1539 es = kzalloc(sizeof(*es), GFP_KERNEL);
1540 if (!es) {
1541 snd_es1968_free_apu_pair(chip, apu1);
1542 return -ENOMEM;
1543 }
1544
1545 es->apu[0] = apu1;
1546 es->apu[1] = apu1 + 1;
1547 es->apu_mode[0] = 0;
1548 es->apu_mode[1] = 0;
1549 es->running = 0;
1550 es->substream = substream;
1551 es->mode = ESM_MODE_PLAY;
1552
1553 runtime->private_data = es;
1554 runtime->hw = snd_es1968_playback;
1555 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1556 calc_available_memory_size(chip);
1557 #if 0
1558 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1559 1024);
1560 #endif
1561 spin_lock_irq(&chip->substream_lock);
1562 list_add(&es->list, &chip->substream_list);
1563 spin_unlock_irq(&chip->substream_lock);
1564
1565 return 0;
1566 }
1567
1568 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1569 {
1570 struct snd_pcm_runtime *runtime = substream->runtime;
1571 struct es1968 *chip = snd_pcm_substream_chip(substream);
1572 struct esschan *es;
1573 int apu1, apu2;
1574
1575 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1576 if (apu1 < 0)
1577 return apu1;
1578 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1579 if (apu2 < 0) {
1580 snd_es1968_free_apu_pair(chip, apu1);
1581 return apu2;
1582 }
1583
1584 es = kzalloc(sizeof(*es), GFP_KERNEL);
1585 if (!es) {
1586 snd_es1968_free_apu_pair(chip, apu1);
1587 snd_es1968_free_apu_pair(chip, apu2);
1588 return -ENOMEM;
1589 }
1590
1591 es->apu[0] = apu1;
1592 es->apu[1] = apu1 + 1;
1593 es->apu[2] = apu2;
1594 es->apu[3] = apu2 + 1;
1595 es->apu_mode[0] = 0;
1596 es->apu_mode[1] = 0;
1597 es->apu_mode[2] = 0;
1598 es->apu_mode[3] = 0;
1599 es->running = 0;
1600 es->substream = substream;
1601 es->mode = ESM_MODE_CAPTURE;
1602
1603 /* get mixbuffer */
1604 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1605 snd_es1968_free_apu_pair(chip, apu1);
1606 snd_es1968_free_apu_pair(chip, apu2);
1607 kfree(es);
1608 return -ENOMEM;
1609 }
1610 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1611
1612 runtime->private_data = es;
1613 runtime->hw = snd_es1968_capture;
1614 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1615 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1616 #if 0
1617 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1618 1024);
1619 #endif
1620 spin_lock_irq(&chip->substream_lock);
1621 list_add(&es->list, &chip->substream_list);
1622 spin_unlock_irq(&chip->substream_lock);
1623
1624 return 0;
1625 }
1626
1627 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1628 {
1629 struct es1968 *chip = snd_pcm_substream_chip(substream);
1630 struct esschan *es;
1631
1632 if (substream->runtime->private_data == NULL)
1633 return 0;
1634 es = substream->runtime->private_data;
1635 spin_lock_irq(&chip->substream_lock);
1636 list_del(&es->list);
1637 spin_unlock_irq(&chip->substream_lock);
1638 snd_es1968_free_apu_pair(chip, es->apu[0]);
1639 kfree(es);
1640
1641 return 0;
1642 }
1643
1644 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1645 {
1646 struct es1968 *chip = snd_pcm_substream_chip(substream);
1647 struct esschan *es;
1648
1649 if (substream->runtime->private_data == NULL)
1650 return 0;
1651 es = substream->runtime->private_data;
1652 spin_lock_irq(&chip->substream_lock);
1653 list_del(&es->list);
1654 spin_unlock_irq(&chip->substream_lock);
1655 snd_es1968_free_memory(chip, es->mixbuf);
1656 snd_es1968_free_apu_pair(chip, es->apu[0]);
1657 snd_es1968_free_apu_pair(chip, es->apu[2]);
1658 kfree(es);
1659
1660 return 0;
1661 }
1662
1663 static struct snd_pcm_ops snd_es1968_playback_ops = {
1664 .open = snd_es1968_playback_open,
1665 .close = snd_es1968_playback_close,
1666 .ioctl = snd_pcm_lib_ioctl,
1667 .hw_params = snd_es1968_hw_params,
1668 .hw_free = snd_es1968_hw_free,
1669 .prepare = snd_es1968_pcm_prepare,
1670 .trigger = snd_es1968_pcm_trigger,
1671 .pointer = snd_es1968_pcm_pointer,
1672 };
1673
1674 static struct snd_pcm_ops snd_es1968_capture_ops = {
1675 .open = snd_es1968_capture_open,
1676 .close = snd_es1968_capture_close,
1677 .ioctl = snd_pcm_lib_ioctl,
1678 .hw_params = snd_es1968_hw_params,
1679 .hw_free = snd_es1968_hw_free,
1680 .prepare = snd_es1968_pcm_prepare,
1681 .trigger = snd_es1968_pcm_trigger,
1682 .pointer = snd_es1968_pcm_pointer,
1683 };
1684
1685
1686 /*
1687 * measure clock
1688 */
1689 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1690
1691 static void __devinit es1968_measure_clock(struct es1968 *chip)
1692 {
1693 int i, apu;
1694 unsigned int pa, offset, t;
1695 struct esm_memory *memory;
1696 struct timeval start_time, stop_time;
1697
1698 if (chip->clock == 0)
1699 chip->clock = 48000; /* default clock value */
1700
1701 /* search 2 APUs (although one apu is enough) */
1702 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1703 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1704 return;
1705 }
1706 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1707 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1708 snd_es1968_free_apu_pair(chip, apu);
1709 return;
1710 }
1711
1712 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1713
1714 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1715
1716 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1717 pa |= 0x00400000; /* System RAM (Bit 22) */
1718
1719 /* initialize apu */
1720 for (i = 0; i < 16; i++)
1721 apu_set_register(chip, apu, i, 0x0000);
1722
1723 apu_set_register(chip, apu, 0, 0x400f);
1724 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1725 apu_set_register(chip, apu, 5, pa & 0xffff);
1726 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1727 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1728 apu_set_register(chip, apu, 8, 0x0000);
1729 apu_set_register(chip, apu, 9, 0xD000);
1730 apu_set_register(chip, apu, 10, 0x8F08);
1731 apu_set_register(chip, apu, 11, 0x0000);
1732 spin_lock_irq(&chip->reg_lock);
1733 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1734 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1735 spin_unlock_irq(&chip->reg_lock);
1736
1737 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1738
1739 chip->in_measurement = 1;
1740 chip->measure_apu = apu;
1741 spin_lock_irq(&chip->reg_lock);
1742 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1743 __apu_set_register(chip, apu, 5, pa & 0xffff);
1744 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1745 do_gettimeofday(&start_time);
1746 spin_unlock_irq(&chip->reg_lock);
1747 msleep(50);
1748 spin_lock_irq(&chip->reg_lock);
1749 offset = __apu_get_register(chip, apu, 5);
1750 do_gettimeofday(&stop_time);
1751 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1752 snd_es1968_bob_dec(chip);
1753 chip->in_measurement = 0;
1754 spin_unlock_irq(&chip->reg_lock);
1755
1756 /* check the current position */
1757 offset -= (pa & 0xffff);
1758 offset &= 0xfffe;
1759 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1760
1761 t = stop_time.tv_sec - start_time.tv_sec;
1762 t *= 1000000;
1763 if (stop_time.tv_usec < start_time.tv_usec)
1764 t -= start_time.tv_usec - stop_time.tv_usec;
1765 else
1766 t += stop_time.tv_usec - start_time.tv_usec;
1767 if (t == 0) {
1768 snd_printk(KERN_ERR "?? calculation error..\n");
1769 } else {
1770 offset *= 1000;
1771 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1772 if (offset < 47500 || offset > 48500) {
1773 if (offset >= 40000 && offset <= 50000)
1774 chip->clock = (chip->clock * offset) / 48000;
1775 }
1776 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1777 }
1778 snd_es1968_free_memory(chip, memory);
1779 snd_es1968_free_apu_pair(chip, apu);
1780 }
1781
1782
1783 /*
1784 */
1785
1786 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1787 {
1788 struct es1968 *esm = pcm->private_data;
1789 snd_es1968_free_dmabuf(esm);
1790 esm->pcm = NULL;
1791 }
1792
1793 static int __devinit
1794 snd_es1968_pcm(struct es1968 *chip, int device)
1795 {
1796 struct snd_pcm *pcm;
1797 int err;
1798
1799 /* get DMA buffer */
1800 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1801 return err;
1802
1803 /* set PCMBAR */
1804 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1805 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1806 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1807 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1808
1809 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1810 chip->playback_streams,
1811 chip->capture_streams, &pcm)) < 0)
1812 return err;
1813
1814 pcm->private_data = chip;
1815 pcm->private_free = snd_es1968_pcm_free;
1816
1817 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1818 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1819
1820 pcm->info_flags = 0;
1821
1822 strcpy(pcm->name, "ESS Maestro");
1823
1824 chip->pcm = pcm;
1825
1826 return 0;
1827 }
1828
1829 /*
1830 * update pointer
1831 */
1832 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1833 {
1834 unsigned int hwptr;
1835 unsigned int diff;
1836 struct snd_pcm_substream *subs = es->substream;
1837
1838 if (subs == NULL || !es->running)
1839 return;
1840
1841 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1842 hwptr %= es->dma_size;
1843
1844 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1845
1846 es->hwptr = hwptr;
1847 es->count += diff;
1848
1849 if (es->count > es->frag_size) {
1850 spin_unlock(&chip->substream_lock);
1851 snd_pcm_period_elapsed(subs);
1852 spin_lock(&chip->substream_lock);
1853 es->count %= es->frag_size;
1854 }
1855 }
1856
1857 /*
1858 */
1859 static void es1968_update_hw_volume(unsigned long private_data)
1860 {
1861 struct es1968 *chip = (struct es1968 *) private_data;
1862 int x, val;
1863 unsigned long flags;
1864
1865 /* Figure out which volume control button was pushed,
1866 based on differences from the default register
1867 values. */
1868 x = inb(chip->io_port + 0x1c) & 0xee;
1869 /* Reset the volume control registers. */
1870 outb(0x88, chip->io_port + 0x1c);
1871 outb(0x88, chip->io_port + 0x1d);
1872 outb(0x88, chip->io_port + 0x1e);
1873 outb(0x88, chip->io_port + 0x1f);
1874
1875 if (chip->in_suspend)
1876 return;
1877
1878 if (! chip->master_switch || ! chip->master_volume)
1879 return;
1880
1881 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1882 spin_lock_irqsave(&chip->ac97_lock, flags);
1883 val = chip->ac97->regs[AC97_MASTER];
1884 switch (x) {
1885 case 0x88:
1886 /* mute */
1887 val ^= 0x8000;
1888 chip->ac97->regs[AC97_MASTER] = val;
1889 outw(val, chip->io_port + ESM_AC97_DATA);
1890 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1891 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1892 &chip->master_switch->id);
1893 break;
1894 case 0xaa:
1895 /* volume up */
1896 if ((val & 0x7f) > 0)
1897 val--;
1898 if ((val & 0x7f00) > 0)
1899 val -= 0x0100;
1900 chip->ac97->regs[AC97_MASTER] = val;
1901 outw(val, chip->io_port + ESM_AC97_DATA);
1902 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1903 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1904 &chip->master_volume->id);
1905 break;
1906 case 0x66:
1907 /* volume down */
1908 if ((val & 0x7f) < 0x1f)
1909 val++;
1910 if ((val & 0x7f00) < 0x1f00)
1911 val += 0x0100;
1912 chip->ac97->regs[AC97_MASTER] = val;
1913 outw(val, chip->io_port + ESM_AC97_DATA);
1914 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1915 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1916 &chip->master_volume->id);
1917 break;
1918 }
1919 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1920 }
1921
1922 /*
1923 * interrupt handler
1924 */
1925 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1926 {
1927 struct es1968 *chip = dev_id;
1928 u32 event;
1929
1930 if (!(event = inb(chip->io_port + 0x1A)))
1931 return IRQ_NONE;
1932
1933 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1934
1935 if (event & ESM_HWVOL_IRQ)
1936 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1937
1938 /* else ack 'em all, i imagine */
1939 outb(0xFF, chip->io_port + 0x1A);
1940
1941 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1942 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1943 }
1944
1945 if (event & ESM_SOUND_IRQ) {
1946 struct list_head *p;
1947 spin_lock(&chip->substream_lock);
1948 list_for_each(p, &chip->substream_list) {
1949 struct esschan *es = list_entry(p, struct esschan, list);
1950 if (es->running)
1951 snd_es1968_update_pcm(chip, es);
1952 }
1953 spin_unlock(&chip->substream_lock);
1954 if (chip->in_measurement) {
1955 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1956 if (curp < chip->measure_lastpos)
1957 chip->measure_count++;
1958 chip->measure_lastpos = curp;
1959 }
1960 }
1961
1962 return IRQ_HANDLED;
1963 }
1964
1965 /*
1966 * Mixer stuff
1967 */
1968
1969 static int __devinit
1970 snd_es1968_mixer(struct es1968 *chip)
1971 {
1972 struct snd_ac97_bus *pbus;
1973 struct snd_ac97_template ac97;
1974 struct snd_ctl_elem_id id;
1975 int err;
1976 static struct snd_ac97_bus_ops ops = {
1977 .write = snd_es1968_ac97_write,
1978 .read = snd_es1968_ac97_read,
1979 };
1980
1981 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1982 return err;
1983 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
1984
1985 memset(&ac97, 0, sizeof(ac97));
1986 ac97.private_data = chip;
1987 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1988 return err;
1989
1990 /* attach master switch / volumes for h/w volume control */
1991 memset(&id, 0, sizeof(id));
1992 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1993 strcpy(id.name, "Master Playback Switch");
1994 chip->master_switch = snd_ctl_find_id(chip->card, &id);
1995 memset(&id, 0, sizeof(id));
1996 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1997 strcpy(id.name, "Master Playback Volume");
1998 chip->master_volume = snd_ctl_find_id(chip->card, &id);
1999
2000 return 0;
2001 }
2002
2003 /*
2004 * reset ac97 codec
2005 */
2006
2007 static void snd_es1968_ac97_reset(struct es1968 *chip)
2008 {
2009 unsigned long ioaddr = chip->io_port;
2010
2011 unsigned short save_ringbus_a;
2012 unsigned short save_68;
2013 unsigned short w;
2014 unsigned int vend;
2015
2016 /* save configuration */
2017 save_ringbus_a = inw(ioaddr + 0x36);
2018
2019 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2020 /* set command/status address i/o to 1st codec */
2021 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2022 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2023
2024 /* disable ac link */
2025 outw(0x0000, ioaddr + 0x36);
2026 save_68 = inw(ioaddr + 0x68);
2027 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2028 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2029 if (w & 1)
2030 save_68 |= 0x10;
2031 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2032 outw(0x0001, ioaddr + 0x68); /* gpio write */
2033 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2034 udelay(20);
2035 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2036 msleep(20);
2037
2038 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2039 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2040 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2041 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2042
2043 /* now the second codec */
2044 /* disable ac link */
2045 outw(0x0000, ioaddr + 0x36);
2046 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2047 save_68 = inw(ioaddr + 0x68);
2048 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2049 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2050 udelay(20);
2051 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2052 msleep(500);
2053 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2054 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2055 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2056
2057 #if 0 /* the loop here needs to be much better if we want it.. */
2058 snd_printk(KERN_INFO "trying software reset\n");
2059 /* try and do a software reset */
2060 outb(0x80 | 0x7c, ioaddr + 0x30);
2061 for (w = 0;; w++) {
2062 if ((inw(ioaddr + 0x30) & 1) == 0) {
2063 if (inb(ioaddr + 0x32) != 0)
2064 break;
2065
2066 outb(0x80 | 0x7d, ioaddr + 0x30);
2067 if (((inw(ioaddr + 0x30) & 1) == 0)
2068 && (inb(ioaddr + 0x32) != 0))
2069 break;
2070 outb(0x80 | 0x7f, ioaddr + 0x30);
2071 if (((inw(ioaddr + 0x30) & 1) == 0)
2072 && (inb(ioaddr + 0x32) != 0))
2073 break;
2074 }
2075
2076 if (w > 10000) {
2077 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2078 msleep(500); /* oh my.. */
2079 outb(inb(ioaddr + 0x37) & ~0x08,
2080 ioaddr + 0x37);
2081 udelay(1);
2082 outw(0x80, ioaddr + 0x30);
2083 for (w = 0; w < 10000; w++) {
2084 if ((inw(ioaddr + 0x30) & 1) == 0)
2085 break;
2086 }
2087 }
2088 }
2089 #endif
2090 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2091 /* turn on external amp? */
2092 outw(0xf9ff, ioaddr + 0x64);
2093 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2094 outw(0x0209, ioaddr + 0x60);
2095 }
2096
2097 /* restore.. */
2098 outw(save_ringbus_a, ioaddr + 0x36);
2099
2100 /* Turn on the 978 docking chip.
2101 First frob the "master output enable" bit,
2102 then set most of the playback volume control registers to max. */
2103 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2104 outb(0xff, ioaddr+0xc3);
2105 outb(0xff, ioaddr+0xc4);
2106 outb(0xff, ioaddr+0xc6);
2107 outb(0xff, ioaddr+0xc8);
2108 outb(0x3f, ioaddr+0xcf);
2109 outb(0x3f, ioaddr+0xd0);
2110 }
2111
2112 static void snd_es1968_reset(struct es1968 *chip)
2113 {
2114 /* Reset */
2115 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2116 chip->io_port + ESM_PORT_HOST_IRQ);
2117 udelay(10);
2118 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2119 udelay(10);
2120 }
2121
2122 /*
2123 * initialize maestro chip
2124 */
2125 static void snd_es1968_chip_init(struct es1968 *chip)
2126 {
2127 struct pci_dev *pci = chip->pci;
2128 int i;
2129 unsigned long iobase = chip->io_port;
2130 u16 w;
2131 u32 n;
2132
2133 /* We used to muck around with pci config space that
2134 * we had no business messing with. We don't know enough
2135 * about the machine to know which DMA mode is appropriate,
2136 * etc. We were guessing wrong on some machines and making
2137 * them unhappy. We now trust in the BIOS to do things right,
2138 * which almost certainly means a new host of problems will
2139 * arise with broken BIOS implementations. screw 'em.
2140 * We're already intolerant of machines that don't assign
2141 * IRQs.
2142 */
2143
2144 /* Config Reg A */
2145 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2146
2147 w &= ~DMA_CLEAR; /* Clear DMA bits */
2148 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2149 w &= ~SAFEGUARD; /* Safeguard off */
2150 w |= POST_WRITE; /* Posted write */
2151 w |= PCI_TIMING; /* PCI timing on */
2152 /* XXX huh? claims to be reserved.. */
2153 w &= ~SWAP_LR; /* swap left/right
2154 seems to only have effect on SB
2155 Emulation */
2156 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2157
2158 pci_write_config_word(pci, ESM_CONFIG_A, w);
2159
2160 /* Config Reg B */
2161
2162 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2163
2164 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2165 /* XXX how do we know which to use? */
2166 w &= ~(1 << 14); /* External clock */
2167
2168 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2169 w |= HWV_CONFB; /* HWV on */
2170 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2171 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2172 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2173 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2174 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2175 w &= ~(1 << 1); /* reserved, always write 0 */
2176 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2177
2178 pci_write_config_word(pci, ESM_CONFIG_B, w);
2179
2180 /* DDMA off */
2181
2182 pci_read_config_word(pci, ESM_DDMA, &w);
2183 w &= ~(1 << 0);
2184 pci_write_config_word(pci, ESM_DDMA, w);
2185
2186 /*
2187 * Legacy mode
2188 */
2189
2190 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2191
2192 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2193 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2194 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2195
2196 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2197
2198 /* Set up 978 docking control chip. */
2199 pci_read_config_word(pci, 0x58, &w);
2200 w|=1<<2; /* Enable 978. */
2201 w|=1<<3; /* Turn on 978 hardware volume control. */
2202 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2203 pci_write_config_word(pci, 0x58, w);
2204
2205 /* Sound Reset */
2206
2207 snd_es1968_reset(chip);
2208
2209 /*
2210 * Ring Bus Setup
2211 */
2212
2213 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2214 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2215 udelay(20);
2216 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2217 udelay(20);
2218
2219 /*
2220 * Reset the CODEC
2221 */
2222
2223 snd_es1968_ac97_reset(chip);
2224
2225 /* Ring Bus Control B */
2226
2227 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2228 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2229 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2230 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2231
2232 /* Set hardware volume control registers to midpoints.
2233 We can tell which button was pushed based on how they change. */
2234 outb(0x88, iobase+0x1c);
2235 outb(0x88, iobase+0x1d);
2236 outb(0x88, iobase+0x1e);
2237 outb(0x88, iobase+0x1f);
2238
2239 /* it appears some maestros (dell 7500) only work if these are set,
2240 regardless of wether we use the assp or not. */
2241
2242 outb(0, iobase + ASSP_CONTROL_B);
2243 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2244 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2245
2246 /*
2247 * set up wavecache
2248 */
2249 for (i = 0; i < 16; i++) {
2250 /* Write 0 into the buffer area 0x1E0->1EF */
2251 outw(0x01E0 + i, iobase + WC_INDEX);
2252 outw(0x0000, iobase + WC_DATA);
2253
2254 /* The 1.10 test program seem to write 0 into the buffer area
2255 * 0x1D0-0x1DF too.*/
2256 outw(0x01D0 + i, iobase + WC_INDEX);
2257 outw(0x0000, iobase + WC_DATA);
2258 }
2259 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2260 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2261 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2262 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2263 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2264 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2265 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2266 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2267
2268
2269 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2270 /* Now back to the DirectSound stuff */
2271 /* audio serial configuration.. ? */
2272 maestro_write(chip, 0x08, 0xB004);
2273 maestro_write(chip, 0x09, 0x001B);
2274 maestro_write(chip, 0x0A, 0x8000);
2275 maestro_write(chip, 0x0B, 0x3F37);
2276 maestro_write(chip, 0x0C, 0x0098);
2277
2278 /* parallel in, has something to do with recording :) */
2279 maestro_write(chip, 0x0C,
2280 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2281 /* parallel out */
2282 maestro_write(chip, 0x0C,
2283 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2284
2285 maestro_write(chip, 0x0D, 0x7632);
2286
2287 /* Wave cache control on - test off, sg off,
2288 enable, enable extra chans 1Mb */
2289
2290 w = inw(iobase + WC_CONTROL);
2291
2292 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2293 w |= 0xA000; /* reserved... I don't know */
2294 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2295 Seems to crash the Computer if enabled... */
2296 w |= 0x0100; /* Wave Cache Operation Enabled */
2297 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2298 w &= ~0x0060; /* Clear Wavtable Size */
2299 w |= 0x0020; /* Wavetable Size : 1MB */
2300 /* Bit 4 is reserved */
2301 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2302 /* Bit 1 is reserved */
2303 w &= ~0x0001; /* Test Mode off */
2304
2305 outw(w, iobase + WC_CONTROL);
2306
2307 /* Now clear the APU control ram */
2308 for (i = 0; i < NR_APUS; i++) {
2309 for (w = 0; w < NR_APU_REGS; w++)
2310 apu_set_register(chip, i, w, 0);
2311
2312 }
2313 }
2314
2315 /* Enable IRQ's */
2316 static void snd_es1968_start_irq(struct es1968 *chip)
2317 {
2318 unsigned short w;
2319 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2320 if (chip->rmidi)
2321 w |= ESM_HIRQ_MPU401;
2322 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2323 }
2324
2325 #ifdef CONFIG_PM
2326 /*
2327 * PM support
2328 */
2329 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2330 {
2331 struct snd_card *card = pci_get_drvdata(pci);
2332 struct es1968 *chip = card->private_data;
2333
2334 if (! chip->do_pm)
2335 return 0;
2336
2337 chip->in_suspend = 1;
2338 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2339 snd_pcm_suspend_all(chip->pcm);
2340 snd_ac97_suspend(chip->ac97);
2341 snd_es1968_bob_stop(chip);
2342
2343 pci_disable_device(pci);
2344 pci_save_state(pci);
2345 pci_set_power_state(pci, pci_choose_state(pci, state));
2346 return 0;
2347 }
2348
2349 static int es1968_resume(struct pci_dev *pci)
2350 {
2351 struct snd_card *card = pci_get_drvdata(pci);
2352 struct es1968 *chip = card->private_data;
2353 struct list_head *p;
2354
2355 if (! chip->do_pm)
2356 return 0;
2357
2358 /* restore all our config */
2359 pci_set_power_state(pci, PCI_D0);
2360 pci_restore_state(pci);
2361 if (pci_enable_device(pci) < 0) {
2362 printk(KERN_ERR "es1968: pci_enable_device failed, "
2363 "disabling device\n");
2364 snd_card_disconnect(card);
2365 return -EIO;
2366 }
2367 pci_set_master(pci);
2368
2369 snd_es1968_chip_init(chip);
2370
2371 /* need to restore the base pointers.. */
2372 if (chip->dma.addr) {
2373 /* set PCMBAR */
2374 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2375 }
2376
2377 snd_es1968_start_irq(chip);
2378
2379 /* restore ac97 state */
2380 snd_ac97_resume(chip->ac97);
2381
2382 list_for_each(p, &chip->substream_list) {
2383 struct esschan *es = list_entry(p, struct esschan, list);
2384 switch (es->mode) {
2385 case ESM_MODE_PLAY:
2386 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2387 break;
2388 case ESM_MODE_CAPTURE:
2389 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2390 break;
2391 }
2392 }
2393
2394 /* start timer again */
2395 if (chip->bobclient)
2396 snd_es1968_bob_start(chip);
2397
2398 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2399 chip->in_suspend = 0;
2400 return 0;
2401 }
2402 #endif /* CONFIG_PM */
2403
2404 #ifdef SUPPORT_JOYSTICK
2405 #define JOYSTICK_ADDR 0x200
2406 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2407 {
2408 struct gameport *gp;
2409 struct resource *r;
2410 u16 val;
2411
2412 if (!joystick[dev])
2413 return -ENODEV;
2414
2415 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2416 if (!r)
2417 return -EBUSY;
2418
2419 chip->gameport = gp = gameport_allocate_port();
2420 if (!gp) {
2421 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2422 release_and_free_resource(r);
2423 return -ENOMEM;
2424 }
2425
2426 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2427 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2428
2429 gameport_set_name(gp, "ES1968 Gameport");
2430 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2431 gameport_set_dev_parent(gp, &chip->pci->dev);
2432 gp->io = JOYSTICK_ADDR;
2433 gameport_set_port_data(gp, r);
2434
2435 gameport_register_port(gp);
2436
2437 return 0;
2438 }
2439
2440 static void snd_es1968_free_gameport(struct es1968 *chip)
2441 {
2442 if (chip->gameport) {
2443 struct resource *r = gameport_get_port_data(chip->gameport);
2444
2445 gameport_unregister_port(chip->gameport);
2446 chip->gameport = NULL;
2447
2448 release_and_free_resource(r);
2449 }
2450 }
2451 #else
2452 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2453 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2454 #endif
2455
2456 static int snd_es1968_free(struct es1968 *chip)
2457 {
2458 if (chip->io_port) {
2459 synchronize_irq(chip->irq);
2460 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2461 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2462 }
2463
2464 if (chip->irq >= 0)
2465 free_irq(chip->irq, chip);
2466 snd_es1968_free_gameport(chip);
2467 chip->master_switch = NULL;
2468 chip->master_volume = NULL;
2469 pci_release_regions(chip->pci);
2470 pci_disable_device(chip->pci);
2471 kfree(chip);
2472 return 0;
2473 }
2474
2475 static int snd_es1968_dev_free(struct snd_device *device)
2476 {
2477 struct es1968 *chip = device->device_data;
2478 return snd_es1968_free(chip);
2479 }
2480
2481 struct ess_device_list {
2482 unsigned short type; /* chip type */
2483 unsigned short vendor; /* subsystem vendor id */
2484 };
2485
2486 static struct ess_device_list pm_whitelist[] __devinitdata = {
2487 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2488 { TYPE_MAESTRO2E, 0x1028 },
2489 { TYPE_MAESTRO2E, 0x103c },
2490 { TYPE_MAESTRO2E, 0x1179 },
2491 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2492 { TYPE_MAESTRO2E, 0x1558 },
2493 };
2494
2495 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2496 { TYPE_MAESTRO2, 0x125d },
2497 };
2498
2499 static int __devinit snd_es1968_create(struct snd_card *card,
2500 struct pci_dev *pci,
2501 int total_bufsize,
2502 int play_streams,
2503 int capt_streams,
2504 int chip_type,
2505 int do_pm,
2506 struct es1968 **chip_ret)
2507 {
2508 static struct snd_device_ops ops = {
2509 .dev_free = snd_es1968_dev_free,
2510 };
2511 struct es1968 *chip;
2512 int i, err;
2513
2514 *chip_ret = NULL;
2515
2516 /* enable PCI device */
2517 if ((err = pci_enable_device(pci)) < 0)
2518 return err;
2519 /* check, if we can restrict PCI DMA transfers to 28 bits */
2520 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2521 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2522 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2523 pci_disable_device(pci);
2524 return -ENXIO;
2525 }
2526
2527 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2528 if (! chip) {
2529 pci_disable_device(pci);
2530 return -ENOMEM;
2531 }
2532
2533 /* Set Vars */
2534 chip->type = chip_type;
2535 spin_lock_init(&chip->reg_lock);
2536 spin_lock_init(&chip->substream_lock);
2537 INIT_LIST_HEAD(&chip->buf_list);
2538 INIT_LIST_HEAD(&chip->substream_list);
2539 spin_lock_init(&chip->ac97_lock);
2540 mutex_init(&chip->memory_mutex);
2541 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2542 chip->card = card;
2543 chip->pci = pci;
2544 chip->irq = -1;
2545 chip->total_bufsize = total_bufsize; /* in bytes */
2546 chip->playback_streams = play_streams;
2547 chip->capture_streams = capt_streams;
2548
2549 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2550 kfree(chip);
2551 pci_disable_device(pci);
2552 return err;
2553 }
2554 chip->io_port = pci_resource_start(pci, 0);
2555 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2556 "ESS Maestro", chip)) {
2557 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2558 snd_es1968_free(chip);
2559 return -EBUSY;
2560 }
2561 chip->irq = pci->irq;
2562
2563 /* Clear Maestro_map */
2564 for (i = 0; i < 32; i++)
2565 chip->maestro_map[i] = 0;
2566
2567 /* Clear Apu Map */
2568 for (i = 0; i < NR_APUS; i++)
2569 chip->apu[i] = ESM_APU_FREE;
2570
2571 /* just to be sure */
2572 pci_set_master(pci);
2573
2574 if (do_pm > 1) {
2575 /* disable power-management if not on the whitelist */
2576 unsigned short vend;
2577 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2578 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2579 if (chip->type == pm_whitelist[i].type &&
2580 vend == pm_whitelist[i].vendor) {
2581 do_pm = 1;
2582 break;
2583 }
2584 }
2585 if (do_pm > 1) {
2586 /* not matched; disabling pm */
2587 printk(KERN_INFO "es1968: not attempting power management.\n");
2588 do_pm = 0;
2589 }
2590 }
2591 chip->do_pm = do_pm;
2592
2593 snd_es1968_chip_init(chip);
2594
2595 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2596 snd_es1968_free(chip);
2597 return err;
2598 }
2599
2600 snd_card_set_dev(card, &pci->dev);
2601
2602 *chip_ret = chip;
2603
2604 return 0;
2605 }
2606
2607
2608 /*
2609 */
2610 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2611 const struct pci_device_id *pci_id)
2612 {
2613 static int dev;
2614 struct snd_card *card;
2615 struct es1968 *chip;
2616 unsigned int i;
2617 int err;
2618
2619 if (dev >= SNDRV_CARDS)
2620 return -ENODEV;
2621 if (!enable[dev]) {
2622 dev++;
2623 return -ENOENT;
2624 }
2625
2626 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2627 if (!card)
2628 return -ENOMEM;
2629
2630 if (total_bufsize[dev] < 128)
2631 total_bufsize[dev] = 128;
2632 if (total_bufsize[dev] > 4096)
2633 total_bufsize[dev] = 4096;
2634 if ((err = snd_es1968_create(card, pci,
2635 total_bufsize[dev] * 1024, /* in bytes */
2636 pcm_substreams_p[dev],
2637 pcm_substreams_c[dev],
2638 pci_id->driver_data,
2639 use_pm[dev],
2640 &chip)) < 0) {
2641 snd_card_free(card);
2642 return err;
2643 }
2644 card->private_data = chip;
2645
2646 switch (chip->type) {
2647 case TYPE_MAESTRO2E:
2648 strcpy(card->driver, "ES1978");
2649 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2650 break;
2651 case TYPE_MAESTRO2:
2652 strcpy(card->driver, "ES1968");
2653 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2654 break;
2655 case TYPE_MAESTRO:
2656 strcpy(card->driver, "ESM1");
2657 strcpy(card->shortname, "ESS Maestro 1");
2658 break;
2659 }
2660
2661 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2662 snd_card_free(card);
2663 return err;
2664 }
2665
2666 if ((err = snd_es1968_mixer(chip)) < 0) {
2667 snd_card_free(card);
2668 return err;
2669 }
2670
2671 if (enable_mpu[dev] == 2) {
2672 /* check the black list */
2673 unsigned short vend;
2674 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2675 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2676 if (chip->type == mpu_blacklist[i].type &&
2677 vend == mpu_blacklist[i].vendor) {
2678 enable_mpu[dev] = 0;
2679 break;
2680 }
2681 }
2682 }
2683 if (enable_mpu[dev]) {
2684 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2685 chip->io_port + ESM_MPU401_PORT,
2686 MPU401_INFO_INTEGRATED,
2687 chip->irq, 0, &chip->rmidi)) < 0) {
2688 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2689 }
2690 }
2691
2692 snd_es1968_create_gameport(chip, dev);
2693
2694 snd_es1968_start_irq(chip);
2695
2696 chip->clock = clock[dev];
2697 if (! chip->clock)
2698 es1968_measure_clock(chip);
2699
2700 sprintf(card->longname, "%s at 0x%lx, irq %i",
2701 card->shortname, chip->io_port, chip->irq);
2702
2703 if ((err = snd_card_register(card)) < 0) {
2704 snd_card_free(card);
2705 return err;
2706 }
2707 pci_set_drvdata(pci, card);
2708 dev++;
2709 return 0;
2710 }
2711
2712 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2713 {
2714 snd_card_free(pci_get_drvdata(pci));
2715 pci_set_drvdata(pci, NULL);
2716 }
2717
2718 static struct pci_driver driver = {
2719 .name = "ES1968 (ESS Maestro)",
2720 .id_table = snd_es1968_ids,
2721 .probe = snd_es1968_probe,
2722 .remove = __devexit_p(snd_es1968_remove),
2723 #ifdef CONFIG_PM
2724 .suspend = es1968_suspend,
2725 .resume = es1968_resume,
2726 #endif
2727 };
2728
2729 static int __init alsa_card_es1968_init(void)
2730 {
2731 return pci_register_driver(&driver);
2732 }
2733
2734 static void __exit alsa_card_es1968_exit(void)
2735 {
2736 pci_unregister_driver(&driver);
2737 }
2738
2739 module_init(alsa_card_es1968_init)
2740 module_exit(alsa_card_es1968_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree