ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_area
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / linux / serial_sci.h
blob1630d9cae22a5f07da7c6345d9ef007ab2d19946
1 #ifndef __LINUX_SERIAL_SCI_H
2 #define __LINUX_SERIAL_SCI_H
4 #include <linux/serial_core.h>
5 #include <linux/sh_dma.h>
7 /*
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
9 */
11 enum {
12 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
13 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
14 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
15 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
16 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
19 #define SCSCR_TIE (1 << 7)
20 #define SCSCR_RIE (1 << 6)
21 #define SCSCR_TE (1 << 5)
22 #define SCSCR_RE (1 << 4)
23 #define SCSCR_REIE (1 << 3) /* not supported by all parts */
24 #define SCSCR_TOIE (1 << 2) /* not supported by all parts */
25 #define SCSCR_CKE1 (1 << 1)
26 #define SCSCR_CKE0 (1 << 0)
28 /* Offsets into the sci_port->irqs array */
29 enum {
30 SCIx_ERI_IRQ,
31 SCIx_RXI_IRQ,
32 SCIx_TXI_IRQ,
33 SCIx_BRI_IRQ,
34 SCIx_NR_IRQS,
37 struct device;
40 * Platform device specific platform_data struct
42 struct plat_sci_port {
43 void __iomem *membase; /* io cookie */
44 unsigned long mapbase; /* resource base */
45 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
46 unsigned int type; /* SCI / SCIF / IRDA */
47 upf_t flags; /* UPF_* flags */
48 char *clk; /* clock string */
50 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
51 unsigned int scscr; /* SCSCR initialization */
53 struct device *dma_dev;
55 #ifdef CONFIG_SERIAL_SH_SCI_DMA
56 unsigned int dma_slave_tx;
57 unsigned int dma_slave_rx;
58 #endif
61 #endif /* __LINUX_SERIAL_SCI_H */