2 * R8A66597 driver platform data
4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #ifndef __LINUX_USB_R8A66597_H
24 #define __LINUX_USB_R8A66597_H
26 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
27 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
28 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
30 struct r8a66597_platdata
{
31 /* This callback can control port power instead of DVSTCTR register. */
32 void (*port_power
)(int port
, int power
);
34 /* set one = on chip controller, set zero = external controller */
37 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
40 /* set one = 3.3V, set zero = 1.5V */
43 /* set one = big endian, set zero = little endian */
46 /* (external controller only) set one = WR0_N shorted to WR1_N */
47 unsigned wr0_shorted_to_wr1
:1;
50 /* Register definitions */
67 #define D0FIFOSEL 0x28
68 #define D0FIFOCTR 0x2A
69 #define D1FIFOSEL 0x2C
70 #define D1FIFOCTR 0x2E
100 #define PIPE2CTR 0x72
101 #define PIPE3CTR 0x74
102 #define PIPE4CTR 0x76
103 #define PIPE5CTR 0x78
104 #define PIPE6CTR 0x7A
105 #define PIPE7CTR 0x7C
106 #define PIPE8CTR 0x7E
107 #define PIPE9CTR 0x80
108 #define PIPE1TRE 0x90
109 #define PIPE1TRN 0x92
110 #define PIPE2TRE 0x94
111 #define PIPE2TRN 0x96
112 #define PIPE3TRE 0x98
113 #define PIPE3TRN 0x9A
114 #define PIPE4TRE 0x9C
115 #define PIPE4TRN 0x9E
116 #define PIPE5TRE 0xA0
117 #define PIPE5TRN 0xA2
130 /* System Configuration Control Register */
131 #define XTAL 0xC000 /* b15-14: Crystal selection */
132 #define XTAL48 0x8000 /* 48MHz */
133 #define XTAL24 0x4000 /* 24MHz */
134 #define XTAL12 0x0000 /* 12MHz */
135 #define XCKE 0x2000 /* b13: External clock enable */
136 #define PLLC 0x0800 /* b11: PLL control */
137 #define SCKE 0x0400 /* b10: USB clock enable */
138 #define PCSDIS 0x0200 /* b9: not CS wakeup */
139 #define LPSME 0x0100 /* b8: Low power sleep mode */
140 #define HSE 0x0080 /* b7: Hi-speed enable */
141 #define DCFM 0x0040 /* b6: Controller function select */
142 #define DRPD 0x0020 /* b5: D+/- pull down control */
143 #define DPRPU 0x0010 /* b4: D+ pull up control */
144 #define USBE 0x0001 /* b0: USB module operation enable */
146 /* System Configuration Status Register */
147 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
148 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
149 #define SOFEA 0x0020 /* b5: SOF monitor */
150 #define IDMON 0x0004 /* b3: ID-pin monitor */
151 #define LNST 0x0003 /* b1-0: D+, D- line status */
152 #define SE1 0x0003 /* SE1 */
153 #define FS_KSTS 0x0002 /* Full-Speed K State */
154 #define FS_JSTS 0x0001 /* Full-Speed J State */
155 #define LS_JSTS 0x0002 /* Low-Speed J State */
156 #define LS_KSTS 0x0001 /* Low-Speed K State */
157 #define SE0 0x0000 /* SE0 */
159 /* Device State Control Register */
160 #define EXTLP0 0x0400 /* b10: External port */
161 #define VBOUT 0x0200 /* b9: VBUS output */
162 #define WKUP 0x0100 /* b8: Remote wakeup */
163 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
164 #define USBRST 0x0040 /* b6: USB reset enable */
165 #define RESUME 0x0020 /* b5: Resume enable */
166 #define UACT 0x0010 /* b4: USB bus enable */
167 #define RHST 0x0007 /* b1-0: Reset handshake status */
168 #define HSPROC 0x0004 /* HS handshake is processing */
169 #define HSMODE 0x0003 /* Hi-Speed mode */
170 #define FSMODE 0x0002 /* Full-Speed mode */
171 #define LSMODE 0x0001 /* Low-Speed mode */
172 #define UNDECID 0x0000 /* Undecided */
174 /* Test Mode Register */
175 #define UTST 0x000F /* b3-0: Test select */
176 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
177 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
178 #define H_TST_K 0x000A /* HOST TEST K */
179 #define H_TST_J 0x0009 /* HOST TEST J */
180 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
181 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
182 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
183 #define P_TST_K 0x0002 /* PERI TEST K */
184 #define P_TST_J 0x0001 /* PERI TEST J */
185 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
187 /* Data Pin Configuration Register */
188 #define LDRV 0x8000 /* b15: Drive Current Adjust */
189 #define VIF1 0x0000 /* VIF = 1.8V */
190 #define VIF3 0x8000 /* VIF = 3.3V */
191 #define INTA 0x0001 /* b1: USB INT-pin active */
193 /* DMAx Pin Configuration Register */
194 #define DREQA 0x4000 /* b14: Dreq active select */
195 #define BURST 0x2000 /* b13: Burst mode */
196 #define DACKA 0x0400 /* b10: Dack active select */
197 #define DFORM 0x0380 /* b9-7: DMA mode select */
198 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
199 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
200 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
201 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
202 #define DENDA 0x0040 /* b6: Dend active select */
203 #define PKTM 0x0020 /* b5: Packet mode */
204 #define DENDE 0x0010 /* b4: Dend enable */
205 #define OBUS 0x0004 /* b2: OUTbus mode */
207 /* CFIFO/DxFIFO Port Select Register */
208 #define RCNT 0x8000 /* b15: Read count mode */
209 #define REW 0x4000 /* b14: Buffer rewind */
210 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
211 #define DREQE 0x1000 /* b12: DREQ output enable */
212 #define MBW_8 0x0000 /* 8bit */
213 #define MBW_16 0x0400 /* 16bit */
214 #define MBW_32 0x0800 /* 32bit */
215 #define BIGEND 0x0100 /* b8: Big endian mode */
216 #define BYTE_LITTLE 0x0000 /* little dendian */
217 #define BYTE_BIG 0x0100 /* big endifan */
218 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
219 #define CURPIPE 0x000F /* b2-0: PIPE select */
221 /* CFIFO/DxFIFO Port Control Register */
222 #define BVAL 0x8000 /* b15: Buffer valid flag */
223 #define BCLR 0x4000 /* b14: Buffer clear */
224 #define FRDY 0x2000 /* b13: FIFO ready */
225 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
227 /* Interrupt Enable Register 0 */
228 #define VBSE 0x8000 /* b15: VBUS interrupt */
229 #define RSME 0x4000 /* b14: Resume interrupt */
230 #define SOFE 0x2000 /* b13: Frame update interrupt */
231 #define DVSE 0x1000 /* b12: Device state transition interrupt */
232 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
233 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
234 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
235 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
237 /* Interrupt Enable Register 1 */
238 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
239 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
240 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
241 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
242 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
243 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
244 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
246 /* BRDY Interrupt Enable/Status Register */
247 #define BRDY9 0x0200 /* b9: PIPE9 */
248 #define BRDY8 0x0100 /* b8: PIPE8 */
249 #define BRDY7 0x0080 /* b7: PIPE7 */
250 #define BRDY6 0x0040 /* b6: PIPE6 */
251 #define BRDY5 0x0020 /* b5: PIPE5 */
252 #define BRDY4 0x0010 /* b4: PIPE4 */
253 #define BRDY3 0x0008 /* b3: PIPE3 */
254 #define BRDY2 0x0004 /* b2: PIPE2 */
255 #define BRDY1 0x0002 /* b1: PIPE1 */
256 #define BRDY0 0x0001 /* b1: PIPE0 */
258 /* NRDY Interrupt Enable/Status Register */
259 #define NRDY9 0x0200 /* b9: PIPE9 */
260 #define NRDY8 0x0100 /* b8: PIPE8 */
261 #define NRDY7 0x0080 /* b7: PIPE7 */
262 #define NRDY6 0x0040 /* b6: PIPE6 */
263 #define NRDY5 0x0020 /* b5: PIPE5 */
264 #define NRDY4 0x0010 /* b4: PIPE4 */
265 #define NRDY3 0x0008 /* b3: PIPE3 */
266 #define NRDY2 0x0004 /* b2: PIPE2 */
267 #define NRDY1 0x0002 /* b1: PIPE1 */
268 #define NRDY0 0x0001 /* b1: PIPE0 */
270 /* BEMP Interrupt Enable/Status Register */
271 #define BEMP9 0x0200 /* b9: PIPE9 */
272 #define BEMP8 0x0100 /* b8: PIPE8 */
273 #define BEMP7 0x0080 /* b7: PIPE7 */
274 #define BEMP6 0x0040 /* b6: PIPE6 */
275 #define BEMP5 0x0020 /* b5: PIPE5 */
276 #define BEMP4 0x0010 /* b4: PIPE4 */
277 #define BEMP3 0x0008 /* b3: PIPE3 */
278 #define BEMP2 0x0004 /* b2: PIPE2 */
279 #define BEMP1 0x0002 /* b1: PIPE1 */
280 #define BEMP0 0x0001 /* b0: PIPE0 */
282 /* SOF Pin Configuration Register */
283 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
284 #define BRDYM 0x0040 /* b6: BRDY clear timing */
285 #define INTL 0x0020 /* b5: Interrupt sense select */
286 #define EDGESTS 0x0010 /* b4: */
287 #define SOFMODE 0x000C /* b3-2: SOF pin select */
288 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
289 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
290 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
292 /* Interrupt Status Register 0 */
293 #define VBINT 0x8000 /* b15: VBUS interrupt */
294 #define RESM 0x4000 /* b14: Resume interrupt */
295 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
296 #define DVST 0x1000 /* b12: Device state transition interrupt */
297 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
298 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
299 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
300 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
301 #define VBSTS 0x0080 /* b7: VBUS input port */
302 #define DVSQ 0x0070 /* b6-4: Device state */
303 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
304 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
305 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
306 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
307 #define DS_SUSP 0x0040 /* Suspend */
308 #define DS_CNFG 0x0030 /* Configured */
309 #define DS_ADDS 0x0020 /* Address */
310 #define DS_DFLT 0x0010 /* Default */
311 #define DS_POWR 0x0000 /* Powered */
312 #define DVSQS 0x0030 /* b5-4: Device state */
313 #define VALID 0x0008 /* b3: Setup packet detected flag */
314 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
315 #define CS_SQER 0x0006 /* Sequence error */
316 #define CS_WRND 0x0005 /* Control write nodata status stage */
317 #define CS_WRSS 0x0004 /* Control write status stage */
318 #define CS_WRDS 0x0003 /* Control write data stage */
319 #define CS_RDSS 0x0002 /* Control read status stage */
320 #define CS_RDDS 0x0001 /* Control read data stage */
321 #define CS_IDST 0x0000 /* Idle or setup stage */
323 /* Interrupt Status Register 1 */
324 #define OVRCR 0x8000 /* b15: Over-current interrupt */
325 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
326 #define DTCH 0x1000 /* b12: Detach sense interrupt */
327 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
328 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
329 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
330 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
332 /* Frame Number Register */
333 #define OVRN 0x8000 /* b15: Overrun error */
334 #define CRCE 0x4000 /* b14: Received data error */
335 #define FRNM 0x07FF /* b10-0: Frame number */
337 /* Micro Frame Number Register */
338 #define UFRNM 0x0007 /* b2-0: Micro frame number */
340 /* Default Control Pipe Maxpacket Size Register */
341 /* Pipe Maxpacket Size Register */
342 #define DEVSEL 0xF000 /* b15-14: Device address select */
343 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
345 /* Default Control Pipe Control Register */
346 #define BSTS 0x8000 /* b15: Buffer status */
347 #define SUREQ 0x4000 /* b14: Send USB request */
348 #define CSCLR 0x2000 /* b13: complete-split status clear */
349 #define CSSTS 0x1000 /* b12: complete-split status */
350 #define SUREQCLR 0x0800 /* b11: stop setup request */
351 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
352 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
353 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
354 #define PBUSY 0x0020 /* b5: pipe busy */
355 #define PINGE 0x0010 /* b4: ping enable */
356 #define CCPL 0x0004 /* b2: Enable control transfer complete */
357 #define PID 0x0003 /* b1-0: Response PID */
358 #define PID_STALL11 0x0003 /* STALL */
359 #define PID_STALL 0x0002 /* STALL */
360 #define PID_BUF 0x0001 /* BUF */
361 #define PID_NAK 0x0000 /* NAK */
363 /* Pipe Window Select Register */
364 #define PIPENM 0x0007 /* b2-0: Pipe select */
366 /* Pipe Configuration Register */
367 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
368 #define R8A66597_ISO 0xC000 /* Isochronous */
369 #define R8A66597_INT 0x8000 /* Interrupt */
370 #define R8A66597_BULK 0x4000 /* Bulk */
371 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
372 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
373 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
374 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
375 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
376 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
378 /* Pipe Buffer Configuration Register */
379 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
380 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
384 /* Pipe Maxpacket Size Register */
385 #define MXPS 0x07FF /* b10-0: Maxpacket size */
387 /* Pipe Cycle Configuration Register */
388 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
389 #define IITV 0x0007 /* b2-0: Isochronous interval */
391 /* Pipex Control Register */
392 #define BSTS 0x8000 /* b15: Buffer status */
393 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
394 #define CSCLR 0x2000 /* b13: complete-split status clear */
395 #define CSSTS 0x1000 /* b12: complete-split status */
396 #define ATREPM 0x0400 /* b10: Auto repeat mode */
397 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
398 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
399 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
400 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
401 #define PBUSY 0x0020 /* b5: pipe busy */
402 #define PID 0x0003 /* b1-0: Response PID */
405 #define TRENB 0x0200 /* b9: Transaction counter enable */
406 #define TRCLR 0x0100 /* b8: Transaction counter clear */
409 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
412 #define UPPHUB 0x7800
413 #define HUBPORT 0x0700
414 #define USBSPD 0x00C0
415 #define RTPORT 0x0001
417 #endif /* __LINUX_USB_R8A66597_H */