drivers/spi/spi_mpc83xx.c

   1 /*
   2  * MPC83xx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/completion.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/irq.h>
  21 #include <linux/device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/spi_bitbang.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/fsl_devices.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29
  30 /* SPI Controller registers */
  31 struct mpc83xx_spi_reg {
  32         u8 res1[0x20];
  33         __be32 mode;
  34         __be32 event;
  35         __be32 mask;
  36         __be32 command;
  37         __be32 transmit;
  38         __be32 receive;
  39 };
  40
  41 /* SPI Controller mode register definitions */
  42 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  43 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  44 #define SPMODE_DIV16            (1 << 27)
  45 #define SPMODE_REV              (1 << 26)
  46 #define SPMODE_MS               (1 << 25)
  47 #define SPMODE_ENABLE           (1 << 24)
  48 #define SPMODE_LEN(x)           ((x) << 20)
  49 #define SPMODE_PM(x)            ((x) << 16)
  50 #define SPMODE_OP               (1 << 14)
  51
  52 /*
  53  * Default for SPI Mode:
  54  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  55  */
  56 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  57                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  58
  59 /* SPIE register values */
  60 #define SPIE_NE         0x00000200      /* Not empty */
  61 #define SPIE_NF         0x00000100      /* Not full */
  62
  63 /* SPIM register values */
  64 #define SPIM_NE         0x00000200      /* Not empty */
  65 #define SPIM_NF         0x00000100      /* Not full */
  66
  67 /* SPI Controller driver's private data. */
  68 struct mpc83xx_spi {
  69         /* bitbang has to be first */
  70         struct spi_bitbang bitbang;
  71         struct completion done;
  72
  73         struct mpc83xx_spi_reg __iomem *base;
  74
  75         /* rx & tx bufs from the spi_transfer */
  76         const void *tx;
  77         void *rx;
  78
  79         /* functions to deal with different sized buffers */
  80         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  81         u32(*get_tx) (struct mpc83xx_spi *);
  82
  83         unsigned int count;
  84         u32 irq;
  85
  86         unsigned nsecs;         /* (clock cycle time)/2 */
  87
  88         u32 sysclk;
  89         u32 rx_shift;           /* RX data reg shift when in qe mode */
  90         u32 tx_shift;           /* TX data reg shift when in qe mode */
  91
  92         bool qe_mode;
  93
  94         void (*activate_cs) (u8 cs, u8 polarity);
  95         void (*deactivate_cs) (u8 cs, u8 polarity);
  96 };
  97
  98 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
  99 {
 100         out_be32(reg, val);
 101 }
 102
 103 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
 104 {
 105         return in_be32(reg);
 106 }
 107
 108 #define MPC83XX_SPI_RX_BUF(type)                                          \
 109 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 110 {                                                                         \
 111         type * rx = mpc83xx_spi->rx;                                      \
 112         *rx++ = (type)(data >> mpc83xx_spi->rx_shift);                    \
 113         mpc83xx_spi->rx = rx;                                             \
 114 }
 115
 116 #define MPC83XX_SPI_TX_BUF(type)                                \
 117 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 118 {                                                               \
 119         u32 data;                                               \
 120         const type * tx = mpc83xx_spi->tx;                      \
 121         if (!tx)                                                \
 122                 return 0;                                       \
 123         data = *tx++ << mpc83xx_spi->tx_shift;                  \
 124         mpc83xx_spi->tx = tx;                                   \
 125         return data;                                            \
 126 }
 127
 128 MPC83XX_SPI_RX_BUF(u8)
 129 MPC83XX_SPI_RX_BUF(u16)
 130 MPC83XX_SPI_RX_BUF(u32)
 131 MPC83XX_SPI_TX_BUF(u8)
 132 MPC83XX_SPI_TX_BUF(u16)
 133 MPC83XX_SPI_TX_BUF(u32)
 134
 135 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 136 {
 137         struct mpc83xx_spi *mpc83xx_spi;
 138         u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 139
 140         mpc83xx_spi = spi_master_get_devdata(spi->master);
 141
 142         if (value == BITBANG_CS_INACTIVE) {
 143                 if (mpc83xx_spi->deactivate_cs)
 144                         mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
 145         }
 146
 147         if (value == BITBANG_CS_ACTIVE) {
 148                 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 149                 u32 len = spi->bits_per_word;
 150                 if (len == 32)
 151                         len = 0;
 152                 else
 153                         len = len - 1;
 154
 155                 /* mask out bits we are going to set */
 156                 regval &= ~0x38ff0000;
 157
 158                 if (spi->mode & SPI_CPHA)
 159                         regval |= SPMODE_CP_BEGIN_EDGECLK;
 160                 if (spi->mode & SPI_CPOL)
 161                         regval |= SPMODE_CI_INACTIVEHIGH;
 162
 163                 regval |= SPMODE_LEN(len);
 164
 165                 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
 166                         u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
 167                         if (pm > 0x0f) {
 168                                 printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
 169                                                 "Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
 170                                                 spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
 171                                 pm = 0x0f;
 172                         }
 173                         regval |= SPMODE_PM(pm) | SPMODE_DIV16;
 174                 } else {
 175                         u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
 176                         regval |= SPMODE_PM(pm);
 177                 }
 178
 179                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 180                 if (mpc83xx_spi->activate_cs)
 181                         mpc83xx_spi->activate_cs(spi->chip_select, pol);
 182         }
 183 }
 184
 185 static
 186 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 187 {
 188         struct mpc83xx_spi *mpc83xx_spi;
 189         u32 regval;
 190         u8 bits_per_word;
 191         u32 hz;
 192
 193         mpc83xx_spi = spi_master_get_devdata(spi->master);
 194
 195         if (t) {
 196                 bits_per_word = t->bits_per_word;
 197                 hz = t->speed_hz;
 198         } else {
 199                 bits_per_word = 0;
 200                 hz = 0;
 201         }
 202
 203         /* spi_transfer level calls that work per-word */
 204         if (!bits_per_word)
 205                 bits_per_word = spi->bits_per_word;
 206
 207         /* Make sure its a bit width we support [4..16, 32] */
 208         if ((bits_per_word < 4)
 209             || ((bits_per_word > 16) && (bits_per_word != 32)))
 210                 return -EINVAL;
 211
 212         mpc83xx_spi->rx_shift = 0;
 213         mpc83xx_spi->tx_shift = 0;
 214         if (bits_per_word <= 8) {
 215                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 216                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 217                 if (mpc83xx_spi->qe_mode) {
 218                         mpc83xx_spi->rx_shift = 16;
 219                         mpc83xx_spi->tx_shift = 24;
 220                 }
 221         } else if (bits_per_word <= 16) {
 222                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
 223                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
 224                 if (mpc83xx_spi->qe_mode) {
 225                         mpc83xx_spi->rx_shift = 16;
 226                         mpc83xx_spi->tx_shift = 16;
 227                 }
 228         } else if (bits_per_word <= 32) {
 229                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
 230                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
 231         } else
 232                 return -EINVAL;
 233
 234         /* nsecs = (clock period)/2 */
 235         if (!hz)
 236                 hz = spi->max_speed_hz;
 237         mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
 238         if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
 239                 return -EINVAL;
 240
 241         if (bits_per_word == 32)
 242                 bits_per_word = 0;
 243         else
 244                 bits_per_word = bits_per_word - 1;
 245
 246         regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 247
 248         /* Mask out bits_per_wordgth */
 249         regval &= 0xff0fffff;
 250         regval |= SPMODE_LEN(bits_per_word);
 251
 252         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 253
 254         return 0;
 255 }
 256
 257 /* the spi->mode bits understood by this driver: */
 258 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 259
 260 static int mpc83xx_spi_setup(struct spi_device *spi)
 261 {
 262         struct spi_bitbang *bitbang;
 263         struct mpc83xx_spi *mpc83xx_spi;
 264         int retval;
 265
 266         if (spi->mode & ~MODEBITS) {
 267                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 268                         spi->mode & ~MODEBITS);
 269                 return -EINVAL;
 270         }
 271
 272         if (!spi->max_speed_hz)
 273                 return -EINVAL;
 274
 275         bitbang = spi_master_get_devdata(spi->master);
 276         mpc83xx_spi = spi_master_get_devdata(spi->master);
 277
 278         if (!spi->bits_per_word)
 279                 spi->bits_per_word = 8;
 280
 281         retval = mpc83xx_spi_setup_transfer(spi, NULL);
 282         if (retval < 0)
 283                 return retval;
 284
 285         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
 286                 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
 287                 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
 288
 289         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 290          * setup, unless the hardware defaults cooperate to avoid confusion
 291          * between normal (active low) and inverted chipselects.
 292          */
 293
 294         /* deselect chip (low or high) */
 295         spin_lock(&bitbang->lock);
 296         if (!bitbang->busy) {
 297                 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 298                 ndelay(mpc83xx_spi->nsecs);
 299         }
 300         spin_unlock(&bitbang->lock);
 301
 302         return 0;
 303 }
 304
 305 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 306 {
 307         struct mpc83xx_spi *mpc83xx_spi;
 308         u32 word;
 309
 310         mpc83xx_spi = spi_master_get_devdata(spi->master);
 311
 312         mpc83xx_spi->tx = t->tx_buf;
 313         mpc83xx_spi->rx = t->rx_buf;
 314         mpc83xx_spi->count = t->len;
 315         INIT_COMPLETION(mpc83xx_spi->done);
 316
 317         /* enable rx ints */
 318         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 319
 320         /* transmit word */
 321         word = mpc83xx_spi->get_tx(mpc83xx_spi);
 322         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 323
 324         wait_for_completion(&mpc83xx_spi->done);
 325
 326         /* disable rx ints */
 327         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 328
 329         return t->len - mpc83xx_spi->count;
 330 }
 331
 332 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 333 {
 334         struct mpc83xx_spi *mpc83xx_spi = context_data;
 335         u32 event;
 336         irqreturn_t ret = IRQ_NONE;
 337
 338         /* Get interrupt events(tx/rx) */
 339         event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 340
 341         /* We need handle RX first */
 342         if (event & SPIE_NE) {
 343                 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 344
 345                 if (mpc83xx_spi->rx)
 346                         mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 347
 348                 ret = IRQ_HANDLED;
 349         }
 350
 351         if ((event & SPIE_NF) == 0)
 352                 /* spin until TX is done */
 353                 while (((event =
 354                          mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 355                                                 SPIE_NF) == 0)
 356                          cpu_relax();
 357
 358         mpc83xx_spi->count -= 1;
 359         if (mpc83xx_spi->count) {
 360                 if (mpc83xx_spi->tx) {
 361                         u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 362                         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
 363                                               word);
 364                 }
 365         } else {
 366                 complete(&mpc83xx_spi->done);
 367         }
 368
 369         /* Clear the events */
 370         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 371
 372         return ret;
 373 }
 374
 375 static int __init mpc83xx_spi_probe(struct platform_device *dev)
 376 {
 377         struct spi_master *master;
 378         struct mpc83xx_spi *mpc83xx_spi;
 379         struct fsl_spi_platform_data *pdata;
 380         struct resource *r;
 381         u32 regval;
 382         int ret = 0;
 383
 384         /* Get resources(memory, IRQ) associated with the device */
 385         master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
 386
 387         if (master == NULL) {
 388                 ret = -ENOMEM;
 389                 goto err;
 390         }
 391
 392         platform_set_drvdata(dev, master);
 393         pdata = dev->dev.platform_data;
 394
 395         if (pdata == NULL) {
 396                 ret = -ENODEV;
 397                 goto free_master;
 398         }
 399
 400         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 401         if (r == NULL) {
 402                 ret = -ENODEV;
 403                 goto free_master;
 404         }
 405         mpc83xx_spi = spi_master_get_devdata(master);
 406         mpc83xx_spi->bitbang.master = spi_master_get(master);
 407         mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
 408         mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
 409         mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
 410         mpc83xx_spi->sysclk = pdata->sysclk;
 411         mpc83xx_spi->activate_cs = pdata->activate_cs;
 412         mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
 413         mpc83xx_spi->qe_mode = pdata->qe_mode;
 414         mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 415         mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 416
 417         mpc83xx_spi->rx_shift = 0;
 418         mpc83xx_spi->tx_shift = 0;
 419         if (mpc83xx_spi->qe_mode) {
 420                 mpc83xx_spi->rx_shift = 16;
 421                 mpc83xx_spi->tx_shift = 24;
 422         }
 423
 424         mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
 425         init_completion(&mpc83xx_spi->done);
 426
 427         mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
 428         if (mpc83xx_spi->base == NULL) {
 429                 ret = -ENOMEM;
 430                 goto put_master;
 431         }
 432
 433         mpc83xx_spi->irq = platform_get_irq(dev, 0);
 434
 435         if (mpc83xx_spi->irq < 0) {
 436                 ret = -ENXIO;
 437                 goto unmap_io;
 438         }
 439
 440         /* Register for SPI Interrupt */
 441         ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 442                           0, "mpc83xx_spi", mpc83xx_spi);
 443
 444         if (ret != 0)
 445                 goto unmap_io;
 446
 447         master->bus_num = pdata->bus_num;
 448         master->num_chipselect = pdata->max_chipselect;
 449
 450         /* SPI controller initializations */
 451         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 452         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 453         mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 454         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 455
 456         /* Enable SPI interface */
 457         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 458         if (pdata->qe_mode)
 459                 regval |= SPMODE_OP;
 460
 461         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 462
 463         ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
 464
 465         if (ret != 0)
 466                 goto free_irq;
 467
 468         printk(KERN_INFO
 469                "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 470                dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
 471
 472         return ret;
 473
 474 free_irq:
 475         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 476 unmap_io:
 477         iounmap(mpc83xx_spi->base);
 478 put_master:
 479         spi_master_put(master);
 480 free_master:
 481         kfree(master);
 482 err:
 483         return ret;
 484 }
 485
 486 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
 487 {
 488         struct mpc83xx_spi *mpc83xx_spi;
 489         struct spi_master *master;
 490
 491         master = platform_get_drvdata(dev);
 492         mpc83xx_spi = spi_master_get_devdata(master);
 493
 494         spi_bitbang_stop(&mpc83xx_spi->bitbang);
 495         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 496         iounmap(mpc83xx_spi->base);
 497         spi_master_put(mpc83xx_spi->bitbang.master);
 498
 499         return 0;
 500 }
 501
 502 static struct platform_driver mpc83xx_spi_driver = {
 503         .probe = mpc83xx_spi_probe,
 504         .remove = __devexit_p(mpc83xx_spi_remove),
 505         .driver = {
 506                    .name = "mpc83xx_spi",
 507         },
 508 };
 509
 510 static int __init mpc83xx_spi_init(void)
 511 {
 512         return platform_driver_register(&mpc83xx_spi_driver);
 513 }
 514
 515 static void __exit mpc83xx_spi_exit(void)
 516 {
 517         platform_driver_unregister(&mpc83xx_spi_driver);
 518 }
 519
 520 module_init(mpc83xx_spi_init);
 521 module_exit(mpc83xx_spi_exit);
 522
 523 MODULE_AUTHOR("Kumar Gala");
 524 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 525 MODULE_LICENSE("GPL");