arch/sparc64/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/pci.h>
  18 #include <linux/msi.h>
  19 #include <linux/irq.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/uaccess.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/irq.h>
  25 #include <asm/ebus.h>
  26 #include <asm/isa.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31
  32 unsigned long pci_memspace_mask = 0xffffffffUL;
  33
  34 #ifndef CONFIG_PCI
  35 /* A "nop" PCI implementation. */
  36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  37                                   unsigned long off, unsigned long len,
  38                                   unsigned char *buf)
  39 {
  40         return 0;
  41 }
  42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  43                                    unsigned long off, unsigned long len,
  44                                    unsigned char *buf)
  45 {
  46         return 0;
  47 }
  48 #else
  49
  50 /* List of all PCI controllers found in the system. */
  51 struct pci_pbm_info *pci_pbm_root = NULL;
  52
  53 /* Each PBM found gets a unique index. */
  54 int pci_num_pbms = 0;
  55
  56 volatile int pci_poke_in_progress;
  57 volatile int pci_poke_cpu = -1;
  58 volatile int pci_poke_faulted;
  59
  60 static DEFINE_SPINLOCK(pci_poke_lock);
  61
  62 void pci_config_read8(u8 *addr, u8 *ret)
  63 {
  64         unsigned long flags;
  65         u8 byte;
  66
  67         spin_lock_irqsave(&pci_poke_lock, flags);
  68         pci_poke_cpu = smp_processor_id();
  69         pci_poke_in_progress = 1;
  70         pci_poke_faulted = 0;
  71         __asm__ __volatile__("membar #Sync\n\t"
  72                              "lduba [%1] %2, %0\n\t"
  73                              "membar #Sync"
  74                              : "=r" (byte)
  75                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  76                              : "memory");
  77         pci_poke_in_progress = 0;
  78         pci_poke_cpu = -1;
  79         if (!pci_poke_faulted)
  80                 *ret = byte;
  81         spin_unlock_irqrestore(&pci_poke_lock, flags);
  82 }
  83
  84 void pci_config_read16(u16 *addr, u16 *ret)
  85 {
  86         unsigned long flags;
  87         u16 word;
  88
  89         spin_lock_irqsave(&pci_poke_lock, flags);
  90         pci_poke_cpu = smp_processor_id();
  91         pci_poke_in_progress = 1;
  92         pci_poke_faulted = 0;
  93         __asm__ __volatile__("membar #Sync\n\t"
  94                              "lduha [%1] %2, %0\n\t"
  95                              "membar #Sync"
  96                              : "=r" (word)
  97                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  98                              : "memory");
  99         pci_poke_in_progress = 0;
 100         pci_poke_cpu = -1;
 101         if (!pci_poke_faulted)
 102                 *ret = word;
 103         spin_unlock_irqrestore(&pci_poke_lock, flags);
 104 }
 105
 106 void pci_config_read32(u32 *addr, u32 *ret)
 107 {
 108         unsigned long flags;
 109         u32 dword;
 110
 111         spin_lock_irqsave(&pci_poke_lock, flags);
 112         pci_poke_cpu = smp_processor_id();
 113         pci_poke_in_progress = 1;
 114         pci_poke_faulted = 0;
 115         __asm__ __volatile__("membar #Sync\n\t"
 116                              "lduwa [%1] %2, %0\n\t"
 117                              "membar #Sync"
 118                              : "=r" (dword)
 119                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 120                              : "memory");
 121         pci_poke_in_progress = 0;
 122         pci_poke_cpu = -1;
 123         if (!pci_poke_faulted)
 124                 *ret = dword;
 125         spin_unlock_irqrestore(&pci_poke_lock, flags);
 126 }
 127
 128 void pci_config_write8(u8 *addr, u8 val)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&pci_poke_lock, flags);
 133         pci_poke_cpu = smp_processor_id();
 134         pci_poke_in_progress = 1;
 135         pci_poke_faulted = 0;
 136         __asm__ __volatile__("membar #Sync\n\t"
 137                              "stba %0, [%1] %2\n\t"
 138                              "membar #Sync"
 139                              : /* no outputs */
 140                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 141                              : "memory");
 142         pci_poke_in_progress = 0;
 143         pci_poke_cpu = -1;
 144         spin_unlock_irqrestore(&pci_poke_lock, flags);
 145 }
 146
 147 void pci_config_write16(u16 *addr, u16 val)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&pci_poke_lock, flags);
 152         pci_poke_cpu = smp_processor_id();
 153         pci_poke_in_progress = 1;
 154         pci_poke_faulted = 0;
 155         __asm__ __volatile__("membar #Sync\n\t"
 156                              "stha %0, [%1] %2\n\t"
 157                              "membar #Sync"
 158                              : /* no outputs */
 159                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 160                              : "memory");
 161         pci_poke_in_progress = 0;
 162         pci_poke_cpu = -1;
 163         spin_unlock_irqrestore(&pci_poke_lock, flags);
 164 }
 165
 166 void pci_config_write32(u32 *addr, u32 val)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&pci_poke_lock, flags);
 171         pci_poke_cpu = smp_processor_id();
 172         pci_poke_in_progress = 1;
 173         pci_poke_faulted = 0;
 174         __asm__ __volatile__("membar #Sync\n\t"
 175                              "stwa %0, [%1] %2\n\t"
 176                              "membar #Sync"
 177                              : /* no outputs */
 178                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 179                              : "memory");
 180         pci_poke_in_progress = 0;
 181         pci_poke_cpu = -1;
 182         spin_unlock_irqrestore(&pci_poke_lock, flags);
 183 }
 184
 185 /* Probe for all PCI controllers in the system. */
 186 extern void sabre_init(struct device_node *, const char *);
 187 extern void psycho_init(struct device_node *, const char *);
 188 extern void schizo_init(struct device_node *, const char *);
 189 extern void schizo_plus_init(struct device_node *, const char *);
 190 extern void tomatillo_init(struct device_node *, const char *);
 191 extern void sun4v_pci_init(struct device_node *, const char *);
 192 extern void fire_pci_init(struct device_node *, const char *);
 193
 194 static struct {
 195         char *model_name;
 196         void (*init)(struct device_node *, const char *);
 197 } pci_controller_table[] __initdata = {
 198         { "SUNW,sabre", sabre_init },
 199         { "pci108e,a000", sabre_init },
 200         { "pci108e,a001", sabre_init },
 201         { "SUNW,psycho", psycho_init },
 202         { "pci108e,8000", psycho_init },
 203         { "SUNW,schizo", schizo_init },
 204         { "pci108e,8001", schizo_init },
 205         { "SUNW,schizo+", schizo_plus_init },
 206         { "pci108e,8002", schizo_plus_init },
 207         { "SUNW,tomatillo", tomatillo_init },
 208         { "pci108e,a801", tomatillo_init },
 209         { "SUNW,sun4v-pci", sun4v_pci_init },
 210         { "pciex108e,80f0", fire_pci_init },
 211 };
 212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 213                                   sizeof(pci_controller_table[0]))
 214
 215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
 216 {
 217         int i;
 218
 219         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 220                 if (!strncmp(model_name,
 221                              pci_controller_table[i].model_name,
 222                              namelen)) {
 223                         pci_controller_table[i].init(dp, model_name);
 224                         return 1;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
 232 {
 233         int i;
 234
 235         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 236                 if (!strncmp(model_name,
 237                              pci_controller_table[i].model_name,
 238                              namelen)) {
 239                         return 1;
 240                 }
 241         }
 242         return 0;
 243 }
 244
 245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
 246 {
 247         struct device_node *dp;
 248         int count = 0;
 249
 250         for_each_node_by_name(dp, "pci") {
 251                 struct property *prop;
 252                 int len;
 253
 254                 prop = of_find_property(dp, "model", &len);
 255                 if (!prop)
 256                         prop = of_find_property(dp, "compatible", &len);
 257
 258                 if (prop) {
 259                         const char *model = prop->value;
 260                         int item_len = 0;
 261
 262                         /* Our value may be a multi-valued string in the
 263                          * case of some compatible properties. For sanity,
 264                          * only try the first one.
 265                          */
 266                         while (model[item_len] && len) {
 267                                 len--;
 268                                 item_len++;
 269                         }
 270
 271                         if (handler(model, item_len, dp))
 272                                 count++;
 273                 }
 274         }
 275
 276         return count;
 277 }
 278
 279
 280 /* Is there some PCI controller in the system?  */
 281 int __init pcic_present(void)
 282 {
 283         return pci_controller_scan(pci_is_controller);
 284 }
 285
 286 const struct pci_iommu_ops *pci_iommu_ops;
 287 EXPORT_SYMBOL(pci_iommu_ops);
 288
 289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
 290         pci_sun4v_iommu_ops;
 291
 292 /* Find each controller in the system, attach and initialize
 293  * software state structure for each and link into the
 294  * pci_pbm_root.  Setup the controller enough such
 295  * that bus scanning can be done.
 296  */
 297 static void __init pci_controller_probe(void)
 298 {
 299         if (tlb_type == hypervisor)
 300                 pci_iommu_ops = &pci_sun4v_iommu_ops;
 301         else
 302                 pci_iommu_ops = &pci_sun4u_iommu_ops;
 303
 304         printk("PCI: Probing for controllers.\n");
 305
 306         pci_controller_scan(pci_controller_init);
 307 }
 308
 309 static int ofpci_verbose;
 310
 311 static int __init ofpci_debug(char *str)
 312 {
 313         int val = 0;
 314
 315         get_option(&str, &val);
 316         if (val)
 317                 ofpci_verbose = 1;
 318         return 1;
 319 }
 320
 321 __setup("ofpci_debug=", ofpci_debug);
 322
 323 static unsigned long pci_parse_of_flags(u32 addr0)
 324 {
 325         unsigned long flags = 0;
 326
 327         if (addr0 & 0x02000000) {
 328                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 329                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
 330                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 331                 if (addr0 & 0x40000000)
 332                         flags |= IORESOURCE_PREFETCH
 333                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 334         } else if (addr0 & 0x01000000)
 335                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 336         return flags;
 337 }
 338
 339 /* The of_device layer has translated all of the assigned-address properties
 340  * into physical address resources, we only have to figure out the register
 341  * mapping.
 342  */
 343 static void pci_parse_of_addrs(struct of_device *op,
 344                                struct device_node *node,
 345                                struct pci_dev *dev)
 346 {
 347         struct resource *op_res;
 348         const u32 *addrs;
 349         int proplen;
 350
 351         addrs = of_get_property(node, "assigned-addresses", &proplen);
 352         if (!addrs)
 353                 return;
 354         if (ofpci_verbose)
 355                 printk("    parse addresses (%d bytes) @ %p\n",
 356                        proplen, addrs);
 357         op_res = &op->resource[0];
 358         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 359                 struct resource *res;
 360                 unsigned long flags;
 361                 int i;
 362
 363                 flags = pci_parse_of_flags(addrs[0]);
 364                 if (!flags)
 365                         continue;
 366                 i = addrs[0] & 0xff;
 367                 if (ofpci_verbose)
 368                         printk("  start: %lx, end: %lx, i: %x\n",
 369                                op_res->start, op_res->end, i);
 370
 371                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 372                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 373                 } else if (i == dev->rom_base_reg) {
 374                         res = &dev->resource[PCI_ROM_RESOURCE];
 375                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 376                 } else {
 377                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 378                         continue;
 379                 }
 380                 res->start = op_res->start;
 381                 res->end = op_res->end;
 382                 res->flags = flags;
 383                 res->name = pci_name(dev);
 384         }
 385 }
 386
 387 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 388                                   struct device_node *node,
 389                                   struct pci_bus *bus, int devfn,
 390                                   int host_controller)
 391 {
 392         struct dev_archdata *sd;
 393         struct pci_dev *dev;
 394         const char *type;
 395         u32 class;
 396
 397         dev = alloc_pci_dev();
 398         if (!dev)
 399                 return NULL;
 400
 401         sd = &dev->dev.archdata;
 402         sd->iommu = pbm->iommu;
 403         sd->stc = &pbm->stc;
 404         sd->host_controller = pbm;
 405         sd->prom_node = node;
 406         sd->op = of_find_device_by_node(node);
 407         sd->msi_num = 0xffffffff;
 408
 409         type = of_get_property(node, "device_type", NULL);
 410         if (type == NULL)
 411                 type = "";
 412
 413         if (ofpci_verbose)
 414                 printk("    create device, devfn: %x, type: %s\n",
 415                        devfn, type);
 416
 417         dev->bus = bus;
 418         dev->sysdata = node;
 419         dev->dev.parent = bus->bridge;
 420         dev->dev.bus = &pci_bus_type;
 421         dev->devfn = devfn;
 422         dev->multifunction = 0;         /* maybe a lie? */
 423
 424         if (host_controller) {
 425                 if (tlb_type != hypervisor) {
 426                         pci_read_config_word(dev, PCI_VENDOR_ID,
 427                                              &dev->vendor);
 428                         pci_read_config_word(dev, PCI_DEVICE_ID,
 429                                              &dev->device);
 430                 } else {
 431                         dev->vendor = PCI_VENDOR_ID_SUN;
 432                         dev->device = 0x80f0;
 433                 }
 434                 dev->cfg_size = 256;
 435                 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
 436                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 437                         0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
 438         } else {
 439                 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 440                 dev->device = of_getintprop_default(node, "device-id", 0xffff);
 441                 dev->subsystem_vendor =
 442                         of_getintprop_default(node, "subsystem-vendor-id", 0);
 443                 dev->subsystem_device =
 444                         of_getintprop_default(node, "subsystem-id", 0);
 445
 446                 dev->cfg_size = pci_cfg_space_size(dev);
 447
 448                 /* We can't actually use the firmware value, we have
 449                  * to read what is in the register right now.  One
 450                  * reason is that in the case of IDE interfaces the
 451                  * firmware can sample the value before the the IDE
 452                  * interface is programmed into native mode.
 453                  */
 454                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 455                 dev->class = class >> 8;
 456
 457                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 458                         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 459         }
 460         if (ofpci_verbose)
 461                 printk("    class: 0x%x device name: %s\n",
 462                        dev->class, pci_name(dev));
 463
 464         /* I have seen IDE devices which will not respond to
 465          * the bmdma simplex check reads if bus mastering is
 466          * disabled.
 467          */
 468         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 469                 pci_set_master(dev);
 470
 471         dev->current_state = 4;         /* unknown power state */
 472         dev->error_state = pci_channel_io_normal;
 473
 474         if (host_controller) {
 475                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 476                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 477                 dev->irq = PCI_IRQ_NONE;
 478         } else {
 479                 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 480                         /* a PCI-PCI bridge */
 481                         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 482                         dev->rom_base_reg = PCI_ROM_ADDRESS1;
 483                 } else if (!strcmp(type, "cardbus")) {
 484                         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 485                 } else {
 486                         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 487                         dev->rom_base_reg = PCI_ROM_ADDRESS;
 488
 489                         dev->irq = sd->op->irqs[0];
 490                         if (dev->irq == 0xffffffff)
 491                                 dev->irq = PCI_IRQ_NONE;
 492                 }
 493         }
 494         pci_parse_of_addrs(sd->op, node, dev);
 495
 496         if (ofpci_verbose)
 497                 printk("    adding to system ...\n");
 498
 499         pci_device_add(dev, bus);
 500
 501         return dev;
 502 }
 503
 504 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 505 {
 506         u32 idx, first, last;
 507
 508         first = 8;
 509         last = 0;
 510         for (idx = 0; idx < 8; idx++) {
 511                 if ((map & (1 << idx)) != 0) {
 512                         if (first > idx)
 513                                 first = idx;
 514                         if (last < idx)
 515                                 last = idx;
 516                 }
 517         }
 518
 519         *first_p = first;
 520         *last_p = last;
 521 }
 522
 523 static void pci_resource_adjust(struct resource *res,
 524                                 struct resource *root)
 525 {
 526         res->start += root->start;
 527         res->end += root->start;
 528 }
 529
 530 /* For PCI bus devices which lack a 'ranges' property we interrogate
 531  * the config space values to set the resources, just like the generic
 532  * Linux PCI probing code does.
 533  */
 534 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
 535                                           struct pci_bus *bus,
 536                                           struct pci_pbm_info *pbm)
 537 {
 538         struct resource *res;
 539         u8 io_base_lo, io_limit_lo;
 540         u16 mem_base_lo, mem_limit_lo;
 541         unsigned long base, limit;
 542
 543         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 544         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 545         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 546         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 547
 548         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 549                 u16 io_base_hi, io_limit_hi;
 550
 551                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 552                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 553                 base |= (io_base_hi << 16);
 554                 limit |= (io_limit_hi << 16);
 555         }
 556
 557         res = bus->resource[0];
 558         if (base <= limit) {
 559                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 560                 if (!res->start)
 561                         res->start = base;
 562                 if (!res->end)
 563                         res->end = limit + 0xfff;
 564                 pci_resource_adjust(res, &pbm->io_space);
 565         }
 566
 567         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 568         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 569         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 570         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 571
 572         res = bus->resource[1];
 573         if (base <= limit) {
 574                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 575                               IORESOURCE_MEM);
 576                 res->start = base;
 577                 res->end = limit + 0xfffff;
 578                 pci_resource_adjust(res, &pbm->mem_space);
 579         }
 580
 581         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 582         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 583         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 584         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 585
 586         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 587                 u32 mem_base_hi, mem_limit_hi;
 588
 589                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 590                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 591
 592                 /*
 593                  * Some bridges set the base > limit by default, and some
 594                  * (broken) BIOSes do not initialize them.  If we find
 595                  * this, just assume they are not being used.
 596                  */
 597                 if (mem_base_hi <= mem_limit_hi) {
 598                         base |= ((long) mem_base_hi) << 32;
 599                         limit |= ((long) mem_limit_hi) << 32;
 600                 }
 601         }
 602
 603         res = bus->resource[2];
 604         if (base <= limit) {
 605                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 606                               IORESOURCE_MEM | IORESOURCE_PREFETCH);
 607                 res->start = base;
 608                 res->end = limit + 0xfffff;
 609                 pci_resource_adjust(res, &pbm->mem_space);
 610         }
 611 }
 612
 613 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 614  * a proper 'ranges' property.
 615  */
 616 static void __devinit apb_fake_ranges(struct pci_dev *dev,
 617                                       struct pci_bus *bus,
 618                                       struct pci_pbm_info *pbm)
 619 {
 620         struct resource *res;
 621         u32 first, last;
 622         u8 map;
 623
 624         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 625         apb_calc_first_last(map, &first, &last);
 626         res = bus->resource[0];
 627         res->start = (first << 21);
 628         res->end = (last << 21) + ((1 << 21) - 1);
 629         res->flags = IORESOURCE_IO;
 630         pci_resource_adjust(res, &pbm->io_space);
 631
 632         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 633         apb_calc_first_last(map, &first, &last);
 634         res = bus->resource[1];
 635         res->start = (first << 21);
 636         res->end = (last << 21) + ((1 << 21) - 1);
 637         res->flags = IORESOURCE_MEM;
 638         pci_resource_adjust(res, &pbm->mem_space);
 639 }
 640
 641 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 642                                       struct device_node *node,
 643                                       struct pci_bus *bus);
 644
 645 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 646
 647 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
 648                                          struct device_node *node,
 649                                          struct pci_dev *dev)
 650 {
 651         struct pci_bus *bus;
 652         const u32 *busrange, *ranges;
 653         int len, i, simba;
 654         struct resource *res;
 655         unsigned int flags;
 656         u64 size;
 657
 658         if (ofpci_verbose)
 659                 printk("of_scan_pci_bridge(%s)\n", node->full_name);
 660
 661         /* parse bus-range property */
 662         busrange = of_get_property(node, "bus-range", &len);
 663         if (busrange == NULL || len != 8) {
 664                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 665                        node->full_name);
 666                 return;
 667         }
 668         ranges = of_get_property(node, "ranges", &len);
 669         simba = 0;
 670         if (ranges == NULL) {
 671                 const char *model = of_get_property(node, "model", NULL);
 672                 if (model && !strcmp(model, "SUNW,simba"))
 673                         simba = 1;
 674         }
 675
 676         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 677         if (!bus) {
 678                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 679                        node->full_name);
 680                 return;
 681         }
 682
 683         bus->primary = dev->bus->number;
 684         bus->subordinate = busrange[1];
 685         bus->bridge_ctl = 0;
 686
 687         /* parse ranges property, or cook one up by hand for Simba */
 688         /* PCI #address-cells == 3 and #size-cells == 2 always */
 689         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 690         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 691                 res->flags = 0;
 692                 bus->resource[i] = res;
 693                 ++res;
 694         }
 695         if (simba) {
 696                 apb_fake_ranges(dev, bus, pbm);
 697                 goto after_ranges;
 698         } else if (ranges == NULL) {
 699                 pci_cfg_fake_ranges(dev, bus, pbm);
 700                 goto after_ranges;
 701         }
 702         i = 1;
 703         for (; len >= 32; len -= 32, ranges += 8) {
 704                 struct resource *root;
 705
 706                 flags = pci_parse_of_flags(ranges[0]);
 707                 size = GET_64BIT(ranges, 6);
 708                 if (flags == 0 || size == 0)
 709                         continue;
 710                 if (flags & IORESOURCE_IO) {
 711                         res = bus->resource[0];
 712                         if (res->flags) {
 713                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 714                                        " for bridge %s\n", node->full_name);
 715                                 continue;
 716                         }
 717                         root = &pbm->io_space;
 718                 } else {
 719                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 720                                 printk(KERN_ERR "PCI: too many memory ranges"
 721                                        " for bridge %s\n", node->full_name);
 722                                 continue;
 723                         }
 724                         res = bus->resource[i];
 725                         ++i;
 726                         root = &pbm->mem_space;
 727                 }
 728
 729                 res->start = GET_64BIT(ranges, 1);
 730                 res->end = res->start + size - 1;
 731                 res->flags = flags;
 732
 733                 /* Another way to implement this would be to add an of_device
 734                  * layer routine that can calculate a resource for a given
 735                  * range property value in a PCI device.
 736                  */
 737                 pci_resource_adjust(res, root);
 738         }
 739 after_ranges:
 740         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 741                 bus->number);
 742         if (ofpci_verbose)
 743                 printk("    bus name: %s\n", bus->name);
 744
 745         pci_of_scan_bus(pbm, node, bus);
 746 }
 747
 748 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 749                                       struct device_node *node,
 750                                       struct pci_bus *bus)
 751 {
 752         struct device_node *child;
 753         const u32 *reg;
 754         int reglen, devfn, prev_devfn;
 755         struct pci_dev *dev;
 756
 757         if (ofpci_verbose)
 758                 printk("PCI: scan_bus[%s] bus no %d\n",
 759                        node->full_name, bus->number);
 760
 761         child = NULL;
 762         prev_devfn = -1;
 763         while ((child = of_get_next_child(node, child)) != NULL) {
 764                 if (ofpci_verbose)
 765                         printk("  * %s\n", child->full_name);
 766                 reg = of_get_property(child, "reg", &reglen);
 767                 if (reg == NULL || reglen < 20)
 768                         continue;
 769
 770                 devfn = (reg[0] >> 8) & 0xff;
 771
 772                 /* This is a workaround for some device trees
 773                  * which list PCI devices twice.  On the V100
 774                  * for example, device number 3 is listed twice.
 775                  * Once as "pm" and once again as "lomp".
 776                  */
 777                 if (devfn == prev_devfn)
 778                         continue;
 779                 prev_devfn = devfn;
 780
 781                 /* create a new pci_dev for this device */
 782                 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
 783                 if (!dev)
 784                         continue;
 785                 if (ofpci_verbose)
 786                         printk("PCI: dev header type: %x\n",
 787                                dev->hdr_type);
 788
 789                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 790                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 791                         of_scan_pci_bridge(pbm, child, dev);
 792         }
 793 }
 794
 795 static ssize_t
 796 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 797 {
 798         struct pci_dev *pdev;
 799         struct device_node *dp;
 800
 801         pdev = to_pci_dev(dev);
 802         dp = pdev->dev.archdata.prom_node;
 803
 804         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 805 }
 806
 807 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 808
 809 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
 810 {
 811         struct pci_dev *dev;
 812         struct pci_bus *child_bus;
 813         int err;
 814
 815         list_for_each_entry(dev, &bus->devices, bus_list) {
 816                 /* we don't really care if we can create this file or
 817                  * not, but we need to assign the result of the call
 818                  * or the world will fall under alien invasion and
 819                  * everybody will be frozen on a spaceship ready to be
 820                  * eaten on alpha centauri by some green and jelly
 821                  * humanoid.
 822                  */
 823                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 824         }
 825         list_for_each_entry(child_bus, &bus->children, node)
 826                 pci_bus_register_of_sysfs(child_bus);
 827 }
 828
 829 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
 830                                  unsigned int devfn,
 831                                  int where, int size,
 832                                  u32 *value)
 833 {
 834         static u8 fake_pci_config[] = {
 835                 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
 836                 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
 837                 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
 838                 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
 839                 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
 840                 0x00, /* Cacheline: 0x00 */
 841                 0x40, /* Latency: 0x40 */
 842                 0x00, /* Header-Type: 0x00 normal */
 843         };
 844
 845         *value = 0;
 846         if (where >= 0 && where < sizeof(fake_pci_config) &&
 847             (where + size) >= 0 &&
 848             (where + size) < sizeof(fake_pci_config) &&
 849             size <= sizeof(u32)) {
 850                 while (size--) {
 851                         *value <<= 8;
 852                         *value |= fake_pci_config[where + size];
 853                 }
 854         }
 855
 856         return PCIBIOS_SUCCESSFUL;
 857 }
 858
 859 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
 860                                   unsigned int devfn,
 861                                   int where, int size,
 862                                   u32 value)
 863 {
 864         return PCIBIOS_SUCCESSFUL;
 865 }
 866
 867 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
 868 {
 869         struct device_node *node = pbm->prom_node;
 870         struct pci_dev *host_pdev;
 871         struct pci_bus *bus;
 872
 873         printk("PCI: Scanning PBM %s\n", node->full_name);
 874
 875         /* XXX parent device? XXX */
 876         bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
 877         if (!bus) {
 878                 printk(KERN_ERR "Failed to create bus for %s\n",
 879                        node->full_name);
 880                 return NULL;
 881         }
 882         bus->secondary = pbm->pci_first_busno;
 883         bus->subordinate = pbm->pci_last_busno;
 884
 885         bus->resource[0] = &pbm->io_space;
 886         bus->resource[1] = &pbm->mem_space;
 887
 888         /* Create the dummy host bridge and link it in.  */
 889         host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
 890         bus->self = host_pdev;
 891
 892         pci_of_scan_bus(pbm, node, bus);
 893         pci_bus_add_devices(bus);
 894         pci_bus_register_of_sysfs(bus);
 895
 896         return bus;
 897 }
 898
 899 static void __init pci_scan_each_controller_bus(void)
 900 {
 901         struct pci_pbm_info *pbm;
 902
 903         for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
 904                 pbm->scan_bus(pbm);
 905 }
 906
 907 extern void power_init(void);
 908
 909 static int __init pcibios_init(void)
 910 {
 911         pci_controller_probe();
 912         if (pci_pbm_root == NULL)
 913                 return 0;
 914
 915         pci_scan_each_controller_bus();
 916
 917         isa_init();
 918         ebus_init();
 919         power_init();
 920
 921         return 0;
 922 }
 923
 924 subsys_initcall(pcibios_init);
 925
 926 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 927 {
 928         struct pci_pbm_info *pbm = pbus->sysdata;
 929
 930         /* Generic PCI bus probing sets these to point at
 931          * &io{port,mem}_resouce which is wrong for us.
 932          */
 933         pbus->resource[0] = &pbm->io_space;
 934         pbus->resource[1] = &pbm->mem_space;
 935 }
 936
 937 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 938 {
 939         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 940         struct resource *root = NULL;
 941
 942         if (r->flags & IORESOURCE_IO)
 943                 root = &pbm->io_space;
 944         if (r->flags & IORESOURCE_MEM)
 945                 root = &pbm->mem_space;
 946
 947         return root;
 948 }
 949
 950 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 951 {
 952 }
 953
 954 void pcibios_align_resource(void *data, struct resource *res,
 955                             resource_size_t size, resource_size_t align)
 956 {
 957 }
 958
 959 int pcibios_enable_device(struct pci_dev *dev, int mask)
 960 {
 961         u16 cmd, oldcmd;
 962         int i;
 963
 964         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 965         oldcmd = cmd;
 966
 967         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 968                 struct resource *res = &dev->resource[i];
 969
 970                 /* Only set up the requested stuff */
 971                 if (!(mask & (1<<i)))
 972                         continue;
 973
 974                 if (res->flags & IORESOURCE_IO)
 975                         cmd |= PCI_COMMAND_IO;
 976                 if (res->flags & IORESOURCE_MEM)
 977                         cmd |= PCI_COMMAND_MEMORY;
 978         }
 979
 980         if (cmd != oldcmd) {
 981                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 982                        pci_name(dev), cmd);
 983                 /* Enable the appropriate bits in the PCI command register.  */
 984                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 985         }
 986         return 0;
 987 }
 988
 989 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 990                              struct resource *res)
 991 {
 992         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 993         struct resource zero_res, *root;
 994
 995         zero_res.start = 0;
 996         zero_res.end = 0;
 997         zero_res.flags = res->flags;
 998
 999         if (res->flags & IORESOURCE_IO)
1000                 root = &pbm->io_space;
1001         else
1002                 root = &pbm->mem_space;
1003
1004         pci_resource_adjust(&zero_res, root);
1005
1006         region->start = res->start - zero_res.start;
1007         region->end = res->end - zero_res.start;
1008 }
1009 EXPORT_SYMBOL(pcibios_resource_to_bus);
1010
1011 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
1012                              struct pci_bus_region *region)
1013 {
1014         struct pci_pbm_info *pbm = pdev->bus->sysdata;
1015         struct resource *root;
1016
1017         res->start = region->start;
1018         res->end = region->end;
1019
1020         if (res->flags & IORESOURCE_IO)
1021                 root = &pbm->io_space;
1022         else
1023                 root = &pbm->mem_space;
1024
1025         pci_resource_adjust(res, root);
1026 }
1027 EXPORT_SYMBOL(pcibios_bus_to_resource);
1028
1029 char * __devinit pcibios_setup(char *str)
1030 {
1031         return str;
1032 }
1033
1034 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1035
1036 /* If the user uses a host-bridge as the PCI device, he may use
1037  * this to perform a raw mmap() of the I/O or MEM space behind
1038  * that controller.
1039  *
1040  * This can be useful for execution of x86 PCI bios initialization code
1041  * on a PCI card, like the xfree86 int10 stuff does.
1042  */
1043 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1044                                       enum pci_mmap_state mmap_state)
1045 {
1046         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1047         unsigned long space_size, user_offset, user_size;
1048
1049         if (mmap_state == pci_mmap_io) {
1050                 space_size = (pbm->io_space.end -
1051                               pbm->io_space.start) + 1;
1052         } else {
1053                 space_size = (pbm->mem_space.end -
1054                               pbm->mem_space.start) + 1;
1055         }
1056
1057         /* Make sure the request is in range. */
1058         user_offset = vma->vm_pgoff << PAGE_SHIFT;
1059         user_size = vma->vm_end - vma->vm_start;
1060
1061         if (user_offset >= space_size ||
1062             (user_offset + user_size) > space_size)
1063                 return -EINVAL;
1064
1065         if (mmap_state == pci_mmap_io) {
1066                 vma->vm_pgoff = (pbm->io_space.start +
1067                                  user_offset) >> PAGE_SHIFT;
1068         } else {
1069                 vma->vm_pgoff = (pbm->mem_space.start +
1070                                  user_offset) >> PAGE_SHIFT;
1071         }
1072
1073         return 0;
1074 }
1075
1076 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1077  * to the 32-bit pci bus offset for DEV requested by the user.
1078  *
1079  * Basically, the user finds the base address for his device which he wishes
1080  * to mmap.  They read the 32-bit value from the config space base register,
1081  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1082  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1083  *
1084  * Returns negative error code on failure, zero on success.
1085  */
1086 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1087                                   enum pci_mmap_state mmap_state)
1088 {
1089         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1090         unsigned long user32 = user_offset & pci_memspace_mask;
1091         unsigned long largest_base, this_base, addr32;
1092         int i;
1093
1094         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1095                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1096
1097         /* Figure out which base address this is for. */
1098         largest_base = 0UL;
1099         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1100                 struct resource *rp = &dev->resource[i];
1101
1102                 /* Active? */
1103                 if (!rp->flags)
1104                         continue;
1105
1106                 /* Same type? */
1107                 if (i == PCI_ROM_RESOURCE) {
1108                         if (mmap_state != pci_mmap_mem)
1109                                 continue;
1110                 } else {
1111                         if ((mmap_state == pci_mmap_io &&
1112                              (rp->flags & IORESOURCE_IO) == 0) ||
1113                             (mmap_state == pci_mmap_mem &&
1114                              (rp->flags & IORESOURCE_MEM) == 0))
1115                                 continue;
1116                 }
1117
1118                 this_base = rp->start;
1119
1120                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1121
1122                 if (mmap_state == pci_mmap_io)
1123                         addr32 &= 0xffffff;
1124
1125                 if (addr32 <= user32 && this_base > largest_base)
1126                         largest_base = this_base;
1127         }
1128
1129         if (largest_base == 0UL)
1130                 return -EINVAL;
1131
1132         /* Now construct the final physical address. */
1133         if (mmap_state == pci_mmap_io)
1134                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1135         else
1136                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1137
1138         return 0;
1139 }
1140
1141 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1142  * mapping.
1143  */
1144 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1145                                             enum pci_mmap_state mmap_state)
1146 {
1147         vma->vm_flags |= (VM_IO | VM_RESERVED);
1148 }
1149
1150 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1151  * device mapping.
1152  */
1153 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1154                                              enum pci_mmap_state mmap_state)
1155 {
1156         /* Our io_remap_pfn_range takes care of this, do nothing.  */
1157 }
1158
1159 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1160  * for this architecture.  The region in the process to map is described by vm_start
1161  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1162  * The pci device structure is provided so that architectures may make mapping
1163  * decisions on a per-device or per-bus basis.
1164  *
1165  * Returns a negative error code on failure, zero on success.
1166  */
1167 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1168                         enum pci_mmap_state mmap_state,
1169                         int write_combine)
1170 {
1171         int ret;
1172
1173         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1174         if (ret < 0)
1175                 return ret;
1176
1177         __pci_mmap_set_flags(dev, vma, mmap_state);
1178         __pci_mmap_set_pgprot(dev, vma, mmap_state);
1179
1180         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1181         ret = io_remap_pfn_range(vma, vma->vm_start,
1182                                  vma->vm_pgoff,
1183                                  vma->vm_end - vma->vm_start,
1184                                  vma->vm_page_prot);
1185         if (ret)
1186                 return ret;
1187
1188         return 0;
1189 }
1190
1191 /* Return the domain nuber for this pci bus */
1192
1193 int pci_domain_nr(struct pci_bus *pbus)
1194 {
1195         struct pci_pbm_info *pbm = pbus->sysdata;
1196         int ret;
1197
1198         if (pbm == NULL || pbm->parent == NULL) {
1199                 ret = -ENXIO;
1200         } else {
1201                 ret = pbm->index;
1202         }
1203
1204         return ret;
1205 }
1206 EXPORT_SYMBOL(pci_domain_nr);
1207
1208 #ifdef CONFIG_PCI_MSI
1209 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1210 {
1211         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1212         int virt_irq;
1213
1214         if (!pbm->setup_msi_irq)
1215                 return -EINVAL;
1216
1217         return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1218 }
1219
1220 void arch_teardown_msi_irq(unsigned int virt_irq)
1221 {
1222         struct msi_desc *entry = get_irq_msi(virt_irq);
1223         struct pci_dev *pdev = entry->dev;
1224         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1225
1226         if (!pbm->teardown_msi_irq)
1227                 return;
1228
1229         return pbm->teardown_msi_irq(virt_irq, pdev);
1230 }
1231 #endif /* !(CONFIG_PCI_MSI) */
1232
1233 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1234 {
1235         return pdev->dev.archdata.prom_node;
1236 }
1237 EXPORT_SYMBOL(pci_device_to_OF_node);
1238
1239 #endif /* !(CONFIG_PCI) */