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Merge branch 'fix/asoc' into for-linus
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / pxa / pxa-ssp.c
blob286be31545df7599fc7b50b6b27e1a43136830c5
1 /*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22
23 #include <asm/irq.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/initval.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/pxa2xx-lib.h>
31
32 #include <mach/hardware.h>
33 #include <mach/dma.h>
34 #include <mach/regs-ssp.h>
35 #include <mach/audio.h>
36 #include <mach/ssp.h>
37
38 #include "pxa2xx-pcm.h"
39 #include "pxa-ssp.h"
40
41 /*
42 * SSP audio private data
43 */
44 struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48 #ifdef CONFIG_PM
49 struct ssp_state state;
50 #endif
51 };
52
53 #define PXA2xx_SSP1_BASE 0x41000000
54 #define PXA27x_SSP2_BASE 0x41700000
55 #define PXA27x_SSP3_BASE 0x41900000
56 #define PXA3xx_SSP4_BASE 0x41a00000
57
58 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
59 .name = "SSP1 PCM Mono out",
60 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
61 .drcmr = &DRCMR(14),
62 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
63 DCMD_BURST16 | DCMD_WIDTH2,
64 };
65
66 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
67 .name = "SSP1 PCM Mono in",
68 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
69 .drcmr = &DRCMR(13),
70 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
71 DCMD_BURST16 | DCMD_WIDTH2,
72 };
73
74 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
75 .name = "SSP1 PCM Stereo out",
76 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
77 .drcmr = &DRCMR(14),
78 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
79 DCMD_BURST16 | DCMD_WIDTH4,
80 };
81
82 static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
83 .name = "SSP1 PCM Stereo in",
84 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
85 .drcmr = &DRCMR(13),
86 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
87 DCMD_BURST16 | DCMD_WIDTH4,
88 };
89
90 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
91 .name = "SSP2 PCM Mono out",
92 .dev_addr = PXA27x_SSP2_BASE + SSDR,
93 .drcmr = &DRCMR(16),
94 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
95 DCMD_BURST16 | DCMD_WIDTH2,
96 };
97
98 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
99 .name = "SSP2 PCM Mono in",
100 .dev_addr = PXA27x_SSP2_BASE + SSDR,
101 .drcmr = &DRCMR(15),
102 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
103 DCMD_BURST16 | DCMD_WIDTH2,
104 };
105
106 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
107 .name = "SSP2 PCM Stereo out",
108 .dev_addr = PXA27x_SSP2_BASE + SSDR,
109 .drcmr = &DRCMR(16),
110 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
111 DCMD_BURST16 | DCMD_WIDTH4,
112 };
113
114 static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
115 .name = "SSP2 PCM Stereo in",
116 .dev_addr = PXA27x_SSP2_BASE + SSDR,
117 .drcmr = &DRCMR(15),
118 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
119 DCMD_BURST16 | DCMD_WIDTH4,
120 };
121
122 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
123 .name = "SSP3 PCM Mono out",
124 .dev_addr = PXA27x_SSP3_BASE + SSDR,
125 .drcmr = &DRCMR(67),
126 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
127 DCMD_BURST16 | DCMD_WIDTH2,
128 };
129
130 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
131 .name = "SSP3 PCM Mono in",
132 .dev_addr = PXA27x_SSP3_BASE + SSDR,
133 .drcmr = &DRCMR(66),
134 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
135 DCMD_BURST16 | DCMD_WIDTH2,
136 };
137
138 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
139 .name = "SSP3 PCM Stereo out",
140 .dev_addr = PXA27x_SSP3_BASE + SSDR,
141 .drcmr = &DRCMR(67),
142 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
143 DCMD_BURST16 | DCMD_WIDTH4,
144 };
145
146 static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
147 .name = "SSP3 PCM Stereo in",
148 .dev_addr = PXA27x_SSP3_BASE + SSDR,
149 .drcmr = &DRCMR(66),
150 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
151 DCMD_BURST16 | DCMD_WIDTH4,
152 };
153
154 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
155 .name = "SSP4 PCM Mono out",
156 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
157 .drcmr = &DRCMR(67),
158 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
159 DCMD_BURST16 | DCMD_WIDTH2,
160 };
161
162 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
163 .name = "SSP4 PCM Mono in",
164 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
165 .drcmr = &DRCMR(66),
166 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
167 DCMD_BURST16 | DCMD_WIDTH2,
168 };
169
170 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
171 .name = "SSP4 PCM Stereo out",
172 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
173 .drcmr = &DRCMR(67),
174 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
175 DCMD_BURST16 | DCMD_WIDTH4,
176 };
177
178 static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
179 .name = "SSP4 PCM Stereo in",
180 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
181 .drcmr = &DRCMR(66),
182 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
183 DCMD_BURST16 | DCMD_WIDTH4,
184 };
185
186 static void dump_registers(struct ssp_device *ssp)
187 {
188 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
189 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
190 ssp_read_reg(ssp, SSTO));
191
192 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
193 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
194 ssp_read_reg(ssp, SSACD));
195 }
196
197 static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
198 {
199 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
200 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
201 },
202 {
203 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
204 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
205 },
206 {
207 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
208 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
209 },
210 {
211 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
212 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
213 },
214 };
215
216 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *dai)
218 {
219 struct snd_soc_pcm_runtime *rtd = substream->private_data;
220 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
221 struct ssp_priv *priv = cpu_dai->private_data;
222 int ret = 0;
223
224 if (!cpu_dai->active) {
225 priv->dev.port = cpu_dai->id + 1;
226 priv->dev.irq = NO_IRQ;
227 clk_enable(priv->dev.ssp->clk);
228 ssp_disable(&priv->dev);
229 }
230 return ret;
231 }
232
233 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
234 struct snd_soc_dai *dai)
235 {
236 struct snd_soc_pcm_runtime *rtd = substream->private_data;
237 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
238 struct ssp_priv *priv = cpu_dai->private_data;
239
240 if (!cpu_dai->active) {
241 ssp_disable(&priv->dev);
242 clk_disable(priv->dev.ssp->clk);
243 }
244 }
245
246 #ifdef CONFIG_PM
247
248 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
249 {
250 struct ssp_priv *priv = cpu_dai->private_data;
251
252 if (!cpu_dai->active)
253 return 0;
254
255 ssp_save_state(&priv->dev, &priv->state);
256 clk_disable(priv->dev.ssp->clk);
257 return 0;
258 }
259
260 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
261 {
262 struct ssp_priv *priv = cpu_dai->private_data;
263
264 if (!cpu_dai->active)
265 return 0;
266
267 clk_enable(priv->dev.ssp->clk);
268 ssp_restore_state(&priv->dev, &priv->state);
269 ssp_enable(&priv->dev);
270
271 return 0;
272 }
273
274 #else
275 #define pxa_ssp_suspend NULL
276 #define pxa_ssp_resume NULL
277 #endif
278
279 /**
280 * ssp_set_clkdiv - set SSP clock divider
281 * @div: serial clock rate divider
282 */
283 static void ssp_set_scr(struct ssp_device *ssp, u32 div)
284 {
285 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
286
287 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
288 sscr0 &= ~0x0000ff00;
289 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
290 } else {
291 sscr0 &= ~0x000fff00;
292 sscr0 |= (div - 1) << 8; /* 1..4096 */
293 }
294 ssp_write_reg(ssp, SSCR0, sscr0);
295 }
296
297 /**
298 * ssp_get_clkdiv - get SSP clock divider
299 */
300 static u32 ssp_get_scr(struct ssp_device *ssp)
301 {
302 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
303 u32 div;
304
305 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
306 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
307 else
308 div = ((sscr0 >> 8) & 0xfff) + 1;
309 return div;
310 }
311
312 /*
313 * Set the SSP ports SYSCLK.
314 */
315 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
316 int clk_id, unsigned int freq, int dir)
317 {
318 struct ssp_priv *priv = cpu_dai->private_data;
319 struct ssp_device *ssp = priv->dev.ssp;
320 int val;
321
322 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
323 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
324
325 dev_dbg(&ssp->pdev->dev,
326 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
327 cpu_dai->id, clk_id, freq);
328
329 switch (clk_id) {
330 case PXA_SSP_CLK_NET_PLL:
331 sscr0 |= SSCR0_MOD;
332 break;
333 case PXA_SSP_CLK_PLL:
334 /* Internal PLL is fixed */
335 if (cpu_is_pxa25x())
336 priv->sysclk = 1843200;
337 else
338 priv->sysclk = 13000000;
339 break;
340 case PXA_SSP_CLK_EXT:
341 priv->sysclk = freq;
342 sscr0 |= SSCR0_ECS;
343 break;
344 case PXA_SSP_CLK_NET:
345 priv->sysclk = freq;
346 sscr0 |= SSCR0_NCS | SSCR0_MOD;
347 break;
348 case PXA_SSP_CLK_AUDIO:
349 priv->sysclk = 0;
350 ssp_set_scr(ssp, 1);
351 sscr0 |= SSCR0_ACS;
352 break;
353 default:
354 return -ENODEV;
355 }
356
357 /* The SSP clock must be disabled when changing SSP clock mode
358 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
359 if (!cpu_is_pxa3xx())
360 clk_disable(priv->dev.ssp->clk);
361 val = ssp_read_reg(ssp, SSCR0) | sscr0;
362 ssp_write_reg(ssp, SSCR0, val);
363 if (!cpu_is_pxa3xx())
364 clk_enable(priv->dev.ssp->clk);
365
366 return 0;
367 }
368
369 /*
370 * Set the SSP clock dividers.
371 */
372 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
373 int div_id, int div)
374 {
375 struct ssp_priv *priv = cpu_dai->private_data;
376 struct ssp_device *ssp = priv->dev.ssp;
377 int val;
378
379 switch (div_id) {
380 case PXA_SSP_AUDIO_DIV_ACDS:
381 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
382 ssp_write_reg(ssp, SSACD, val);
383 break;
384 case PXA_SSP_AUDIO_DIV_SCDB:
385 val = ssp_read_reg(ssp, SSACD);
386 val &= ~SSACD_SCDB;
387 #if defined(CONFIG_PXA3xx)
388 if (cpu_is_pxa3xx())
389 val &= ~SSACD_SCDX8;
390 #endif
391 switch (div) {
392 case PXA_SSP_CLK_SCDB_1:
393 val |= SSACD_SCDB;
394 break;
395 case PXA_SSP_CLK_SCDB_4:
396 break;
397 #if defined(CONFIG_PXA3xx)
398 case PXA_SSP_CLK_SCDB_8:
399 if (cpu_is_pxa3xx())
400 val |= SSACD_SCDX8;
401 else
402 return -EINVAL;
403 break;
404 #endif
405 default:
406 return -EINVAL;
407 }
408 ssp_write_reg(ssp, SSACD, val);
409 break;
410 case PXA_SSP_DIV_SCR:
411 ssp_set_scr(ssp, div);
412 break;
413 default:
414 return -ENODEV;
415 }
416
417 return 0;
418 }
419
420 /*
421 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
422 */
423 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
424 int pll_id, unsigned int freq_in, unsigned int freq_out)
425 {
426 struct ssp_priv *priv = cpu_dai->private_data;
427 struct ssp_device *ssp = priv->dev.ssp;
428 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
429
430 #if defined(CONFIG_PXA3xx)
431 if (cpu_is_pxa3xx())
432 ssp_write_reg(ssp, SSACDD, 0);
433 #endif
434
435 switch (freq_out) {
436 case 5622000:
437 break;
438 case 11345000:
439 ssacd |= (0x1 << 4);
440 break;
441 case 12235000:
442 ssacd |= (0x2 << 4);
443 break;
444 case 14857000:
445 ssacd |= (0x3 << 4);
446 break;
447 case 32842000:
448 ssacd |= (0x4 << 4);
449 break;
450 case 48000000:
451 ssacd |= (0x5 << 4);
452 break;
453 case 0:
454 /* Disable */
455 break;
456
457 default:
458 #ifdef CONFIG_PXA3xx
459 /* PXA3xx has a clock ditherer which can be used to generate
460 * a wider range of frequencies - calculate a value for it.
461 */
462 if (cpu_is_pxa3xx()) {
463 u32 val;
464 u64 tmp = 19968;
465 tmp *= 1000000;
466 do_div(tmp, freq_out);
467 val = tmp;
468
469 val = (val << 16) | 64;;
470 ssp_write_reg(ssp, SSACDD, val);
471
472 ssacd |= (0x6 << 4);
473
474 dev_dbg(&ssp->pdev->dev,
475 "Using SSACDD %x to supply %dHz\n",
476 val, freq_out);
477 break;
478 }
479 #endif
480
481 return -EINVAL;
482 }
483
484 ssp_write_reg(ssp, SSACD, ssacd);
485
486 return 0;
487 }
488
489 /*
490 * Set the active slots in TDM/Network mode
491 */
492 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
493 unsigned int mask, int slots)
494 {
495 struct ssp_priv *priv = cpu_dai->private_data;
496 struct ssp_device *ssp = priv->dev.ssp;
497 u32 sscr0;
498
499 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
500
501 /* set number of active slots */
502 sscr0 |= SSCR0_SlotsPerFrm(slots);
503 ssp_write_reg(ssp, SSCR0, sscr0);
504
505 /* set active slot mask */
506 ssp_write_reg(ssp, SSTSA, mask);
507 ssp_write_reg(ssp, SSRSA, mask);
508 return 0;
509 }
510
511 /*
512 * Tristate the SSP DAI lines
513 */
514 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
515 int tristate)
516 {
517 struct ssp_priv *priv = cpu_dai->private_data;
518 struct ssp_device *ssp = priv->dev.ssp;
519 u32 sscr1;
520
521 sscr1 = ssp_read_reg(ssp, SSCR1);
522 if (tristate)
523 sscr1 &= ~SSCR1_TTE;
524 else
525 sscr1 |= SSCR1_TTE;
526 ssp_write_reg(ssp, SSCR1, sscr1);
527
528 return 0;
529 }
530
531 /*
532 * Set up the SSP DAI format.
533 * The SSP Port must be inactive before calling this function as the
534 * physical interface format is changed.
535 */
536 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
537 unsigned int fmt)
538 {
539 struct ssp_priv *priv = cpu_dai->private_data;
540 struct ssp_device *ssp = priv->dev.ssp;
541 u32 sscr0;
542 u32 sscr1;
543 u32 sspsp;
544
545 /* check if we need to change anything at all */
546 if (priv->dai_fmt == fmt)
547 return 0;
548
549 /* we can only change the settings if the port is not in use */
550 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
551 dev_err(&ssp->pdev->dev,
552 "can't change hardware dai format: stream is in use");
553 return -EINVAL;
554 }
555
556 /* reset port settings */
557 sscr0 = ssp_read_reg(ssp, SSCR0) &
558 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
559 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
560 sspsp = 0;
561
562 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
563 case SND_SOC_DAIFMT_CBM_CFM:
564 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
565 break;
566 case SND_SOC_DAIFMT_CBM_CFS:
567 sscr1 |= SSCR1_SCLKDIR;
568 break;
569 case SND_SOC_DAIFMT_CBS_CFS:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 ssp_write_reg(ssp, SSCR0, sscr0);
576 ssp_write_reg(ssp, SSCR1, sscr1);
577 ssp_write_reg(ssp, SSPSP, sspsp);
578
579 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
580 case SND_SOC_DAIFMT_I2S:
581 sscr0 |= SSCR0_PSP;
582 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
583
584 /* See hw_params() */
585 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
586 case SND_SOC_DAIFMT_NB_NF:
587 sspsp |= SSPSP_SFRMP;
588 break;
589 case SND_SOC_DAIFMT_NB_IF:
590 break;
591 case SND_SOC_DAIFMT_IB_IF:
592 sspsp |= SSPSP_SCMODE(3);
593 break;
594 default:
595 return -EINVAL;
596 }
597 break;
598
599 case SND_SOC_DAIFMT_DSP_A:
600 sspsp |= SSPSP_FSRT;
601 case SND_SOC_DAIFMT_DSP_B:
602 sscr0 |= SSCR0_MOD | SSCR0_PSP;
603 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
604
605 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
606 case SND_SOC_DAIFMT_NB_NF:
607 sspsp |= SSPSP_SFRMP;
608 break;
609 case SND_SOC_DAIFMT_IB_IF:
610 break;
611 default:
612 return -EINVAL;
613 }
614 break;
615
616 default:
617 return -EINVAL;
618 }
619
620 ssp_write_reg(ssp, SSCR0, sscr0);
621 ssp_write_reg(ssp, SSCR1, sscr1);
622 ssp_write_reg(ssp, SSPSP, sspsp);
623
624 dump_registers(ssp);
625
626 /* Since we are configuring the timings for the format by hand
627 * we have to defer some things until hw_params() where we
628 * know parameters like the sample size.
629 */
630 priv->dai_fmt = fmt;
631
632 return 0;
633 }
634
635 /*
636 * Set the SSP audio DMA parameters and sample size.
637 * Can be called multiple times by oss emulation.
638 */
639 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
640 struct snd_pcm_hw_params *params,
641 struct snd_soc_dai *dai)
642 {
643 struct snd_soc_pcm_runtime *rtd = substream->private_data;
644 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
645 struct ssp_priv *priv = cpu_dai->private_data;
646 struct ssp_device *ssp = priv->dev.ssp;
647 int dma = 0, chn = params_channels(params);
648 u32 sscr0;
649 u32 sspsp;
650 int width = snd_pcm_format_physical_width(params_format(params));
651 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
652
653 /* select correct DMA params */
654 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
655 dma = 1; /* capture DMA offset is 1,3 */
656 /* Network mode with one active slot (ttsa == 1) can be used
657 * to force 16-bit frame width on the wire (for S16_LE), even
658 * with two channels. Use 16-bit DMA transfers for this case.
659 */
660 if (((chn == 2) && (ttsa != 1)) || (width == 32))
661 dma += 2; /* 32-bit DMA offset is 2, 16-bit is 0 */
662
663 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
664
665 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
666
667 /* we can only change the settings if the port is not in use */
668 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
669 return 0;
670
671 /* clear selected SSP bits */
672 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
673 ssp_write_reg(ssp, SSCR0, sscr0);
674
675 /* bit size */
676 sscr0 = ssp_read_reg(ssp, SSCR0);
677 switch (params_format(params)) {
678 case SNDRV_PCM_FORMAT_S16_LE:
679 #ifdef CONFIG_PXA3xx
680 if (cpu_is_pxa3xx())
681 sscr0 |= SSCR0_FPCKE;
682 #endif
683 sscr0 |= SSCR0_DataSize(16);
684 break;
685 case SNDRV_PCM_FORMAT_S24_LE:
686 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
687 break;
688 case SNDRV_PCM_FORMAT_S32_LE:
689 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
690 break;
691 }
692 ssp_write_reg(ssp, SSCR0, sscr0);
693
694 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
695 case SND_SOC_DAIFMT_I2S:
696 sspsp = ssp_read_reg(ssp, SSPSP);
697
698 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
699 /* This is a special case where the bitclk is 64fs
700 * and we're not dealing with 2*32 bits of audio
701 * samples.
702 *
703 * The SSP values used for that are all found out by
704 * trying and failing a lot; some of the registers
705 * needed for that mode are only available on PXA3xx.
706 */
707
708 #ifdef CONFIG_PXA3xx
709 if (!cpu_is_pxa3xx())
710 return -EINVAL;
711
712 sspsp |= SSPSP_SFRMWDTH(width * 2);
713 sspsp |= SSPSP_SFRMDLY(width * 4);
714 sspsp |= SSPSP_EDMYSTOP(3);
715 sspsp |= SSPSP_DMYSTOP(3);
716 sspsp |= SSPSP_DMYSTRT(1);
717 #else
718 return -EINVAL;
719 #endif
720 } else {
721 /* The frame width is the width the LRCLK is
722 * asserted for; the delay is expressed in
723 * half cycle units. We need the extra cycle
724 * because the data starts clocking out one BCLK
725 * after LRCLK changes polarity.
726 */
727 sspsp |= SSPSP_SFRMWDTH(width + 1);
728 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
729 sspsp |= SSPSP_DMYSTRT(1);
730 }
731
732 ssp_write_reg(ssp, SSPSP, sspsp);
733 break;
734 default:
735 break;
736 }
737
738 /* When we use a network mode, we always require TDM slots
739 * - complain loudly and fail if they've not been set up yet.
740 */
741 if ((sscr0 & SSCR0_MOD) && !ttsa) {
742 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
743 return -EINVAL;
744 }
745
746 dump_registers(ssp);
747
748 return 0;
749 }
750
751 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
752 struct snd_soc_dai *dai)
753 {
754 struct snd_soc_pcm_runtime *rtd = substream->private_data;
755 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
756 int ret = 0;
757 struct ssp_priv *priv = cpu_dai->private_data;
758 struct ssp_device *ssp = priv->dev.ssp;
759 int val;
760
761 switch (cmd) {
762 case SNDRV_PCM_TRIGGER_RESUME:
763 ssp_enable(&priv->dev);
764 break;
765 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
766 val = ssp_read_reg(ssp, SSCR1);
767 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
768 val |= SSCR1_TSRE;
769 else
770 val |= SSCR1_RSRE;
771 ssp_write_reg(ssp, SSCR1, val);
772 val = ssp_read_reg(ssp, SSSR);
773 ssp_write_reg(ssp, SSSR, val);
774 break;
775 case SNDRV_PCM_TRIGGER_START:
776 val = ssp_read_reg(ssp, SSCR1);
777 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
778 val |= SSCR1_TSRE;
779 else
780 val |= SSCR1_RSRE;
781 ssp_write_reg(ssp, SSCR1, val);
782 ssp_enable(&priv->dev);
783 break;
784 case SNDRV_PCM_TRIGGER_STOP:
785 val = ssp_read_reg(ssp, SSCR1);
786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
787 val &= ~SSCR1_TSRE;
788 else
789 val &= ~SSCR1_RSRE;
790 ssp_write_reg(ssp, SSCR1, val);
791 break;
792 case SNDRV_PCM_TRIGGER_SUSPEND:
793 ssp_disable(&priv->dev);
794 break;
795 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
796 val = ssp_read_reg(ssp, SSCR1);
797 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
798 val &= ~SSCR1_TSRE;
799 else
800 val &= ~SSCR1_RSRE;
801 ssp_write_reg(ssp, SSCR1, val);
802 break;
803
804 default:
805 ret = -EINVAL;
806 }
807
808 dump_registers(ssp);
809
810 return ret;
811 }
812
813 static int pxa_ssp_probe(struct platform_device *pdev,
814 struct snd_soc_dai *dai)
815 {
816 struct ssp_priv *priv;
817 int ret;
818
819 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
820 if (!priv)
821 return -ENOMEM;
822
823 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
824 if (priv->dev.ssp == NULL) {
825 ret = -ENODEV;
826 goto err_priv;
827 }
828
829 priv->dai_fmt = (unsigned int) -1;
830 dai->private_data = priv;
831
832 return 0;
833
834 err_priv:
835 kfree(priv);
836 return ret;
837 }
838
839 static void pxa_ssp_remove(struct platform_device *pdev,
840 struct snd_soc_dai *dai)
841 {
842 struct ssp_priv *priv = dai->private_data;
843 ssp_free(priv->dev.ssp);
844 }
845
846 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
847 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
848 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
849 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
850
851 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
852 SNDRV_PCM_FMTBIT_S24_LE | \
853 SNDRV_PCM_FMTBIT_S32_LE)
854
855 static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
856 .startup = pxa_ssp_startup,
857 .shutdown = pxa_ssp_shutdown,
858 .trigger = pxa_ssp_trigger,
859 .hw_params = pxa_ssp_hw_params,
860 .set_sysclk = pxa_ssp_set_dai_sysclk,
861 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
862 .set_pll = pxa_ssp_set_dai_pll,
863 .set_fmt = pxa_ssp_set_dai_fmt,
864 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
865 .set_tristate = pxa_ssp_set_dai_tristate,
866 };
867
868 struct snd_soc_dai pxa_ssp_dai[] = {
869 {
870 .name = "pxa2xx-ssp1",
871 .id = 0,
872 .probe = pxa_ssp_probe,
873 .remove = pxa_ssp_remove,
874 .suspend = pxa_ssp_suspend,
875 .resume = pxa_ssp_resume,
876 .playback = {
877 .channels_min = 1,
878 .channels_max = 2,
879 .rates = PXA_SSP_RATES,
880 .formats = PXA_SSP_FORMATS,
881 },
882 .capture = {
883 .channels_min = 1,
884 .channels_max = 2,
885 .rates = PXA_SSP_RATES,
886 .formats = PXA_SSP_FORMATS,
887 },
888 .ops = &pxa_ssp_dai_ops,
889 },
890 { .name = "pxa2xx-ssp2",
891 .id = 1,
892 .probe = pxa_ssp_probe,
893 .remove = pxa_ssp_remove,
894 .suspend = pxa_ssp_suspend,
895 .resume = pxa_ssp_resume,
896 .playback = {
897 .channels_min = 1,
898 .channels_max = 2,
899 .rates = PXA_SSP_RATES,
900 .formats = PXA_SSP_FORMATS,
901 },
902 .capture = {
903 .channels_min = 1,
904 .channels_max = 2,
905 .rates = PXA_SSP_RATES,
906 .formats = PXA_SSP_FORMATS,
907 },
908 .ops = &pxa_ssp_dai_ops,
909 },
910 {
911 .name = "pxa2xx-ssp3",
912 .id = 2,
913 .probe = pxa_ssp_probe,
914 .remove = pxa_ssp_remove,
915 .suspend = pxa_ssp_suspend,
916 .resume = pxa_ssp_resume,
917 .playback = {
918 .channels_min = 1,
919 .channels_max = 2,
920 .rates = PXA_SSP_RATES,
921 .formats = PXA_SSP_FORMATS,
922 },
923 .capture = {
924 .channels_min = 1,
925 .channels_max = 2,
926 .rates = PXA_SSP_RATES,
927 .formats = PXA_SSP_FORMATS,
928 },
929 .ops = &pxa_ssp_dai_ops,
930 },
931 {
932 .name = "pxa2xx-ssp4",
933 .id = 3,
934 .probe = pxa_ssp_probe,
935 .remove = pxa_ssp_remove,
936 .suspend = pxa_ssp_suspend,
937 .resume = pxa_ssp_resume,
938 .playback = {
939 .channels_min = 1,
940 .channels_max = 2,
941 .rates = PXA_SSP_RATES,
942 .formats = PXA_SSP_FORMATS,
943 },
944 .capture = {
945 .channels_min = 1,
946 .channels_max = 2,
947 .rates = PXA_SSP_RATES,
948 .formats = PXA_SSP_FORMATS,
949 },
950 .ops = &pxa_ssp_dai_ops,
951 },
952 };
953 EXPORT_SYMBOL_GPL(pxa_ssp_dai);
954
955 static int __init pxa_ssp_init(void)
956 {
957 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
958 }
959 module_init(pxa_ssp_init);
960
961 static void __exit pxa_ssp_exit(void)
962 {
963 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
964 }
965 module_exit(pxa_ssp_exit);
966
967 /* Module information */
968 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
969 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
970 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree