2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
28 #include <asm/system.h>
29 #include <asm/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/hardware/amba.h>
35 #include <asm/hardware/amba_clcd.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
46 #include <asm/hardware/gic.h>
51 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
54 * This is the RealView sched_clock implementation. This has
55 * a resolution of 41.7ns, and a maximum value of about 179s.
57 unsigned long long sched_clock(void)
61 v
= (unsigned long long)readl(REALVIEW_REFCOUNTER
) * 125;
68 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
70 static int realview_flash_init(void)
74 val
= __raw_readl(REALVIEW_FLASHCTRL
);
75 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
76 __raw_writel(val
, REALVIEW_FLASHCTRL
);
81 static void realview_flash_exit(void)
85 val
= __raw_readl(REALVIEW_FLASHCTRL
);
86 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
87 __raw_writel(val
, REALVIEW_FLASHCTRL
);
90 static void realview_flash_set_vpp(int on
)
94 val
= __raw_readl(REALVIEW_FLASHCTRL
);
96 val
|= REALVIEW_FLASHPROG_FLVPPEN
;
98 val
&= ~REALVIEW_FLASHPROG_FLVPPEN
;
99 __raw_writel(val
, REALVIEW_FLASHCTRL
);
102 static struct flash_platform_data realview_flash_data
= {
103 .map_name
= "cfi_probe",
105 .init
= realview_flash_init
,
106 .exit
= realview_flash_exit
,
107 .set_vpp
= realview_flash_set_vpp
,
110 static struct resource realview_flash_resource
= {
111 .start
= REALVIEW_FLASH_BASE
,
112 .end
= REALVIEW_FLASH_BASE
+ REALVIEW_FLASH_SIZE
,
113 .flags
= IORESOURCE_MEM
,
116 struct platform_device realview_flash_device
= {
120 .platform_data
= &realview_flash_data
,
123 .resource
= &realview_flash_resource
,
126 static struct resource realview_smc91x_resources
[] = {
128 .start
= REALVIEW_ETH_BASE
,
129 .end
= REALVIEW_ETH_BASE
+ SZ_64K
- 1,
130 .flags
= IORESOURCE_MEM
,
135 .flags
= IORESOURCE_IRQ
,
139 struct platform_device realview_smc91x_device
= {
142 .num_resources
= ARRAY_SIZE(realview_smc91x_resources
),
143 .resource
= realview_smc91x_resources
,
146 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
148 static unsigned int realview_mmc_status(struct device
*dev
)
150 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
153 if (adev
->res
.start
== REALVIEW_MMCI0_BASE
)
158 return readl(REALVIEW_SYSMCI
) & mask
;
161 struct mmc_platform_data realview_mmc0_plat_data
= {
162 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
163 .status
= realview_mmc_status
,
166 struct mmc_platform_data realview_mmc1_plat_data
= {
167 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
168 .status
= realview_mmc_status
,
174 static const struct icst307_params realview_oscvco_params
= {
183 static void realview_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
185 void __iomem
*sys_lock
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_LOCK_OFFSET
;
186 void __iomem
*sys_osc
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_OSC1_OFFSET
;
189 val
= readl(sys_osc
) & ~0x7ffff;
190 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
192 writel(0xa05f, sys_lock
);
193 writel(val
, sys_osc
);
197 struct clk realview_clcd_clk
= {
199 .params
= &realview_oscvco_params
,
200 .setvco
= realview_oscvco_set
,
206 #define SYS_CLCD_MODE_MASK (3 << 0)
207 #define SYS_CLCD_MODE_888 (0 << 0)
208 #define SYS_CLCD_MODE_5551 (1 << 0)
209 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
210 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
211 #define SYS_CLCD_NLCDIOON (1 << 2)
212 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
213 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
214 #define SYS_CLCD_ID_MASK (0x1f << 8)
215 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
216 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
217 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
218 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
219 #define SYS_CLCD_ID_VGA (0x1f << 8)
221 static struct clcd_panel vga
= {
235 .vmode
= FB_VMODE_NONINTERLACED
,
239 .tim2
= TIM2_BCD
| TIM2_IPC
,
240 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
244 static struct clcd_panel sanyo_3_8_in
= {
246 .name
= "Sanyo QVGA",
258 .vmode
= FB_VMODE_NONINTERLACED
,
263 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
267 static struct clcd_panel sanyo_2_5_in
= {
269 .name
= "Sanyo QVGA Portrait",
280 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
281 .vmode
= FB_VMODE_NONINTERLACED
,
285 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
286 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
290 static struct clcd_panel epson_2_2_in
= {
292 .name
= "Epson QCIF",
304 .vmode
= FB_VMODE_NONINTERLACED
,
308 .tim2
= TIM2_BCD
| TIM2_IPC
,
309 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
314 * Detect which LCD panel is connected, and return the appropriate
315 * clcd_panel structure. Note: we do not have any information on
316 * the required timings for the 8.4in panel, so we presently assume
319 static struct clcd_panel
*realview_clcd_panel(void)
321 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
322 struct clcd_panel
*panel
= &vga
;
325 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
326 if (val
== SYS_CLCD_ID_SANYO_3_8
)
327 panel
= &sanyo_3_8_in
;
328 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
329 panel
= &sanyo_2_5_in
;
330 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
331 panel
= &epson_2_2_in
;
332 else if (val
== SYS_CLCD_ID_VGA
)
335 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
344 * Disable all display connectors on the interface module.
346 static void realview_clcd_disable(struct clcd_fb
*fb
)
348 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
351 val
= readl(sys_clcd
);
352 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
353 writel(val
, sys_clcd
);
357 * Enable the relevant connector on the interface module.
359 static void realview_clcd_enable(struct clcd_fb
*fb
)
361 void __iomem
*sys_clcd
= __io_address(REALVIEW_SYS_BASE
) + REALVIEW_SYS_CLCD_OFFSET
;
364 val
= readl(sys_clcd
);
365 val
&= ~SYS_CLCD_MODE_MASK
;
367 switch (fb
->fb
.var
.green
.length
) {
369 val
|= SYS_CLCD_MODE_5551
;
372 val
|= SYS_CLCD_MODE_565_RLSB
;
375 val
|= SYS_CLCD_MODE_888
;
382 writel(val
, sys_clcd
);
385 * And now enable the PSUs
387 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
388 writel(val
, sys_clcd
);
391 static unsigned long framesize
= SZ_1M
;
393 static int realview_clcd_setup(struct clcd_fb
*fb
)
397 fb
->panel
= realview_clcd_panel();
399 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
401 if (!fb
->fb
.screen_base
) {
402 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
406 fb
->fb
.fix
.smem_start
= dma
;
407 fb
->fb
.fix
.smem_len
= framesize
;
412 static int realview_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
414 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
416 fb
->fb
.fix
.smem_start
,
417 fb
->fb
.fix
.smem_len
);
420 static void realview_clcd_remove(struct clcd_fb
*fb
)
422 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
423 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
426 struct clcd_board clcd_plat_data
= {
428 .check
= clcdfb_check
,
429 .decode
= clcdfb_decode
,
430 .disable
= realview_clcd_disable
,
431 .enable
= realview_clcd_enable
,
432 .setup
= realview_clcd_setup
,
433 .mmap
= realview_clcd_mmap
,
434 .remove
= realview_clcd_remove
,
438 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
440 void realview_leds_event(led_event_t ledevt
)
445 local_irq_save(flags
);
446 val
= readl(VA_LEDS_BASE
);
450 val
= val
& ~REALVIEW_SYS_LED0
;
454 val
= val
| REALVIEW_SYS_LED0
;
458 val
= val
^ REALVIEW_SYS_LED1
;
469 writel(val
, VA_LEDS_BASE
);
470 local_irq_restore(flags
);
472 #endif /* CONFIG_LEDS */
475 * Where is the timer (VA)?
477 #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
478 #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
479 #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
480 #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
483 * How long is the timer interval?
485 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
486 #if TIMER_INTERVAL >= 0x100000
487 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
488 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
489 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
490 #elif TIMER_INTERVAL >= 0x10000
491 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
492 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
493 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
495 #define TIMER_RELOAD (TIMER_INTERVAL)
496 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
497 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
501 * Returns number of ms since last clock interrupt. Note that interrupts
502 * will have been disabled by do_gettimeoffset()
504 static unsigned long realview_gettimeoffset(void)
506 unsigned long ticks1
, ticks2
, status
;
509 * Get the current number of ticks. Note that there is a race
510 * condition between us reading the timer and checking for
511 * an interrupt. We get around this by ensuring that the
512 * counter has not reloaded between our two reads.
514 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
517 status
= __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE
+ GIC_DIST_PENDING_SET
)
518 + ((IRQ_TIMERINT0_1
>> 5) << 2));
519 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
520 } while (ticks2
> ticks1
);
523 * Number of ticks since last interrupt.
525 ticks1
= TIMER_RELOAD
- ticks2
;
528 * Interrupt pending? If so, we've reloaded once already.
530 * FIXME: Need to check this is effectively timer 0 that expires
532 if (status
& IRQMASK_TIMERINT0_1
)
533 ticks1
+= TIMER_RELOAD
;
536 * Convert the ticks to usecs
538 return TICKS2USECS(ticks1
);
542 * IRQ handler for the timer
544 static irqreturn_t
realview_timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
546 write_seqlock(&xtime_lock
);
548 // ...clear the interrupt
549 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
553 write_sequnlock(&xtime_lock
);
558 static struct irqaction realview_timer_irq
= {
559 .name
= "RealView Timer Tick",
560 .flags
= SA_INTERRUPT
| SA_TIMER
,
561 .handler
= realview_timer_interrupt
,
565 * Set up timer interrupt, and return the current time in seconds.
567 static void __init
realview_timer_init(void)
572 * set clock frequency:
573 * REALVIEW_REFCLK is 32KHz
574 * REALVIEW_TIMCLK is 1MHz
576 val
= readl(__io_address(REALVIEW_SCTL_BASE
));
577 writel((REALVIEW_TIMCLK
<< REALVIEW_TIMER1_EnSel
) |
578 (REALVIEW_TIMCLK
<< REALVIEW_TIMER2_EnSel
) |
579 (REALVIEW_TIMCLK
<< REALVIEW_TIMER3_EnSel
) |
580 (REALVIEW_TIMCLK
<< REALVIEW_TIMER4_EnSel
) | val
,
581 __io_address(REALVIEW_SCTL_BASE
));
584 * Initialise to a known state (all timers off)
586 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
587 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
588 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
589 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
591 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
592 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_VALUE
);
593 writel(TIMER_DIVISOR
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
|
594 TIMER_CTRL_IE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
597 * Make irqs happen for the system timer
599 setup_irq(IRQ_TIMERINT0_1
, &realview_timer_irq
);
602 struct sys_timer realview_timer
= {
603 .init
= realview_timer_init
,
604 .offset
= realview_gettimeoffset
,