arch/arm/mach-ixp2000/core.c

   1 /*
   2  * arch/arm/mach-ixp2000/core.c
   3  *
   4  * Common routines used by all IXP2400/2800 based platforms.
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2004 (C) MontaVista Software, Inc.
   9  *
  10  * Based on work Copyright (C) 2002-2003 Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/mm.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware.h>
  33 #include <asm/irq.h>
  34 #include <asm/system.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/pgtable.h>
  37
  38 #include <asm/mach/map.h>
  39 #include <asm/mach/time.h>
  40 #include <asm/mach/irq.h>
  41
  42 #include <asm/arch/gpio.h>
  43
  44 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  45 static unsigned long ixp2000_slowport_irq_flags;
  46
  47 /*************************************************************************
  48  * Slowport access routines
  49  *************************************************************************/
  50 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  51 {
  52         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  53
  54         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  55         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  56         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  57         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  58         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  59
  60         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  61         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  62         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  63         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  64         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  65 }
  66
  67 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  68 {
  69         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  70         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  71         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  72         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  73         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  74
  75         spin_unlock_irqrestore(&ixp2000_slowport_lock,
  76                                         ixp2000_slowport_irq_flags);
  77 }
  78
  79 /*************************************************************************
  80  * Chip specific mappings shared by all IXP2000 systems
  81  *************************************************************************/
  82 static struct map_desc ixp2000_io_desc[] __initdata = {
  83         {
  84                 .virtual        = IXP2000_CAP_VIRT_BASE,
  85                 .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
  86                 .length         = IXP2000_CAP_SIZE,
  87                 .type           = MT_DEVICE
  88         }, {
  89                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
  90                 .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
  91                 .length         = IXP2000_INTCTL_SIZE,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
  95                 .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
  96                 .length         = IXP2000_PCI_CREG_SIZE,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
 100                 .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
 101                 .length         = IXP2000_PCI_CSR_SIZE,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IXP2000_MSF_VIRT_BASE,
 105                 .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
 106                 .length         = IXP2000_MSF_SIZE,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
 110                 .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
 111                 .length         = IXP2000_PCI_IO_SIZE,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
 115                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
 116                 .length         = IXP2000_PCI_CFG0_SIZE,
 117                 .type           = MT_DEVICE
 118         }, {
 119                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
 120                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
 121                 .length         = IXP2000_PCI_CFG1_SIZE,
 122                 .type           = MT_DEVICE
 123         }
 124 };
 125
 126 void __init ixp2000_map_io(void)
 127 {
 128         extern unsigned int processor_id;
 129
 130         /*
 131          * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
 132          * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
 133          * PMD flags.
 134          */
 135         if ((processor_id & 0xfffffff0) == 0x69054190) {
 136                 int i;
 137
 138                 printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
 139
 140                 for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
 141                         ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
 142         }
 143
 144         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 145
 146         /* Set slowport to 8-bit mode.  */
 147         ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
 148 }
 149
 150
 151 /*************************************************************************
 152  * Serial port support for IXP2000
 153  *************************************************************************/
 154 static struct plat_serial8250_port ixp2000_serial_port[] = {
 155         {
 156                 .mapbase        = IXP2000_UART_PHYS_BASE,
 157                 .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
 158                 .irq            = IRQ_IXP2000_UART,
 159                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 160                 .iotype         = UPIO_MEM,
 161                 .regshift       = 2,
 162                 .uartclk        = 50000000,
 163         },
 164         { },
 165 };
 166
 167 static struct resource ixp2000_uart_resource = {
 168         .start          = IXP2000_UART_PHYS_BASE,
 169         .end            = IXP2000_UART_PHYS_BASE + 0x1f,
 170         .flags          = IORESOURCE_MEM,
 171 };
 172
 173 static struct platform_device ixp2000_serial_device = {
 174         .name           = "serial8250",
 175         .id             = PLAT8250_DEV_PLATFORM,
 176         .dev            = {
 177                 .platform_data          = ixp2000_serial_port,
 178         },
 179         .num_resources  = 1,
 180         .resource       = &ixp2000_uart_resource,
 181 };
 182
 183 void __init ixp2000_uart_init(void)
 184 {
 185         platform_device_register(&ixp2000_serial_device);
 186 }
 187
 188
 189 /*************************************************************************
 190  * Timer-tick functions for IXP2000
 191  *************************************************************************/
 192 static unsigned ticks_per_jiffy;
 193 static unsigned ticks_per_usec;
 194 static unsigned next_jiffy_time;
 195 static volatile unsigned long *missing_jiffy_timer_csr;
 196
 197 unsigned long ixp2000_gettimeoffset (void)
 198 {
 199         unsigned long offset;
 200
 201         offset = next_jiffy_time - *missing_jiffy_timer_csr;
 202
 203         return offset / ticks_per_usec;
 204 }
 205
 206 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 207 {
 208         write_seqlock(&xtime_lock);
 209
 210         /* clear timer 1 */
 211         ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
 212
 213         while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
 214                 timer_tick(regs);
 215                 next_jiffy_time -= ticks_per_jiffy;
 216         }
 217
 218         write_sequnlock(&xtime_lock);
 219
 220         return IRQ_HANDLED;
 221 }
 222
 223 static struct irqaction ixp2000_timer_irq = {
 224         .name           = "IXP2000 Timer Tick",
 225         .flags          = SA_INTERRUPT | SA_TIMER,
 226         .handler        = ixp2000_timer_interrupt,
 227 };
 228
 229 void __init ixp2000_init_time(unsigned long tick_rate)
 230 {
 231         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
 232         ticks_per_usec = tick_rate / 1000000;
 233
 234         /*
 235          * We use timer 1 as our timer interrupt.
 236          */
 237         ixp2000_reg_write(IXP2000_T1_CLR, 0);
 238         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
 239         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 240
 241         /*
 242          * We use a second timer as a monotonic counter for tracking
 243          * missed jiffies.  The IXP2000 has four timers, but if we're
 244          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
 245          * chips we use timer 4.  Timer 4 is the only timer that can
 246          * be used for the watchdog, so we use timer 2 if we're on a
 247          * non-buggy chip.
 248          */
 249         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
 250                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
 251
 252                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
 253                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
 254                 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
 255                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
 256         } else {
 257                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
 258                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
 259                 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
 260                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
 261         }
 262         next_jiffy_time = 0xffffffff;
 263
 264         /* register for interrupt */
 265         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
 266 }
 267
 268 /*************************************************************************
 269  * GPIO helpers
 270  *************************************************************************/
 271 static unsigned long GPIO_IRQ_falling_edge;
 272 static unsigned long GPIO_IRQ_rising_edge;
 273 static unsigned long GPIO_IRQ_level_low;
 274 static unsigned long GPIO_IRQ_level_high;
 275
 276 static void update_gpio_int_csrs(void)
 277 {
 278         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
 279         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
 280         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
 281         ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
 282 }
 283
 284 void gpio_line_config(int line, int direction)
 285 {
 286         unsigned long flags;
 287
 288         local_irq_save(flags);
 289         if (direction == GPIO_OUT) {
 290                 irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
 291
 292                 /* if it's an output, it ain't an interrupt anymore */
 293                 GPIO_IRQ_falling_edge &= ~(1 << line);
 294                 GPIO_IRQ_rising_edge &= ~(1 << line);
 295                 GPIO_IRQ_level_low &= ~(1 << line);
 296                 GPIO_IRQ_level_high &= ~(1 << line);
 297                 update_gpio_int_csrs();
 298
 299                 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
 300         } else if (direction == GPIO_IN) {
 301                 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
 302         }
 303         local_irq_restore(flags);
 304 }
 305
 306
 307 /*************************************************************************
 308  * IRQ handling IXP2000
 309  *************************************************************************/
 310 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 311 {
 312         int i;
 313         unsigned long status = *IXP2000_GPIO_INST;
 314
 315         for (i = 0; i <= 7; i++) {
 316                 if (status & (1<<i)) {
 317                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
 318                         desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
 319                 }
 320         }
 321 }
 322
 323 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
 324 {
 325         int line = irq - IRQ_IXP2000_GPIO0;
 326
 327         /*
 328          * First, configure this GPIO line as an input.
 329          */
 330         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 331
 332         /*
 333          * Then, set the proper trigger type.
 334          */
 335         if (type & IRQT_FALLING)
 336                 GPIO_IRQ_falling_edge |= 1 << line;
 337         else
 338                 GPIO_IRQ_falling_edge &= ~(1 << line);
 339         if (type & IRQT_RISING)
 340                 GPIO_IRQ_rising_edge |= 1 << line;
 341         else
 342                 GPIO_IRQ_rising_edge &= ~(1 << line);
 343         if (type & IRQT_LOW)
 344                 GPIO_IRQ_level_low |= 1 << line;
 345         else
 346                 GPIO_IRQ_level_low &= ~(1 << line);
 347         if (type & IRQT_HIGH)
 348                 GPIO_IRQ_level_high |= 1 << line;
 349         else
 350                 GPIO_IRQ_level_high &= ~(1 << line);
 351         update_gpio_int_csrs();
 352
 353         /*
 354          * Finally, mark the corresponding IRQ as valid.
 355          */
 356         irq_desc[irq].valid = 1;
 357
 358         return 0;
 359 }
 360
 361 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
 362 {
 363         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 364
 365         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 366         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 367         ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 368 }
 369
 370 static void ixp2000_GPIO_irq_mask(unsigned int irq)
 371 {
 372         ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 373 }
 374
 375 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
 376 {
 377         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 378 }
 379
 380 static struct irqchip ixp2000_GPIO_irq_chip = {
 381         .ack            = ixp2000_GPIO_irq_mask_ack,
 382         .mask           = ixp2000_GPIO_irq_mask,
 383         .unmask         = ixp2000_GPIO_irq_unmask,
 384         .set_type       = ixp2000_GPIO_irq_type,
 385 };
 386
 387 static void ixp2000_pci_irq_mask(unsigned int irq)
 388 {
 389         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 390         if (irq == IRQ_IXP2000_PCIA)
 391                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
 392         else if (irq == IRQ_IXP2000_PCIB)
 393                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 394 }
 395
 396 static void ixp2000_pci_irq_unmask(unsigned int irq)
 397 {
 398         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 399         if (irq == IRQ_IXP2000_PCIA)
 400                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
 401         else if (irq == IRQ_IXP2000_PCIB)
 402                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 403 }
 404
 405 /*
 406  * Error interrupts. These are used extensively by the microengine drivers
 407  */
 408 static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc,  struct pt_regs *regs)
 409 {
 410         int i;
 411         unsigned long status = *IXP2000_IRQ_ERR_STATUS;
 412
 413         for(i = 31; i >= 0; i--) {
 414                 if(status & (1 << i)) {
 415                         desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
 416                         desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
 417                 }
 418         }
 419 }
 420
 421 static void ixp2000_err_irq_mask(unsigned int irq)
 422 {
 423         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
 424                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 425 }
 426
 427 static void ixp2000_err_irq_unmask(unsigned int irq)
 428 {
 429         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
 430                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
 431 }
 432
 433 static struct irqchip ixp2000_err_irq_chip = {
 434         .ack    = ixp2000_err_irq_mask,
 435         .mask   = ixp2000_err_irq_mask,
 436         .unmask = ixp2000_err_irq_unmask
 437 };
 438
 439 static struct irqchip ixp2000_pci_irq_chip = {
 440         .ack    = ixp2000_pci_irq_mask,
 441         .mask   = ixp2000_pci_irq_mask,
 442         .unmask = ixp2000_pci_irq_unmask
 443 };
 444
 445 static void ixp2000_irq_mask(unsigned int irq)
 446 {
 447         ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
 448 }
 449
 450 static void ixp2000_irq_unmask(unsigned int irq)
 451 {
 452         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
 453 }
 454
 455 static struct irqchip ixp2000_irq_chip = {
 456         .ack    = ixp2000_irq_mask,
 457         .mask   = ixp2000_irq_mask,
 458         .unmask = ixp2000_irq_unmask
 459 };
 460
 461 void __init ixp2000_init_irq(void)
 462 {
 463         int irq;
 464
 465         /*
 466          * Mask all sources
 467          */
 468         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
 469         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
 470
 471         /* clear all GPIO edge/level detects */
 472         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
 473         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
 474         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
 475         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
 476         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
 477
 478         /* clear PCI interrupt sources */
 479         ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
 480
 481         /*
 482          * Certain bits in the IRQ status register of the
 483          * IXP2000 are reserved. Instead of trying to map
 484          * things non 1:1 from bit position to IRQ number,
 485          * we mark the reserved IRQs as invalid. This makes
 486          * our mask/unmask code much simpler.
 487          */
 488         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 489                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 490                         set_irq_chip(irq, &ixp2000_irq_chip);
 491                         set_irq_handler(irq, do_level_IRQ);
 492                         set_irq_flags(irq, IRQF_VALID);
 493                 } else set_irq_flags(irq, 0);
 494         }
 495
 496         for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
 497                 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
 498                                 IXP2000_VALID_ERR_IRQ_MASK) {
 499                         set_irq_chip(irq, &ixp2000_err_irq_chip);
 500                         set_irq_handler(irq, do_level_IRQ);
 501                         set_irq_flags(irq, IRQF_VALID);
 502                 }
 503                 else
 504                         set_irq_flags(irq, 0);
 505         }
 506         set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
 507
 508         /*
 509          * GPIO IRQs are invalid until someone sets the interrupt mode
 510          * by calling set_irq_type().
 511          */
 512         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
 513                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
 514                 set_irq_handler(irq, do_level_IRQ);
 515                 set_irq_flags(irq, 0);
 516         }
 517         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 518
 519         /*
 520          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
 521          * entry-macro.S, so we don't need a chained handler for the
 522          * PCI interrupt source.
 523          */
 524         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 525         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 526                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
 527                 set_irq_handler(irq, do_level_IRQ);
 528                 set_irq_flags(irq, IRQF_VALID);
 529         }
 530 }
 531