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gma500: begin adding GEM
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / gma500 / psb_drv.c
blob725feb2a69cbc11d61719ce317500d28caca2229
1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "psb_fb.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include <drm/drm_pciids.h>
31 #include "psb_powermgmt.h"
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/spinlock.h>
35 #include <linux/pm_runtime.h>
36 #include <acpi/video.h>
37
38 int drm_psb_debug;
39 static int drm_psb_trap_pagefaults;
40
41 int drm_psb_no_fb;
42
43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44
45 MODULE_PARM_DESC(debug, "Enable debug output");
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(debug, drm_psb_debug, int, 0600);
49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
51
52
53 static struct pci_device_id pciidlist[] = {
54 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
55 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
64 { 0, 0, 0}
65 };
66 MODULE_DEVICE_TABLE(pci, pciidlist);
67
68 /*
69 * Standard IOCTLs.
70 */
71
72 #define DRM_IOCTL_PSB_KMS_OFF \
73 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
74 #define DRM_IOCTL_PSB_KMS_ON \
75 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
76 #define DRM_IOCTL_PSB_SIZES \
77 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
78 struct drm_psb_sizes_arg)
79 #define DRM_IOCTL_PSB_FUSE_REG \
80 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
81 #define DRM_IOCTL_PSB_DC_STATE \
82 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
83 struct drm_psb_dc_state_arg)
84 #define DRM_IOCTL_PSB_ADB \
85 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
86 #define DRM_IOCTL_PSB_MODE_OPERATION \
87 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
88 struct drm_psb_mode_operation_arg)
89 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
90 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
91 struct drm_psb_stolen_memory_arg)
92 #define DRM_IOCTL_PSB_REGISTER_RW \
93 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
94 struct drm_psb_register_rw_arg)
95 #define DRM_IOCTL_PSB_DPST \
96 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
97 uint32_t)
98 #define DRM_IOCTL_PSB_GAMMA \
99 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
100 struct drm_psb_dpst_lut_arg)
101 #define DRM_IOCTL_PSB_DPST_BL \
102 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
103 uint32_t)
104 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
105 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
106 struct drm_psb_get_pipe_from_crtc_id_arg)
107
108 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
109 struct drm_file *file_priv);
110 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
111 struct drm_file *file_priv);
112 static int psb_adb_ioctl(struct drm_device *dev, void *data,
113 struct drm_file *file_priv);
114 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv);
116 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv);
118 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
119 struct drm_file *file_priv);
120 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
121 struct drm_file *file_priv);
122 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
123 struct drm_file *file_priv);
124 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv);
126
127 #define PSB_IOCTL_DEF(ioctl, func, flags) \
128 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
129
130 static struct drm_ioctl_desc psb_ioctls[] = {
131 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
132 DRM_ROOT_ONLY),
133 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
134 psbfb_kms_on_ioctl,
135 DRM_ROOT_ONLY),
136 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
137 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
138 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
139 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
140 DRM_AUTH),
141 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
142 DRM_AUTH),
143 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
144 DRM_AUTH),
145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
146 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
148 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
149 psb_intel_get_pipe_from_crtc_id, 0),
150
151 };
152
153 static void psb_lastclose(struct drm_device *dev)
154 {
155 return;
156 }
157
158 static void psb_do_takedown(struct drm_device *dev)
159 {
160 /* FIXME: do we need to clean up the gtt here ? */
161 }
162
163 void mrst_get_fuse_settings(struct drm_device *dev)
164 {
165 struct drm_psb_private *dev_priv = dev->dev_private;
166 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
167 uint32_t fuse_value = 0;
168 uint32_t fuse_value_tmp = 0;
169
170 #define FB_REG06 0xD0810600
171 #define FB_MIPI_DISABLE (1 << 11)
172 #define FB_REG09 0xD0810900
173 #define FB_REG09 0xD0810900
174 #define FB_SKU_MASK 0x7000
175 #define FB_SKU_SHIFT 12
176 #define FB_SKU_100 0
177 #define FB_SKU_100L 1
178 #define FB_SKU_83 2
179 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
180 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
181
182 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
183
184 DRM_INFO("internal display is %s\n",
185 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
186
187 /*prevent Runtime suspend at start*/
188 if (dev_priv->iLVDS_enable) {
189 dev_priv->is_lvds_on = true;
190 dev_priv->is_mipi_on = false;
191 }
192 else {
193 dev_priv->is_mipi_on = true;
194 dev_priv->is_lvds_on = false;
195 }
196
197 dev_priv->video_device_fuse = fuse_value;
198
199 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
200 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
201
202 DRM_INFO("SKU values is 0x%x. \n", fuse_value);
203 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
204
205 dev_priv->fuse_reg_value = fuse_value;
206
207 switch (fuse_value_tmp) {
208 case FB_SKU_100:
209 dev_priv->core_freq = 200;
210 break;
211 case FB_SKU_100L:
212 dev_priv->core_freq = 100;
213 break;
214 case FB_SKU_83:
215 dev_priv->core_freq = 166;
216 break;
217 default:
218 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
219 dev_priv->core_freq = 0;
220 }
221 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
222 pci_dev_put(pci_root);
223 }
224
225 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
226 {
227 uint32_t platform_rev_id = 0;
228 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
229
230 /*get the revison ID, B0:D2:F0;0x08 */
231 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
232 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
233 pci_dev_put(pci_gfx_root);
234 PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
235 }
236
237 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
238 {
239 struct mrst_vbt *vbt = &dev_priv->vbt_data;
240 u32 platform_config_address;
241 u16 new_size;
242 u8 *vbt_virtual;
243 u8 bpi;
244 u8 number_desc = 0;
245 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
246 struct gct_r10_timing_info ti;
247 void *pGCT;
248 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
249
250 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
251 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
252 pci_dev_put(pci_gfx_root);
253 DRM_INFO("drm platform config address is %x\n",
254 platform_config_address);
255
256 /* check for platform config address == 0. */
257 /* this means fw doesn't support vbt */
258
259 if (platform_config_address == 0) {
260 vbt->size = 0;
261 return;
262 }
263
264 /* get the virtual address of the vbt */
265 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
266
267 memcpy(vbt, vbt_virtual, sizeof(*vbt));
268 iounmap(vbt_virtual); /* Free virtual address space */
269
270 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
271
272 switch (vbt->revision) {
273 case 0:
274 vbt->mrst_gct = NULL;
275 vbt->mrst_gct = \
276 ioremap(platform_config_address + sizeof(*vbt) - 4,
277 vbt->size - sizeof(*vbt) + 4);
278 pGCT = vbt->mrst_gct;
279 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
280 dev_priv->gct_data.bpi = bpi;
281 dev_priv->gct_data.pt =
282 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
283 memcpy(&dev_priv->gct_data.DTD,
284 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
285 sizeof(struct mrst_timing_info));
286 dev_priv->gct_data.Panel_Port_Control =
287 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
288 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
289 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
290 break;
291 case 1:
292 vbt->mrst_gct = NULL;
293 vbt->mrst_gct = \
294 ioremap(platform_config_address + sizeof(*vbt) - 4,
295 vbt->size - sizeof(*vbt) + 4);
296 pGCT = vbt->mrst_gct;
297 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
298 dev_priv->gct_data.bpi = bpi;
299 dev_priv->gct_data.pt =
300 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
301 memcpy(&dev_priv->gct_data.DTD,
302 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
303 sizeof(struct mrst_timing_info));
304 dev_priv->gct_data.Panel_Port_Control =
305 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
306 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
307 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
308 break;
309 case 0x10:
310 /*header definition changed from rev 01 (v2) to rev 10h. */
311 /*so, some values have changed location*/
312 new_size = vbt->checksum; /*checksum contains lo size byte*/
313 /*LSB of mrst_gct contains hi size byte*/
314 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
315
316 vbt->checksum = vbt->size; /*size contains the checksum*/
317 if (new_size > 0xff)
318 vbt->size = 0xff; /*restrict size to 255*/
319 else
320 vbt->size = new_size;
321
322 /* number of descriptors defined in the GCT */
323 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
324 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
325 vbt->mrst_gct = NULL;
326 vbt->mrst_gct = \
327 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
328 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
329 pGCT = vbt->mrst_gct;
330 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
331 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
332
333 /*copy the GCT display timings into a temp structure*/
334 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
335
336 /*now copy the temp struct into the dev_priv->gct_data*/
337 dp_ti->pixel_clock = ti.pixel_clock;
338 dp_ti->hactive_hi = ti.hactive_hi;
339 dp_ti->hactive_lo = ti.hactive_lo;
340 dp_ti->hblank_hi = ti.hblank_hi;
341 dp_ti->hblank_lo = ti.hblank_lo;
342 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
343 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
344 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
345 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
346 dp_ti->vactive_hi = ti.vactive_hi;
347 dp_ti->vactive_lo = ti.vactive_lo;
348 dp_ti->vblank_hi = ti.vblank_hi;
349 dp_ti->vblank_lo = ti.vblank_lo;
350 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
351 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
352 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
353 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
354
355 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
356 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
357 *((u8 *)pGCT + 0x0d);
358 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
359 (*((u8 *)pGCT + 0x0e)) << 8;
360 break;
361 default:
362 printk(KERN_ERR "Unknown revision of GCT!\n");
363 vbt->size = 0;
364 }
365 }
366
367 static void psb_get_core_freq(struct drm_device *dev)
368 {
369 uint32_t clock;
370 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
371 struct drm_psb_private *dev_priv = dev->dev_private;
372
373 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
374 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
375
376 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
377 pci_read_config_dword(pci_root, 0xD4, &clock);
378 pci_dev_put(pci_root);
379
380 switch (clock & 0x07) {
381 case 0:
382 dev_priv->core_freq = 100;
383 break;
384 case 1:
385 dev_priv->core_freq = 133;
386 break;
387 case 2:
388 dev_priv->core_freq = 150;
389 break;
390 case 3:
391 dev_priv->core_freq = 178;
392 break;
393 case 4:
394 dev_priv->core_freq = 200;
395 break;
396 case 5:
397 case 6:
398 case 7:
399 dev_priv->core_freq = 266;
400 default:
401 dev_priv->core_freq = 0;
402 }
403 }
404
405 static int psb_do_init(struct drm_device *dev)
406 {
407 struct drm_psb_private *dev_priv =
408 (struct drm_psb_private *) dev->dev_private;
409 struct psb_gtt *pg = dev_priv->pg;
410
411 uint32_t stolen_gtt;
412 uint32_t tt_start;
413 uint32_t tt_pages;
414
415 int ret = -ENOMEM;
416
417 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
418 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
419 ret = -EINVAL;
420 goto out_err;
421 }
422
423
424 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
425 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
426 stolen_gtt =
427 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
428
429 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
430 (stolen_gtt << PAGE_SHIFT) * 1024;
431
432 if (1 || drm_debug) {
433 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
434 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
435 DRM_INFO("SGX core id = 0x%08x\n", core_id);
436 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
437 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
438 _PSB_CC_REVISION_MAJOR_SHIFT,
439 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
440 _PSB_CC_REVISION_MINOR_SHIFT);
441 DRM_INFO
442 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
443 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
444 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
445 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
446 _PSB_CC_REVISION_DESIGNER_SHIFT);
447 }
448
449
450 spin_lock_init(&dev_priv->irqmask_lock);
451
452 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
453 pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
454 tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
455 tt_pages -= tt_start >> PAGE_SHIFT;
456 /* FIXME: can we kill ta_mem_size ? */
457 dev_priv->sizes.ta_mem_size = 0;
458
459 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
460 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
461 PSB_RSGX32(PSB_CR_BIF_BANK1);
462 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
463 PSB_CR_BIF_CTRL);
464 psb_spank(dev_priv);
465
466 /* mmu_gatt ?? */
467 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
468
469 return 0;
470 out_err:
471 psb_do_takedown(dev);
472 return ret;
473 }
474
475 static int psb_driver_unload(struct drm_device *dev)
476 {
477 struct drm_psb_private *dev_priv =
478 (struct drm_psb_private *) dev->dev_private;
479
480 /* Kill vblank etc here */
481
482 psb_backlight_exit(); /*writes minimum value to backlight HW reg */
483
484 if (drm_psb_no_fb == 0)
485 psb_modeset_cleanup(dev);
486
487 if (dev_priv) {
488 psb_lid_timer_takedown(dev_priv);
489
490 psb_do_takedown(dev);
491
492
493 if (dev_priv->pf_pd) {
494 psb_mmu_free_pagedir(dev_priv->pf_pd);
495 dev_priv->pf_pd = NULL;
496 }
497 if (dev_priv->mmu) {
498 struct psb_gtt *pg = dev_priv->pg;
499
500 down_read(&pg->sem);
501 psb_mmu_remove_pfn_sequence(
502 psb_mmu_get_default_pd
503 (dev_priv->mmu),
504 pg->mmu_gatt_start,
505 pg->vram_stolen_size >> PAGE_SHIFT);
506 up_read(&pg->sem);
507 psb_mmu_driver_takedown(dev_priv->mmu);
508 dev_priv->mmu = NULL;
509 }
510 psb_gtt_takedown(dev_priv->pg, 1);
511 if (dev_priv->scratch_page) {
512 __free_page(dev_priv->scratch_page);
513 dev_priv->scratch_page = NULL;
514 }
515 if (dev_priv->vdc_reg) {
516 iounmap(dev_priv->vdc_reg);
517 dev_priv->vdc_reg = NULL;
518 }
519 if (dev_priv->sgx_reg) {
520 iounmap(dev_priv->sgx_reg);
521 dev_priv->sgx_reg = NULL;
522 }
523
524 kfree(dev_priv);
525 dev->dev_private = NULL;
526
527 /*destroy VBT data*/
528 psb_intel_destroy_bios(dev);
529 }
530
531 gma_power_uninit(dev);
532
533 return 0;
534 }
535
536
537 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
538 {
539 struct drm_psb_private *dev_priv;
540 unsigned long resource_start;
541 struct psb_gtt *pg;
542 unsigned long irqflags;
543 int ret = -ENOMEM;
544 uint32_t tt_pages;
545
546 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
547 if (dev_priv == NULL)
548 return -ENOMEM;
549
550 if (IS_MRST(dev))
551 dev_priv->num_pipe = 1;
552 else
553 dev_priv->num_pipe = 2;
554
555 dev_priv->dev = dev;
556
557 dev->dev_private = (void *) dev_priv;
558 dev_priv->chipset = chipset;
559
560 PSB_DEBUG_INIT("Mapping MMIO\n");
561 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
562
563 dev_priv->vdc_reg =
564 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
565 if (!dev_priv->vdc_reg)
566 goto out_err;
567
568 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
569 PSB_SGX_SIZE);
570
571 if (!dev_priv->sgx_reg)
572 goto out_err;
573
574 if (IS_MRST(dev)) {
575 mrst_get_fuse_settings(dev);
576 mrst_get_vbt_data(dev_priv);
577 mid_get_pci_revID(dev_priv);
578 } else {
579 psb_get_core_freq(dev);
580 psb_intel_opregion_init(dev);
581 psb_intel_init_bios(dev);
582 }
583
584 /* Init OSPM support */
585 gma_power_init(dev);
586
587 ret = -ENOMEM;
588
589 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
590 if (!dev_priv->scratch_page)
591 goto out_err;
592
593 set_pages_uc(dev_priv->scratch_page, 1);
594
595 dev_priv->pg = psb_gtt_alloc(dev);
596 if (!dev_priv->pg)
597 goto out_err;
598
599 ret = psb_gtt_init(dev_priv->pg, 0);
600 if (ret)
601 goto out_err;
602
603 ret = psb_gtt_mm_init(dev_priv->pg);
604 if (ret)
605 goto out_err;
606
607 dev_priv->mmu = psb_mmu_driver_init((void *)0,
608 drm_psb_trap_pagefaults, 0,
609 dev_priv);
610 if (!dev_priv->mmu)
611 goto out_err;
612
613 pg = dev_priv->pg;
614
615 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
616 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
617
618
619 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
620 if (!dev_priv->pf_pd)
621 goto out_err;
622
623 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
624 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
625
626 ret = psb_do_init(dev);
627 if (ret)
628 return ret;
629
630 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
631 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
632
633 /* igd_opregion_init(&dev_priv->opregion_dev); */
634 acpi_video_register();
635 if (dev_priv->lid_state)
636 psb_lid_timer_init(dev_priv);
637
638 ret = drm_vblank_init(dev, dev_priv->num_pipe);
639 if (ret)
640 goto out_err;
641
642 /*
643 * Install interrupt handlers prior to powering off SGX or else we will
644 * crash.
645 */
646 dev_priv->vdc_irq_mask = 0;
647 dev_priv->pipestat[0] = 0;
648 dev_priv->pipestat[1] = 0;
649 dev_priv->pipestat[2] = 0;
650 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
651 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
652 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
653 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
654 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
655 if (drm_core_check_feature(dev, DRIVER_MODESET))
656 drm_irq_install(dev);
657
658 dev->vblank_disable_allowed = 1;
659
660 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
661
662 dev->driver->get_vblank_counter = psb_get_vblank_counter;
663
664 if (drm_psb_no_fb == 0) {
665 psb_modeset_init(dev);
666 psb_fbdev_init(dev);
667 drm_kms_helper_poll_init(dev);
668 }
669
670 ret = psb_backlight_init(dev);
671 if (ret)
672 return ret;
673 #if 0
674 /*enable runtime pm at last*/
675 pm_runtime_enable(&dev->pdev->dev);
676 pm_runtime_set_active(&dev->pdev->dev);
677 #endif
678 /*Intel drm driver load is done, continue doing pvr load*/
679 DRM_DEBUG("Pvr driver load\n");
680 return 0;
681 out_err:
682 psb_driver_unload(dev);
683 return ret;
684 }
685
686 int psb_driver_device_is_agp(struct drm_device *dev)
687 {
688 return 0;
689 }
690
691
692 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
693 struct drm_file *file_priv)
694 {
695 struct drm_psb_private *dev_priv = psb_priv(dev);
696 struct drm_psb_sizes_arg *arg =
697 (struct drm_psb_sizes_arg *) data;
698
699 *arg = dev_priv->sizes;
700 return 0;
701 }
702
703 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
704 struct drm_file *file_priv)
705 {
706 uint32_t flags;
707 uint32_t obj_id;
708 struct drm_mode_object *obj;
709 struct drm_connector *connector;
710 struct drm_crtc *crtc;
711 struct drm_psb_dc_state_arg *arg =
712 (struct drm_psb_dc_state_arg *)data;
713
714 flags = arg->flags;
715 obj_id = arg->obj_id;
716
717 if (flags & PSB_DC_CRTC_MASK) {
718 obj = drm_mode_object_find(dev, obj_id,
719 DRM_MODE_OBJECT_CRTC);
720 if (!obj) {
721 DRM_DEBUG("Invalid CRTC object.\n");
722 return -EINVAL;
723 }
724
725 crtc = obj_to_crtc(obj);
726
727 mutex_lock(&dev->mode_config.mutex);
728 if (drm_helper_crtc_in_use(crtc)) {
729 if (flags & PSB_DC_CRTC_SAVE)
730 crtc->funcs->save(crtc);
731 else
732 crtc->funcs->restore(crtc);
733 }
734 mutex_unlock(&dev->mode_config.mutex);
735
736 return 0;
737 } else if (flags & PSB_DC_OUTPUT_MASK) {
738 obj = drm_mode_object_find(dev, obj_id,
739 DRM_MODE_OBJECT_CONNECTOR);
740 if (!obj) {
741 DRM_DEBUG("Invalid connector id.\n");
742 return -EINVAL;
743 }
744
745 connector = obj_to_connector(obj);
746 if (flags & PSB_DC_OUTPUT_SAVE)
747 connector->funcs->save(connector);
748 else
749 connector->funcs->restore(connector);
750
751 return 0;
752 }
753
754 DRM_DEBUG("Bad flags 0x%x\n", flags);
755 return -EINVAL;
756 }
757
758 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
759 struct drm_file *file_priv)
760 {
761 struct drm_psb_private *dev_priv = psb_priv(dev);
762 uint32_t *arg = data;
763 struct backlight_device bd;
764 dev_priv->blc_adj2 = *arg;
765
766 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
767 bd.props.brightness = psb_get_brightness(&bd);
768 psb_set_brightness(&bd);
769 #endif
770 return 0;
771 }
772
773 static int psb_adb_ioctl(struct drm_device *dev, void *data,
774 struct drm_file *file_priv)
775 {
776 struct drm_psb_private *dev_priv = psb_priv(dev);
777 uint32_t *arg = data;
778 struct backlight_device bd;
779 dev_priv->blc_adj1 = *arg;
780
781 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
782 bd.props.brightness = psb_get_brightness(&bd);
783 psb_set_brightness(&bd);
784 #endif
785 return 0;
786 }
787
788 /* return the current mode to the dpst module */
789 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
790 struct drm_file *file_priv)
791 {
792 struct drm_psb_private *dev_priv = psb_priv(dev);
793 uint32_t *arg = data;
794 uint32_t x;
795 uint32_t y;
796 uint32_t reg;
797
798 if (!gma_power_begin(dev, 0))
799 return -EIO;
800
801 reg = PSB_RVDC32(PIPEASRC);
802
803 gma_power_end(dev);
804
805 /* horizontal is the left 16 bits */
806 x = reg >> 16;
807 /* vertical is the right 16 bits */
808 y = reg & 0x0000ffff;
809
810 /* the values are the image size minus one */
811 x++;
812 y++;
813
814 *arg = (x << 16) | y;
815
816 return 0;
817 }
818 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
819 struct drm_file *file_priv)
820 {
821 struct drm_psb_dpst_lut_arg *lut_arg = data;
822 struct drm_mode_object *obj;
823 struct drm_crtc *crtc;
824 struct drm_connector *connector;
825 struct psb_intel_crtc *psb_intel_crtc;
826 int i = 0;
827 int32_t obj_id;
828
829 obj_id = lut_arg->output_id;
830 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
831 if (!obj) {
832 DRM_DEBUG("Invalid Connector object.\n");
833 return -EINVAL;
834 }
835
836 connector = obj_to_connector(obj);
837 crtc = connector->encoder->crtc;
838 psb_intel_crtc = to_psb_intel_crtc(crtc);
839
840 for (i = 0; i < 256; i++)
841 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
842
843 psb_intel_crtc_load_lut(crtc);
844
845 return 0;
846 }
847
848 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file_priv)
850 {
851 uint32_t obj_id;
852 uint16_t op;
853 struct drm_mode_modeinfo *umode;
854 struct drm_display_mode *mode = NULL;
855 struct drm_psb_mode_operation_arg *arg;
856 struct drm_mode_object *obj;
857 struct drm_connector *connector;
858 struct drm_framebuffer *drm_fb;
859 struct psb_framebuffer *psb_fb;
860 struct drm_connector_helper_funcs *connector_funcs;
861 int ret = 0;
862 int resp = MODE_OK;
863 struct drm_psb_private *dev_priv = psb_priv(dev);
864
865 arg = (struct drm_psb_mode_operation_arg *)data;
866 obj_id = arg->obj_id;
867 op = arg->operation;
868
869 switch (op) {
870 case PSB_MODE_OPERATION_SET_DC_BASE:
871 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
872 if (!obj) {
873 DRM_ERROR("Invalid FB id %d\n", obj_id);
874 return -EINVAL;
875 }
876
877 drm_fb = obj_to_fb(obj);
878 psb_fb = to_psb_fb(drm_fb);
879
880 if (gma_power_begin(dev, 0)) {
881 REG_WRITE(DSPASURF, psb_fb->offset);
882 REG_READ(DSPASURF);
883 gma_power_end(dev);
884 } else {
885 dev_priv->saveDSPASURF = psb_fb->offset;
886 }
887
888 return 0;
889 case PSB_MODE_OPERATION_MODE_VALID:
890 umode = &arg->mode;
891
892 mutex_lock(&dev->mode_config.mutex);
893
894 obj = drm_mode_object_find(dev, obj_id,
895 DRM_MODE_OBJECT_CONNECTOR);
896 if (!obj) {
897 ret = -EINVAL;
898 goto mode_op_out;
899 }
900
901 connector = obj_to_connector(obj);
902
903 mode = drm_mode_create(dev);
904 if (!mode) {
905 ret = -ENOMEM;
906 goto mode_op_out;
907 }
908
909 /* drm_crtc_convert_umode(mode, umode); */
910 {
911 mode->clock = umode->clock;
912 mode->hdisplay = umode->hdisplay;
913 mode->hsync_start = umode->hsync_start;
914 mode->hsync_end = umode->hsync_end;
915 mode->htotal = umode->htotal;
916 mode->hskew = umode->hskew;
917 mode->vdisplay = umode->vdisplay;
918 mode->vsync_start = umode->vsync_start;
919 mode->vsync_end = umode->vsync_end;
920 mode->vtotal = umode->vtotal;
921 mode->vscan = umode->vscan;
922 mode->vrefresh = umode->vrefresh;
923 mode->flags = umode->flags;
924 mode->type = umode->type;
925 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
926 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
927 }
928
929 connector_funcs = (struct drm_connector_helper_funcs *)
930 connector->helper_private;
931
932 if (connector_funcs->mode_valid) {
933 resp = connector_funcs->mode_valid(connector, mode);
934 arg->data = (void *)resp;
935 }
936
937 /*do some clean up work*/
938 if (mode)
939 drm_mode_destroy(dev, mode);
940 mode_op_out:
941 mutex_unlock(&dev->mode_config.mutex);
942 return ret;
943
944 default:
945 DRM_DEBUG("Unsupported psb mode operation");
946 return -EOPNOTSUPP;
947 }
948
949 return 0;
950 }
951
952 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
953 struct drm_file *file_priv)
954 {
955 struct drm_psb_private *dev_priv = psb_priv(dev);
956 struct drm_psb_stolen_memory_arg *arg = data;
957
958 arg->base = dev_priv->pg->stolen_base;
959 arg->size = dev_priv->pg->vram_stolen_size;
960
961 return 0;
962 }
963
964 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
965 struct drm_file *file_priv)
966 {
967 struct drm_psb_private *dev_priv = psb_priv(dev);
968 struct drm_psb_register_rw_arg *arg = data;
969 bool usage = arg->b_force_hw_on ? true : false;
970
971 if (arg->display_write_mask != 0) {
972 if (gma_power_begin(dev, usage)) {
973 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
974 PSB_WVDC32(arg->display.pfit_controls,
975 PFIT_CONTROL);
976 if (arg->display_write_mask &
977 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
978 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
979 PFIT_AUTO_RATIOS);
980 if (arg->display_write_mask &
981 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
982 PSB_WVDC32(
983 arg->display.pfit_programmed_scale_ratios,
984 PFIT_PGM_RATIOS);
985 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
986 PSB_WVDC32(arg->display.pipeasrc,
987 PIPEASRC);
988 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
989 PSB_WVDC32(arg->display.pipebsrc,
990 PIPEBSRC);
991 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
992 PSB_WVDC32(arg->display.vtotal_a,
993 VTOTAL_A);
994 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
995 PSB_WVDC32(arg->display.vtotal_b,
996 VTOTAL_B);
997 gma_power_end(dev);
998 } else {
999 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1000 dev_priv->savePFIT_CONTROL =
1001 arg->display.pfit_controls;
1002 if (arg->display_write_mask &
1003 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1004 dev_priv->savePFIT_AUTO_RATIOS =
1005 arg->display.pfit_autoscale_ratios;
1006 if (arg->display_write_mask &
1007 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1008 dev_priv->savePFIT_PGM_RATIOS =
1009 arg->display.pfit_programmed_scale_ratios;
1010 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1011 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1012 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1013 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1014 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1015 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1016 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1017 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1018 }
1019 }
1020
1021 if (arg->display_read_mask != 0) {
1022 if (gma_power_begin(dev, usage)) {
1023 if (arg->display_read_mask &
1024 REGRWBITS_PFIT_CONTROLS)
1025 arg->display.pfit_controls =
1026 PSB_RVDC32(PFIT_CONTROL);
1027 if (arg->display_read_mask &
1028 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1029 arg->display.pfit_autoscale_ratios =
1030 PSB_RVDC32(PFIT_AUTO_RATIOS);
1031 if (arg->display_read_mask &
1032 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1033 arg->display.pfit_programmed_scale_ratios =
1034 PSB_RVDC32(PFIT_PGM_RATIOS);
1035 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1036 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1037 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1038 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1039 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1040 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1041 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1042 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1043 gma_power_end(dev);
1044 } else {
1045 if (arg->display_read_mask &
1046 REGRWBITS_PFIT_CONTROLS)
1047 arg->display.pfit_controls =
1048 dev_priv->savePFIT_CONTROL;
1049 if (arg->display_read_mask &
1050 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1051 arg->display.pfit_autoscale_ratios =
1052 dev_priv->savePFIT_AUTO_RATIOS;
1053 if (arg->display_read_mask &
1054 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1055 arg->display.pfit_programmed_scale_ratios =
1056 dev_priv->savePFIT_PGM_RATIOS;
1057 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1058 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1059 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1060 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1061 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1062 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1063 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1064 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1065 }
1066 }
1067
1068 if (arg->overlay_write_mask != 0) {
1069 if (gma_power_begin(dev, usage)) {
1070 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1071 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1072 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1073 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1074 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1075 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1076 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1077 }
1078 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1079 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1080 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1081 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1082 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1083 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1084 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1085 }
1086
1087 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1088 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1089
1090 if (arg->overlay.b_wait_vblank) {
1091 /* Wait for 20ms.*/
1092 unsigned long vblank_timeout = jiffies
1093 + HZ/50;
1094 uint32_t temp;
1095 while (time_before_eq(jiffies,
1096 vblank_timeout)) {
1097 temp = PSB_RVDC32(OV_DOVASTA);
1098 if ((temp & (0x1 << 31)) != 0)
1099 break;
1100 cpu_relax();
1101 }
1102 }
1103 }
1104 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1105 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1106 if (arg->overlay.b_wait_vblank) {
1107 /* Wait for 20ms.*/
1108 unsigned long vblank_timeout =
1109 jiffies + HZ/50;
1110 uint32_t temp;
1111 while (time_before_eq(jiffies,
1112 vblank_timeout)) {
1113 temp = PSB_RVDC32(OVC_DOVCSTA);
1114 if ((temp & (0x1 << 31)) != 0)
1115 break;
1116 cpu_relax();
1117 }
1118 }
1119 }
1120 gma_power_end(dev);
1121 } else {
1122 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1123 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1124 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1125 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1126 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1127 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1128 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1129 }
1130 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1131 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1132 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1133 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1134 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1135 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1136 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1137 }
1138 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1139 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1140 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1141 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1142 }
1143 }
1144
1145 if (arg->overlay_read_mask != 0) {
1146 if (gma_power_begin(dev, usage)) {
1147 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1148 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1149 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1150 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1151 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1152 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1153 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1154 }
1155 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1156 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1157 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1158 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1159 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1160 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1161 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1162 }
1163 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1164 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1165 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1166 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1167 gma_power_end(dev);
1168 } else {
1169 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1170 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1171 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1172 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1173 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1174 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1175 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1176 }
1177 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1178 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1179 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1180 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1181 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1182 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1183 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1184 }
1185 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1186 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1187 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1188 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1189 }
1190 }
1191
1192 if (arg->sprite_enable_mask != 0) {
1193 if (gma_power_begin(dev, usage)) {
1194 PSB_WVDC32(0x1F3E, DSPARB);
1195 PSB_WVDC32(arg->sprite.dspa_control
1196 | PSB_RVDC32(DSPACNTR), DSPACNTR);
1197 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1198 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1199 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1200 PSB_RVDC32(DSPASURF);
1201 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1202 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1203 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1204 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1205 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1206 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1207 PSB_RVDC32(DSPCSURF);
1208 gma_power_end(dev);
1209 }
1210 }
1211
1212 if (arg->sprite_disable_mask != 0) {
1213 if (gma_power_begin(dev, usage)) {
1214 PSB_WVDC32(0x3F3E, DSPARB);
1215 PSB_WVDC32(0x0, DSPCCNTR);
1216 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1217 PSB_RVDC32(DSPCSURF);
1218 gma_power_end(dev);
1219 }
1220 }
1221
1222 if (arg->subpicture_enable_mask != 0) {
1223 if (gma_power_begin(dev, usage)) {
1224 uint32_t temp;
1225 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1226 temp = PSB_RVDC32(DSPACNTR);
1227 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1228 temp &= ~DISPPLANE_BOTTOM;
1229 temp |= DISPPLANE_32BPP;
1230 PSB_WVDC32(temp, DSPACNTR);
1231
1232 temp = PSB_RVDC32(DSPABASE);
1233 PSB_WVDC32(temp, DSPABASE);
1234 PSB_RVDC32(DSPABASE);
1235 temp = PSB_RVDC32(DSPASURF);
1236 PSB_WVDC32(temp, DSPASURF);
1237 PSB_RVDC32(DSPASURF);
1238 }
1239 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1240 temp = PSB_RVDC32(DSPBCNTR);
1241 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1242 temp &= ~DISPPLANE_BOTTOM;
1243 temp |= DISPPLANE_32BPP;
1244 PSB_WVDC32(temp, DSPBCNTR);
1245
1246 temp = PSB_RVDC32(DSPBBASE);
1247 PSB_WVDC32(temp, DSPBBASE);
1248 PSB_RVDC32(DSPBBASE);
1249 temp = PSB_RVDC32(DSPBSURF);
1250 PSB_WVDC32(temp, DSPBSURF);
1251 PSB_RVDC32(DSPBSURF);
1252 }
1253 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1254 temp = PSB_RVDC32(DSPCCNTR);
1255 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1256 temp &= ~DISPPLANE_BOTTOM;
1257 temp |= DISPPLANE_32BPP;
1258 PSB_WVDC32(temp, DSPCCNTR);
1259
1260 temp = PSB_RVDC32(DSPCBASE);
1261 PSB_WVDC32(temp, DSPCBASE);
1262 PSB_RVDC32(DSPCBASE);
1263 temp = PSB_RVDC32(DSPCSURF);
1264 PSB_WVDC32(temp, DSPCSURF);
1265 PSB_RVDC32(DSPCSURF);
1266 }
1267 gma_power_end(dev);
1268 }
1269 }
1270
1271 if (arg->subpicture_disable_mask != 0) {
1272 if (gma_power_begin(dev, usage)) {
1273 uint32_t temp;
1274 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1275 temp = PSB_RVDC32(DSPACNTR);
1276 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1277 temp |= DISPPLANE_32BPP_NO_ALPHA;
1278 PSB_WVDC32(temp, DSPACNTR);
1279
1280 temp = PSB_RVDC32(DSPABASE);
1281 PSB_WVDC32(temp, DSPABASE);
1282 PSB_RVDC32(DSPABASE);
1283 temp = PSB_RVDC32(DSPASURF);
1284 PSB_WVDC32(temp, DSPASURF);
1285 PSB_RVDC32(DSPASURF);
1286 }
1287 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1288 temp = PSB_RVDC32(DSPBCNTR);
1289 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1290 temp |= DISPPLANE_32BPP_NO_ALPHA;
1291 PSB_WVDC32(temp, DSPBCNTR);
1292
1293 temp = PSB_RVDC32(DSPBBASE);
1294 PSB_WVDC32(temp, DSPBBASE);
1295 PSB_RVDC32(DSPBBASE);
1296 temp = PSB_RVDC32(DSPBSURF);
1297 PSB_WVDC32(temp, DSPBSURF);
1298 PSB_RVDC32(DSPBSURF);
1299 }
1300 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1301 temp = PSB_RVDC32(DSPCCNTR);
1302 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1303 temp |= DISPPLANE_32BPP_NO_ALPHA;
1304 PSB_WVDC32(temp, DSPCCNTR);
1305
1306 temp = PSB_RVDC32(DSPCBASE);
1307 PSB_WVDC32(temp, DSPCBASE);
1308 PSB_RVDC32(DSPCBASE);
1309 temp = PSB_RVDC32(DSPCSURF);
1310 PSB_WVDC32(temp, DSPCSURF);
1311 PSB_RVDC32(DSPCSURF);
1312 }
1313 gma_power_end(dev);
1314 }
1315 }
1316
1317 return 0;
1318 }
1319
1320 /* always available as we are SIGIO'd */
1321 static unsigned int psb_poll(struct file *filp,
1322 struct poll_table_struct *wait)
1323 {
1324 return POLLIN | POLLRDNORM;
1325 }
1326
1327 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1328 {
1329 return 0;
1330 }
1331
1332 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1333 {
1334 }
1335
1336 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1337 unsigned long arg)
1338 {
1339 struct drm_file *file_priv = filp->private_data;
1340 struct drm_device *dev = file_priv->minor->dev;
1341 struct drm_psb_private *dev_priv = dev->dev_private;
1342 static unsigned int runtime_allowed;
1343 unsigned int nr = DRM_IOCTL_NR(cmd);
1344
1345 DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1346
1347 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1348 runtime_allowed++;
1349 pm_runtime_allow(&dev->pdev->dev);
1350 dev_priv->rpm_enabled = 1;
1351 }
1352 /*
1353 * The driver private ioctls should be thread-safe.
1354 */
1355
1356 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1357 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1358 struct drm_ioctl_desc *ioctl =
1359 &psb_ioctls[nr - DRM_COMMAND_BASE];
1360
1361 if (unlikely(ioctl->cmd != cmd)) {
1362 DRM_ERROR(
1363 "Invalid drm cmnd %d ioctl->cmd %x, cmd %x\n",
1364 nr - DRM_COMMAND_BASE, ioctl->cmd, cmd);
1365 return -EINVAL;
1366 }
1367
1368 return drm_ioctl(filp, cmd, arg);
1369 }
1370 /*
1371 * Not all old drm ioctls are thread-safe.
1372 */
1373
1374 return drm_ioctl(filp, cmd, arg);
1375 }
1376
1377
1378 /* When a client dies:
1379 * - Check for and clean up flipped page state
1380 */
1381 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1382 {
1383 }
1384
1385 static void psb_remove(struct pci_dev *pdev)
1386 {
1387 struct drm_device *dev = pci_get_drvdata(pdev);
1388 drm_put_dev(dev);
1389 }
1390
1391 static int psb_open(struct inode *inode, struct file *filp)
1392 {
1393 return 0;
1394 }
1395
1396 static int psb_release(struct inode *inode, struct file *filp)
1397 {
1398 return 0;
1399 }
1400
1401
1402 static const struct dev_pm_ops psb_pm_ops = {
1403 .runtime_suspend = psb_runtime_suspend,
1404 .runtime_resume = psb_runtime_resume,
1405 .runtime_idle = psb_runtime_idle,
1406 };
1407
1408 static struct vm_operations_struct psb_gem_vm_ops = {
1409 .fault = psb_gem_fault,
1410 .open = drm_gem_vm_open,
1411 .close = drm_gem_vm_close,
1412 };
1413
1414 static struct drm_driver driver = {
1415 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1416 DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
1417 .load = psb_driver_load,
1418 .unload = psb_driver_unload,
1419
1420 .ioctls = psb_ioctls,
1421 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1422 .device_is_agp = psb_driver_device_is_agp,
1423 .irq_preinstall = psb_irq_preinstall,
1424 .irq_postinstall = psb_irq_postinstall,
1425 .irq_uninstall = psb_irq_uninstall,
1426 .irq_handler = psb_irq_handler,
1427 .enable_vblank = psb_enable_vblank,
1428 .disable_vblank = psb_disable_vblank,
1429 .get_vblank_counter = psb_get_vblank_counter,
1430 .lastclose = psb_lastclose,
1431 .open = psb_driver_open,
1432 .preclose = psb_driver_preclose,
1433 .postclose = psb_driver_close,
1434 .reclaim_buffers = drm_core_reclaim_buffers,
1435
1436 .gem_init_object = psb_gem_init_object,
1437 .gem_free_object = psb_gem_free_object,
1438 .gem_vm_ops = &psb_gem_vm_ops,
1439 .dumb_create = psb_gem_dumb_create,
1440 .dumb_map_offset = psb_gem_dumb_map_gtt,
1441 .dumb_destroy = psb_gem_dumb_destroy,
1442
1443 .fops = {
1444 .owner = THIS_MODULE,
1445 .open = psb_open,
1446 .release = psb_release,
1447 .unlocked_ioctl = psb_unlocked_ioctl,
1448 /* .mmap = psb_mmap, */
1449 .poll = psb_poll,
1450 .fasync = drm_fasync,
1451 .read = drm_read,
1452 },
1453 .name = DRIVER_NAME,
1454 .desc = DRIVER_DESC,
1455 .date = PSB_DRM_DRIVER_DATE,
1456 .major = PSB_DRM_DRIVER_MAJOR,
1457 .minor = PSB_DRM_DRIVER_MINOR,
1458 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1459 };
1460
1461 static struct pci_driver psb_pci_driver = {
1462 .name = DRIVER_NAME,
1463 .id_table = pciidlist,
1464 .resume = gma_power_resume,
1465 .suspend = gma_power_suspend,
1466 .probe = psb_probe,
1467 .remove = psb_remove,
1468 #ifdef CONFIG_PM
1469 .driver.pm = &psb_pm_ops,
1470 #endif
1471 };
1472
1473 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1474 {
1475 /* MLD Added this from Inaky's patch */
1476 if (pci_enable_msi(pdev))
1477 DRM_ERROR("Enable MSI failed!\n");
1478 return drm_get_pci_dev(pdev, ent, &driver);
1479 }
1480
1481 static int __init psb_init(void)
1482 {
1483 return drm_pci_init(&driver, &psb_pci_driver);
1484 }
1485
1486 static void __exit psb_exit(void)
1487 {
1488 drm_pci_exit(&driver, &psb_pci_driver);
1489 }
1490
1491 late_initcall(psb_init);
1492 module_exit(psb_exit);
1493
1494 MODULE_AUTHOR(DRIVER_AUTHOR);
1495 MODULE_DESCRIPTION(DRIVER_DESC);
1496 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree