arch/mips/include/asm/system.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/types.h>
  16 #include <linux/irqflags.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/barrier.h>
  20 #include <asm/cmpxchg.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/dsp.h>
  23 #include <asm/watch.h>
  24 #include <asm/war.h>
  25
  26
  27 /*
  28  * switch_to(n) should switch tasks to task nr n, first
  29  * checking that n isn't the current task, in which case it does nothing.
  30  */
  31 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
  32
  33 struct task_struct;
  34
  35 extern unsigned int ll_bit;
  36 extern struct task_struct *ll_task;
  37
  38 #ifdef CONFIG_MIPS_MT_FPAFF
  39
  40 /*
  41  * Handle the scheduler resume end of FPU affinity management.  We do this
  42  * inline to try to keep the overhead down. If we have been forced to run on
  43  * a "CPU" with an FPU because of a previous high level of FP computation,
  44  * but did not actually use the FPU during the most recent time-slice (CU1
  45  * isn't set), we undo the restriction on cpus_allowed.
  46  *
  47  * We're not calling set_cpus_allowed() here, because we have no need to
  48  * force prompt migration - we're already switching the current CPU to a
  49  * different thread.
  50  */
  51
  52 #define __mips_mt_fpaff_switch_to(prev)                                 \
  53 do {                                                                    \
  54         struct thread_info *__prev_ti = task_thread_info(prev);         \
  55                                                                         \
  56         if (cpu_has_fpu &&                                              \
  57             test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
  58             (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
  59                 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
  60                 prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
  61         }                                                               \
  62         next->thread.emulated_fp = 0;                                   \
  63 } while(0)
  64
  65 #else
  66 #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
  67 #endif
  68
  69 #ifdef CONFIG_CPU_HAS_LLSC
  70 #define __clear_software_ll_bit() do { } while (0)
  71 #else
  72 extern unsigned long ll_bit;
  73
  74 #define __clear_software_ll_bit()                                       \
  75 do {                                                                    \
  76         ll_bit = 0;                                                     \
  77 } while (0)
  78 #endif
  79
  80 #define switch_to(prev, next, last)                                     \
  81 do {                                                                    \
  82         __mips_mt_fpaff_switch_to(prev);                                \
  83         if (cpu_has_dsp)                                                \
  84                 __save_dsp(prev);                                       \
  85         __clear_software_ll_bit();                                      \
  86         (last) = resume(prev, next, task_thread_info(next));            \
  87 } while (0)
  88
  89 #define finish_arch_switch(prev)                                        \
  90 do {                                                                    \
  91         if (cpu_has_dsp)                                                \
  92                 __restore_dsp(current);                                 \
  93         if (cpu_has_userlocal)                                          \
  94                 write_c0_userlocal(current_thread_info()->tp_value);    \
  95         __restore_watch();                                              \
  96 } while (0)
  97
  98 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
  99 {
 100         __u32 retval;
 101
 102         if (cpu_has_llsc && R10000_LLSC_WAR) {
 103                 unsigned long dummy;
 104
 105                 __asm__ __volatile__(
 106                 "       .set    mips3                                   \n"
 107                 "1:     ll      %0, %3                  # xchg_u32      \n"
 108                 "       .set    mips0                                   \n"
 109                 "       move    %2, %z4                                 \n"
 110                 "       .set    mips3                                   \n"
 111                 "       sc      %2, %1                                  \n"
 112                 "       beqzl   %2, 1b                                  \n"
 113                 "       .set    mips0                                   \n"
 114                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 115                 : "R" (*m), "Jr" (val)
 116                 : "memory");
 117         } else if (cpu_has_llsc) {
 118                 unsigned long dummy;
 119
 120                 __asm__ __volatile__(
 121                 "       .set    mips3                                   \n"
 122                 "1:     ll      %0, %3                  # xchg_u32      \n"
 123                 "       .set    mips0                                   \n"
 124                 "       move    %2, %z4                                 \n"
 125                 "       .set    mips3                                   \n"
 126                 "       sc      %2, %1                                  \n"
 127                 "       beqz    %2, 2f                                  \n"
 128                 "       .subsection 2                                   \n"
 129                 "2:     b       1b                                      \n"
 130                 "       .previous                                       \n"
 131                 "       .set    mips0                                   \n"
 132                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 133                 : "R" (*m), "Jr" (val)
 134                 : "memory");
 135         } else {
 136                 unsigned long flags;
 137
 138                 raw_local_irq_save(flags);
 139                 retval = *m;
 140                 *m = val;
 141                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 142         }
 143
 144         smp_llsc_mb();
 145
 146         return retval;
 147 }
 148
 149 #ifdef CONFIG_64BIT
 150 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 151 {
 152         __u64 retval;
 153
 154         if (cpu_has_llsc && R10000_LLSC_WAR) {
 155                 unsigned long dummy;
 156
 157                 __asm__ __volatile__(
 158                 "       .set    mips3                                   \n"
 159                 "1:     lld     %0, %3                  # xchg_u64      \n"
 160                 "       move    %2, %z4                                 \n"
 161                 "       scd     %2, %1                                  \n"
 162                 "       beqzl   %2, 1b                                  \n"
 163                 "       .set    mips0                                   \n"
 164                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 165                 : "R" (*m), "Jr" (val)
 166                 : "memory");
 167         } else if (cpu_has_llsc) {
 168                 unsigned long dummy;
 169
 170                 __asm__ __volatile__(
 171                 "       .set    mips3                                   \n"
 172                 "1:     lld     %0, %3                  # xchg_u64      \n"
 173                 "       move    %2, %z4                                 \n"
 174                 "       scd     %2, %1                                  \n"
 175                 "       beqz    %2, 2f                                  \n"
 176                 "       .subsection 2                                   \n"
 177                 "2:     b       1b                                      \n"
 178                 "       .previous                                       \n"
 179                 "       .set    mips0                                   \n"
 180                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 181                 : "R" (*m), "Jr" (val)
 182                 : "memory");
 183         } else {
 184                 unsigned long flags;
 185
 186                 raw_local_irq_save(flags);
 187                 retval = *m;
 188                 *m = val;
 189                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 190         }
 191
 192         smp_llsc_mb();
 193
 194         return retval;
 195 }
 196 #else
 197 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 198 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 199 #endif
 200
 201 /* This function doesn't exist, so you'll get a linker error
 202    if something tries to do an invalid xchg().  */
 203 extern void __xchg_called_with_bad_pointer(void);
 204
 205 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 206 {
 207         switch (size) {
 208         case 4:
 209                 return __xchg_u32(ptr, x);
 210         case 8:
 211                 return __xchg_u64(ptr, x);
 212         }
 213         __xchg_called_with_bad_pointer();
 214         return x;
 215 }
 216
 217 #define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
 218
 219 extern void set_handler(unsigned long offset, void *addr, unsigned long len);
 220 extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
 221
 222 typedef void (*vi_handler_t)(void);
 223 extern void *set_vi_handler(int n, vi_handler_t addr);
 224
 225 extern void *set_except_vector(int n, void *addr);
 226 extern unsigned long ebase;
 227 extern void per_cpu_trap_init(void);
 228
 229 /*
 230  * See include/asm-ia64/system.h; prevents deadlock on SMP
 231  * systems.
 232  */
 233 #define __ARCH_WANT_UNLOCKED_CTXSW
 234
 235 extern unsigned long arch_align_stack(unsigned long sp);
 236
 237 #endif /* _ASM_SYSTEM_H */