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bnx2x: Use pr_fmt and message logging cleanups
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blobf90e3fa61ac225bc4da9270c651b0a2d27a13f53
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/stringify.h>
55 #include <linux/vmalloc.h>
56
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59 #include "bnx2x_init_ops.h"
60 #include "bnx2x_cmn.h"
61 #include "bnx2x_dcb.h"
62 #include "bnx2x_sp.h"
63
64 #include <linux/firmware.h>
65 #include "bnx2x_fw_file_hdr.h"
66 /* FW files */
67 #define FW_FILE_VERSION \
68 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
69 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
70 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
71 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
72 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
73 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
75
76 /* Time in jiffies before concluding the transmitter is hung */
77 #define TX_TIMEOUT (5*HZ)
78
79 static char version[] __devinitdata =
80 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
81 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
82
83 MODULE_AUTHOR("Eliezer Tamir");
84 MODULE_DESCRIPTION("Broadcom NetXtreme II "
85 "BCM57710/57711/57711E/"
86 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
87 "57840/57840_MF Driver");
88 MODULE_LICENSE("GPL");
89 MODULE_VERSION(DRV_MODULE_VERSION);
90 MODULE_FIRMWARE(FW_FILE_NAME_E1);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
92 MODULE_FIRMWARE(FW_FILE_NAME_E2);
93
94 static int multi_mode = 1;
95 module_param(multi_mode, int, 0);
96 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
97 "(0 Disable; 1 Enable (default))");
98
99 int num_queues;
100 module_param(num_queues, int, 0);
101 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
102 " (default is as a number of CPUs)");
103
104 static int disable_tpa;
105 module_param(disable_tpa, int, 0);
106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107
108 #define INT_MODE_INTx 1
109 #define INT_MODE_MSI 2
110 static int int_mode;
111 module_param(int_mode, int, 0);
112 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 "(1 INT#x; 2 MSI)");
114
115 static int dropless_fc;
116 module_param(dropless_fc, int, 0);
117 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118
119 static int poll;
120 module_param(poll, int, 0);
121 MODULE_PARM_DESC(poll, " Use polling (for debug)");
122
123 static int mrrs = -1;
124 module_param(mrrs, int, 0);
125 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
126
127 static int debug;
128 module_param(debug, int, 0);
129 MODULE_PARM_DESC(debug, " Default debug msglevel");
130
131
132
133 struct workqueue_struct *bnx2x_wq;
134
135 enum bnx2x_board_type {
136 BCM57710 = 0,
137 BCM57711,
138 BCM57711E,
139 BCM57712,
140 BCM57712_MF,
141 BCM57800,
142 BCM57800_MF,
143 BCM57810,
144 BCM57810_MF,
145 BCM57840,
146 BCM57840_MF
147 };
148
149 /* indexed by board_type, above */
150 static struct {
151 char *name;
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
164 "Ethernet Multi Function"}
165 };
166
167 #ifndef PCI_DEVICE_ID_NX2_57710
168 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
169 #endif
170 #ifndef PCI_DEVICE_ID_NX2_57711
171 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
172 #endif
173 #ifndef PCI_DEVICE_ID_NX2_57711E
174 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
175 #endif
176 #ifndef PCI_DEVICE_ID_NX2_57712
177 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
178 #endif
179 #ifndef PCI_DEVICE_ID_NX2_57712_MF
180 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
181 #endif
182 #ifndef PCI_DEVICE_ID_NX2_57800
183 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
184 #endif
185 #ifndef PCI_DEVICE_ID_NX2_57800_MF
186 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
187 #endif
188 #ifndef PCI_DEVICE_ID_NX2_57810
189 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57810_MF
192 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57840
195 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57840_MF
198 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
199 #endif
200 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
212 { 0 }
213 };
214
215 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
216
217 /****************************************************************************
218 * General service functions
219 ****************************************************************************/
220
221 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
222 u32 addr, dma_addr_t mapping)
223 {
224 REG_WR(bp, addr, U64_LO(mapping));
225 REG_WR(bp, addr + 4, U64_HI(mapping));
226 }
227
228 static inline void storm_memset_spq_addr(struct bnx2x *bp,
229 dma_addr_t mapping, u16 abs_fid)
230 {
231 u32 addr = XSEM_REG_FAST_MEMORY +
232 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
233
234 __storm_memset_dma_mapping(bp, addr, mapping);
235 }
236
237 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
238 u16 pf_id)
239 {
240 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
246 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
247 pf_id);
248 }
249
250 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
251 u8 enable)
252 {
253 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
260 enable);
261 }
262
263 static inline void storm_memset_eq_data(struct bnx2x *bp,
264 struct event_ring_data *eq_data,
265 u16 pfid)
266 {
267 size_t size = sizeof(struct event_ring_data);
268
269 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
270
271 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
272 }
273
274 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
275 u16 pfid)
276 {
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
278 REG_WR16(bp, addr, eq_prod);
279 }
280
281 /* used only at init
282 * locking is done by mcp
283 */
284 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
285 {
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
289 PCICFG_VENDOR_ID_OFFSET);
290 }
291
292 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
293 {
294 u32 val;
295
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
297 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
298 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
299 PCICFG_VENDOR_ID_OFFSET);
300
301 return val;
302 }
303
304 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
305 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
306 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
307 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
308 #define DMAE_DP_DST_NONE "dst_addr [none]"
309
310 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
311 int msglvl)
312 {
313 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
314
315 switch (dmae->opcode & DMAE_COMMAND_DST) {
316 case DMAE_CMD_DST_PCI:
317 if (src_type == DMAE_CMD_SRC_PCI)
318 DP(msglvl, "DMAE: opcode 0x%08x\n"
319 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
320 "comp_addr [%x:%08x], comp_val 0x%08x\n",
321 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
322 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
323 dmae->comp_addr_hi, dmae->comp_addr_lo,
324 dmae->comp_val);
325 else
326 DP(msglvl, "DMAE: opcode 0x%08x\n"
327 "src [%08x], len [%d*4], dst [%x:%08x]\n"
328 "comp_addr [%x:%08x], comp_val 0x%08x\n",
329 dmae->opcode, dmae->src_addr_lo >> 2,
330 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
331 dmae->comp_addr_hi, dmae->comp_addr_lo,
332 dmae->comp_val);
333 break;
334 case DMAE_CMD_DST_GRC:
335 if (src_type == DMAE_CMD_SRC_PCI)
336 DP(msglvl, "DMAE: opcode 0x%08x\n"
337 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
338 "comp_addr [%x:%08x], comp_val 0x%08x\n",
339 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
340 dmae->len, dmae->dst_addr_lo >> 2,
341 dmae->comp_addr_hi, dmae->comp_addr_lo,
342 dmae->comp_val);
343 else
344 DP(msglvl, "DMAE: opcode 0x%08x\n"
345 "src [%08x], len [%d*4], dst [%08x]\n"
346 "comp_addr [%x:%08x], comp_val 0x%08x\n",
347 dmae->opcode, dmae->src_addr_lo >> 2,
348 dmae->len, dmae->dst_addr_lo >> 2,
349 dmae->comp_addr_hi, dmae->comp_addr_lo,
350 dmae->comp_val);
351 break;
352 default:
353 if (src_type == DMAE_CMD_SRC_PCI)
354 DP(msglvl, "DMAE: opcode 0x%08x\n"
355 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
356 "comp_addr [%x:%08x] comp_val 0x%08x\n",
357 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
358 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
359 dmae->comp_val);
360 else
361 DP(msglvl, "DMAE: opcode 0x%08x\n"
362 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
363 "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370 }
371
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
374 {
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386 }
387
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
389 {
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392 }
393
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395 {
396 return opcode & ~DMAE_CMD_SRC_RESET;
397 }
398
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401 {
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
406
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
413
414 #ifdef __BIG_ENDIAN
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
416 #else
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
418 #endif
419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422 }
423
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
427 {
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438 }
439
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
443 {
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
451
452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
457 spin_lock_bh(&bp->dmae_lock);
458
459 /* reset completion */
460 *wb_comp = 0;
461
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
464
465 /* wait for completion */
466 udelay(5);
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
470 if (!cnt) {
471 BNX2X_ERR("DMAE timeout!\n");
472 rc = DMAE_TIMEOUT;
473 goto unlock;
474 }
475 cnt--;
476 udelay(50);
477 }
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
486
487 unlock:
488 spin_unlock_bh(&bp->dmae_lock);
489 return rc;
490 }
491
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494 {
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
520 }
521
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
523 {
524 struct dmae_command dmae;
525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
539
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
546
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
548
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
551 }
552
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
555 {
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
557 int offset = 0;
558
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567 }
568
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571 {
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
577 }
578
579 #ifdef USE_WB_RD
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581 {
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587 }
588 #endif
589
590 static int bnx2x_mc_assert(struct bnx2x *bp)
591 {
592 char last_idx;
593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 return rc;
709 }
710
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
712 {
713 u32 addr, val;
714 u32 mark, offset;
715 __be32 data[9];
716 int word;
717 u32 trace_shmem_base;
718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
730
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
740
741 printk("%s", lvl);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
745 data[8] = 0x0;
746 pr_cont("%s", (char *)data);
747 }
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
751 data[8] = 0x0;
752 pr_cont("%s", (char *)data);
753 }
754 printk("%s" "end of fw dump\n", lvl);
755 }
756
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
758 {
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
760 }
761
762 void bnx2x_panic_dump(struct bnx2x *bp)
763 {
764 int i;
765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
770 u8 cos;
771 #endif
772
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
776 BNX2X_ERR("begin crash dump -----------------\n");
777
778 /* Indices */
779 /* Common */
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
801 sp_sb_data.igu_sb_id,
802 sp_sb_data.igu_seg_id,
803 sp_sb_data.p_func.pf_id,
804 sp_sb_data.p_func.vnic_id,
805 sp_sb_data.p_func.vf_id,
806 sp_sb_data.p_func.vf_valid,
807 sp_sb_data.state);
808
809
810 for_each_eth_queue(bp, i) {
811 struct bnx2x_fastpath *fp = &bp->fp[i];
812 int loop;
813 struct hc_status_block_data_e2 sb_data_e2;
814 struct hc_status_block_data_e1x sb_data_e1x;
815 struct hc_status_block_sm *hc_sm_p =
816 CHIP_IS_E1x(bp) ?
817 sb_data_e1x.common.state_machine :
818 sb_data_e2.common.state_machine;
819 struct hc_index_data *hc_index_p =
820 CHIP_IS_E1x(bp) ?
821 sb_data_e1x.index_data :
822 sb_data_e2.index_data;
823 u8 data_size, cos;
824 u32 *sb_data_p;
825 struct bnx2x_fp_txdata txdata;
826
827 /* Rx */
828 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
829 " rx_comp_prod(0x%x)"
830 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
831 i, fp->rx_bd_prod, fp->rx_bd_cons,
832 fp->rx_comp_prod,
833 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
834 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
835 " fp_hc_idx(0x%x)\n",
836 fp->rx_sge_prod, fp->last_max_sge,
837 le16_to_cpu(fp->fp_hc_idx));
838
839 /* Tx */
840 for_each_cos_in_tx_queue(fp, cos)
841 {
842 txdata = fp->txdata[cos];
843 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
844 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
845 " *tx_cons_sb(0x%x)\n",
846 i, txdata.tx_pkt_prod,
847 txdata.tx_pkt_cons, txdata.tx_bd_prod,
848 txdata.tx_bd_cons,
849 le16_to_cpu(*txdata.tx_cons_sb));
850 }
851
852 loop = CHIP_IS_E1x(bp) ?
853 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
854
855 /* host sb data */
856
857 #ifdef BCM_CNIC
858 if (IS_FCOE_FP(fp))
859 continue;
860 #endif
861 BNX2X_ERR(" run indexes (");
862 for (j = 0; j < HC_SB_MAX_SM; j++)
863 pr_cont("0x%x%s",
864 fp->sb_running_index[j],
865 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
866
867 BNX2X_ERR(" indexes (");
868 for (j = 0; j < loop; j++)
869 pr_cont("0x%x%s",
870 fp->sb_index_values[j],
871 (j == loop - 1) ? ")" : " ");
872 /* fw sb data */
873 data_size = CHIP_IS_E1x(bp) ?
874 sizeof(struct hc_status_block_data_e1x) :
875 sizeof(struct hc_status_block_data_e2);
876 data_size /= sizeof(u32);
877 sb_data_p = CHIP_IS_E1x(bp) ?
878 (u32 *)&sb_data_e1x :
879 (u32 *)&sb_data_e2;
880 /* copy sb data in here */
881 for (j = 0; j < data_size; j++)
882 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
883 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
884 j * sizeof(u32));
885
886 if (!CHIP_IS_E1x(bp)) {
887 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
888 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
889 "state(0x%x)\n",
890 sb_data_e2.common.p_func.pf_id,
891 sb_data_e2.common.p_func.vf_id,
892 sb_data_e2.common.p_func.vf_valid,
893 sb_data_e2.common.p_func.vnic_id,
894 sb_data_e2.common.same_igu_sb_1b,
895 sb_data_e2.common.state);
896 } else {
897 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
898 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
899 "state(0x%x)\n",
900 sb_data_e1x.common.p_func.pf_id,
901 sb_data_e1x.common.p_func.vf_id,
902 sb_data_e1x.common.p_func.vf_valid,
903 sb_data_e1x.common.p_func.vnic_id,
904 sb_data_e1x.common.same_igu_sb_1b,
905 sb_data_e1x.common.state);
906 }
907
908 /* SB_SMs data */
909 for (j = 0; j < HC_SB_MAX_SM; j++) {
910 pr_cont("SM[%d] __flags (0x%x) "
911 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
912 "time_to_expire (0x%x) "
913 "timer_value(0x%x)\n", j,
914 hc_sm_p[j].__flags,
915 hc_sm_p[j].igu_sb_id,
916 hc_sm_p[j].igu_seg_id,
917 hc_sm_p[j].time_to_expire,
918 hc_sm_p[j].timer_value);
919 }
920
921 /* Indecies data */
922 for (j = 0; j < loop; j++) {
923 pr_cont("INDEX[%d] flags (0x%x) "
924 "timeout (0x%x)\n", j,
925 hc_index_p[j].flags,
926 hc_index_p[j].timeout);
927 }
928 }
929
930 #ifdef BNX2X_STOP_ON_ERROR
931 /* Rings */
932 /* Rx */
933 for_each_rx_queue(bp, i) {
934 struct bnx2x_fastpath *fp = &bp->fp[i];
935
936 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
937 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
938 for (j = start; j != end; j = RX_BD(j + 1)) {
939 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
940 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
941
942 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
943 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
944 }
945
946 start = RX_SGE(fp->rx_sge_prod);
947 end = RX_SGE(fp->last_max_sge);
948 for (j = start; j != end; j = RX_SGE(j + 1)) {
949 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
950 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
951
952 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
953 i, j, rx_sge[1], rx_sge[0], sw_page->page);
954 }
955
956 start = RCQ_BD(fp->rx_comp_cons - 10);
957 end = RCQ_BD(fp->rx_comp_cons + 503);
958 for (j = start; j != end; j = RCQ_BD(j + 1)) {
959 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
960
961 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
962 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
963 }
964 }
965
966 /* Tx */
967 for_each_tx_queue(bp, i) {
968 struct bnx2x_fastpath *fp = &bp->fp[i];
969 for_each_cos_in_tx_queue(fp, cos) {
970 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
971
972 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
973 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
974 for (j = start; j != end; j = TX_BD(j + 1)) {
975 struct sw_tx_bd *sw_bd =
976 &txdata->tx_buf_ring[j];
977
978 BNX2X_ERR("fp%d: txdata %d, "
979 "packet[%x]=[%p,%x]\n",
980 i, cos, j, sw_bd->skb,
981 sw_bd->first_bd);
982 }
983
984 start = TX_BD(txdata->tx_bd_cons - 10);
985 end = TX_BD(txdata->tx_bd_cons + 254);
986 for (j = start; j != end; j = TX_BD(j + 1)) {
987 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
988
989 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
990 "[%x:%x:%x:%x]\n",
991 i, cos, j, tx_bd[0], tx_bd[1],
992 tx_bd[2], tx_bd[3]);
993 }
994 }
995 }
996 #endif
997 bnx2x_fw_dump(bp);
998 bnx2x_mc_assert(bp);
999 BNX2X_ERR("end crash dump -----------------\n");
1000 }
1001
1002 /*
1003 * FLR Support for E2
1004 *
1005 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1006 * initialization.
1007 */
1008 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1009 #define FLR_WAIT_INTERAVAL 50 /* usec */
1010 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1011
1012 struct pbf_pN_buf_regs {
1013 int pN;
1014 u32 init_crd;
1015 u32 crd;
1016 u32 crd_freed;
1017 };
1018
1019 struct pbf_pN_cmd_regs {
1020 int pN;
1021 u32 lines_occup;
1022 u32 lines_freed;
1023 };
1024
1025 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1026 struct pbf_pN_buf_regs *regs,
1027 u32 poll_count)
1028 {
1029 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1030 u32 cur_cnt = poll_count;
1031
1032 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1033 crd = crd_start = REG_RD(bp, regs->crd);
1034 init_crd = REG_RD(bp, regs->init_crd);
1035
1036 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1037 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1038 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1039
1040 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1041 (init_crd - crd_start))) {
1042 if (cur_cnt--) {
1043 udelay(FLR_WAIT_INTERAVAL);
1044 crd = REG_RD(bp, regs->crd);
1045 crd_freed = REG_RD(bp, regs->crd_freed);
1046 } else {
1047 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1048 regs->pN);
1049 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1050 regs->pN, crd);
1051 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1052 regs->pN, crd_freed);
1053 break;
1054 }
1055 }
1056 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1057 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1058 }
1059
1060 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1061 struct pbf_pN_cmd_regs *regs,
1062 u32 poll_count)
1063 {
1064 u32 occup, to_free, freed, freed_start;
1065 u32 cur_cnt = poll_count;
1066
1067 occup = to_free = REG_RD(bp, regs->lines_occup);
1068 freed = freed_start = REG_RD(bp, regs->lines_freed);
1069
1070 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1071 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1072
1073 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1074 if (cur_cnt--) {
1075 udelay(FLR_WAIT_INTERAVAL);
1076 occup = REG_RD(bp, regs->lines_occup);
1077 freed = REG_RD(bp, regs->lines_freed);
1078 } else {
1079 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1080 regs->pN);
1081 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1082 regs->pN, occup);
1083 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1084 regs->pN, freed);
1085 break;
1086 }
1087 }
1088 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1089 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1090 }
1091
1092 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1093 u32 expected, u32 poll_count)
1094 {
1095 u32 cur_cnt = poll_count;
1096 u32 val;
1097
1098 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1099 udelay(FLR_WAIT_INTERAVAL);
1100
1101 return val;
1102 }
1103
1104 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1105 char *msg, u32 poll_cnt)
1106 {
1107 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1108 if (val != 0) {
1109 BNX2X_ERR("%s usage count=%d\n", msg, val);
1110 return 1;
1111 }
1112 return 0;
1113 }
1114
1115 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1116 {
1117 /* adjust polling timeout */
1118 if (CHIP_REV_IS_EMUL(bp))
1119 return FLR_POLL_CNT * 2000;
1120
1121 if (CHIP_REV_IS_FPGA(bp))
1122 return FLR_POLL_CNT * 120;
1123
1124 return FLR_POLL_CNT;
1125 }
1126
1127 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1128 {
1129 struct pbf_pN_cmd_regs cmd_regs[] = {
1130 {0, (CHIP_IS_E3B0(bp)) ?
1131 PBF_REG_TQ_OCCUPANCY_Q0 :
1132 PBF_REG_P0_TQ_OCCUPANCY,
1133 (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1135 PBF_REG_P0_TQ_LINES_FREED_CNT},
1136 {1, (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_OCCUPANCY_Q1 :
1138 PBF_REG_P1_TQ_OCCUPANCY,
1139 (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1141 PBF_REG_P1_TQ_LINES_FREED_CNT},
1142 {4, (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_OCCUPANCY_LB_Q :
1144 PBF_REG_P4_TQ_OCCUPANCY,
1145 (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1147 PBF_REG_P4_TQ_LINES_FREED_CNT}
1148 };
1149
1150 struct pbf_pN_buf_regs buf_regs[] = {
1151 {0, (CHIP_IS_E3B0(bp)) ?
1152 PBF_REG_INIT_CRD_Q0 :
1153 PBF_REG_P0_INIT_CRD ,
1154 (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_CREDIT_Q0 :
1156 PBF_REG_P0_CREDIT,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1159 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1160 {1, (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INIT_CRD_Q1 :
1162 PBF_REG_P1_INIT_CRD,
1163 (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_CREDIT_Q1 :
1165 PBF_REG_P1_CREDIT,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1168 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1169 {4, (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INIT_CRD_LB_Q :
1171 PBF_REG_P4_INIT_CRD,
1172 (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_CREDIT_LB_Q :
1174 PBF_REG_P4_CREDIT,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1177 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1178 };
1179
1180 int i;
1181
1182 /* Verify the command queues are flushed P0, P1, P4 */
1183 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1184 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1185
1186
1187 /* Verify the transmission buffers are flushed P0, P1, P4 */
1188 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1189 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1190 }
1191
1192 #define OP_GEN_PARAM(param) \
1193 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1194
1195 #define OP_GEN_TYPE(type) \
1196 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1197
1198 #define OP_GEN_AGG_VECT(index) \
1199 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1200
1201
1202 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1203 u32 poll_cnt)
1204 {
1205 struct sdm_op_gen op_gen = {0};
1206
1207 u32 comp_addr = BAR_CSTRORM_INTMEM +
1208 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1209 int ret = 0;
1210
1211 if (REG_RD(bp, comp_addr)) {
1212 BNX2X_ERR("Cleanup complete is not 0\n");
1213 return 1;
1214 }
1215
1216 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1217 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1218 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1219 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1220
1221 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1222 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1223
1224 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1225 BNX2X_ERR("FW final cleanup did not succeed\n");
1226 ret = 1;
1227 }
1228 /* Zero completion for nxt FLR */
1229 REG_WR(bp, comp_addr, 0);
1230
1231 return ret;
1232 }
1233
1234 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1235 {
1236 int pos;
1237 u16 status;
1238
1239 pos = pci_pcie_cap(dev);
1240 if (!pos)
1241 return false;
1242
1243 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1244 return status & PCI_EXP_DEVSTA_TRPND;
1245 }
1246
1247 /* PF FLR specific routines
1248 */
1249 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1250 {
1251
1252 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1253 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1254 CFC_REG_NUM_LCIDS_INSIDE_PF,
1255 "CFC PF usage counter timed out",
1256 poll_cnt))
1257 return 1;
1258
1259
1260 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 DORQ_REG_PF_USAGE_CNT,
1263 "DQ PF usage counter timed out",
1264 poll_cnt))
1265 return 1;
1266
1267 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1268 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1269 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1270 "QM PF usage counter timed out",
1271 poll_cnt))
1272 return 1;
1273
1274 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1275 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1276 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1277 "Timers VNIC usage counter timed out",
1278 poll_cnt))
1279 return 1;
1280 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1281 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1282 "Timers NUM_SCANS usage counter timed out",
1283 poll_cnt))
1284 return 1;
1285
1286 /* Wait DMAE PF usage counter to zero */
1287 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1288 dmae_reg_go_c[INIT_DMAE_C(bp)],
1289 "DMAE dommand register timed out",
1290 poll_cnt))
1291 return 1;
1292
1293 return 0;
1294 }
1295
1296 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1297 {
1298 u32 val;
1299
1300 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1301 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1302
1303 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1304 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1307 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1314
1315 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1316 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1323 val);
1324 }
1325
1326 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1327 {
1328 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1329
1330 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1331
1332 /* Re-enable PF target read access */
1333 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1334
1335 /* Poll HW usage counters */
1336 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1337 return -EBUSY;
1338
1339 /* Zero the igu 'trailing edge' and 'leading edge' */
1340
1341 /* Send the FW cleanup command */
1342 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1343 return -EBUSY;
1344
1345 /* ATC cleanup */
1346
1347 /* Verify TX hw is flushed */
1348 bnx2x_tx_hw_flushed(bp, poll_cnt);
1349
1350 /* Wait 100ms (not adjusted according to platform) */
1351 msleep(100);
1352
1353 /* Verify no pending pci transactions */
1354 if (bnx2x_is_pcie_pending(bp->pdev))
1355 BNX2X_ERR("PCIE Transactions still pending\n");
1356
1357 /* Debug */
1358 bnx2x_hw_enable_status(bp);
1359
1360 /*
1361 * Master enable - Due to WB DMAE writes performed before this
1362 * register is re-initialized as part of the regular function init
1363 */
1364 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1365
1366 return 0;
1367 }
1368
1369 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1370 {
1371 int port = BP_PORT(bp);
1372 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1373 u32 val = REG_RD(bp, addr);
1374 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1375 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1376
1377 if (msix) {
1378 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1379 HC_CONFIG_0_REG_INT_LINE_EN_0);
1380 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1381 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1382 } else if (msi) {
1383 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1384 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1385 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1386 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1387 } else {
1388 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1389 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1390 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1391 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1392
1393 if (!CHIP_IS_E1(bp)) {
1394 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1395 val, port, addr);
1396
1397 REG_WR(bp, addr, val);
1398
1399 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1400 }
1401 }
1402
1403 if (CHIP_IS_E1(bp))
1404 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1405
1406 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1407 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1408
1409 REG_WR(bp, addr, val);
1410 /*
1411 * Ensure that HC_CONFIG is written before leading/trailing edge config
1412 */
1413 mmiowb();
1414 barrier();
1415
1416 if (!CHIP_IS_E1(bp)) {
1417 /* init leading/trailing edge */
1418 if (IS_MF(bp)) {
1419 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1420 if (bp->port.pmf)
1421 /* enable nig and gpio3 attention */
1422 val |= 0x1100;
1423 } else
1424 val = 0xffff;
1425
1426 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1427 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1428 }
1429
1430 /* Make sure that interrupts are indeed enabled from here on */
1431 mmiowb();
1432 }
1433
1434 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1435 {
1436 u32 val;
1437 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1438 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1439
1440 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1441
1442 if (msix) {
1443 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1444 IGU_PF_CONF_SINGLE_ISR_EN);
1445 val |= (IGU_PF_CONF_FUNC_EN |
1446 IGU_PF_CONF_MSI_MSIX_EN |
1447 IGU_PF_CONF_ATTN_BIT_EN);
1448 } else if (msi) {
1449 val &= ~IGU_PF_CONF_INT_LINE_EN;
1450 val |= (IGU_PF_CONF_FUNC_EN |
1451 IGU_PF_CONF_MSI_MSIX_EN |
1452 IGU_PF_CONF_ATTN_BIT_EN |
1453 IGU_PF_CONF_SINGLE_ISR_EN);
1454 } else {
1455 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1456 val |= (IGU_PF_CONF_FUNC_EN |
1457 IGU_PF_CONF_INT_LINE_EN |
1458 IGU_PF_CONF_ATTN_BIT_EN |
1459 IGU_PF_CONF_SINGLE_ISR_EN);
1460 }
1461
1462 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1463 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1464
1465 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1466
1467 barrier();
1468
1469 /* init leading/trailing edge */
1470 if (IS_MF(bp)) {
1471 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1472 if (bp->port.pmf)
1473 /* enable nig and gpio3 attention */
1474 val |= 0x1100;
1475 } else
1476 val = 0xffff;
1477
1478 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1479 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1480
1481 /* Make sure that interrupts are indeed enabled from here on */
1482 mmiowb();
1483 }
1484
1485 void bnx2x_int_enable(struct bnx2x *bp)
1486 {
1487 if (bp->common.int_block == INT_BLOCK_HC)
1488 bnx2x_hc_int_enable(bp);
1489 else
1490 bnx2x_igu_int_enable(bp);
1491 }
1492
1493 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1494 {
1495 int port = BP_PORT(bp);
1496 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1497 u32 val = REG_RD(bp, addr);
1498
1499 /*
1500 * in E1 we must use only PCI configuration space to disable
1501 * MSI/MSIX capablility
1502 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1503 */
1504 if (CHIP_IS_E1(bp)) {
1505 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1506 * Use mask register to prevent from HC sending interrupts
1507 * after we exit the function
1508 */
1509 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1510
1511 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1512 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1513 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1514 } else
1515 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1516 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1517 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1518 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1519
1520 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1521 val, port, addr);
1522
1523 /* flush all outstanding writes */
1524 mmiowb();
1525
1526 REG_WR(bp, addr, val);
1527 if (REG_RD(bp, addr) != val)
1528 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1529 }
1530
1531 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1532 {
1533 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1534
1535 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1536 IGU_PF_CONF_INT_LINE_EN |
1537 IGU_PF_CONF_ATTN_BIT_EN);
1538
1539 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1540
1541 /* flush all outstanding writes */
1542 mmiowb();
1543
1544 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1545 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1546 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1547 }
1548
1549 void bnx2x_int_disable(struct bnx2x *bp)
1550 {
1551 if (bp->common.int_block == INT_BLOCK_HC)
1552 bnx2x_hc_int_disable(bp);
1553 else
1554 bnx2x_igu_int_disable(bp);
1555 }
1556
1557 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1558 {
1559 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1560 int i, offset;
1561
1562 if (disable_hw)
1563 /* prevent the HW from sending interrupts */
1564 bnx2x_int_disable(bp);
1565
1566 /* make sure all ISRs are done */
1567 if (msix) {
1568 synchronize_irq(bp->msix_table[0].vector);
1569 offset = 1;
1570 #ifdef BCM_CNIC
1571 offset++;
1572 #endif
1573 for_each_eth_queue(bp, i)
1574 synchronize_irq(bp->msix_table[offset++].vector);
1575 } else
1576 synchronize_irq(bp->pdev->irq);
1577
1578 /* make sure sp_task is not running */
1579 cancel_delayed_work(&bp->sp_task);
1580 cancel_delayed_work(&bp->period_task);
1581 flush_workqueue(bnx2x_wq);
1582 }
1583
1584 /* fast path */
1585
1586 /*
1587 * General service functions
1588 */
1589
1590 /* Return true if succeeded to acquire the lock */
1591 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1592 {
1593 u32 lock_status;
1594 u32 resource_bit = (1 << resource);
1595 int func = BP_FUNC(bp);
1596 u32 hw_lock_control_reg;
1597
1598 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1599
1600 /* Validating that the resource is within range */
1601 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1602 DP(NETIF_MSG_HW,
1603 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1604 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1605 return false;
1606 }
1607
1608 if (func <= 5)
1609 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1610 else
1611 hw_lock_control_reg =
1612 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1613
1614 /* Try to acquire the lock */
1615 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1616 lock_status = REG_RD(bp, hw_lock_control_reg);
1617 if (lock_status & resource_bit)
1618 return true;
1619
1620 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1621 return false;
1622 }
1623
1624 /**
1625 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1626 *
1627 * @bp: driver handle
1628 *
1629 * Returns the recovery leader resource id according to the engine this function
1630 * belongs to. Currently only only 2 engines is supported.
1631 */
1632 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1633 {
1634 if (BP_PATH(bp))
1635 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1636 else
1637 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1638 }
1639
1640 /**
1641 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1642 *
1643 * @bp: driver handle
1644 *
1645 * Tries to aquire a leader lock for cuurent engine.
1646 */
1647 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1648 {
1649 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1650 }
1651
1652 #ifdef BCM_CNIC
1653 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1654 #endif
1655
1656 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1657 {
1658 struct bnx2x *bp = fp->bp;
1659 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1660 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1662 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1663
1664 DP(BNX2X_MSG_SP,
1665 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1666 fp->index, cid, command, bp->state,
1667 rr_cqe->ramrod_cqe.ramrod_type);
1668
1669 switch (command) {
1670 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1671 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1672 drv_cmd = BNX2X_Q_CMD_UPDATE;
1673 break;
1674
1675 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1676 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1677 drv_cmd = BNX2X_Q_CMD_SETUP;
1678 break;
1679
1680 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1681 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1682 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1683 break;
1684
1685 case (RAMROD_CMD_ID_ETH_HALT):
1686 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1687 drv_cmd = BNX2X_Q_CMD_HALT;
1688 break;
1689
1690 case (RAMROD_CMD_ID_ETH_TERMINATE):
1691 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1692 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1693 break;
1694
1695 case (RAMROD_CMD_ID_ETH_EMPTY):
1696 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1697 drv_cmd = BNX2X_Q_CMD_EMPTY;
1698 break;
1699
1700 default:
1701 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1702 command, fp->index);
1703 return;
1704 }
1705
1706 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1707 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1708 /* q_obj->complete_cmd() failure means that this was
1709 * an unexpected completion.
1710 *
1711 * In this case we don't want to increase the bp->spq_left
1712 * because apparently we haven't sent this command the first
1713 * place.
1714 */
1715 #ifdef BNX2X_STOP_ON_ERROR
1716 bnx2x_panic();
1717 #else
1718 return;
1719 #endif
1720
1721 smp_mb__before_atomic_inc();
1722 atomic_inc(&bp->cq_spq_left);
1723 /* push the change in bp->spq_left and towards the memory */
1724 smp_mb__after_atomic_inc();
1725
1726 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1727
1728 return;
1729 }
1730
1731 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1732 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1733 {
1734 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1735
1736 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1737 start);
1738 }
1739
1740 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1741 {
1742 struct bnx2x *bp = netdev_priv(dev_instance);
1743 u16 status = bnx2x_ack_int(bp);
1744 u16 mask;
1745 int i;
1746 u8 cos;
1747
1748 /* Return here if interrupt is shared and it's not for us */
1749 if (unlikely(status == 0)) {
1750 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1751 return IRQ_NONE;
1752 }
1753 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1754
1755 #ifdef BNX2X_STOP_ON_ERROR
1756 if (unlikely(bp->panic))
1757 return IRQ_HANDLED;
1758 #endif
1759
1760 for_each_eth_queue(bp, i) {
1761 struct bnx2x_fastpath *fp = &bp->fp[i];
1762
1763 mask = 0x2 << (fp->index + CNIC_PRESENT);
1764 if (status & mask) {
1765 /* Handle Rx or Tx according to SB id */
1766 prefetch(fp->rx_cons_sb);
1767 for_each_cos_in_tx_queue(fp, cos)
1768 prefetch(fp->txdata[cos].tx_cons_sb);
1769 prefetch(&fp->sb_running_index[SM_RX_ID]);
1770 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1771 status &= ~mask;
1772 }
1773 }
1774
1775 #ifdef BCM_CNIC
1776 mask = 0x2;
1777 if (status & (mask | 0x1)) {
1778 struct cnic_ops *c_ops = NULL;
1779
1780 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1781 rcu_read_lock();
1782 c_ops = rcu_dereference(bp->cnic_ops);
1783 if (c_ops)
1784 c_ops->cnic_handler(bp->cnic_data, NULL);
1785 rcu_read_unlock();
1786 }
1787
1788 status &= ~mask;
1789 }
1790 #endif
1791
1792 if (unlikely(status & 0x1)) {
1793 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1794
1795 status &= ~0x1;
1796 if (!status)
1797 return IRQ_HANDLED;
1798 }
1799
1800 if (unlikely(status))
1801 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1802 status);
1803
1804 return IRQ_HANDLED;
1805 }
1806
1807 /* Link */
1808
1809 /*
1810 * General service functions
1811 */
1812
1813 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1814 {
1815 u32 lock_status;
1816 u32 resource_bit = (1 << resource);
1817 int func = BP_FUNC(bp);
1818 u32 hw_lock_control_reg;
1819 int cnt;
1820
1821 /* Validating that the resource is within range */
1822 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1823 DP(NETIF_MSG_HW,
1824 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1825 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1826 return -EINVAL;
1827 }
1828
1829 if (func <= 5) {
1830 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1831 } else {
1832 hw_lock_control_reg =
1833 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1834 }
1835
1836 /* Validating that the resource is not already taken */
1837 lock_status = REG_RD(bp, hw_lock_control_reg);
1838 if (lock_status & resource_bit) {
1839 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1840 lock_status, resource_bit);
1841 return -EEXIST;
1842 }
1843
1844 /* Try for 5 second every 5ms */
1845 for (cnt = 0; cnt < 1000; cnt++) {
1846 /* Try to acquire the lock */
1847 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1848 lock_status = REG_RD(bp, hw_lock_control_reg);
1849 if (lock_status & resource_bit)
1850 return 0;
1851
1852 msleep(5);
1853 }
1854 DP(NETIF_MSG_HW, "Timeout\n");
1855 return -EAGAIN;
1856 }
1857
1858 int bnx2x_release_leader_lock(struct bnx2x *bp)
1859 {
1860 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1861 }
1862
1863 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1864 {
1865 u32 lock_status;
1866 u32 resource_bit = (1 << resource);
1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
1869
1870 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1871
1872 /* Validating that the resource is within range */
1873 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1874 DP(NETIF_MSG_HW,
1875 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1876 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1877 return -EINVAL;
1878 }
1879
1880 if (func <= 5) {
1881 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1882 } else {
1883 hw_lock_control_reg =
1884 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1885 }
1886
1887 /* Validating that the resource is currently taken */
1888 lock_status = REG_RD(bp, hw_lock_control_reg);
1889 if (!(lock_status & resource_bit)) {
1890 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1891 lock_status, resource_bit);
1892 return -EFAULT;
1893 }
1894
1895 REG_WR(bp, hw_lock_control_reg, resource_bit);
1896 return 0;
1897 }
1898
1899
1900 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1901 {
1902 /* The GPIO should be swapped if swap register is set and active */
1903 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1904 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1905 int gpio_shift = gpio_num +
1906 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1907 u32 gpio_mask = (1 << gpio_shift);
1908 u32 gpio_reg;
1909 int value;
1910
1911 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1912 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1913 return -EINVAL;
1914 }
1915
1916 /* read GPIO value */
1917 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1918
1919 /* get the requested pin value */
1920 if ((gpio_reg & gpio_mask) == gpio_mask)
1921 value = 1;
1922 else
1923 value = 0;
1924
1925 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1926
1927 return value;
1928 }
1929
1930 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1931 {
1932 /* The GPIO should be swapped if swap register is set and active */
1933 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1934 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1935 int gpio_shift = gpio_num +
1936 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1937 u32 gpio_mask = (1 << gpio_shift);
1938 u32 gpio_reg;
1939
1940 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1941 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1942 return -EINVAL;
1943 }
1944
1945 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1946 /* read GPIO and mask except the float bits */
1947 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1948
1949 switch (mode) {
1950 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1951 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1952 gpio_num, gpio_shift);
1953 /* clear FLOAT and set CLR */
1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1956 break;
1957
1958 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1959 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set SET */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1964 break;
1965
1966 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1967 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1968 gpio_num, gpio_shift);
1969 /* set FLOAT */
1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1971 break;
1972
1973 default:
1974 break;
1975 }
1976
1977 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1978 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1979
1980 return 0;
1981 }
1982
1983 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1984 {
1985 u32 gpio_reg = 0;
1986 int rc = 0;
1987
1988 /* Any port swapping should be handled by caller. */
1989
1990 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 /* read GPIO and mask except the float bits */
1992 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1993 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1996
1997 switch (mode) {
1998 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2000 /* set CLR */
2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2002 break;
2003
2004 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2005 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2006 /* set SET */
2007 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2008 break;
2009
2010 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2012 /* set FLOAT */
2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2014 break;
2015
2016 default:
2017 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2018 rc = -EINVAL;
2019 break;
2020 }
2021
2022 if (rc == 0)
2023 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2024
2025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2026
2027 return rc;
2028 }
2029
2030 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2031 {
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2038 u32 gpio_reg;
2039
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2042 return -EINVAL;
2043 }
2044
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO int */
2047 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2048
2049 switch (mode) {
2050 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2051 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2052 "output low\n", gpio_num, gpio_shift);
2053 /* clear SET and set CLR */
2054 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2055 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2056 break;
2057
2058 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2059 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2060 "output high\n", gpio_num, gpio_shift);
2061 /* clear CLR and set SET */
2062 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2063 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2064 break;
2065
2066 default:
2067 break;
2068 }
2069
2070 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2072
2073 return 0;
2074 }
2075
2076 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2077 {
2078 u32 spio_mask = (1 << spio_num);
2079 u32 spio_reg;
2080
2081 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2082 (spio_num > MISC_REGISTERS_SPIO_7)) {
2083 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2084 return -EINVAL;
2085 }
2086
2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088 /* read SPIO and mask except the float bits */
2089 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2090
2091 switch (mode) {
2092 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2093 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2094 /* clear FLOAT and set CLR */
2095 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2096 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2097 break;
2098
2099 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2100 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2101 /* clear FLOAT and set SET */
2102 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2103 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2104 break;
2105
2106 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2108 /* set FLOAT */
2109 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2110 break;
2111
2112 default:
2113 break;
2114 }
2115
2116 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2117 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2118
2119 return 0;
2120 }
2121
2122 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2123 {
2124 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2125 switch (bp->link_vars.ieee_fc &
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2128 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2129 ADVERTISED_Pause);
2130 break;
2131
2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2133 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2134 ADVERTISED_Pause);
2135 break;
2136
2137 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2138 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2139 break;
2140
2141 default:
2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2143 ADVERTISED_Pause);
2144 break;
2145 }
2146 }
2147
2148 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2149 {
2150 if (!BP_NOMCP(bp)) {
2151 u8 rc;
2152 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2153 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2154 /*
2155 * Initialize link parameters structure variables
2156 * It is recommended to turn off RX FC for jumbo frames
2157 * for better performance
2158 */
2159 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2160 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2161 else
2162 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2163
2164 bnx2x_acquire_phy_lock(bp);
2165
2166 if (load_mode == LOAD_DIAG) {
2167 struct link_params *lp = &bp->link_params;
2168 lp->loopback_mode = LOOPBACK_XGXS;
2169 /* do PHY loopback at 10G speed, if possible */
2170 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2171 if (lp->speed_cap_mask[cfx_idx] &
2172 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2173 lp->req_line_speed[cfx_idx] =
2174 SPEED_10000;
2175 else
2176 lp->req_line_speed[cfx_idx] =
2177 SPEED_1000;
2178 }
2179 }
2180
2181 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2182
2183 bnx2x_release_phy_lock(bp);
2184
2185 bnx2x_calc_fc_adv(bp);
2186
2187 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2188 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2189 bnx2x_link_report(bp);
2190 } else
2191 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2192 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2193 return rc;
2194 }
2195 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2196 return -EINVAL;
2197 }
2198
2199 void bnx2x_link_set(struct bnx2x *bp)
2200 {
2201 if (!BP_NOMCP(bp)) {
2202 bnx2x_acquire_phy_lock(bp);
2203 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2204 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2205 bnx2x_release_phy_lock(bp);
2206
2207 bnx2x_calc_fc_adv(bp);
2208 } else
2209 BNX2X_ERR("Bootcode is missing - can not set link\n");
2210 }
2211
2212 static void bnx2x__link_reset(struct bnx2x *bp)
2213 {
2214 if (!BP_NOMCP(bp)) {
2215 bnx2x_acquire_phy_lock(bp);
2216 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2217 bnx2x_release_phy_lock(bp);
2218 } else
2219 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2220 }
2221
2222 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2223 {
2224 u8 rc = 0;
2225
2226 if (!BP_NOMCP(bp)) {
2227 bnx2x_acquire_phy_lock(bp);
2228 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2229 is_serdes);
2230 bnx2x_release_phy_lock(bp);
2231 } else
2232 BNX2X_ERR("Bootcode is missing - can not test link\n");
2233
2234 return rc;
2235 }
2236
2237 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2238 {
2239 u32 r_param = bp->link_vars.line_speed / 8;
2240 u32 fair_periodic_timeout_usec;
2241 u32 t_fair;
2242
2243 memset(&(bp->cmng.rs_vars), 0,
2244 sizeof(struct rate_shaping_vars_per_port));
2245 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2246
2247 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2248 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2249
2250 /* this is the threshold below which no timer arming will occur
2251 1.25 coefficient is for the threshold to be a little bigger
2252 than the real time, to compensate for timer in-accuracy */
2253 bp->cmng.rs_vars.rs_threshold =
2254 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2255
2256 /* resolution of fairness timer */
2257 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2258 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2259 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2260
2261 /* this is the threshold below which we won't arm the timer anymore */
2262 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2263
2264 /* we multiply by 1e3/8 to get bytes/msec.
2265 We don't want the credits to pass a credit
2266 of the t_fair*FAIR_MEM (algorithm resolution) */
2267 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2268 /* since each tick is 4 usec */
2269 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2270 }
2271
2272 /* Calculates the sum of vn_min_rates.
2273 It's needed for further normalizing of the min_rates.
2274 Returns:
2275 sum of vn_min_rates.
2276 or
2277 0 - if all the min_rates are 0.
2278 In the later case fainess algorithm should be deactivated.
2279 If not all min_rates are zero then those that are zeroes will be set to 1.
2280 */
2281 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2282 {
2283 int all_zero = 1;
2284 int vn;
2285
2286 bp->vn_weight_sum = 0;
2287 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2288 u32 vn_cfg = bp->mf_config[vn];
2289 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2290 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2291
2292 /* Skip hidden vns */
2293 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2294 continue;
2295
2296 /* If min rate is zero - set it to 1 */
2297 if (!vn_min_rate)
2298 vn_min_rate = DEF_MIN_RATE;
2299 else
2300 all_zero = 0;
2301
2302 bp->vn_weight_sum += vn_min_rate;
2303 }
2304
2305 /* if ETS or all min rates are zeros - disable fairness */
2306 if (BNX2X_IS_ETS_ENABLED(bp)) {
2307 bp->cmng.flags.cmng_enables &=
2308 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2309 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2310 } else if (all_zero) {
2311 bp->cmng.flags.cmng_enables &=
2312 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2313 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2314 " fairness will be disabled\n");
2315 } else
2316 bp->cmng.flags.cmng_enables |=
2317 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2318 }
2319
2320 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2321 {
2322 struct rate_shaping_vars_per_vn m_rs_vn;
2323 struct fairness_vars_per_vn m_fair_vn;
2324 u32 vn_cfg = bp->mf_config[vn];
2325 int func = 2*vn + BP_PORT(bp);
2326 u16 vn_min_rate, vn_max_rate;
2327 int i;
2328
2329 /* If function is hidden - set min and max to zeroes */
2330 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2331 vn_min_rate = 0;
2332 vn_max_rate = 0;
2333
2334 } else {
2335 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2336
2337 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2338 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2339 /* If fairness is enabled (not all min rates are zeroes) and
2340 if current min rate is zero - set it to 1.
2341 This is a requirement of the algorithm. */
2342 if (bp->vn_weight_sum && (vn_min_rate == 0))
2343 vn_min_rate = DEF_MIN_RATE;
2344
2345 if (IS_MF_SI(bp))
2346 /* maxCfg in percents of linkspeed */
2347 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2348 else
2349 /* maxCfg is absolute in 100Mb units */
2350 vn_max_rate = maxCfg * 100;
2351 }
2352
2353 DP(NETIF_MSG_IFUP,
2354 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2355 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2356
2357 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2358 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2359
2360 /* global vn counter - maximal Mbps for this vn */
2361 m_rs_vn.vn_counter.rate = vn_max_rate;
2362
2363 /* quota - number of bytes transmitted in this period */
2364 m_rs_vn.vn_counter.quota =
2365 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2366
2367 if (bp->vn_weight_sum) {
2368 /* credit for each period of the fairness algorithm:
2369 number of bytes in T_FAIR (the vn share the port rate).
2370 vn_weight_sum should not be larger than 10000, thus
2371 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2372 than zero */
2373 m_fair_vn.vn_credit_delta =
2374 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2375 (8 * bp->vn_weight_sum))),
2376 (bp->cmng.fair_vars.fair_threshold +
2377 MIN_ABOVE_THRESH));
2378 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2379 m_fair_vn.vn_credit_delta);
2380 }
2381
2382 /* Store it to internal memory */
2383 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2384 REG_WR(bp, BAR_XSTRORM_INTMEM +
2385 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2386 ((u32 *)(&m_rs_vn))[i]);
2387
2388 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2389 REG_WR(bp, BAR_XSTRORM_INTMEM +
2390 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2391 ((u32 *)(&m_fair_vn))[i]);
2392 }
2393
2394 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2395 {
2396 if (CHIP_REV_IS_SLOW(bp))
2397 return CMNG_FNS_NONE;
2398 if (IS_MF(bp))
2399 return CMNG_FNS_MINMAX;
2400
2401 return CMNG_FNS_NONE;
2402 }
2403
2404 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2405 {
2406 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2407
2408 if (BP_NOMCP(bp))
2409 return; /* what should be the default bvalue in this case */
2410
2411 /* For 2 port configuration the absolute function number formula
2412 * is:
2413 * abs_func = 2 * vn + BP_PORT + BP_PATH
2414 *
2415 * and there are 4 functions per port
2416 *
2417 * For 4 port configuration it is
2418 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2419 *
2420 * and there are 2 functions per port
2421 */
2422 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2423 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2424
2425 if (func >= E1H_FUNC_MAX)
2426 break;
2427
2428 bp->mf_config[vn] =
2429 MF_CFG_RD(bp, func_mf_config[func].config);
2430 }
2431 }
2432
2433 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2434 {
2435
2436 if (cmng_type == CMNG_FNS_MINMAX) {
2437 int vn;
2438
2439 /* clear cmng_enables */
2440 bp->cmng.flags.cmng_enables = 0;
2441
2442 /* read mf conf from shmem */
2443 if (read_cfg)
2444 bnx2x_read_mf_cfg(bp);
2445
2446 /* Init rate shaping and fairness contexts */
2447 bnx2x_init_port_minmax(bp);
2448
2449 /* vn_weight_sum and enable fairness if not 0 */
2450 bnx2x_calc_vn_weight_sum(bp);
2451
2452 /* calculate and set min-max rate for each vn */
2453 if (bp->port.pmf)
2454 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2455 bnx2x_init_vn_minmax(bp, vn);
2456
2457 /* always enable rate shaping and fairness */
2458 bp->cmng.flags.cmng_enables |=
2459 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2460 if (!bp->vn_weight_sum)
2461 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2462 " fairness will be disabled\n");
2463 return;
2464 }
2465
2466 /* rate shaping and fairness are disabled */
2467 DP(NETIF_MSG_IFUP,
2468 "rate shaping and fairness are disabled\n");
2469 }
2470
2471 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2472 {
2473 int port = BP_PORT(bp);
2474 int func;
2475 int vn;
2476
2477 /* Set the attention towards other drivers on the same port */
2478 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2479 if (vn == BP_E1HVN(bp))
2480 continue;
2481
2482 func = ((vn << 1) | port);
2483 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2484 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2485 }
2486 }
2487
2488 /* This function is called upon link interrupt */
2489 static void bnx2x_link_attn(struct bnx2x *bp)
2490 {
2491 /* Make sure that we are synced with the current statistics */
2492 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2493
2494 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2495
2496 if (bp->link_vars.link_up) {
2497
2498 /* dropless flow control */
2499 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2500 int port = BP_PORT(bp);
2501 u32 pause_enabled = 0;
2502
2503 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2504 pause_enabled = 1;
2505
2506 REG_WR(bp, BAR_USTRORM_INTMEM +
2507 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2508 pause_enabled);
2509 }
2510
2511 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2512 struct host_port_stats *pstats;
2513
2514 pstats = bnx2x_sp(bp, port_stats);
2515 /* reset old mac stats */
2516 memset(&(pstats->mac_stx[0]), 0,
2517 sizeof(struct mac_stx));
2518 }
2519 if (bp->state == BNX2X_STATE_OPEN)
2520 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2521 }
2522
2523 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2524 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2525
2526 if (cmng_fns != CMNG_FNS_NONE) {
2527 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2528 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2529 } else
2530 /* rate shaping and fairness are disabled */
2531 DP(NETIF_MSG_IFUP,
2532 "single function mode without fairness\n");
2533 }
2534
2535 __bnx2x_link_report(bp);
2536
2537 if (IS_MF(bp))
2538 bnx2x_link_sync_notify(bp);
2539 }
2540
2541 void bnx2x__link_status_update(struct bnx2x *bp)
2542 {
2543 if (bp->state != BNX2X_STATE_OPEN)
2544 return;
2545
2546 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2547
2548 if (bp->link_vars.link_up)
2549 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2550 else
2551 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2552
2553 /* indicate link status */
2554 bnx2x_link_report(bp);
2555 }
2556
2557 static void bnx2x_pmf_update(struct bnx2x *bp)
2558 {
2559 int port = BP_PORT(bp);
2560 u32 val;
2561
2562 bp->port.pmf = 1;
2563 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2564
2565 /*
2566 * We need the mb() to ensure the ordering between the writing to
2567 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2568 */
2569 smp_mb();
2570
2571 /* queue a periodic task */
2572 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2573
2574 bnx2x_dcbx_pmf_update(bp);
2575
2576 /* enable nig attention */
2577 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2578 if (bp->common.int_block == INT_BLOCK_HC) {
2579 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2580 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2581 } else if (!CHIP_IS_E1x(bp)) {
2582 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2583 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2584 }
2585
2586 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2587 }
2588
2589 /* end of Link */
2590
2591 /* slow path */
2592
2593 /*
2594 * General service functions
2595 */
2596
2597 /* send the MCP a request, block until there is a reply */
2598 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2599 {
2600 int mb_idx = BP_FW_MB_IDX(bp);
2601 u32 seq;
2602 u32 rc = 0;
2603 u32 cnt = 1;
2604 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2605
2606 mutex_lock(&bp->fw_mb_mutex);
2607 seq = ++bp->fw_seq;
2608 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2609 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2610
2611 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2612 (command | seq), param);
2613
2614 do {
2615 /* let the FW do it's magic ... */
2616 msleep(delay);
2617
2618 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2619
2620 /* Give the FW up to 5 second (500*10ms) */
2621 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2622
2623 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2624 cnt*delay, rc, seq);
2625
2626 /* is this a reply to our command? */
2627 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2628 rc &= FW_MSG_CODE_MASK;
2629 else {
2630 /* FW BUG! */
2631 BNX2X_ERR("FW failed to respond!\n");
2632 bnx2x_fw_dump(bp);
2633 rc = 0;
2634 }
2635 mutex_unlock(&bp->fw_mb_mutex);
2636
2637 return rc;
2638 }
2639
2640 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2641 {
2642 #ifdef BCM_CNIC
2643 /* Statistics are not supported for CNIC Clients at the moment */
2644 if (IS_FCOE_FP(fp))
2645 return false;
2646 #endif
2647 return true;
2648 }
2649
2650 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2651 {
2652 if (CHIP_IS_E1x(bp)) {
2653 struct tstorm_eth_function_common_config tcfg = {0};
2654
2655 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2656 }
2657
2658 /* Enable the function in the FW */
2659 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2660 storm_memset_func_en(bp, p->func_id, 1);
2661
2662 /* spq */
2663 if (p->func_flgs & FUNC_FLG_SPQ) {
2664 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2665 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2666 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2667 }
2668 }
2669
2670 /**
2671 * bnx2x_get_tx_only_flags - Return common flags
2672 *
2673 * @bp device handle
2674 * @fp queue handle
2675 * @zero_stats TRUE if statistics zeroing is needed
2676 *
2677 * Return the flags that are common for the Tx-only and not normal connections.
2678 */
2679 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2680 struct bnx2x_fastpath *fp,
2681 bool zero_stats)
2682 {
2683 unsigned long flags = 0;
2684
2685 /* PF driver will always initialize the Queue to an ACTIVE state */
2686 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2687
2688 /* tx only connections collect statistics (on the same index as the
2689 * parent connection). The statistics are zeroed when the parent
2690 * connection is initialized.
2691 */
2692 if (stat_counter_valid(bp, fp)) {
2693 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2694 if (zero_stats)
2695 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2696 }
2697
2698 return flags;
2699 }
2700
2701 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2702 struct bnx2x_fastpath *fp,
2703 bool leading)
2704 {
2705 unsigned long flags = 0;
2706
2707 /* calculate other queue flags */
2708 if (IS_MF_SD(bp))
2709 __set_bit(BNX2X_Q_FLG_OV, &flags);
2710
2711 if (IS_FCOE_FP(fp))
2712 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2713
2714 if (!fp->disable_tpa) {
2715 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2716 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2717 }
2718
2719 if (leading) {
2720 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2721 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2722 }
2723
2724 /* Always set HW VLAN stripping */
2725 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2726
2727
2728 return flags | bnx2x_get_common_flags(bp, fp, true);
2729 }
2730
2731 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2732 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2733 u8 cos)
2734 {
2735 gen_init->stat_id = bnx2x_stats_id(fp);
2736 gen_init->spcl_id = fp->cl_id;
2737
2738 /* Always use mini-jumbo MTU for FCoE L2 ring */
2739 if (IS_FCOE_FP(fp))
2740 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2741 else
2742 gen_init->mtu = bp->dev->mtu;
2743
2744 gen_init->cos = cos;
2745 }
2746
2747 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2748 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2749 struct bnx2x_rxq_setup_params *rxq_init)
2750 {
2751 u8 max_sge = 0;
2752 u16 sge_sz = 0;
2753 u16 tpa_agg_size = 0;
2754
2755 if (!fp->disable_tpa) {
2756 pause->sge_th_hi = 250;
2757 pause->sge_th_lo = 150;
2758 tpa_agg_size = min_t(u32,
2759 (min_t(u32, 8, MAX_SKB_FRAGS) *
2760 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2761 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2762 SGE_PAGE_SHIFT;
2763 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2764 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2765 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2766 0xffff);
2767 }
2768
2769 /* pause - not for e1 */
2770 if (!CHIP_IS_E1(bp)) {
2771 pause->bd_th_hi = 350;
2772 pause->bd_th_lo = 250;
2773 pause->rcq_th_hi = 350;
2774 pause->rcq_th_lo = 250;
2775
2776 pause->pri_map = 1;
2777 }
2778
2779 /* rxq setup */
2780 rxq_init->dscr_map = fp->rx_desc_mapping;
2781 rxq_init->sge_map = fp->rx_sge_mapping;
2782 rxq_init->rcq_map = fp->rx_comp_mapping;
2783 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2784
2785 /* This should be a maximum number of data bytes that may be
2786 * placed on the BD (not including paddings).
2787 */
2788 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2789 IP_HEADER_ALIGNMENT_PADDING;
2790
2791 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2792 rxq_init->tpa_agg_sz = tpa_agg_size;
2793 rxq_init->sge_buf_sz = sge_sz;
2794 rxq_init->max_sges_pkt = max_sge;
2795 rxq_init->rss_engine_id = BP_FUNC(bp);
2796
2797 /* Maximum number or simultaneous TPA aggregation for this Queue.
2798 *
2799 * For PF Clients it should be the maximum avaliable number.
2800 * VF driver(s) may want to define it to a smaller value.
2801 */
2802 rxq_init->max_tpa_queues =
2803 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2804 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2805
2806 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2807 rxq_init->fw_sb_id = fp->fw_sb_id;
2808
2809 if (IS_FCOE_FP(fp))
2810 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2811 else
2812 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2813 }
2814
2815 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2816 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2817 u8 cos)
2818 {
2819 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2820 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2821 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2822 txq_init->fw_sb_id = fp->fw_sb_id;
2823
2824 /*
2825 * set the tss leading client id for TX classfication ==
2826 * leading RSS client id
2827 */
2828 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2829
2830 if (IS_FCOE_FP(fp)) {
2831 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2832 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2833 }
2834 }
2835
2836 static void bnx2x_pf_init(struct bnx2x *bp)
2837 {
2838 struct bnx2x_func_init_params func_init = {0};
2839 struct event_ring_data eq_data = { {0} };
2840 u16 flags;
2841
2842 if (!CHIP_IS_E1x(bp)) {
2843 /* reset IGU PF statistics: MSIX + ATTN */
2844 /* PF */
2845 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2846 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2847 (CHIP_MODE_IS_4_PORT(bp) ?
2848 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2849 /* ATTN */
2850 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2851 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2852 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2853 (CHIP_MODE_IS_4_PORT(bp) ?
2854 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2855 }
2856
2857 /* function setup flags */
2858 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2859
2860 /* This flag is relevant for E1x only.
2861 * E2 doesn't have a TPA configuration in a function level.
2862 */
2863 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2864
2865 func_init.func_flgs = flags;
2866 func_init.pf_id = BP_FUNC(bp);
2867 func_init.func_id = BP_FUNC(bp);
2868 func_init.spq_map = bp->spq_mapping;
2869 func_init.spq_prod = bp->spq_prod_idx;
2870
2871 bnx2x_func_init(bp, &func_init);
2872
2873 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2874
2875 /*
2876 * Congestion management values depend on the link rate
2877 * There is no active link so initial link rate is set to 10 Gbps.
2878 * When the link comes up The congestion management values are
2879 * re-calculated according to the actual link rate.
2880 */
2881 bp->link_vars.line_speed = SPEED_10000;
2882 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2883
2884 /* Only the PMF sets the HW */
2885 if (bp->port.pmf)
2886 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2887
2888 /* init Event Queue */
2889 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2890 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2891 eq_data.producer = bp->eq_prod;
2892 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2893 eq_data.sb_id = DEF_SB_ID;
2894 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2895 }
2896
2897
2898 static void bnx2x_e1h_disable(struct bnx2x *bp)
2899 {
2900 int port = BP_PORT(bp);
2901
2902 bnx2x_tx_disable(bp);
2903
2904 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2905 }
2906
2907 static void bnx2x_e1h_enable(struct bnx2x *bp)
2908 {
2909 int port = BP_PORT(bp);
2910
2911 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2912
2913 /* Tx queue should be only reenabled */
2914 netif_tx_wake_all_queues(bp->dev);
2915
2916 /*
2917 * Should not call netif_carrier_on since it will be called if the link
2918 * is up when checking for link state
2919 */
2920 }
2921
2922 /* called due to MCP event (on pmf):
2923 * reread new bandwidth configuration
2924 * configure FW
2925 * notify others function about the change
2926 */
2927 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2928 {
2929 if (bp->link_vars.link_up) {
2930 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2931 bnx2x_link_sync_notify(bp);
2932 }
2933 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2934 }
2935
2936 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2937 {
2938 bnx2x_config_mf_bw(bp);
2939 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2940 }
2941
2942 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2943 {
2944 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2945
2946 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2947
2948 /*
2949 * This is the only place besides the function initialization
2950 * where the bp->flags can change so it is done without any
2951 * locks
2952 */
2953 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2954 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2955 bp->flags |= MF_FUNC_DIS;
2956
2957 bnx2x_e1h_disable(bp);
2958 } else {
2959 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2960 bp->flags &= ~MF_FUNC_DIS;
2961
2962 bnx2x_e1h_enable(bp);
2963 }
2964 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2965 }
2966 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2967 bnx2x_config_mf_bw(bp);
2968 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2969 }
2970
2971 /* Report results to MCP */
2972 if (dcc_event)
2973 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2974 else
2975 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2976 }
2977
2978 /* must be called under the spq lock */
2979 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2980 {
2981 struct eth_spe *next_spe = bp->spq_prod_bd;
2982
2983 if (bp->spq_prod_bd == bp->spq_last_bd) {
2984 bp->spq_prod_bd = bp->spq;
2985 bp->spq_prod_idx = 0;
2986 DP(NETIF_MSG_TIMER, "end of spq\n");
2987 } else {
2988 bp->spq_prod_bd++;
2989 bp->spq_prod_idx++;
2990 }
2991 return next_spe;
2992 }
2993
2994 /* must be called under the spq lock */
2995 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2996 {
2997 int func = BP_FUNC(bp);
2998
2999 /*
3000 * Make sure that BD data is updated before writing the producer:
3001 * BD data is written to the memory, the producer is read from the
3002 * memory, thus we need a full memory barrier to ensure the ordering.
3003 */
3004 mb();
3005
3006 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3007 bp->spq_prod_idx);
3008 mmiowb();
3009 }
3010
3011 /**
3012 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3013 *
3014 * @cmd: command to check
3015 * @cmd_type: command type
3016 */
3017 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3018 {
3019 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3020 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3021 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3022 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3023 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3024 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3025 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3026 return true;
3027 else
3028 return false;
3029
3030 }
3031
3032
3033 /**
3034 * bnx2x_sp_post - place a single command on an SP ring
3035 *
3036 * @bp: driver handle
3037 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3038 * @cid: SW CID the command is related to
3039 * @data_hi: command private data address (high 32 bits)
3040 * @data_lo: command private data address (low 32 bits)
3041 * @cmd_type: command type (e.g. NONE, ETH)
3042 *
3043 * SP data is handled as if it's always an address pair, thus data fields are
3044 * not swapped to little endian in upper functions. Instead this function swaps
3045 * data as if it's two u32 fields.
3046 */
3047 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3048 u32 data_hi, u32 data_lo, int cmd_type)
3049 {
3050 struct eth_spe *spe;
3051 u16 type;
3052 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3053
3054 #ifdef BNX2X_STOP_ON_ERROR
3055 if (unlikely(bp->panic))
3056 return -EIO;
3057 #endif
3058
3059 spin_lock_bh(&bp->spq_lock);
3060
3061 if (common) {
3062 if (!atomic_read(&bp->eq_spq_left)) {
3063 BNX2X_ERR("BUG! EQ ring full!\n");
3064 spin_unlock_bh(&bp->spq_lock);
3065 bnx2x_panic();
3066 return -EBUSY;
3067 }
3068 } else if (!atomic_read(&bp->cq_spq_left)) {
3069 BNX2X_ERR("BUG! SPQ ring full!\n");
3070 spin_unlock_bh(&bp->spq_lock);
3071 bnx2x_panic();
3072 return -EBUSY;
3073 }
3074
3075 spe = bnx2x_sp_get_next(bp);
3076
3077 /* CID needs port number to be encoded int it */
3078 spe->hdr.conn_and_cmd_data =
3079 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3080 HW_CID(bp, cid));
3081
3082 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3083
3084 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3085 SPE_HDR_FUNCTION_ID);
3086
3087 spe->hdr.type = cpu_to_le16(type);
3088
3089 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3090 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3091
3092 /*
3093 * It's ok if the actual decrement is issued towards the memory
3094 * somewhere between the spin_lock and spin_unlock. Thus no
3095 * more explict memory barrier is needed.
3096 */
3097 if (common)
3098 atomic_dec(&bp->eq_spq_left);
3099 else
3100 atomic_dec(&bp->cq_spq_left);
3101
3102
3103 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3104 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3105 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3106 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3107 (u32)(U64_LO(bp->spq_mapping) +
3108 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3109 HW_CID(bp, cid), data_hi, data_lo, type,
3110 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3111
3112 bnx2x_sp_prod_update(bp);
3113 spin_unlock_bh(&bp->spq_lock);
3114 return 0;
3115 }
3116
3117 /* acquire split MCP access lock register */
3118 static int bnx2x_acquire_alr(struct bnx2x *bp)
3119 {
3120 u32 j, val;
3121 int rc = 0;
3122
3123 might_sleep();
3124 for (j = 0; j < 1000; j++) {
3125 val = (1UL << 31);
3126 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3127 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3128 if (val & (1L << 31))
3129 break;
3130
3131 msleep(5);
3132 }
3133 if (!(val & (1L << 31))) {
3134 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3135 rc = -EBUSY;
3136 }
3137
3138 return rc;
3139 }
3140
3141 /* release split MCP access lock register */
3142 static void bnx2x_release_alr(struct bnx2x *bp)
3143 {
3144 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3145 }
3146
3147 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3148 #define BNX2X_DEF_SB_IDX 0x0002
3149
3150 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3151 {
3152 struct host_sp_status_block *def_sb = bp->def_status_blk;
3153 u16 rc = 0;
3154
3155 barrier(); /* status block is written to by the chip */
3156 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3157 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3158 rc |= BNX2X_DEF_SB_ATT_IDX;
3159 }
3160
3161 if (bp->def_idx != def_sb->sp_sb.running_index) {
3162 bp->def_idx = def_sb->sp_sb.running_index;
3163 rc |= BNX2X_DEF_SB_IDX;
3164 }
3165
3166 /* Do not reorder: indecies reading should complete before handling */
3167 barrier();
3168 return rc;
3169 }
3170
3171 /*
3172 * slow path service functions
3173 */
3174
3175 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3176 {
3177 int port = BP_PORT(bp);
3178 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3179 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3180 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3181 NIG_REG_MASK_INTERRUPT_PORT0;
3182 u32 aeu_mask;
3183 u32 nig_mask = 0;
3184 u32 reg_addr;
3185
3186 if (bp->attn_state & asserted)
3187 BNX2X_ERR("IGU ERROR\n");
3188
3189 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3190 aeu_mask = REG_RD(bp, aeu_addr);
3191
3192 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3193 aeu_mask, asserted);
3194 aeu_mask &= ~(asserted & 0x3ff);
3195 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3196
3197 REG_WR(bp, aeu_addr, aeu_mask);
3198 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3199
3200 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3201 bp->attn_state |= asserted;
3202 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3203
3204 if (asserted & ATTN_HARD_WIRED_MASK) {
3205 if (asserted & ATTN_NIG_FOR_FUNC) {
3206
3207 bnx2x_acquire_phy_lock(bp);
3208
3209 /* save nig interrupt mask */
3210 nig_mask = REG_RD(bp, nig_int_mask_addr);
3211
3212 /* If nig_mask is not set, no need to call the update
3213 * function.
3214 */
3215 if (nig_mask) {
3216 REG_WR(bp, nig_int_mask_addr, 0);
3217
3218 bnx2x_link_attn(bp);
3219 }
3220
3221 /* handle unicore attn? */
3222 }
3223 if (asserted & ATTN_SW_TIMER_4_FUNC)
3224 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3225
3226 if (asserted & GPIO_2_FUNC)
3227 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3228
3229 if (asserted & GPIO_3_FUNC)
3230 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3231
3232 if (asserted & GPIO_4_FUNC)
3233 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3234
3235 if (port == 0) {
3236 if (asserted & ATTN_GENERAL_ATTN_1) {
3237 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3238 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3239 }
3240 if (asserted & ATTN_GENERAL_ATTN_2) {
3241 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3242 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3243 }
3244 if (asserted & ATTN_GENERAL_ATTN_3) {
3245 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3246 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3247 }
3248 } else {
3249 if (asserted & ATTN_GENERAL_ATTN_4) {
3250 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3251 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3252 }
3253 if (asserted & ATTN_GENERAL_ATTN_5) {
3254 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3255 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3256 }
3257 if (asserted & ATTN_GENERAL_ATTN_6) {
3258 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3259 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3260 }
3261 }
3262
3263 } /* if hardwired */
3264
3265 if (bp->common.int_block == INT_BLOCK_HC)
3266 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3267 COMMAND_REG_ATTN_BITS_SET);
3268 else
3269 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3270
3271 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3272 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3273 REG_WR(bp, reg_addr, asserted);
3274
3275 /* now set back the mask */
3276 if (asserted & ATTN_NIG_FOR_FUNC) {
3277 REG_WR(bp, nig_int_mask_addr, nig_mask);
3278 bnx2x_release_phy_lock(bp);
3279 }
3280 }
3281
3282 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3283 {
3284 int port = BP_PORT(bp);
3285 u32 ext_phy_config;
3286 /* mark the failure */
3287 ext_phy_config =
3288 SHMEM_RD(bp,
3289 dev_info.port_hw_config[port].external_phy_config);
3290
3291 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3292 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3293 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3294 ext_phy_config);
3295
3296 /* log the failure */
3297 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3298 " the driver to shutdown the card to prevent permanent"
3299 " damage. Please contact OEM Support for assistance\n");
3300 }
3301
3302 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3303 {
3304 int port = BP_PORT(bp);
3305 int reg_offset;
3306 u32 val;
3307
3308 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3309 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3310
3311 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3312
3313 val = REG_RD(bp, reg_offset);
3314 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3315 REG_WR(bp, reg_offset, val);
3316
3317 BNX2X_ERR("SPIO5 hw attention\n");
3318
3319 /* Fan failure attention */
3320 bnx2x_hw_reset_phy(&bp->link_params);
3321 bnx2x_fan_failure(bp);
3322 }
3323
3324 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3325 bnx2x_acquire_phy_lock(bp);
3326 bnx2x_handle_module_detect_int(&bp->link_params);
3327 bnx2x_release_phy_lock(bp);
3328 }
3329
3330 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3331
3332 val = REG_RD(bp, reg_offset);
3333 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3334 REG_WR(bp, reg_offset, val);
3335
3336 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3337 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3338 bnx2x_panic();
3339 }
3340 }
3341
3342 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3343 {
3344 u32 val;
3345
3346 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3347
3348 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3349 BNX2X_ERR("DB hw attention 0x%x\n", val);
3350 /* DORQ discard attention */
3351 if (val & 0x2)
3352 BNX2X_ERR("FATAL error from DORQ\n");
3353 }
3354
3355 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3356
3357 int port = BP_PORT(bp);
3358 int reg_offset;
3359
3360 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3361 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3362
3363 val = REG_RD(bp, reg_offset);
3364 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3365 REG_WR(bp, reg_offset, val);
3366
3367 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3368 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3369 bnx2x_panic();
3370 }
3371 }
3372
3373 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3374 {
3375 u32 val;
3376
3377 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3378
3379 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3380 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3381 /* CFC error attention */
3382 if (val & 0x2)
3383 BNX2X_ERR("FATAL error from CFC\n");
3384 }
3385
3386 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3387 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3388 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3389 /* RQ_USDMDP_FIFO_OVERFLOW */
3390 if (val & 0x18000)
3391 BNX2X_ERR("FATAL error from PXP\n");
3392
3393 if (!CHIP_IS_E1x(bp)) {
3394 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3395 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3396 }
3397 }
3398
3399 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3400
3401 int port = BP_PORT(bp);
3402 int reg_offset;
3403
3404 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3405 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3406
3407 val = REG_RD(bp, reg_offset);
3408 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3409 REG_WR(bp, reg_offset, val);
3410
3411 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3412 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3413 bnx2x_panic();
3414 }
3415 }
3416
3417 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3418 {
3419 u32 val;
3420
3421 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3422
3423 if (attn & BNX2X_PMF_LINK_ASSERT) {
3424 int func = BP_FUNC(bp);
3425
3426 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3427 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3428 func_mf_config[BP_ABS_FUNC(bp)].config);
3429 val = SHMEM_RD(bp,
3430 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3431 if (val & DRV_STATUS_DCC_EVENT_MASK)
3432 bnx2x_dcc_event(bp,
3433 (val & DRV_STATUS_DCC_EVENT_MASK));
3434
3435 if (val & DRV_STATUS_SET_MF_BW)
3436 bnx2x_set_mf_bw(bp);
3437
3438 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3439 bnx2x_pmf_update(bp);
3440
3441 if (bp->port.pmf &&
3442 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3443 bp->dcbx_enabled > 0)
3444 /* start dcbx state machine */
3445 bnx2x_dcbx_set_params(bp,
3446 BNX2X_DCBX_STATE_NEG_RECEIVED);
3447 if (bp->link_vars.periodic_flags &
3448 PERIODIC_FLAGS_LINK_EVENT) {
3449 /* sync with link */
3450 bnx2x_acquire_phy_lock(bp);
3451 bp->link_vars.periodic_flags &=
3452 ~PERIODIC_FLAGS_LINK_EVENT;
3453 bnx2x_release_phy_lock(bp);
3454 if (IS_MF(bp))
3455 bnx2x_link_sync_notify(bp);
3456 bnx2x_link_report(bp);
3457 }
3458 /* Always call it here: bnx2x_link_report() will
3459 * prevent the link indication duplication.
3460 */
3461 bnx2x__link_status_update(bp);
3462 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3463
3464 BNX2X_ERR("MC assert!\n");
3465 bnx2x_mc_assert(bp);
3466 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3467 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3468 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3470 bnx2x_panic();
3471
3472 } else if (attn & BNX2X_MCP_ASSERT) {
3473
3474 BNX2X_ERR("MCP assert!\n");
3475 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3476 bnx2x_fw_dump(bp);
3477
3478 } else
3479 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3480 }
3481
3482 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3483 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3484 if (attn & BNX2X_GRC_TIMEOUT) {
3485 val = CHIP_IS_E1(bp) ? 0 :
3486 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3487 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3488 }
3489 if (attn & BNX2X_GRC_RSV) {
3490 val = CHIP_IS_E1(bp) ? 0 :
3491 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3492 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3493 }
3494 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3495 }
3496 }
3497
3498 /*
3499 * Bits map:
3500 * 0-7 - Engine0 load counter.
3501 * 8-15 - Engine1 load counter.
3502 * 16 - Engine0 RESET_IN_PROGRESS bit.
3503 * 17 - Engine1 RESET_IN_PROGRESS bit.
3504 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3505 * on the engine
3506 * 19 - Engine1 ONE_IS_LOADED.
3507 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3508 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3509 * just the one belonging to its engine).
3510 *
3511 */
3512 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3513
3514 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3515 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3516 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3517 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3518 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3519 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3520 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3521
3522 /*
3523 * Set the GLOBAL_RESET bit.
3524 *
3525 * Should be run under rtnl lock
3526 */
3527 void bnx2x_set_reset_global(struct bnx2x *bp)
3528 {
3529 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3530
3531 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3532 barrier();
3533 mmiowb();
3534 }
3535
3536 /*
3537 * Clear the GLOBAL_RESET bit.
3538 *
3539 * Should be run under rtnl lock
3540 */
3541 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3542 {
3543 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3544
3545 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3546 barrier();
3547 mmiowb();
3548 }
3549
3550 /*
3551 * Checks the GLOBAL_RESET bit.
3552 *
3553 * should be run under rtnl lock
3554 */
3555 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3556 {
3557 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3558
3559 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3560 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3561 }
3562
3563 /*
3564 * Clear RESET_IN_PROGRESS bit for the current engine.
3565 *
3566 * Should be run under rtnl lock
3567 */
3568 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3569 {
3570 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3571 u32 bit = BP_PATH(bp) ?
3572 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3573
3574 /* Clear the bit */
3575 val &= ~bit;
3576 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3577 barrier();
3578 mmiowb();
3579 }
3580
3581 /*
3582 * Set RESET_IN_PROGRESS for the current engine.
3583 *
3584 * should be run under rtnl lock
3585 */
3586 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3587 {
3588 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3589 u32 bit = BP_PATH(bp) ?
3590 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3591
3592 /* Set the bit */
3593 val |= bit;
3594 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3595 barrier();
3596 mmiowb();
3597 }
3598
3599 /*
3600 * Checks the RESET_IN_PROGRESS bit for the given engine.
3601 * should be run under rtnl lock
3602 */
3603 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3604 {
3605 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3606 u32 bit = engine ?
3607 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3608
3609 /* return false if bit is set */
3610 return (val & bit) ? false : true;
3611 }
3612
3613 /*
3614 * Increment the load counter for the current engine.
3615 *
3616 * should be run under rtnl lock
3617 */
3618 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3619 {
3620 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3621 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3622 BNX2X_PATH0_LOAD_CNT_MASK;
3623 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3624 BNX2X_PATH0_LOAD_CNT_SHIFT;
3625
3626 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3627
3628 /* get the current counter value */
3629 val1 = (val & mask) >> shift;
3630
3631 /* increment... */
3632 val1++;
3633
3634 /* clear the old value */
3635 val &= ~mask;
3636
3637 /* set the new one */
3638 val |= ((val1 << shift) & mask);
3639
3640 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3641 barrier();
3642 mmiowb();
3643 }
3644
3645 /**
3646 * bnx2x_dec_load_cnt - decrement the load counter
3647 *
3648 * @bp: driver handle
3649 *
3650 * Should be run under rtnl lock.
3651 * Decrements the load counter for the current engine. Returns
3652 * the new counter value.
3653 */
3654 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3655 {
3656 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3657 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3658 BNX2X_PATH0_LOAD_CNT_MASK;
3659 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3660 BNX2X_PATH0_LOAD_CNT_SHIFT;
3661
3662 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3663
3664 /* get the current counter value */
3665 val1 = (val & mask) >> shift;
3666
3667 /* decrement... */
3668 val1--;
3669
3670 /* clear the old value */
3671 val &= ~mask;
3672
3673 /* set the new one */
3674 val |= ((val1 << shift) & mask);
3675
3676 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3677 barrier();
3678 mmiowb();
3679
3680 return val1;
3681 }
3682
3683 /*
3684 * Read the load counter for the current engine.
3685 *
3686 * should be run under rtnl lock
3687 */
3688 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3689 {
3690 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3691 BNX2X_PATH0_LOAD_CNT_MASK);
3692 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3693 BNX2X_PATH0_LOAD_CNT_SHIFT);
3694 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3695
3696 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3697
3698 val = (val & mask) >> shift;
3699
3700 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3701
3702 return val;
3703 }
3704
3705 /*
3706 * Reset the load counter for the current engine.
3707 *
3708 * should be run under rtnl lock
3709 */
3710 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3711 {
3712 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3713 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3714 BNX2X_PATH0_LOAD_CNT_MASK);
3715
3716 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3717 }
3718
3719 static inline void _print_next_block(int idx, const char *blk)
3720 {
3721 pr_cont("%s%s", idx ? ", " : "", blk);
3722 }
3723
3724 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3725 bool print)
3726 {
3727 int i = 0;
3728 u32 cur_bit = 0;
3729 for (i = 0; sig; i++) {
3730 cur_bit = ((u32)0x1 << i);
3731 if (sig & cur_bit) {
3732 switch (cur_bit) {
3733 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3734 if (print)
3735 _print_next_block(par_num++, "BRB");
3736 break;
3737 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3738 if (print)
3739 _print_next_block(par_num++, "PARSER");
3740 break;
3741 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3742 if (print)
3743 _print_next_block(par_num++, "TSDM");
3744 break;
3745 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3746 if (print)
3747 _print_next_block(par_num++,
3748 "SEARCHER");
3749 break;
3750 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3751 if (print)
3752 _print_next_block(par_num++, "TCM");
3753 break;
3754 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3755 if (print)
3756 _print_next_block(par_num++, "TSEMI");
3757 break;
3758 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3759 if (print)
3760 _print_next_block(par_num++, "XPB");
3761 break;
3762 }
3763
3764 /* Clear the bit */
3765 sig &= ~cur_bit;
3766 }
3767 }
3768
3769 return par_num;
3770 }
3771
3772 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3773 bool *global, bool print)
3774 {
3775 int i = 0;
3776 u32 cur_bit = 0;
3777 for (i = 0; sig; i++) {
3778 cur_bit = ((u32)0x1 << i);
3779 if (sig & cur_bit) {
3780 switch (cur_bit) {
3781 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3782 if (print)
3783 _print_next_block(par_num++, "PBF");
3784 break;
3785 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3786 if (print)
3787 _print_next_block(par_num++, "QM");
3788 break;
3789 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3790 if (print)
3791 _print_next_block(par_num++, "TM");
3792 break;
3793 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3794 if (print)
3795 _print_next_block(par_num++, "XSDM");
3796 break;
3797 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3798 if (print)
3799 _print_next_block(par_num++, "XCM");
3800 break;
3801 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3802 if (print)
3803 _print_next_block(par_num++, "XSEMI");
3804 break;
3805 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3806 if (print)
3807 _print_next_block(par_num++,
3808 "DOORBELLQ");
3809 break;
3810 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3811 if (print)
3812 _print_next_block(par_num++, "NIG");
3813 break;
3814 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3815 if (print)
3816 _print_next_block(par_num++,
3817 "VAUX PCI CORE");
3818 *global = true;
3819 break;
3820 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3821 if (print)
3822 _print_next_block(par_num++, "DEBUG");
3823 break;
3824 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3825 if (print)
3826 _print_next_block(par_num++, "USDM");
3827 break;
3828 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3829 if (print)
3830 _print_next_block(par_num++, "UCM");
3831 break;
3832 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3833 if (print)
3834 _print_next_block(par_num++, "USEMI");
3835 break;
3836 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3837 if (print)
3838 _print_next_block(par_num++, "UPB");
3839 break;
3840 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3841 if (print)
3842 _print_next_block(par_num++, "CSDM");
3843 break;
3844 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3845 if (print)
3846 _print_next_block(par_num++, "CCM");
3847 break;
3848 }
3849
3850 /* Clear the bit */
3851 sig &= ~cur_bit;
3852 }
3853 }
3854
3855 return par_num;
3856 }
3857
3858 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3859 bool print)
3860 {
3861 int i = 0;
3862 u32 cur_bit = 0;
3863 for (i = 0; sig; i++) {
3864 cur_bit = ((u32)0x1 << i);
3865 if (sig & cur_bit) {
3866 switch (cur_bit) {
3867 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3868 if (print)
3869 _print_next_block(par_num++, "CSEMI");
3870 break;
3871 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3872 if (print)
3873 _print_next_block(par_num++, "PXP");
3874 break;
3875 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3876 if (print)
3877 _print_next_block(par_num++,
3878 "PXPPCICLOCKCLIENT");
3879 break;
3880 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3881 if (print)
3882 _print_next_block(par_num++, "CFC");
3883 break;
3884 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3885 if (print)
3886 _print_next_block(par_num++, "CDU");
3887 break;
3888 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3889 if (print)
3890 _print_next_block(par_num++, "DMAE");
3891 break;
3892 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3893 if (print)
3894 _print_next_block(par_num++, "IGU");
3895 break;
3896 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3897 if (print)
3898 _print_next_block(par_num++, "MISC");
3899 break;
3900 }
3901
3902 /* Clear the bit */
3903 sig &= ~cur_bit;
3904 }
3905 }
3906
3907 return par_num;
3908 }
3909
3910 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3911 bool *global, bool print)
3912 {
3913 int i = 0;
3914 u32 cur_bit = 0;
3915 for (i = 0; sig; i++) {
3916 cur_bit = ((u32)0x1 << i);
3917 if (sig & cur_bit) {
3918 switch (cur_bit) {
3919 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3920 if (print)
3921 _print_next_block(par_num++, "MCP ROM");
3922 *global = true;
3923 break;
3924 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3925 if (print)
3926 _print_next_block(par_num++,
3927 "MCP UMP RX");
3928 *global = true;
3929 break;
3930 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3931 if (print)
3932 _print_next_block(par_num++,
3933 "MCP UMP TX");
3934 *global = true;
3935 break;
3936 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3937 if (print)
3938 _print_next_block(par_num++,
3939 "MCP SCPAD");
3940 *global = true;
3941 break;
3942 }
3943
3944 /* Clear the bit */
3945 sig &= ~cur_bit;
3946 }
3947 }
3948
3949 return par_num;
3950 }
3951
3952 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3953 bool print)
3954 {
3955 int i = 0;
3956 u32 cur_bit = 0;
3957 for (i = 0; sig; i++) {
3958 cur_bit = ((u32)0x1 << i);
3959 if (sig & cur_bit) {
3960 switch (cur_bit) {
3961 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3962 if (print)
3963 _print_next_block(par_num++, "PGLUE_B");
3964 break;
3965 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3966 if (print)
3967 _print_next_block(par_num++, "ATC");
3968 break;
3969 }
3970
3971 /* Clear the bit */
3972 sig &= ~cur_bit;
3973 }
3974 }
3975
3976 return par_num;
3977 }
3978
3979 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3980 u32 *sig)
3981 {
3982 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3983 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3984 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3985 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3986 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3987 int par_num = 0;
3988 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3989 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3990 "[4]:0x%08x\n",
3991 sig[0] & HW_PRTY_ASSERT_SET_0,
3992 sig[1] & HW_PRTY_ASSERT_SET_1,
3993 sig[2] & HW_PRTY_ASSERT_SET_2,
3994 sig[3] & HW_PRTY_ASSERT_SET_3,
3995 sig[4] & HW_PRTY_ASSERT_SET_4);
3996 if (print)
3997 netdev_err(bp->dev,
3998 "Parity errors detected in blocks: ");
3999 par_num = bnx2x_check_blocks_with_parity0(
4000 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4001 par_num = bnx2x_check_blocks_with_parity1(
4002 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4003 par_num = bnx2x_check_blocks_with_parity2(
4004 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4005 par_num = bnx2x_check_blocks_with_parity3(
4006 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4007 par_num = bnx2x_check_blocks_with_parity4(
4008 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4009
4010 if (print)
4011 pr_cont("\n");
4012
4013 return true;
4014 } else
4015 return false;
4016 }
4017
4018 /**
4019 * bnx2x_chk_parity_attn - checks for parity attentions.
4020 *
4021 * @bp: driver handle
4022 * @global: true if there was a global attention
4023 * @print: show parity attention in syslog
4024 */
4025 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4026 {
4027 struct attn_route attn = { {0} };
4028 int port = BP_PORT(bp);
4029
4030 attn.sig[0] = REG_RD(bp,
4031 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4032 port*4);
4033 attn.sig[1] = REG_RD(bp,
4034 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4035 port*4);
4036 attn.sig[2] = REG_RD(bp,
4037 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4038 port*4);
4039 attn.sig[3] = REG_RD(bp,
4040 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4041 port*4);
4042
4043 if (!CHIP_IS_E1x(bp))
4044 attn.sig[4] = REG_RD(bp,
4045 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4046 port*4);
4047
4048 return bnx2x_parity_attn(bp, global, print, attn.sig);
4049 }
4050
4051
4052 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4053 {
4054 u32 val;
4055 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4056
4057 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4058 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4059 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4060 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4061 "ADDRESS_ERROR\n");
4062 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4063 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4064 "INCORRECT_RCV_BEHAVIOR\n");
4065 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4066 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4067 "WAS_ERROR_ATTN\n");
4068 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4069 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4070 "VF_LENGTH_VIOLATION_ATTN\n");
4071 if (val &
4072 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4074 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4075 if (val &
4076 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4077 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4078 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4079 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4080 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4081 "TCPL_ERROR_ATTN\n");
4082 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4083 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4084 "TCPL_IN_TWO_RCBS_ATTN\n");
4085 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4086 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4087 "CSSNOOP_FIFO_OVERFLOW\n");
4088 }
4089 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4090 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4091 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4092 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4093 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4094 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4095 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4096 "_ATC_TCPL_TO_NOT_PEND\n");
4097 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4098 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4099 "ATC_GPA_MULTIPLE_HITS\n");
4100 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4101 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4102 "ATC_RCPL_TO_EMPTY_CNT\n");
4103 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4104 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4105 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4107 "ATC_IREQ_LESS_THAN_STU\n");
4108 }
4109
4110 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4111 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4112 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4113 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4114 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4115 }
4116
4117 }
4118
4119 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4120 {
4121 struct attn_route attn, *group_mask;
4122 int port = BP_PORT(bp);
4123 int index;
4124 u32 reg_addr;
4125 u32 val;
4126 u32 aeu_mask;
4127 bool global = false;
4128
4129 /* need to take HW lock because MCP or other port might also
4130 try to handle this event */
4131 bnx2x_acquire_alr(bp);
4132
4133 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4134 #ifndef BNX2X_STOP_ON_ERROR
4135 bp->recovery_state = BNX2X_RECOVERY_INIT;
4136 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4137 /* Disable HW interrupts */
4138 bnx2x_int_disable(bp);
4139 /* In case of parity errors don't handle attentions so that
4140 * other function would "see" parity errors.
4141 */
4142 #else
4143 bnx2x_panic();
4144 #endif
4145 bnx2x_release_alr(bp);
4146 return;
4147 }
4148
4149 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4150 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4151 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4152 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4153 if (!CHIP_IS_E1x(bp))
4154 attn.sig[4] =
4155 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4156 else
4157 attn.sig[4] = 0;
4158
4159 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4160 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4161
4162 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4163 if (deasserted & (1 << index)) {
4164 group_mask = &bp->attn_group[index];
4165
4166 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4167 "%08x %08x %08x\n",
4168 index,
4169 group_mask->sig[0], group_mask->sig[1],
4170 group_mask->sig[2], group_mask->sig[3],
4171 group_mask->sig[4]);
4172
4173 bnx2x_attn_int_deasserted4(bp,
4174 attn.sig[4] & group_mask->sig[4]);
4175 bnx2x_attn_int_deasserted3(bp,
4176 attn.sig[3] & group_mask->sig[3]);
4177 bnx2x_attn_int_deasserted1(bp,
4178 attn.sig[1] & group_mask->sig[1]);
4179 bnx2x_attn_int_deasserted2(bp,
4180 attn.sig[2] & group_mask->sig[2]);
4181 bnx2x_attn_int_deasserted0(bp,
4182 attn.sig[0] & group_mask->sig[0]);
4183 }
4184 }
4185
4186 bnx2x_release_alr(bp);
4187
4188 if (bp->common.int_block == INT_BLOCK_HC)
4189 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4190 COMMAND_REG_ATTN_BITS_CLR);
4191 else
4192 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4193
4194 val = ~deasserted;
4195 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4196 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4197 REG_WR(bp, reg_addr, val);
4198
4199 if (~bp->attn_state & deasserted)
4200 BNX2X_ERR("IGU ERROR\n");
4201
4202 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4203 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4204
4205 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4206 aeu_mask = REG_RD(bp, reg_addr);
4207
4208 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4209 aeu_mask, deasserted);
4210 aeu_mask |= (deasserted & 0x3ff);
4211 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4212
4213 REG_WR(bp, reg_addr, aeu_mask);
4214 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4215
4216 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4217 bp->attn_state &= ~deasserted;
4218 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4219 }
4220
4221 static void bnx2x_attn_int(struct bnx2x *bp)
4222 {
4223 /* read local copy of bits */
4224 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4225 attn_bits);
4226 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4227 attn_bits_ack);
4228 u32 attn_state = bp->attn_state;
4229
4230 /* look for changed bits */
4231 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4232 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4233
4234 DP(NETIF_MSG_HW,
4235 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4236 attn_bits, attn_ack, asserted, deasserted);
4237
4238 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4239 BNX2X_ERR("BAD attention state\n");
4240
4241 /* handle bits that were raised */
4242 if (asserted)
4243 bnx2x_attn_int_asserted(bp, asserted);
4244
4245 if (deasserted)
4246 bnx2x_attn_int_deasserted(bp, deasserted);
4247 }
4248
4249 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4250 u16 index, u8 op, u8 update)
4251 {
4252 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4253
4254 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4255 igu_addr);
4256 }
4257
4258 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4259 {
4260 /* No memory barriers */
4261 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4262 mmiowb(); /* keep prod updates ordered */
4263 }
4264
4265 #ifdef BCM_CNIC
4266 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4267 union event_ring_elem *elem)
4268 {
4269 u8 err = elem->message.error;
4270
4271 if (!bp->cnic_eth_dev.starting_cid ||
4272 (cid < bp->cnic_eth_dev.starting_cid &&
4273 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4274 return 1;
4275
4276 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4277
4278 if (unlikely(err)) {
4279
4280 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4281 cid);
4282 bnx2x_panic_dump(bp);
4283 }
4284 bnx2x_cnic_cfc_comp(bp, cid, err);
4285 return 0;
4286 }
4287 #endif
4288
4289 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4290 {
4291 struct bnx2x_mcast_ramrod_params rparam;
4292 int rc;
4293
4294 memset(&rparam, 0, sizeof(rparam));
4295
4296 rparam.mcast_obj = &bp->mcast_obj;
4297
4298 netif_addr_lock_bh(bp->dev);
4299
4300 /* Clear pending state for the last command */
4301 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4302
4303 /* If there are pending mcast commands - send them */
4304 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4305 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4306 if (rc < 0)
4307 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4308 rc);
4309 }
4310
4311 netif_addr_unlock_bh(bp->dev);
4312 }
4313
4314 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4315 union event_ring_elem *elem)
4316 {
4317 unsigned long ramrod_flags = 0;
4318 int rc = 0;
4319 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4320 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4321
4322 /* Always push next commands out, don't wait here */
4323 __set_bit(RAMROD_CONT, &ramrod_flags);
4324
4325 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4326 case BNX2X_FILTER_MAC_PENDING:
4327 #ifdef BCM_CNIC
4328 if (cid == BNX2X_ISCSI_ETH_CID)
4329 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4330 else
4331 #endif
4332 vlan_mac_obj = &bp->fp[cid].mac_obj;
4333
4334 break;
4335 vlan_mac_obj = &bp->fp[cid].mac_obj;
4336
4337 case BNX2X_FILTER_MCAST_PENDING:
4338 /* This is only relevant for 57710 where multicast MACs are
4339 * configured as unicast MACs using the same ramrod.
4340 */
4341 bnx2x_handle_mcast_eqe(bp);
4342 return;
4343 default:
4344 BNX2X_ERR("Unsupported classification command: %d\n",
4345 elem->message.data.eth_event.echo);
4346 return;
4347 }
4348
4349 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4350
4351 if (rc < 0)
4352 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4353 else if (rc > 0)
4354 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4355
4356 }
4357
4358 #ifdef BCM_CNIC
4359 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4360 #endif
4361
4362 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4363 {
4364 netif_addr_lock_bh(bp->dev);
4365
4366 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4367
4368 /* Send rx_mode command again if was requested */
4369 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4370 bnx2x_set_storm_rx_mode(bp);
4371 #ifdef BCM_CNIC
4372 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4373 &bp->sp_state))
4374 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4375 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4376 &bp->sp_state))
4377 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4378 #endif
4379
4380 netif_addr_unlock_bh(bp->dev);
4381 }
4382
4383 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4384 struct bnx2x *bp, u32 cid)
4385 {
4386 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4387 #ifdef BCM_CNIC
4388 if (cid == BNX2X_FCOE_ETH_CID)
4389 return &bnx2x_fcoe(bp, q_obj);
4390 else
4391 #endif
4392 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4393 }
4394
4395 static void bnx2x_eq_int(struct bnx2x *bp)
4396 {
4397 u16 hw_cons, sw_cons, sw_prod;
4398 union event_ring_elem *elem;
4399 u32 cid;
4400 u8 opcode;
4401 int spqe_cnt = 0;
4402 struct bnx2x_queue_sp_obj *q_obj;
4403 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4404 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4405
4406 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4407
4408 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4409 * when we get the the next-page we nned to adjust so the loop
4410 * condition below will be met. The next element is the size of a
4411 * regular element and hence incrementing by 1
4412 */
4413 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4414 hw_cons++;
4415
4416 /* This function may never run in parallel with itself for a
4417 * specific bp, thus there is no need in "paired" read memory
4418 * barrier here.
4419 */
4420 sw_cons = bp->eq_cons;
4421 sw_prod = bp->eq_prod;
4422
4423 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4424 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4425
4426 for (; sw_cons != hw_cons;
4427 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4428
4429
4430 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4431
4432 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4433 opcode = elem->message.opcode;
4434
4435
4436 /* handle eq element */
4437 switch (opcode) {
4438 case EVENT_RING_OPCODE_STAT_QUERY:
4439 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4440 bp->stats_comp++);
4441 /* nothing to do with stats comp */
4442 goto next_spqe;
4443
4444 case EVENT_RING_OPCODE_CFC_DEL:
4445 /* handle according to cid range */
4446 /*
4447 * we may want to verify here that the bp state is
4448 * HALTING
4449 */
4450 DP(BNX2X_MSG_SP,
4451 "got delete ramrod for MULTI[%d]\n", cid);
4452 #ifdef BCM_CNIC
4453 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4454 goto next_spqe;
4455 #endif
4456 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4457
4458 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4459 break;
4460
4461
4462
4463 goto next_spqe;
4464
4465 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4466 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4467 if (f_obj->complete_cmd(bp, f_obj,
4468 BNX2X_F_CMD_TX_STOP))
4469 break;
4470 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4471 goto next_spqe;
4472
4473 case EVENT_RING_OPCODE_START_TRAFFIC:
4474 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4475 if (f_obj->complete_cmd(bp, f_obj,
4476 BNX2X_F_CMD_TX_START))
4477 break;
4478 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4479 goto next_spqe;
4480 case EVENT_RING_OPCODE_FUNCTION_START:
4481 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4482 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4483 break;
4484
4485 goto next_spqe;
4486
4487 case EVENT_RING_OPCODE_FUNCTION_STOP:
4488 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4489 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4490 break;
4491
4492 goto next_spqe;
4493 }
4494
4495 switch (opcode | bp->state) {
4496 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4497 BNX2X_STATE_OPEN):
4498 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4499 BNX2X_STATE_OPENING_WAIT4_PORT):
4500 cid = elem->message.data.eth_event.echo &
4501 BNX2X_SWCID_MASK;
4502 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4503 cid);
4504 rss_raw->clear_pending(rss_raw);
4505 break;
4506
4507 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4508 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4509 case (EVENT_RING_OPCODE_SET_MAC |
4510 BNX2X_STATE_CLOSING_WAIT4_HALT):
4511 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4512 BNX2X_STATE_OPEN):
4513 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4514 BNX2X_STATE_DIAG):
4515 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4516 BNX2X_STATE_CLOSING_WAIT4_HALT):
4517 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4518 bnx2x_handle_classification_eqe(bp, elem);
4519 break;
4520
4521 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4522 BNX2X_STATE_OPEN):
4523 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4524 BNX2X_STATE_DIAG):
4525 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4526 BNX2X_STATE_CLOSING_WAIT4_HALT):
4527 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4528 bnx2x_handle_mcast_eqe(bp);
4529 break;
4530
4531 case (EVENT_RING_OPCODE_FILTERS_RULES |
4532 BNX2X_STATE_OPEN):
4533 case (EVENT_RING_OPCODE_FILTERS_RULES |
4534 BNX2X_STATE_DIAG):
4535 case (EVENT_RING_OPCODE_FILTERS_RULES |
4536 BNX2X_STATE_CLOSING_WAIT4_HALT):
4537 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4538 bnx2x_handle_rx_mode_eqe(bp);
4539 break;
4540 default:
4541 /* unknown event log error and continue */
4542 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4543 elem->message.opcode, bp->state);
4544 }
4545 next_spqe:
4546 spqe_cnt++;
4547 } /* for */
4548
4549 smp_mb__before_atomic_inc();
4550 atomic_add(spqe_cnt, &bp->eq_spq_left);
4551
4552 bp->eq_cons = sw_cons;
4553 bp->eq_prod = sw_prod;
4554 /* Make sure that above mem writes were issued towards the memory */
4555 smp_wmb();
4556
4557 /* update producer */
4558 bnx2x_update_eq_prod(bp, bp->eq_prod);
4559 }
4560
4561 static void bnx2x_sp_task(struct work_struct *work)
4562 {
4563 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4564 u16 status;
4565
4566 status = bnx2x_update_dsb_idx(bp);
4567 /* if (status == 0) */
4568 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4569
4570 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4571
4572 /* HW attentions */
4573 if (status & BNX2X_DEF_SB_ATT_IDX) {
4574 bnx2x_attn_int(bp);
4575 status &= ~BNX2X_DEF_SB_ATT_IDX;
4576 }
4577
4578 /* SP events: STAT_QUERY and others */
4579 if (status & BNX2X_DEF_SB_IDX) {
4580 #ifdef BCM_CNIC
4581 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4582
4583 if ((!NO_FCOE(bp)) &&
4584 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4585 /*
4586 * Prevent local bottom-halves from running as
4587 * we are going to change the local NAPI list.
4588 */
4589 local_bh_disable();
4590 napi_schedule(&bnx2x_fcoe(bp, napi));
4591 local_bh_enable();
4592 }
4593 #endif
4594 /* Handle EQ completions */
4595 bnx2x_eq_int(bp);
4596
4597 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4598 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4599
4600 status &= ~BNX2X_DEF_SB_IDX;
4601 }
4602
4603 if (unlikely(status))
4604 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4605 status);
4606
4607 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4608 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4609 }
4610
4611 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4612 {
4613 struct net_device *dev = dev_instance;
4614 struct bnx2x *bp = netdev_priv(dev);
4615
4616 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4617 IGU_INT_DISABLE, 0);
4618
4619 #ifdef BNX2X_STOP_ON_ERROR
4620 if (unlikely(bp->panic))
4621 return IRQ_HANDLED;
4622 #endif
4623
4624 #ifdef BCM_CNIC
4625 {
4626 struct cnic_ops *c_ops;
4627
4628 rcu_read_lock();
4629 c_ops = rcu_dereference(bp->cnic_ops);
4630 if (c_ops)
4631 c_ops->cnic_handler(bp->cnic_data, NULL);
4632 rcu_read_unlock();
4633 }
4634 #endif
4635 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4636
4637 return IRQ_HANDLED;
4638 }
4639
4640 /* end of slow path */
4641
4642
4643 void bnx2x_drv_pulse(struct bnx2x *bp)
4644 {
4645 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4646 bp->fw_drv_pulse_wr_seq);
4647 }
4648
4649
4650 static void bnx2x_timer(unsigned long data)
4651 {
4652 u8 cos;
4653 struct bnx2x *bp = (struct bnx2x *) data;
4654
4655 if (!netif_running(bp->dev))
4656 return;
4657
4658 if (poll) {
4659 struct bnx2x_fastpath *fp = &bp->fp[0];
4660
4661 for_each_cos_in_tx_queue(fp, cos)
4662 bnx2x_tx_int(bp, &fp->txdata[cos]);
4663 bnx2x_rx_int(fp, 1000);
4664 }
4665
4666 if (!BP_NOMCP(bp)) {
4667 int mb_idx = BP_FW_MB_IDX(bp);
4668 u32 drv_pulse;
4669 u32 mcp_pulse;
4670
4671 ++bp->fw_drv_pulse_wr_seq;
4672 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4673 /* TBD - add SYSTEM_TIME */
4674 drv_pulse = bp->fw_drv_pulse_wr_seq;
4675 bnx2x_drv_pulse(bp);
4676
4677 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4678 MCP_PULSE_SEQ_MASK);
4679 /* The delta between driver pulse and mcp response
4680 * should be 1 (before mcp response) or 0 (after mcp response)
4681 */
4682 if ((drv_pulse != mcp_pulse) &&
4683 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4684 /* someone lost a heartbeat... */
4685 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4686 drv_pulse, mcp_pulse);
4687 }
4688 }
4689
4690 if (bp->state == BNX2X_STATE_OPEN)
4691 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4692
4693 mod_timer(&bp->timer, jiffies + bp->current_interval);
4694 }
4695
4696 /* end of Statistics */
4697
4698 /* nic init */
4699
4700 /*
4701 * nic init service functions
4702 */
4703
4704 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4705 {
4706 u32 i;
4707 if (!(len%4) && !(addr%4))
4708 for (i = 0; i < len; i += 4)
4709 REG_WR(bp, addr + i, fill);
4710 else
4711 for (i = 0; i < len; i++)
4712 REG_WR8(bp, addr + i, fill);
4713
4714 }
4715
4716 /* helper: writes FP SP data to FW - data_size in dwords */
4717 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4718 int fw_sb_id,
4719 u32 *sb_data_p,
4720 u32 data_size)
4721 {
4722 int index;
4723 for (index = 0; index < data_size; index++)
4724 REG_WR(bp, BAR_CSTRORM_INTMEM +
4725 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4726 sizeof(u32)*index,
4727 *(sb_data_p + index));
4728 }
4729
4730 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4731 {
4732 u32 *sb_data_p;
4733 u32 data_size = 0;
4734 struct hc_status_block_data_e2 sb_data_e2;
4735 struct hc_status_block_data_e1x sb_data_e1x;
4736
4737 /* disable the function first */
4738 if (!CHIP_IS_E1x(bp)) {
4739 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4740 sb_data_e2.common.state = SB_DISABLED;
4741 sb_data_e2.common.p_func.vf_valid = false;
4742 sb_data_p = (u32 *)&sb_data_e2;
4743 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4744 } else {
4745 memset(&sb_data_e1x, 0,
4746 sizeof(struct hc_status_block_data_e1x));
4747 sb_data_e1x.common.state = SB_DISABLED;
4748 sb_data_e1x.common.p_func.vf_valid = false;
4749 sb_data_p = (u32 *)&sb_data_e1x;
4750 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4751 }
4752 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4753
4754 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4755 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4756 CSTORM_STATUS_BLOCK_SIZE);
4757 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4758 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4759 CSTORM_SYNC_BLOCK_SIZE);
4760 }
4761
4762 /* helper: writes SP SB data to FW */
4763 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4764 struct hc_sp_status_block_data *sp_sb_data)
4765 {
4766 int func = BP_FUNC(bp);
4767 int i;
4768 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4769 REG_WR(bp, BAR_CSTRORM_INTMEM +
4770 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4771 i*sizeof(u32),
4772 *((u32 *)sp_sb_data + i));
4773 }
4774
4775 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4776 {
4777 int func = BP_FUNC(bp);
4778 struct hc_sp_status_block_data sp_sb_data;
4779 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4780
4781 sp_sb_data.state = SB_DISABLED;
4782 sp_sb_data.p_func.vf_valid = false;
4783
4784 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4785
4786 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4787 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4788 CSTORM_SP_STATUS_BLOCK_SIZE);
4789 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4790 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4791 CSTORM_SP_SYNC_BLOCK_SIZE);
4792
4793 }
4794
4795
4796 static inline
4797 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4798 int igu_sb_id, int igu_seg_id)
4799 {
4800 hc_sm->igu_sb_id = igu_sb_id;
4801 hc_sm->igu_seg_id = igu_seg_id;
4802 hc_sm->timer_value = 0xFF;
4803 hc_sm->time_to_expire = 0xFFFFFFFF;
4804 }
4805
4806 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4807 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4808 {
4809 int igu_seg_id;
4810
4811 struct hc_status_block_data_e2 sb_data_e2;
4812 struct hc_status_block_data_e1x sb_data_e1x;
4813 struct hc_status_block_sm *hc_sm_p;
4814 int data_size;
4815 u32 *sb_data_p;
4816
4817 if (CHIP_INT_MODE_IS_BC(bp))
4818 igu_seg_id = HC_SEG_ACCESS_NORM;
4819 else
4820 igu_seg_id = IGU_SEG_ACCESS_NORM;
4821
4822 bnx2x_zero_fp_sb(bp, fw_sb_id);
4823
4824 if (!CHIP_IS_E1x(bp)) {
4825 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4826 sb_data_e2.common.state = SB_ENABLED;
4827 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4828 sb_data_e2.common.p_func.vf_id = vfid;
4829 sb_data_e2.common.p_func.vf_valid = vf_valid;
4830 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4831 sb_data_e2.common.same_igu_sb_1b = true;
4832 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4833 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4834 hc_sm_p = sb_data_e2.common.state_machine;
4835 sb_data_p = (u32 *)&sb_data_e2;
4836 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4837 } else {
4838 memset(&sb_data_e1x, 0,
4839 sizeof(struct hc_status_block_data_e1x));
4840 sb_data_e1x.common.state = SB_ENABLED;
4841 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4842 sb_data_e1x.common.p_func.vf_id = 0xff;
4843 sb_data_e1x.common.p_func.vf_valid = false;
4844 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4845 sb_data_e1x.common.same_igu_sb_1b = true;
4846 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4847 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4848 hc_sm_p = sb_data_e1x.common.state_machine;
4849 sb_data_p = (u32 *)&sb_data_e1x;
4850 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4851 }
4852
4853 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4854 igu_sb_id, igu_seg_id);
4855 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4856 igu_sb_id, igu_seg_id);
4857
4858 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4859
4860 /* write indecies to HW */
4861 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4862 }
4863
4864 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4865 u16 tx_usec, u16 rx_usec)
4866 {
4867 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4868 false, rx_usec);
4869 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4870 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4871 tx_usec);
4872 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4873 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4874 tx_usec);
4875 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4876 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4877 tx_usec);
4878 }
4879
4880 static void bnx2x_init_def_sb(struct bnx2x *bp)
4881 {
4882 struct host_sp_status_block *def_sb = bp->def_status_blk;
4883 dma_addr_t mapping = bp->def_status_blk_mapping;
4884 int igu_sp_sb_index;
4885 int igu_seg_id;
4886 int port = BP_PORT(bp);
4887 int func = BP_FUNC(bp);
4888 int reg_offset;
4889 u64 section;
4890 int index;
4891 struct hc_sp_status_block_data sp_sb_data;
4892 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4893
4894 if (CHIP_INT_MODE_IS_BC(bp)) {
4895 igu_sp_sb_index = DEF_SB_IGU_ID;
4896 igu_seg_id = HC_SEG_ACCESS_DEF;
4897 } else {
4898 igu_sp_sb_index = bp->igu_dsb_id;
4899 igu_seg_id = IGU_SEG_ACCESS_DEF;
4900 }
4901
4902 /* ATTN */
4903 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4904 atten_status_block);
4905 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4906
4907 bp->attn_state = 0;
4908
4909 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4910 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4911 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4912 int sindex;
4913 /* take care of sig[0]..sig[4] */
4914 for (sindex = 0; sindex < 4; sindex++)
4915 bp->attn_group[index].sig[sindex] =
4916 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4917
4918 if (!CHIP_IS_E1x(bp))
4919 /*
4920 * enable5 is separate from the rest of the registers,
4921 * and therefore the address skip is 4
4922 * and not 16 between the different groups
4923 */
4924 bp->attn_group[index].sig[4] = REG_RD(bp,
4925 reg_offset + 0x10 + 0x4*index);
4926 else
4927 bp->attn_group[index].sig[4] = 0;
4928 }
4929
4930 if (bp->common.int_block == INT_BLOCK_HC) {
4931 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4932 HC_REG_ATTN_MSG0_ADDR_L);
4933
4934 REG_WR(bp, reg_offset, U64_LO(section));
4935 REG_WR(bp, reg_offset + 4, U64_HI(section));
4936 } else if (!CHIP_IS_E1x(bp)) {
4937 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4938 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4939 }
4940
4941 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4942 sp_sb);
4943
4944 bnx2x_zero_sp_sb(bp);
4945
4946 sp_sb_data.state = SB_ENABLED;
4947 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4948 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4949 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4950 sp_sb_data.igu_seg_id = igu_seg_id;
4951 sp_sb_data.p_func.pf_id = func;
4952 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4953 sp_sb_data.p_func.vf_id = 0xff;
4954
4955 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4956
4957 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4958 }
4959
4960 void bnx2x_update_coalesce(struct bnx2x *bp)
4961 {
4962 int i;
4963
4964 for_each_eth_queue(bp, i)
4965 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4966 bp->tx_ticks, bp->rx_ticks);
4967 }
4968
4969 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4970 {
4971 spin_lock_init(&bp->spq_lock);
4972 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4973
4974 bp->spq_prod_idx = 0;
4975 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4976 bp->spq_prod_bd = bp->spq;
4977 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4978 }
4979
4980 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4981 {
4982 int i;
4983 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4984 union event_ring_elem *elem =
4985 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4986
4987 elem->next_page.addr.hi =
4988 cpu_to_le32(U64_HI(bp->eq_mapping +
4989 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4990 elem->next_page.addr.lo =
4991 cpu_to_le32(U64_LO(bp->eq_mapping +
4992 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4993 }
4994 bp->eq_cons = 0;
4995 bp->eq_prod = NUM_EQ_DESC;
4996 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4997 /* we want a warning message before it gets rought... */
4998 atomic_set(&bp->eq_spq_left,
4999 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5000 }
5001
5002
5003 /* called with netif_addr_lock_bh() */
5004 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5005 unsigned long rx_mode_flags,
5006 unsigned long rx_accept_flags,
5007 unsigned long tx_accept_flags,
5008 unsigned long ramrod_flags)
5009 {
5010 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5011 int rc;
5012
5013 memset(&ramrod_param, 0, sizeof(ramrod_param));
5014
5015 /* Prepare ramrod parameters */
5016 ramrod_param.cid = 0;
5017 ramrod_param.cl_id = cl_id;
5018 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5019 ramrod_param.func_id = BP_FUNC(bp);
5020
5021 ramrod_param.pstate = &bp->sp_state;
5022 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5023
5024 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5025 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5026
5027 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5028
5029 ramrod_param.ramrod_flags = ramrod_flags;
5030 ramrod_param.rx_mode_flags = rx_mode_flags;
5031
5032 ramrod_param.rx_accept_flags = rx_accept_flags;
5033 ramrod_param.tx_accept_flags = tx_accept_flags;
5034
5035 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5036 if (rc < 0) {
5037 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5038 return;
5039 }
5040 }
5041
5042 /* called with netif_addr_lock_bh() */
5043 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5044 {
5045 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5046 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5047
5048 #ifdef BCM_CNIC
5049 if (!NO_FCOE(bp))
5050
5051 /* Configure rx_mode of FCoE Queue */
5052 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5053 #endif
5054
5055 switch (bp->rx_mode) {
5056 case BNX2X_RX_MODE_NONE:
5057 /*
5058 * 'drop all' supersedes any accept flags that may have been
5059 * passed to the function.
5060 */
5061 break;
5062 case BNX2X_RX_MODE_NORMAL:
5063 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5064 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5065 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5066
5067 /* internal switching mode */
5068 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5069 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5070 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5071
5072 break;
5073 case BNX2X_RX_MODE_ALLMULTI:
5074 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5075 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5076 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5077
5078 /* internal switching mode */
5079 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5080 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5081 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5082
5083 break;
5084 case BNX2X_RX_MODE_PROMISC:
5085 /* According to deffinition of SI mode, iface in promisc mode
5086 * should receive matched and unmatched (in resolution of port)
5087 * unicast packets.
5088 */
5089 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5090 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5091 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5092 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5093
5094 /* internal switching mode */
5095 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5096 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5097
5098 if (IS_MF_SI(bp))
5099 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5100 else
5101 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5102
5103 break;
5104 default:
5105 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5106 return;
5107 }
5108
5109 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5110 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5111 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5112 }
5113
5114 __set_bit(RAMROD_RX, &ramrod_flags);
5115 __set_bit(RAMROD_TX, &ramrod_flags);
5116
5117 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5118 tx_accept_flags, ramrod_flags);
5119 }
5120
5121 static void bnx2x_init_internal_common(struct bnx2x *bp)
5122 {
5123 int i;
5124
5125 if (IS_MF_SI(bp))
5126 /*
5127 * In switch independent mode, the TSTORM needs to accept
5128 * packets that failed classification, since approximate match
5129 * mac addresses aren't written to NIG LLH
5130 */
5131 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5132 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5133 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5134 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5135 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5136
5137 /* Zero this manually as its initialization is
5138 currently missing in the initTool */
5139 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5140 REG_WR(bp, BAR_USTRORM_INTMEM +
5141 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5142 if (!CHIP_IS_E1x(bp)) {
5143 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5144 CHIP_INT_MODE_IS_BC(bp) ?
5145 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5146 }
5147 }
5148
5149 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5150 {
5151 switch (load_code) {
5152 case FW_MSG_CODE_DRV_LOAD_COMMON:
5153 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5154 bnx2x_init_internal_common(bp);
5155 /* no break */
5156
5157 case FW_MSG_CODE_DRV_LOAD_PORT:
5158 /* nothing to do */
5159 /* no break */
5160
5161 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5162 /* internal memory per function is
5163 initialized inside bnx2x_pf_init */
5164 break;
5165
5166 default:
5167 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5168 break;
5169 }
5170 }
5171
5172 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5173 {
5174 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5175 }
5176
5177 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5178 {
5179 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5180 }
5181
5182 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5183 {
5184 if (CHIP_IS_E1x(fp->bp))
5185 return BP_L_ID(fp->bp) + fp->index;
5186 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5187 return bnx2x_fp_igu_sb_id(fp);
5188 }
5189
5190 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5191 {
5192 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5193 u8 cos;
5194 unsigned long q_type = 0;
5195 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5196
5197 fp->cid = fp_idx;
5198 fp->cl_id = bnx2x_fp_cl_id(fp);
5199 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5200 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5201 /* qZone id equals to FW (per path) client id */
5202 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5203
5204 /* init shortcut */
5205 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5206 /* Setup SB indicies */
5207 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5208
5209 /* Configure Queue State object */
5210 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5211 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5212
5213 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5214
5215 /* init tx data */
5216 for_each_cos_in_tx_queue(fp, cos) {
5217 bnx2x_init_txdata(bp, &fp->txdata[cos],
5218 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5219 FP_COS_TO_TXQ(fp, cos),
5220 BNX2X_TX_SB_INDEX_BASE + cos);
5221 cids[cos] = fp->txdata[cos].cid;
5222 }
5223
5224 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5225 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5226 bnx2x_sp_mapping(bp, q_rdata), q_type);
5227
5228 /**
5229 * Configure classification DBs: Always enable Tx switching
5230 */
5231 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5232
5233 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5234 "cl_id %d fw_sb %d igu_sb %d\n",
5235 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5236 fp->igu_sb_id);
5237 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5238 fp->fw_sb_id, fp->igu_sb_id);
5239
5240 bnx2x_update_fpsb_idx(fp);
5241 }
5242
5243 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5244 {
5245 int i;
5246
5247 for_each_eth_queue(bp, i)
5248 bnx2x_init_eth_fp(bp, i);
5249 #ifdef BCM_CNIC
5250 if (!NO_FCOE(bp))
5251 bnx2x_init_fcoe_fp(bp);
5252
5253 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5254 BNX2X_VF_ID_INVALID, false,
5255 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5256
5257 #endif
5258
5259 /* Initialize MOD_ABS interrupts */
5260 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5261 bp->common.shmem_base, bp->common.shmem2_base,
5262 BP_PORT(bp));
5263 /* ensure status block indices were read */
5264 rmb();
5265
5266 bnx2x_init_def_sb(bp);
5267 bnx2x_update_dsb_idx(bp);
5268 bnx2x_init_rx_rings(bp);
5269 bnx2x_init_tx_rings(bp);
5270 bnx2x_init_sp_ring(bp);
5271 bnx2x_init_eq_ring(bp);
5272 bnx2x_init_internal(bp, load_code);
5273 bnx2x_pf_init(bp);
5274 bnx2x_stats_init(bp);
5275
5276 /* flush all before enabling interrupts */
5277 mb();
5278 mmiowb();
5279
5280 bnx2x_int_enable(bp);
5281
5282 /* Check for SPIO5 */
5283 bnx2x_attn_int_deasserted0(bp,
5284 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5285 AEU_INPUTS_ATTN_BITS_SPIO5);
5286 }
5287
5288 /* end of nic init */
5289
5290 /*
5291 * gzip service functions
5292 */
5293
5294 static int bnx2x_gunzip_init(struct bnx2x *bp)
5295 {
5296 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5297 &bp->gunzip_mapping, GFP_KERNEL);
5298 if (bp->gunzip_buf == NULL)
5299 goto gunzip_nomem1;
5300
5301 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5302 if (bp->strm == NULL)
5303 goto gunzip_nomem2;
5304
5305 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5306 if (bp->strm->workspace == NULL)
5307 goto gunzip_nomem3;
5308
5309 return 0;
5310
5311 gunzip_nomem3:
5312 kfree(bp->strm);
5313 bp->strm = NULL;
5314
5315 gunzip_nomem2:
5316 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5317 bp->gunzip_mapping);
5318 bp->gunzip_buf = NULL;
5319
5320 gunzip_nomem1:
5321 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5322 " un-compression\n");
5323 return -ENOMEM;
5324 }
5325
5326 static void bnx2x_gunzip_end(struct bnx2x *bp)
5327 {
5328 if (bp->strm) {
5329 vfree(bp->strm->workspace);
5330 kfree(bp->strm);
5331 bp->strm = NULL;
5332 }
5333
5334 if (bp->gunzip_buf) {
5335 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5336 bp->gunzip_mapping);
5337 bp->gunzip_buf = NULL;
5338 }
5339 }
5340
5341 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5342 {
5343 int n, rc;
5344
5345 /* check gzip header */
5346 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5347 BNX2X_ERR("Bad gzip header\n");
5348 return -EINVAL;
5349 }
5350
5351 n = 10;
5352
5353 #define FNAME 0x8
5354
5355 if (zbuf[3] & FNAME)
5356 while ((zbuf[n++] != 0) && (n < len));
5357
5358 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5359 bp->strm->avail_in = len - n;
5360 bp->strm->next_out = bp->gunzip_buf;
5361 bp->strm->avail_out = FW_BUF_SIZE;
5362
5363 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5364 if (rc != Z_OK)
5365 return rc;
5366
5367 rc = zlib_inflate(bp->strm, Z_FINISH);
5368 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5369 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5370 bp->strm->msg);
5371
5372 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5373 if (bp->gunzip_outlen & 0x3)
5374 netdev_err(bp->dev, "Firmware decompression error:"
5375 " gunzip_outlen (%d) not aligned\n",
5376 bp->gunzip_outlen);
5377 bp->gunzip_outlen >>= 2;
5378
5379 zlib_inflateEnd(bp->strm);
5380
5381 if (rc == Z_STREAM_END)
5382 return 0;
5383
5384 return rc;
5385 }
5386
5387 /* nic load/unload */
5388
5389 /*
5390 * General service functions
5391 */
5392
5393 /* send a NIG loopback debug packet */
5394 static void bnx2x_lb_pckt(struct bnx2x *bp)
5395 {
5396 u32 wb_write[3];
5397
5398 /* Ethernet source and destination addresses */
5399 wb_write[0] = 0x55555555;
5400 wb_write[1] = 0x55555555;
5401 wb_write[2] = 0x20; /* SOP */
5402 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5403
5404 /* NON-IP protocol */
5405 wb_write[0] = 0x09000000;
5406 wb_write[1] = 0x55555555;
5407 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5408 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5409 }
5410
5411 /* some of the internal memories
5412 * are not directly readable from the driver
5413 * to test them we send debug packets
5414 */
5415 static int bnx2x_int_mem_test(struct bnx2x *bp)
5416 {
5417 int factor;
5418 int count, i;
5419 u32 val = 0;
5420
5421 if (CHIP_REV_IS_FPGA(bp))
5422 factor = 120;
5423 else if (CHIP_REV_IS_EMUL(bp))
5424 factor = 200;
5425 else
5426 factor = 1;
5427
5428 /* Disable inputs of parser neighbor blocks */
5429 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5430 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5431 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5432 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5433
5434 /* Write 0 to parser credits for CFC search request */
5435 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5436
5437 /* send Ethernet packet */
5438 bnx2x_lb_pckt(bp);
5439
5440 /* TODO do i reset NIG statistic? */
5441 /* Wait until NIG register shows 1 packet of size 0x10 */
5442 count = 1000 * factor;
5443 while (count) {
5444
5445 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5446 val = *bnx2x_sp(bp, wb_data[0]);
5447 if (val == 0x10)
5448 break;
5449
5450 msleep(10);
5451 count--;
5452 }
5453 if (val != 0x10) {
5454 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5455 return -1;
5456 }
5457
5458 /* Wait until PRS register shows 1 packet */
5459 count = 1000 * factor;
5460 while (count) {
5461 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5462 if (val == 1)
5463 break;
5464
5465 msleep(10);
5466 count--;
5467 }
5468 if (val != 0x1) {
5469 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5470 return -2;
5471 }
5472
5473 /* Reset and init BRB, PRS */
5474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5475 msleep(50);
5476 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5477 msleep(50);
5478 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5479 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5480
5481 DP(NETIF_MSG_HW, "part2\n");
5482
5483 /* Disable inputs of parser neighbor blocks */
5484 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5485 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5486 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5487 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5488
5489 /* Write 0 to parser credits for CFC search request */
5490 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5491
5492 /* send 10 Ethernet packets */
5493 for (i = 0; i < 10; i++)
5494 bnx2x_lb_pckt(bp);
5495
5496 /* Wait until NIG register shows 10 + 1
5497 packets of size 11*0x10 = 0xb0 */
5498 count = 1000 * factor;
5499 while (count) {
5500
5501 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5502 val = *bnx2x_sp(bp, wb_data[0]);
5503 if (val == 0xb0)
5504 break;
5505
5506 msleep(10);
5507 count--;
5508 }
5509 if (val != 0xb0) {
5510 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5511 return -3;
5512 }
5513
5514 /* Wait until PRS register shows 2 packets */
5515 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5516 if (val != 2)
5517 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5518
5519 /* Write 1 to parser credits for CFC search request */
5520 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5521
5522 /* Wait until PRS register shows 3 packets */
5523 msleep(10 * factor);
5524 /* Wait until NIG register shows 1 packet of size 0x10 */
5525 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5526 if (val != 3)
5527 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5528
5529 /* clear NIG EOP FIFO */
5530 for (i = 0; i < 11; i++)
5531 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5532 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5533 if (val != 1) {
5534 BNX2X_ERR("clear of NIG failed\n");
5535 return -4;
5536 }
5537
5538 /* Reset and init BRB, PRS, NIG */
5539 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5540 msleep(50);
5541 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5542 msleep(50);
5543 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5544 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5545 #ifndef BCM_CNIC
5546 /* set NIC mode */
5547 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5548 #endif
5549
5550 /* Enable inputs of parser neighbor blocks */
5551 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5552 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5553 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5554 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5555
5556 DP(NETIF_MSG_HW, "done\n");
5557
5558 return 0; /* OK */
5559 }
5560
5561 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5562 {
5563 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5564 if (!CHIP_IS_E1x(bp))
5565 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5566 else
5567 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5568 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5569 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5570 /*
5571 * mask read length error interrupts in brb for parser
5572 * (parsing unit and 'checksum and crc' unit)
5573 * these errors are legal (PU reads fixed length and CAC can cause
5574 * read length error on truncated packets)
5575 */
5576 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5577 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5578 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5579 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5580 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5581 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5582 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5583 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5584 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5585 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5586 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5587 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5588 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5589 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5590 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5591 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5592 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5593 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5594 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5595
5596 if (CHIP_REV_IS_FPGA(bp))
5597 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5598 else if (!CHIP_IS_E1x(bp))
5599 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5600 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5601 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5602 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5603 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5604 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5605 else
5606 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5607 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5608 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5609 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5610 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5611
5612 if (!CHIP_IS_E1x(bp))
5613 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5614 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5615
5616 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5617 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5618 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5619 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5620 }
5621
5622 static void bnx2x_reset_common(struct bnx2x *bp)
5623 {
5624 u32 val = 0x1400;
5625
5626 /* reset_common */
5627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5628 0xd3ffff7f);
5629
5630 if (CHIP_IS_E3(bp)) {
5631 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5632 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5633 }
5634
5635 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5636 }
5637
5638 static void bnx2x_setup_dmae(struct bnx2x *bp)
5639 {
5640 bp->dmae_ready = 0;
5641 spin_lock_init(&bp->dmae_lock);
5642 }
5643
5644 static void bnx2x_init_pxp(struct bnx2x *bp)
5645 {
5646 u16 devctl;
5647 int r_order, w_order;
5648
5649 pci_read_config_word(bp->pdev,
5650 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5651 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5652 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5653 if (bp->mrrs == -1)
5654 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5655 else {
5656 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5657 r_order = bp->mrrs;
5658 }
5659
5660 bnx2x_init_pxp_arb(bp, r_order, w_order);
5661 }
5662
5663 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5664 {
5665 int is_required;
5666 u32 val;
5667 int port;
5668
5669 if (BP_NOMCP(bp))
5670 return;
5671
5672 is_required = 0;
5673 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5674 SHARED_HW_CFG_FAN_FAILURE_MASK;
5675
5676 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5677 is_required = 1;
5678
5679 /*
5680 * The fan failure mechanism is usually related to the PHY type since
5681 * the power consumption of the board is affected by the PHY. Currently,
5682 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5683 */
5684 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5685 for (port = PORT_0; port < PORT_MAX; port++) {
5686 is_required |=
5687 bnx2x_fan_failure_det_req(
5688 bp,
5689 bp->common.shmem_base,
5690 bp->common.shmem2_base,
5691 port);
5692 }
5693
5694 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5695
5696 if (is_required == 0)
5697 return;
5698
5699 /* Fan failure is indicated by SPIO 5 */
5700 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5701 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5702
5703 /* set to active low mode */
5704 val = REG_RD(bp, MISC_REG_SPIO_INT);
5705 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5706 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5707 REG_WR(bp, MISC_REG_SPIO_INT, val);
5708
5709 /* enable interrupt to signal the IGU */
5710 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5711 val |= (1 << MISC_REGISTERS_SPIO_5);
5712 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5713 }
5714
5715 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5716 {
5717 u32 offset = 0;
5718
5719 if (CHIP_IS_E1(bp))
5720 return;
5721 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5722 return;
5723
5724 switch (BP_ABS_FUNC(bp)) {
5725 case 0:
5726 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5727 break;
5728 case 1:
5729 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5730 break;
5731 case 2:
5732 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5733 break;
5734 case 3:
5735 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5736 break;
5737 case 4:
5738 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5739 break;
5740 case 5:
5741 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5742 break;
5743 case 6:
5744 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5745 break;
5746 case 7:
5747 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5748 break;
5749 default:
5750 return;
5751 }
5752
5753 REG_WR(bp, offset, pretend_func_num);
5754 REG_RD(bp, offset);
5755 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5756 }
5757
5758 void bnx2x_pf_disable(struct bnx2x *bp)
5759 {
5760 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5761 val &= ~IGU_PF_CONF_FUNC_EN;
5762
5763 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5764 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5765 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5766 }
5767
5768 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5769 {
5770 u32 shmem_base[2], shmem2_base[2];
5771 shmem_base[0] = bp->common.shmem_base;
5772 shmem2_base[0] = bp->common.shmem2_base;
5773 if (!CHIP_IS_E1x(bp)) {
5774 shmem_base[1] =
5775 SHMEM2_RD(bp, other_shmem_base_addr);
5776 shmem2_base[1] =
5777 SHMEM2_RD(bp, other_shmem2_base_addr);
5778 }
5779 bnx2x_acquire_phy_lock(bp);
5780 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5781 bp->common.chip_id);
5782 bnx2x_release_phy_lock(bp);
5783 }
5784
5785 /**
5786 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5787 *
5788 * @bp: driver handle
5789 */
5790 static int bnx2x_init_hw_common(struct bnx2x *bp)
5791 {
5792 u32 val;
5793
5794 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5795
5796 bnx2x_reset_common(bp);
5797 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5798
5799 val = 0xfffc;
5800 if (CHIP_IS_E3(bp)) {
5801 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5802 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5803 }
5804 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5805
5806 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5807
5808 if (!CHIP_IS_E1x(bp)) {
5809 u8 abs_func_id;
5810
5811 /**
5812 * 4-port mode or 2-port mode we need to turn of master-enable
5813 * for everyone, after that, turn it back on for self.
5814 * so, we disregard multi-function or not, and always disable
5815 * for all functions on the given path, this means 0,2,4,6 for
5816 * path 0 and 1,3,5,7 for path 1
5817 */
5818 for (abs_func_id = BP_PATH(bp);
5819 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5820 if (abs_func_id == BP_ABS_FUNC(bp)) {
5821 REG_WR(bp,
5822 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5823 1);
5824 continue;
5825 }
5826
5827 bnx2x_pretend_func(bp, abs_func_id);
5828 /* clear pf enable */
5829 bnx2x_pf_disable(bp);
5830 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5831 }
5832 }
5833
5834 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5835 if (CHIP_IS_E1(bp)) {
5836 /* enable HW interrupt from PXP on USDM overflow
5837 bit 16 on INT_MASK_0 */
5838 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5839 }
5840
5841 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5842 bnx2x_init_pxp(bp);
5843
5844 #ifdef __BIG_ENDIAN
5845 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5846 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5847 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5848 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5849 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5850 /* make sure this value is 0 */
5851 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5852
5853 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5854 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5855 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5856 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5857 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5858 #endif
5859
5860 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5861
5862 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5863 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5864
5865 /* let the HW do it's magic ... */
5866 msleep(100);
5867 /* finish PXP init */
5868 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5869 if (val != 1) {
5870 BNX2X_ERR("PXP2 CFG failed\n");
5871 return -EBUSY;
5872 }
5873 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5874 if (val != 1) {
5875 BNX2X_ERR("PXP2 RD_INIT failed\n");
5876 return -EBUSY;
5877 }
5878
5879 /* Timers bug workaround E2 only. We need to set the entire ILT to
5880 * have entries with value "0" and valid bit on.
5881 * This needs to be done by the first PF that is loaded in a path
5882 * (i.e. common phase)
5883 */
5884 if (!CHIP_IS_E1x(bp)) {
5885 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5886 * (i.e. vnic3) to start even if it is marked as "scan-off".
5887 * This occurs when a different function (func2,3) is being marked
5888 * as "scan-off". Real-life scenario for example: if a driver is being
5889 * load-unloaded while func6,7 are down. This will cause the timer to access
5890 * the ilt, translate to a logical address and send a request to read/write.
5891 * Since the ilt for the function that is down is not valid, this will cause
5892 * a translation error which is unrecoverable.
5893 * The Workaround is intended to make sure that when this happens nothing fatal
5894 * will occur. The workaround:
5895 * 1. First PF driver which loads on a path will:
5896 * a. After taking the chip out of reset, by using pretend,
5897 * it will write "0" to the following registers of
5898 * the other vnics.
5899 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5900 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5901 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5902 * And for itself it will write '1' to
5903 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5904 * dmae-operations (writing to pram for example.)
5905 * note: can be done for only function 6,7 but cleaner this
5906 * way.
5907 * b. Write zero+valid to the entire ILT.
5908 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5909 * VNIC3 (of that port). The range allocated will be the
5910 * entire ILT. This is needed to prevent ILT range error.
5911 * 2. Any PF driver load flow:
5912 * a. ILT update with the physical addresses of the allocated
5913 * logical pages.
5914 * b. Wait 20msec. - note that this timeout is needed to make
5915 * sure there are no requests in one of the PXP internal
5916 * queues with "old" ILT addresses.
5917 * c. PF enable in the PGLC.
5918 * d. Clear the was_error of the PF in the PGLC. (could have
5919 * occured while driver was down)
5920 * e. PF enable in the CFC (WEAK + STRONG)
5921 * f. Timers scan enable
5922 * 3. PF driver unload flow:
5923 * a. Clear the Timers scan_en.
5924 * b. Polling for scan_on=0 for that PF.
5925 * c. Clear the PF enable bit in the PXP.
5926 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5927 * e. Write zero+valid to all ILT entries (The valid bit must
5928 * stay set)
5929 * f. If this is VNIC 3 of a port then also init
5930 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5931 * to the last enrty in the ILT.
5932 *
5933 * Notes:
5934 * Currently the PF error in the PGLC is non recoverable.
5935 * In the future the there will be a recovery routine for this error.
5936 * Currently attention is masked.
5937 * Having an MCP lock on the load/unload process does not guarantee that
5938 * there is no Timer disable during Func6/7 enable. This is because the
5939 * Timers scan is currently being cleared by the MCP on FLR.
5940 * Step 2.d can be done only for PF6/7 and the driver can also check if
5941 * there is error before clearing it. But the flow above is simpler and
5942 * more general.
5943 * All ILT entries are written by zero+valid and not just PF6/7
5944 * ILT entries since in the future the ILT entries allocation for
5945 * PF-s might be dynamic.
5946 */
5947 struct ilt_client_info ilt_cli;
5948 struct bnx2x_ilt ilt;
5949 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5950 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5951
5952 /* initialize dummy TM client */
5953 ilt_cli.start = 0;
5954 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5955 ilt_cli.client_num = ILT_CLIENT_TM;
5956
5957 /* Step 1: set zeroes to all ilt page entries with valid bit on
5958 * Step 2: set the timers first/last ilt entry to point
5959 * to the entire range to prevent ILT range error for 3rd/4th
5960 * vnic (this code assumes existance of the vnic)
5961 *
5962 * both steps performed by call to bnx2x_ilt_client_init_op()
5963 * with dummy TM client
5964 *
5965 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5966 * and his brother are split registers
5967 */
5968 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5969 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5970 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5971
5972 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5973 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5974 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5975 }
5976
5977
5978 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5979 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5980
5981 if (!CHIP_IS_E1x(bp)) {
5982 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5983 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5984 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5985
5986 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
5987
5988 /* let the HW do it's magic ... */
5989 do {
5990 msleep(200);
5991 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5992 } while (factor-- && (val != 1));
5993
5994 if (val != 1) {
5995 BNX2X_ERR("ATC_INIT failed\n");
5996 return -EBUSY;
5997 }
5998 }
5999
6000 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6001
6002 /* clean the DMAE memory */
6003 bp->dmae_ready = 1;
6004 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6005
6006 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6007
6008 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6009
6010 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6011
6012 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6013
6014 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6015 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6016 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6017 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6018
6019 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6020
6021
6022 /* QM queues pointers table */
6023 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6024
6025 /* soft reset pulse */
6026 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6027 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6028
6029 #ifdef BCM_CNIC
6030 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6031 #endif
6032
6033 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6034 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6035 if (!CHIP_REV_IS_SLOW(bp))
6036 /* enable hw interrupt from doorbell Q */
6037 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6038
6039 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6040
6041 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6042 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6043
6044 if (!CHIP_IS_E1(bp))
6045 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6046
6047 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6048 /* Bit-map indicating which L2 hdrs may appear
6049 * after the basic Ethernet header
6050 */
6051 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6052 bp->path_has_ovlan ? 7 : 6);
6053
6054 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6055 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6056 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6057 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6058
6059 if (!CHIP_IS_E1x(bp)) {
6060 /* reset VFC memories */
6061 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6062 VFC_MEMORIES_RST_REG_CAM_RST |
6063 VFC_MEMORIES_RST_REG_RAM_RST);
6064 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6065 VFC_MEMORIES_RST_REG_CAM_RST |
6066 VFC_MEMORIES_RST_REG_RAM_RST);
6067
6068 msleep(20);
6069 }
6070
6071 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6072 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6073 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6074 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6075
6076 /* sync semi rtc */
6077 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6078 0x80000000);
6079 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6080 0x80000000);
6081
6082 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6083 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6084 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6085
6086 if (!CHIP_IS_E1x(bp))
6087 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6088 bp->path_has_ovlan ? 7 : 6);
6089
6090 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6091
6092 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6093
6094 #ifdef BCM_CNIC
6095 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6096 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6097 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6098 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6099 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6100 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6101 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6102 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6103 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6104 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6105 #endif
6106 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6107
6108 if (sizeof(union cdu_context) != 1024)
6109 /* we currently assume that a context is 1024 bytes */
6110 dev_alert(&bp->pdev->dev, "please adjust the size "
6111 "of cdu_context(%ld)\n",
6112 (long)sizeof(union cdu_context));
6113
6114 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6115 val = (4 << 24) + (0 << 12) + 1024;
6116 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6117
6118 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6119 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6120 /* enable context validation interrupt from CFC */
6121 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6122
6123 /* set the thresholds to prevent CFC/CDU race */
6124 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6125
6126 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6127
6128 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6129 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6130
6131 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6132 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6133
6134 /* Reset PCIE errors for debug */
6135 REG_WR(bp, 0x2814, 0xffffffff);
6136 REG_WR(bp, 0x3820, 0xffffffff);
6137
6138 if (!CHIP_IS_E1x(bp)) {
6139 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6140 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6141 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6142 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6143 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6144 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6145 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6146 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6147 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6148 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6149 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6150 }
6151
6152 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6153 if (!CHIP_IS_E1(bp)) {
6154 /* in E3 this done in per-port section */
6155 if (!CHIP_IS_E3(bp))
6156 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6157 }
6158 if (CHIP_IS_E1H(bp))
6159 /* not applicable for E2 (and above ...) */
6160 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6161
6162 if (CHIP_REV_IS_SLOW(bp))
6163 msleep(200);
6164
6165 /* finish CFC init */
6166 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6167 if (val != 1) {
6168 BNX2X_ERR("CFC LL_INIT failed\n");
6169 return -EBUSY;
6170 }
6171 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6172 if (val != 1) {
6173 BNX2X_ERR("CFC AC_INIT failed\n");
6174 return -EBUSY;
6175 }
6176 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6177 if (val != 1) {
6178 BNX2X_ERR("CFC CAM_INIT failed\n");
6179 return -EBUSY;
6180 }
6181 REG_WR(bp, CFC_REG_DEBUG0, 0);
6182
6183 if (CHIP_IS_E1(bp)) {
6184 /* read NIG statistic
6185 to see if this is our first up since powerup */
6186 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6187 val = *bnx2x_sp(bp, wb_data[0]);
6188
6189 /* do internal memory self test */
6190 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6191 BNX2X_ERR("internal mem self test failed\n");
6192 return -EBUSY;
6193 }
6194 }
6195
6196 bnx2x_setup_fan_failure_detection(bp);
6197
6198 /* clear PXP2 attentions */
6199 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6200
6201 bnx2x_enable_blocks_attention(bp);
6202 bnx2x_enable_blocks_parity(bp);
6203
6204 if (!BP_NOMCP(bp)) {
6205 if (CHIP_IS_E1x(bp))
6206 bnx2x__common_init_phy(bp);
6207 } else
6208 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6209
6210 return 0;
6211 }
6212
6213 /**
6214 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6215 *
6216 * @bp: driver handle
6217 */
6218 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6219 {
6220 int rc = bnx2x_init_hw_common(bp);
6221
6222 if (rc)
6223 return rc;
6224
6225 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6226 if (!BP_NOMCP(bp))
6227 bnx2x__common_init_phy(bp);
6228
6229 return 0;
6230 }
6231
6232 static int bnx2x_init_hw_port(struct bnx2x *bp)
6233 {
6234 int port = BP_PORT(bp);
6235 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6236 u32 low, high;
6237 u32 val;
6238
6239 bnx2x__link_reset(bp);
6240
6241 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6242
6243 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6244
6245 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6246 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6247 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6248
6249 /* Timers bug workaround: disables the pf_master bit in pglue at
6250 * common phase, we need to enable it here before any dmae access are
6251 * attempted. Therefore we manually added the enable-master to the
6252 * port phase (it also happens in the function phase)
6253 */
6254 if (!CHIP_IS_E1x(bp))
6255 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6256
6257 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6258 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6259 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6260 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6261
6262 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6263 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6264 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6265 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6266
6267 /* QM cid (connection) count */
6268 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6269
6270 #ifdef BCM_CNIC
6271 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6272 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6273 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6274 #endif
6275
6276 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6277
6278 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6279 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6280
6281 if (IS_MF(bp))
6282 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6283 else if (bp->dev->mtu > 4096) {
6284 if (bp->flags & ONE_PORT_FLAG)
6285 low = 160;
6286 else {
6287 val = bp->dev->mtu;
6288 /* (24*1024 + val*4)/256 */
6289 low = 96 + (val/64) +
6290 ((val % 64) ? 1 : 0);
6291 }
6292 } else
6293 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6294 high = low + 56; /* 14*1024/256 */
6295 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6296 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6297 }
6298
6299 if (CHIP_MODE_IS_4_PORT(bp))
6300 REG_WR(bp, (BP_PORT(bp) ?
6301 BRB1_REG_MAC_GUARANTIED_1 :
6302 BRB1_REG_MAC_GUARANTIED_0), 40);
6303
6304
6305 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6306 if (CHIP_IS_E3B0(bp))
6307 /* Ovlan exists only if we are in multi-function +
6308 * switch-dependent mode, in switch-independent there
6309 * is no ovlan headers
6310 */
6311 REG_WR(bp, BP_PORT(bp) ?
6312 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6313 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6314 (bp->path_has_ovlan ? 7 : 6));
6315
6316 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6317 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6318 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6319 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6320
6321 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6322 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6323 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6324 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6325
6326 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6327 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6328
6329 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6330
6331 if (CHIP_IS_E1x(bp)) {
6332 /* configure PBF to work without PAUSE mtu 9000 */
6333 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6334
6335 /* update threshold */
6336 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6337 /* update init credit */
6338 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6339
6340 /* probe changes */
6341 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6342 udelay(50);
6343 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6344 }
6345
6346 #ifdef BCM_CNIC
6347 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6348 #endif
6349 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6350 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6351
6352 if (CHIP_IS_E1(bp)) {
6353 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6354 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6355 }
6356 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6357
6358 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6359
6360 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6361 /* init aeu_mask_attn_func_0/1:
6362 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6363 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6364 * bits 4-7 are used for "per vn group attention" */
6365 val = IS_MF(bp) ? 0xF7 : 0x7;
6366 /* Enable DCBX attention for all but E1 */
6367 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6368 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6369
6370 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6371
6372 if (!CHIP_IS_E1x(bp)) {
6373 /* Bit-map indicating which L2 hdrs may appear after the
6374 * basic Ethernet header
6375 */
6376 REG_WR(bp, BP_PORT(bp) ?
6377 NIG_REG_P1_HDRS_AFTER_BASIC :
6378 NIG_REG_P0_HDRS_AFTER_BASIC,
6379 IS_MF_SD(bp) ? 7 : 6);
6380
6381 if (CHIP_IS_E3(bp))
6382 REG_WR(bp, BP_PORT(bp) ?
6383 NIG_REG_LLH1_MF_MODE :
6384 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6385 }
6386 if (!CHIP_IS_E3(bp))
6387 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6388
6389 if (!CHIP_IS_E1(bp)) {
6390 /* 0x2 disable mf_ov, 0x1 enable */
6391 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6392 (IS_MF_SD(bp) ? 0x1 : 0x2));
6393
6394 if (!CHIP_IS_E1x(bp)) {
6395 val = 0;
6396 switch (bp->mf_mode) {
6397 case MULTI_FUNCTION_SD:
6398 val = 1;
6399 break;
6400 case MULTI_FUNCTION_SI:
6401 val = 2;
6402 break;
6403 }
6404
6405 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6406 NIG_REG_LLH0_CLS_TYPE), val);
6407 }
6408 {
6409 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6410 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6411 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6412 }
6413 }
6414
6415
6416 /* If SPIO5 is set to generate interrupts, enable it for this port */
6417 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6418 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6419 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6420 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6421 val = REG_RD(bp, reg_addr);
6422 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6423 REG_WR(bp, reg_addr, val);
6424 }
6425
6426 return 0;
6427 }
6428
6429 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6430 {
6431 int reg;
6432
6433 if (CHIP_IS_E1(bp))
6434 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6435 else
6436 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6437
6438 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6439 }
6440
6441 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6442 {
6443 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6444 }
6445
6446 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6447 {
6448 u32 i, base = FUNC_ILT_BASE(func);
6449 for (i = base; i < base + ILT_PER_FUNC; i++)
6450 bnx2x_ilt_wr(bp, i, 0);
6451 }
6452
6453 static int bnx2x_init_hw_func(struct bnx2x *bp)
6454 {
6455 int port = BP_PORT(bp);
6456 int func = BP_FUNC(bp);
6457 int init_phase = PHASE_PF0 + func;
6458 struct bnx2x_ilt *ilt = BP_ILT(bp);
6459 u16 cdu_ilt_start;
6460 u32 addr, val;
6461 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6462 int i, main_mem_width;
6463
6464 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6465
6466 /* FLR cleanup - hmmm */
6467 if (!CHIP_IS_E1x(bp))
6468 bnx2x_pf_flr_clnup(bp);
6469
6470 /* set MSI reconfigure capability */
6471 if (bp->common.int_block == INT_BLOCK_HC) {
6472 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6473 val = REG_RD(bp, addr);
6474 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6475 REG_WR(bp, addr, val);
6476 }
6477
6478 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6479 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6480
6481 ilt = BP_ILT(bp);
6482 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6483
6484 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6485 ilt->lines[cdu_ilt_start + i].page =
6486 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6487 ilt->lines[cdu_ilt_start + i].page_mapping =
6488 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6489 /* cdu ilt pages are allocated manually so there's no need to
6490 set the size */
6491 }
6492 bnx2x_ilt_init_op(bp, INITOP_SET);
6493
6494 #ifdef BCM_CNIC
6495 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6496
6497 /* T1 hash bits value determines the T1 number of entries */
6498 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6499 #endif
6500
6501 #ifndef BCM_CNIC
6502 /* set NIC mode */
6503 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6504 #endif /* BCM_CNIC */
6505
6506 if (!CHIP_IS_E1x(bp)) {
6507 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6508
6509 /* Turn on a single ISR mode in IGU if driver is going to use
6510 * INT#x or MSI
6511 */
6512 if (!(bp->flags & USING_MSIX_FLAG))
6513 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6514 /*
6515 * Timers workaround bug: function init part.
6516 * Need to wait 20msec after initializing ILT,
6517 * needed to make sure there are no requests in
6518 * one of the PXP internal queues with "old" ILT addresses
6519 */
6520 msleep(20);
6521 /*
6522 * Master enable - Due to WB DMAE writes performed before this
6523 * register is re-initialized as part of the regular function
6524 * init
6525 */
6526 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6527 /* Enable the function in IGU */
6528 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6529 }
6530
6531 bp->dmae_ready = 1;
6532
6533 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6534
6535 if (!CHIP_IS_E1x(bp))
6536 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6537
6538 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6539 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6540 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6541 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6542 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6543 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6544 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6545 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6546 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6547 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6548 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6549 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6550 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6551
6552 if (!CHIP_IS_E1x(bp))
6553 REG_WR(bp, QM_REG_PF_EN, 1);
6554
6555 if (!CHIP_IS_E1x(bp)) {
6556 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6557 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6558 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6559 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6560 }
6561 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6562
6563 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6564 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6565 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6566 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6567 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6568 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6569 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6570 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6571 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6572 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6573 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6574 if (!CHIP_IS_E1x(bp))
6575 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6576
6577 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6578
6579 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6580
6581 if (!CHIP_IS_E1x(bp))
6582 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6583
6584 if (IS_MF(bp)) {
6585 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6586 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6587 }
6588
6589 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6590
6591 /* HC init per function */
6592 if (bp->common.int_block == INT_BLOCK_HC) {
6593 if (CHIP_IS_E1H(bp)) {
6594 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6595
6596 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6597 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6598 }
6599 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6600
6601 } else {
6602 int num_segs, sb_idx, prod_offset;
6603
6604 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6605
6606 if (!CHIP_IS_E1x(bp)) {
6607 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6608 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6609 }
6610
6611 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6612
6613 if (!CHIP_IS_E1x(bp)) {
6614 int dsb_idx = 0;
6615 /**
6616 * Producer memory:
6617 * E2 mode: address 0-135 match to the mapping memory;
6618 * 136 - PF0 default prod; 137 - PF1 default prod;
6619 * 138 - PF2 default prod; 139 - PF3 default prod;
6620 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6621 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6622 * 144-147 reserved.
6623 *
6624 * E1.5 mode - In backward compatible mode;
6625 * for non default SB; each even line in the memory
6626 * holds the U producer and each odd line hold
6627 * the C producer. The first 128 producers are for
6628 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6629 * producers are for the DSB for each PF.
6630 * Each PF has five segments: (the order inside each
6631 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6632 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6633 * 144-147 attn prods;
6634 */
6635 /* non-default-status-blocks */
6636 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6637 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6638 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6639 prod_offset = (bp->igu_base_sb + sb_idx) *
6640 num_segs;
6641
6642 for (i = 0; i < num_segs; i++) {
6643 addr = IGU_REG_PROD_CONS_MEMORY +
6644 (prod_offset + i) * 4;
6645 REG_WR(bp, addr, 0);
6646 }
6647 /* send consumer update with value 0 */
6648 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6649 USTORM_ID, 0, IGU_INT_NOP, 1);
6650 bnx2x_igu_clear_sb(bp,
6651 bp->igu_base_sb + sb_idx);
6652 }
6653
6654 /* default-status-blocks */
6655 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6656 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6657
6658 if (CHIP_MODE_IS_4_PORT(bp))
6659 dsb_idx = BP_FUNC(bp);
6660 else
6661 dsb_idx = BP_E1HVN(bp);
6662
6663 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6664 IGU_BC_BASE_DSB_PROD + dsb_idx :
6665 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6666
6667 for (i = 0; i < (num_segs * E1HVN_MAX);
6668 i += E1HVN_MAX) {
6669 addr = IGU_REG_PROD_CONS_MEMORY +
6670 (prod_offset + i)*4;
6671 REG_WR(bp, addr, 0);
6672 }
6673 /* send consumer update with 0 */
6674 if (CHIP_INT_MODE_IS_BC(bp)) {
6675 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6676 USTORM_ID, 0, IGU_INT_NOP, 1);
6677 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6678 CSTORM_ID, 0, IGU_INT_NOP, 1);
6679 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6680 XSTORM_ID, 0, IGU_INT_NOP, 1);
6681 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6682 TSTORM_ID, 0, IGU_INT_NOP, 1);
6683 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6684 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6685 } else {
6686 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6687 USTORM_ID, 0, IGU_INT_NOP, 1);
6688 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6689 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6690 }
6691 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6692
6693 /* !!! these should become driver const once
6694 rf-tool supports split-68 const */
6695 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6696 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6697 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6698 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6699 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6700 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6701 }
6702 }
6703
6704 /* Reset PCIE errors for debug */
6705 REG_WR(bp, 0x2114, 0xffffffff);
6706 REG_WR(bp, 0x2120, 0xffffffff);
6707
6708 if (CHIP_IS_E1x(bp)) {
6709 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6710 main_mem_base = HC_REG_MAIN_MEMORY +
6711 BP_PORT(bp) * (main_mem_size * 4);
6712 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6713 main_mem_width = 8;
6714
6715 val = REG_RD(bp, main_mem_prty_clr);
6716 if (val)
6717 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6718 "block during "
6719 "function init (0x%x)!\n", val);
6720
6721 /* Clear "false" parity errors in MSI-X table */
6722 for (i = main_mem_base;
6723 i < main_mem_base + main_mem_size * 4;
6724 i += main_mem_width) {
6725 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6726 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6727 i, main_mem_width / 4);
6728 }
6729 /* Clear HC parity attention */
6730 REG_RD(bp, main_mem_prty_clr);
6731 }
6732
6733 #ifdef BNX2X_STOP_ON_ERROR
6734 /* Enable STORMs SP logging */
6735 REG_WR8(bp, BAR_USTRORM_INTMEM +
6736 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6737 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6738 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6739 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6740 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6741 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6742 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6743 #endif
6744
6745 bnx2x_phy_probe(&bp->link_params);
6746
6747 return 0;
6748 }
6749
6750
6751 void bnx2x_free_mem(struct bnx2x *bp)
6752 {
6753 /* fastpath */
6754 bnx2x_free_fp_mem(bp);
6755 /* end of fastpath */
6756
6757 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6758 sizeof(struct host_sp_status_block));
6759
6760 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6761 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6762
6763 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6764 sizeof(struct bnx2x_slowpath));
6765
6766 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6767 bp->context.size);
6768
6769 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6770
6771 BNX2X_FREE(bp->ilt->lines);
6772
6773 #ifdef BCM_CNIC
6774 if (!CHIP_IS_E1x(bp))
6775 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6776 sizeof(struct host_hc_status_block_e2));
6777 else
6778 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6779 sizeof(struct host_hc_status_block_e1x));
6780
6781 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6782 #endif
6783
6784 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6785
6786 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6787 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6788 }
6789
6790 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6791 {
6792 int num_groups;
6793
6794 /* number of eth_queues */
6795 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6796
6797 /* Total number of FW statistics requests =
6798 * 1 for port stats + 1 for PF stats + num_eth_queues */
6799 bp->fw_stats_num = 2 + num_queue_stats;
6800
6801
6802 /* Request is built from stats_query_header and an array of
6803 * stats_query_cmd_group each of which contains
6804 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6805 * configured in the stats_query_header.
6806 */
6807 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6808 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6809
6810 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6811 num_groups * sizeof(struct stats_query_cmd_group);
6812
6813 /* Data for statistics requests + stats_conter
6814 *
6815 * stats_counter holds per-STORM counters that are incremented
6816 * when STORM has finished with the current request.
6817 */
6818 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6819 sizeof(struct per_pf_stats) +
6820 sizeof(struct per_queue_stats) * num_queue_stats +
6821 sizeof(struct stats_counter);
6822
6823 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6824 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6825
6826 /* Set shortcuts */
6827 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6828 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6829
6830 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6831 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6832
6833 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6834 bp->fw_stats_req_sz;
6835 return 0;
6836
6837 alloc_mem_err:
6838 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6839 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6840 return -ENOMEM;
6841 }
6842
6843
6844 int bnx2x_alloc_mem(struct bnx2x *bp)
6845 {
6846 #ifdef BCM_CNIC
6847 if (!CHIP_IS_E1x(bp))
6848 /* size = the status block + ramrod buffers */
6849 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6850 sizeof(struct host_hc_status_block_e2));
6851 else
6852 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6853 sizeof(struct host_hc_status_block_e1x));
6854
6855 /* allocate searcher T2 table */
6856 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6857 #endif
6858
6859
6860 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6861 sizeof(struct host_sp_status_block));
6862
6863 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6864 sizeof(struct bnx2x_slowpath));
6865
6866 /* Allocated memory for FW statistics */
6867 if (bnx2x_alloc_fw_stats_mem(bp))
6868 goto alloc_mem_err;
6869
6870 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6871
6872 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6873 bp->context.size);
6874
6875 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6876
6877 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6878 goto alloc_mem_err;
6879
6880 /* Slow path ring */
6881 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6882
6883 /* EQ */
6884 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6885 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6886
6887
6888 /* fastpath */
6889 /* need to be done at the end, since it's self adjusting to amount
6890 * of memory available for RSS queues
6891 */
6892 if (bnx2x_alloc_fp_mem(bp))
6893 goto alloc_mem_err;
6894 return 0;
6895
6896 alloc_mem_err:
6897 bnx2x_free_mem(bp);
6898 return -ENOMEM;
6899 }
6900
6901 /*
6902 * Init service functions
6903 */
6904
6905 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6906 struct bnx2x_vlan_mac_obj *obj, bool set,
6907 int mac_type, unsigned long *ramrod_flags)
6908 {
6909 int rc;
6910 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6911
6912 memset(&ramrod_param, 0, sizeof(ramrod_param));
6913
6914 /* Fill general parameters */
6915 ramrod_param.vlan_mac_obj = obj;
6916 ramrod_param.ramrod_flags = *ramrod_flags;
6917
6918 /* Fill a user request section if needed */
6919 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6920 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6921
6922 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6923
6924 /* Set the command: ADD or DEL */
6925 if (set)
6926 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6927 else
6928 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6929 }
6930
6931 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6932 if (rc < 0)
6933 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6934 return rc;
6935 }
6936
6937 int bnx2x_del_all_macs(struct bnx2x *bp,
6938 struct bnx2x_vlan_mac_obj *mac_obj,
6939 int mac_type, bool wait_for_comp)
6940 {
6941 int rc;
6942 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6943
6944 /* Wait for completion of requested */
6945 if (wait_for_comp)
6946 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6947
6948 /* Set the mac type of addresses we want to clear */
6949 __set_bit(mac_type, &vlan_mac_flags);
6950
6951 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6952 if (rc < 0)
6953 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6954
6955 return rc;
6956 }
6957
6958 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6959 {
6960 unsigned long ramrod_flags = 0;
6961
6962 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6963
6964 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6965 /* Eth MAC is set on RSS leading client (fp[0]) */
6966 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6967 BNX2X_ETH_MAC, &ramrod_flags);
6968 }
6969
6970 int bnx2x_setup_leading(struct bnx2x *bp)
6971 {
6972 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6973 }
6974
6975 /**
6976 * bnx2x_set_int_mode - configure interrupt mode
6977 *
6978 * @bp: driver handle
6979 *
6980 * In case of MSI-X it will also try to enable MSI-X.
6981 */
6982 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6983 {
6984 switch (int_mode) {
6985 case INT_MODE_MSI:
6986 bnx2x_enable_msi(bp);
6987 /* falling through... */
6988 case INT_MODE_INTx:
6989 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
6990 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6991 break;
6992 default:
6993 /* Set number of queues according to bp->multi_mode value */
6994 bnx2x_set_num_queues(bp);
6995
6996 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6997 bp->num_queues);
6998
6999 /* if we can't use MSI-X we only need one fp,
7000 * so try to enable MSI-X with the requested number of fp's
7001 * and fallback to MSI or legacy INTx with one fp
7002 */
7003 if (bnx2x_enable_msix(bp)) {
7004 /* failed to enable MSI-X */
7005 if (bp->multi_mode)
7006 DP(NETIF_MSG_IFUP,
7007 "Multi requested but failed to "
7008 "enable MSI-X (%d), "
7009 "set number of queues to %d\n",
7010 bp->num_queues,
7011 1 + NON_ETH_CONTEXT_USE);
7012 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7013
7014 /* Try to enable MSI */
7015 if (!(bp->flags & DISABLE_MSI_FLAG))
7016 bnx2x_enable_msi(bp);
7017 }
7018 break;
7019 }
7020 }
7021
7022 /* must be called prioir to any HW initializations */
7023 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7024 {
7025 return L2_ILT_LINES(bp);
7026 }
7027
7028 void bnx2x_ilt_set_info(struct bnx2x *bp)
7029 {
7030 struct ilt_client_info *ilt_client;
7031 struct bnx2x_ilt *ilt = BP_ILT(bp);
7032 u16 line = 0;
7033
7034 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7035 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7036
7037 /* CDU */
7038 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7039 ilt_client->client_num = ILT_CLIENT_CDU;
7040 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7041 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7042 ilt_client->start = line;
7043 line += bnx2x_cid_ilt_lines(bp);
7044 #ifdef BCM_CNIC
7045 line += CNIC_ILT_LINES;
7046 #endif
7047 ilt_client->end = line - 1;
7048
7049 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7050 "flags 0x%x, hw psz %d\n",
7051 ilt_client->start,
7052 ilt_client->end,
7053 ilt_client->page_size,
7054 ilt_client->flags,
7055 ilog2(ilt_client->page_size >> 12));
7056
7057 /* QM */
7058 if (QM_INIT(bp->qm_cid_count)) {
7059 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7060 ilt_client->client_num = ILT_CLIENT_QM;
7061 ilt_client->page_size = QM_ILT_PAGE_SZ;
7062 ilt_client->flags = 0;
7063 ilt_client->start = line;
7064
7065 /* 4 bytes for each cid */
7066 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7067 QM_ILT_PAGE_SZ);
7068
7069 ilt_client->end = line - 1;
7070
7071 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7072 "flags 0x%x, hw psz %d\n",
7073 ilt_client->start,
7074 ilt_client->end,
7075 ilt_client->page_size,
7076 ilt_client->flags,
7077 ilog2(ilt_client->page_size >> 12));
7078
7079 }
7080 /* SRC */
7081 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7082 #ifdef BCM_CNIC
7083 ilt_client->client_num = ILT_CLIENT_SRC;
7084 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7085 ilt_client->flags = 0;
7086 ilt_client->start = line;
7087 line += SRC_ILT_LINES;
7088 ilt_client->end = line - 1;
7089
7090 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7091 "flags 0x%x, hw psz %d\n",
7092 ilt_client->start,
7093 ilt_client->end,
7094 ilt_client->page_size,
7095 ilt_client->flags,
7096 ilog2(ilt_client->page_size >> 12));
7097
7098 #else
7099 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7100 #endif
7101
7102 /* TM */
7103 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7104 #ifdef BCM_CNIC
7105 ilt_client->client_num = ILT_CLIENT_TM;
7106 ilt_client->page_size = TM_ILT_PAGE_SZ;
7107 ilt_client->flags = 0;
7108 ilt_client->start = line;
7109 line += TM_ILT_LINES;
7110 ilt_client->end = line - 1;
7111
7112 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7113 "flags 0x%x, hw psz %d\n",
7114 ilt_client->start,
7115 ilt_client->end,
7116 ilt_client->page_size,
7117 ilt_client->flags,
7118 ilog2(ilt_client->page_size >> 12));
7119
7120 #else
7121 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7122 #endif
7123 BUG_ON(line > ILT_MAX_LINES);
7124 }
7125
7126 /**
7127 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7128 *
7129 * @bp: driver handle
7130 * @fp: pointer to fastpath
7131 * @init_params: pointer to parameters structure
7132 *
7133 * parameters configured:
7134 * - HC configuration
7135 * - Queue's CDU context
7136 */
7137 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7138 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7139 {
7140
7141 u8 cos;
7142 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7143 if (!IS_FCOE_FP(fp)) {
7144 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7145 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7146
7147 /* If HC is supporterd, enable host coalescing in the transition
7148 * to INIT state.
7149 */
7150 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7151 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7152
7153 /* HC rate */
7154 init_params->rx.hc_rate = bp->rx_ticks ?
7155 (1000000 / bp->rx_ticks) : 0;
7156 init_params->tx.hc_rate = bp->tx_ticks ?
7157 (1000000 / bp->tx_ticks) : 0;
7158
7159 /* FW SB ID */
7160 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7161 fp->fw_sb_id;
7162
7163 /*
7164 * CQ index among the SB indices: FCoE clients uses the default
7165 * SB, therefore it's different.
7166 */
7167 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7168 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7169 }
7170
7171 /* set maximum number of COSs supported by this queue */
7172 init_params->max_cos = fp->max_cos;
7173
7174 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
7175 fp->index, init_params->max_cos);
7176
7177 /* set the context pointers queue object */
7178 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7179 init_params->cxts[cos] =
7180 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7181 }
7182
7183 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7184 struct bnx2x_queue_state_params *q_params,
7185 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7186 int tx_index, bool leading)
7187 {
7188 memset(tx_only_params, 0, sizeof(*tx_only_params));
7189
7190 /* Set the command */
7191 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7192
7193 /* Set tx-only QUEUE flags: don't zero statistics */
7194 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7195
7196 /* choose the index of the cid to send the slow path on */
7197 tx_only_params->cid_index = tx_index;
7198
7199 /* Set general TX_ONLY_SETUP parameters */
7200 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7201
7202 /* Set Tx TX_ONLY_SETUP parameters */
7203 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7204
7205 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7206 "cos %d, primary cid %d, cid %d, "
7207 "client id %d, sp-client id %d, flags %lx\n",
7208 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7209 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7210 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7211
7212 /* send the ramrod */
7213 return bnx2x_queue_state_change(bp, q_params);
7214 }
7215
7216
7217 /**
7218 * bnx2x_setup_queue - setup queue
7219 *
7220 * @bp: driver handle
7221 * @fp: pointer to fastpath
7222 * @leading: is leading
7223 *
7224 * This function performs 2 steps in a Queue state machine
7225 * actually: 1) RESET->INIT 2) INIT->SETUP
7226 */
7227
7228 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7229 bool leading)
7230 {
7231 struct bnx2x_queue_state_params q_params = {0};
7232 struct bnx2x_queue_setup_params *setup_params =
7233 &q_params.params.setup;
7234 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7235 &q_params.params.tx_only;
7236 int rc;
7237 u8 tx_index;
7238
7239 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
7240
7241 /* reset IGU state skip FCoE L2 queue */
7242 if (!IS_FCOE_FP(fp))
7243 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7244 IGU_INT_ENABLE, 0);
7245
7246 q_params.q_obj = &fp->q_obj;
7247 /* We want to wait for completion in this context */
7248 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7249
7250 /* Prepare the INIT parameters */
7251 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7252
7253 /* Set the command */
7254 q_params.cmd = BNX2X_Q_CMD_INIT;
7255
7256 /* Change the state to INIT */
7257 rc = bnx2x_queue_state_change(bp, &q_params);
7258 if (rc) {
7259 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7260 return rc;
7261 }
7262
7263 DP(BNX2X_MSG_SP, "init complete\n");
7264
7265
7266 /* Now move the Queue to the SETUP state... */
7267 memset(setup_params, 0, sizeof(*setup_params));
7268
7269 /* Set QUEUE flags */
7270 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7271
7272 /* Set general SETUP parameters */
7273 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7274 FIRST_TX_COS_INDEX);
7275
7276 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7277 &setup_params->rxq_params);
7278
7279 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7280 FIRST_TX_COS_INDEX);
7281
7282 /* Set the command */
7283 q_params.cmd = BNX2X_Q_CMD_SETUP;
7284
7285 /* Change the state to SETUP */
7286 rc = bnx2x_queue_state_change(bp, &q_params);
7287 if (rc) {
7288 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7289 return rc;
7290 }
7291
7292 /* loop through the relevant tx-only indices */
7293 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7294 tx_index < fp->max_cos;
7295 tx_index++) {
7296
7297 /* prepare and send tx-only ramrod*/
7298 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7299 tx_only_params, tx_index, leading);
7300 if (rc) {
7301 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7302 fp->index, tx_index);
7303 return rc;
7304 }
7305 }
7306
7307 return rc;
7308 }
7309
7310 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7311 {
7312 struct bnx2x_fastpath *fp = &bp->fp[index];
7313 struct bnx2x_fp_txdata *txdata;
7314 struct bnx2x_queue_state_params q_params = {0};
7315 int rc, tx_index;
7316
7317 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
7318
7319 q_params.q_obj = &fp->q_obj;
7320 /* We want to wait for completion in this context */
7321 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7322
7323
7324 /* close tx-only connections */
7325 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7326 tx_index < fp->max_cos;
7327 tx_index++){
7328
7329 /* ascertain this is a normal queue*/
7330 txdata = &fp->txdata[tx_index];
7331
7332 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
7333 txdata->txq_index);
7334
7335 /* send halt terminate on tx-only connection */
7336 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7337 memset(&q_params.params.terminate, 0,
7338 sizeof(q_params.params.terminate));
7339 q_params.params.terminate.cid_index = tx_index;
7340
7341 rc = bnx2x_queue_state_change(bp, &q_params);
7342 if (rc)
7343 return rc;
7344
7345 /* send halt terminate on tx-only connection */
7346 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7347 memset(&q_params.params.cfc_del, 0,
7348 sizeof(q_params.params.cfc_del));
7349 q_params.params.cfc_del.cid_index = tx_index;
7350 rc = bnx2x_queue_state_change(bp, &q_params);
7351 if (rc)
7352 return rc;
7353 }
7354 /* Stop the primary connection: */
7355 /* ...halt the connection */
7356 q_params.cmd = BNX2X_Q_CMD_HALT;
7357 rc = bnx2x_queue_state_change(bp, &q_params);
7358 if (rc)
7359 return rc;
7360
7361 /* ...terminate the connection */
7362 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7363 memset(&q_params.params.terminate, 0,
7364 sizeof(q_params.params.terminate));
7365 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7366 rc = bnx2x_queue_state_change(bp, &q_params);
7367 if (rc)
7368 return rc;
7369 /* ...delete cfc entry */
7370 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7371 memset(&q_params.params.cfc_del, 0,
7372 sizeof(q_params.params.cfc_del));
7373 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7374 return bnx2x_queue_state_change(bp, &q_params);
7375 }
7376
7377
7378 static void bnx2x_reset_func(struct bnx2x *bp)
7379 {
7380 int port = BP_PORT(bp);
7381 int func = BP_FUNC(bp);
7382 int i;
7383
7384 /* Disable the function in the FW */
7385 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7386 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7387 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7388 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7389
7390 /* FP SBs */
7391 for_each_eth_queue(bp, i) {
7392 struct bnx2x_fastpath *fp = &bp->fp[i];
7393 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7394 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7395 SB_DISABLED);
7396 }
7397
7398 #ifdef BCM_CNIC
7399 /* CNIC SB */
7400 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7401 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7402 SB_DISABLED);
7403 #endif
7404 /* SP SB */
7405 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7406 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7407 SB_DISABLED);
7408
7409 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7410 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7411 0);
7412
7413 /* Configure IGU */
7414 if (bp->common.int_block == INT_BLOCK_HC) {
7415 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7416 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7417 } else {
7418 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7419 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7420 }
7421
7422 #ifdef BCM_CNIC
7423 /* Disable Timer scan */
7424 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7425 /*
7426 * Wait for at least 10ms and up to 2 second for the timers scan to
7427 * complete
7428 */
7429 for (i = 0; i < 200; i++) {
7430 msleep(10);
7431 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7432 break;
7433 }
7434 #endif
7435 /* Clear ILT */
7436 bnx2x_clear_func_ilt(bp, func);
7437
7438 /* Timers workaround bug for E2: if this is vnic-3,
7439 * we need to set the entire ilt range for this timers.
7440 */
7441 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7442 struct ilt_client_info ilt_cli;
7443 /* use dummy TM client */
7444 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7445 ilt_cli.start = 0;
7446 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7447 ilt_cli.client_num = ILT_CLIENT_TM;
7448
7449 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7450 }
7451
7452 /* this assumes that reset_port() called before reset_func()*/
7453 if (!CHIP_IS_E1x(bp))
7454 bnx2x_pf_disable(bp);
7455
7456 bp->dmae_ready = 0;
7457 }
7458
7459 static void bnx2x_reset_port(struct bnx2x *bp)
7460 {
7461 int port = BP_PORT(bp);
7462 u32 val;
7463
7464 /* Reset physical Link */
7465 bnx2x__link_reset(bp);
7466
7467 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7468
7469 /* Do not rcv packets to BRB */
7470 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7471 /* Do not direct rcv packets that are not for MCP to the BRB */
7472 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7473 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7474
7475 /* Configure AEU */
7476 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7477
7478 msleep(100);
7479 /* Check for BRB port occupancy */
7480 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7481 if (val)
7482 DP(NETIF_MSG_IFDOWN,
7483 "BRB1 is not empty %d blocks are occupied\n", val);
7484
7485 /* TODO: Close Doorbell port? */
7486 }
7487
7488 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7489 {
7490 struct bnx2x_func_state_params func_params = {0};
7491
7492 /* Prepare parameters for function state transitions */
7493 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7494
7495 func_params.f_obj = &bp->func_obj;
7496 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7497
7498 func_params.params.hw_init.load_phase = load_code;
7499
7500 return bnx2x_func_state_change(bp, &func_params);
7501 }
7502
7503 static inline int bnx2x_func_stop(struct bnx2x *bp)
7504 {
7505 struct bnx2x_func_state_params func_params = {0};
7506 int rc;
7507
7508 /* Prepare parameters for function state transitions */
7509 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7510 func_params.f_obj = &bp->func_obj;
7511 func_params.cmd = BNX2X_F_CMD_STOP;
7512
7513 /*
7514 * Try to stop the function the 'good way'. If fails (in case
7515 * of a parity error during bnx2x_chip_cleanup()) and we are
7516 * not in a debug mode, perform a state transaction in order to
7517 * enable further HW_RESET transaction.
7518 */
7519 rc = bnx2x_func_state_change(bp, &func_params);
7520 if (rc) {
7521 #ifdef BNX2X_STOP_ON_ERROR
7522 return rc;
7523 #else
7524 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7525 "transaction\n");
7526 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7527 return bnx2x_func_state_change(bp, &func_params);
7528 #endif
7529 }
7530
7531 return 0;
7532 }
7533
7534 /**
7535 * bnx2x_send_unload_req - request unload mode from the MCP.
7536 *
7537 * @bp: driver handle
7538 * @unload_mode: requested function's unload mode
7539 *
7540 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7541 */
7542 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7543 {
7544 u32 reset_code = 0;
7545 int port = BP_PORT(bp);
7546
7547 /* Select the UNLOAD request mode */
7548 if (unload_mode == UNLOAD_NORMAL)
7549 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7550
7551 else if (bp->flags & NO_WOL_FLAG)
7552 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7553
7554 else if (bp->wol) {
7555 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7556 u8 *mac_addr = bp->dev->dev_addr;
7557 u32 val;
7558 /* The mac address is written to entries 1-4 to
7559 preserve entry 0 which is used by the PMF */
7560 u8 entry = (BP_E1HVN(bp) + 1)*8;
7561
7562 val = (mac_addr[0] << 8) | mac_addr[1];
7563 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7564
7565 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7566 (mac_addr[4] << 8) | mac_addr[5];
7567 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7568
7569 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7570
7571 } else
7572 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7573
7574 /* Send the request to the MCP */
7575 if (!BP_NOMCP(bp))
7576 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7577 else {
7578 int path = BP_PATH(bp);
7579
7580 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7581 "%d, %d, %d\n",
7582 path, load_count[path][0], load_count[path][1],
7583 load_count[path][2]);
7584 load_count[path][0]--;
7585 load_count[path][1 + port]--;
7586 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7587 "%d, %d, %d\n",
7588 path, load_count[path][0], load_count[path][1],
7589 load_count[path][2]);
7590 if (load_count[path][0] == 0)
7591 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7592 else if (load_count[path][1 + port] == 0)
7593 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7594 else
7595 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7596 }
7597
7598 return reset_code;
7599 }
7600
7601 /**
7602 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7603 *
7604 * @bp: driver handle
7605 */
7606 void bnx2x_send_unload_done(struct bnx2x *bp)
7607 {
7608 /* Report UNLOAD_DONE to MCP */
7609 if (!BP_NOMCP(bp))
7610 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7611 }
7612
7613 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7614 {
7615 int tout = 50;
7616 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7617
7618 if (!bp->port.pmf)
7619 return 0;
7620
7621 /*
7622 * (assumption: No Attention from MCP at this stage)
7623 * PMF probably in the middle of TXdisable/enable transaction
7624 * 1. Sync IRS for default SB
7625 * 2. Sync SP queue - this guarantes us that attention handling started
7626 * 3. Wait, that TXdisable/enable transaction completes
7627 *
7628 * 1+2 guranty that if DCBx attention was scheduled it already changed
7629 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7630 * received complettion for the transaction the state is TX_STOPPED.
7631 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7632 * transaction.
7633 */
7634
7635 /* make sure default SB ISR is done */
7636 if (msix)
7637 synchronize_irq(bp->msix_table[0].vector);
7638 else
7639 synchronize_irq(bp->pdev->irq);
7640
7641 flush_workqueue(bnx2x_wq);
7642
7643 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7644 BNX2X_F_STATE_STARTED && tout--)
7645 msleep(20);
7646
7647 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7648 BNX2X_F_STATE_STARTED) {
7649 #ifdef BNX2X_STOP_ON_ERROR
7650 return -EBUSY;
7651 #else
7652 /*
7653 * Failed to complete the transaction in a "good way"
7654 * Force both transactions with CLR bit
7655 */
7656 struct bnx2x_func_state_params func_params = {0};
7657
7658 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7659 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7660
7661 func_params.f_obj = &bp->func_obj;
7662 __set_bit(RAMROD_DRV_CLR_ONLY,
7663 &func_params.ramrod_flags);
7664
7665 /* STARTED-->TX_ST0PPED */
7666 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7667 bnx2x_func_state_change(bp, &func_params);
7668
7669 /* TX_ST0PPED-->STARTED */
7670 func_params.cmd = BNX2X_F_CMD_TX_START;
7671 return bnx2x_func_state_change(bp, &func_params);
7672 #endif
7673 }
7674
7675 return 0;
7676 }
7677
7678 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7679 {
7680 int port = BP_PORT(bp);
7681 int i, rc = 0;
7682 u8 cos;
7683 struct bnx2x_mcast_ramrod_params rparam = {0};
7684 u32 reset_code;
7685
7686 /* Wait until tx fastpath tasks complete */
7687 for_each_tx_queue(bp, i) {
7688 struct bnx2x_fastpath *fp = &bp->fp[i];
7689
7690 for_each_cos_in_tx_queue(fp, cos)
7691 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7692 #ifdef BNX2X_STOP_ON_ERROR
7693 if (rc)
7694 return;
7695 #endif
7696 }
7697
7698 /* Give HW time to discard old tx messages */
7699 usleep_range(1000, 1000);
7700
7701 /* Clean all ETH MACs */
7702 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7703 if (rc < 0)
7704 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7705
7706 /* Clean up UC list */
7707 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7708 true);
7709 if (rc < 0)
7710 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7711 "%d\n", rc);
7712
7713 /* Disable LLH */
7714 if (!CHIP_IS_E1(bp))
7715 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7716
7717 /* Set "drop all" (stop Rx).
7718 * We need to take a netif_addr_lock() here in order to prevent
7719 * a race between the completion code and this code.
7720 */
7721 netif_addr_lock_bh(bp->dev);
7722 /* Schedule the rx_mode command */
7723 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7724 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7725 else
7726 bnx2x_set_storm_rx_mode(bp);
7727
7728 /* Cleanup multicast configuration */
7729 rparam.mcast_obj = &bp->mcast_obj;
7730 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7731 if (rc < 0)
7732 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7733
7734 netif_addr_unlock_bh(bp->dev);
7735
7736
7737
7738 /*
7739 * Send the UNLOAD_REQUEST to the MCP. This will return if
7740 * this function should perform FUNC, PORT or COMMON HW
7741 * reset.
7742 */
7743 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7744
7745 /*
7746 * (assumption: No Attention from MCP at this stage)
7747 * PMF probably in the middle of TXdisable/enable transaction
7748 */
7749 rc = bnx2x_func_wait_started(bp);
7750 if (rc) {
7751 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7752 #ifdef BNX2X_STOP_ON_ERROR
7753 return;
7754 #endif
7755 }
7756
7757 /* Close multi and leading connections
7758 * Completions for ramrods are collected in a synchronous way
7759 */
7760 for_each_queue(bp, i)
7761 if (bnx2x_stop_queue(bp, i))
7762 #ifdef BNX2X_STOP_ON_ERROR
7763 return;
7764 #else
7765 goto unload_error;
7766 #endif
7767 /* If SP settings didn't get completed so far - something
7768 * very wrong has happen.
7769 */
7770 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7771 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7772
7773 #ifndef BNX2X_STOP_ON_ERROR
7774 unload_error:
7775 #endif
7776 rc = bnx2x_func_stop(bp);
7777 if (rc) {
7778 BNX2X_ERR("Function stop failed!\n");
7779 #ifdef BNX2X_STOP_ON_ERROR
7780 return;
7781 #endif
7782 }
7783
7784 /* Disable HW interrupts, NAPI */
7785 bnx2x_netif_stop(bp, 1);
7786
7787 /* Release IRQs */
7788 bnx2x_free_irq(bp);
7789
7790 /* Reset the chip */
7791 rc = bnx2x_reset_hw(bp, reset_code);
7792 if (rc)
7793 BNX2X_ERR("HW_RESET failed\n");
7794
7795
7796 /* Report UNLOAD_DONE to MCP */
7797 bnx2x_send_unload_done(bp);
7798 }
7799
7800 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7801 {
7802 u32 val;
7803
7804 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7805
7806 if (CHIP_IS_E1(bp)) {
7807 int port = BP_PORT(bp);
7808 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7809 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7810
7811 val = REG_RD(bp, addr);
7812 val &= ~(0x300);
7813 REG_WR(bp, addr, val);
7814 } else {
7815 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7816 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7817 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7818 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7819 }
7820 }
7821
7822 /* Close gates #2, #3 and #4: */
7823 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7824 {
7825 u32 val;
7826
7827 /* Gates #2 and #4a are closed/opened for "not E1" only */
7828 if (!CHIP_IS_E1(bp)) {
7829 /* #4 */
7830 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7831 /* #2 */
7832 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7833 }
7834
7835 /* #3 */
7836 if (CHIP_IS_E1x(bp)) {
7837 /* Prevent interrupts from HC on both ports */
7838 val = REG_RD(bp, HC_REG_CONFIG_1);
7839 REG_WR(bp, HC_REG_CONFIG_1,
7840 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7841 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7842
7843 val = REG_RD(bp, HC_REG_CONFIG_0);
7844 REG_WR(bp, HC_REG_CONFIG_0,
7845 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7846 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7847 } else {
7848 /* Prevent incomming interrupts in IGU */
7849 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7850
7851 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7852 (!close) ?
7853 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7854 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7855 }
7856
7857 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7858 close ? "closing" : "opening");
7859 mmiowb();
7860 }
7861
7862 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7863
7864 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7865 {
7866 /* Do some magic... */
7867 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7868 *magic_val = val & SHARED_MF_CLP_MAGIC;
7869 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7870 }
7871
7872 /**
7873 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7874 *
7875 * @bp: driver handle
7876 * @magic_val: old value of the `magic' bit.
7877 */
7878 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7879 {
7880 /* Restore the `magic' bit value... */
7881 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7882 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7883 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7884 }
7885
7886 /**
7887 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7888 *
7889 * @bp: driver handle
7890 * @magic_val: old value of 'magic' bit.
7891 *
7892 * Takes care of CLP configurations.
7893 */
7894 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7895 {
7896 u32 shmem;
7897 u32 validity_offset;
7898
7899 DP(NETIF_MSG_HW, "Starting\n");
7900
7901 /* Set `magic' bit in order to save MF config */
7902 if (!CHIP_IS_E1(bp))
7903 bnx2x_clp_reset_prep(bp, magic_val);
7904
7905 /* Get shmem offset */
7906 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7907 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7908
7909 /* Clear validity map flags */
7910 if (shmem > 0)
7911 REG_WR(bp, shmem + validity_offset, 0);
7912 }
7913
7914 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7915 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7916
7917 /**
7918 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7919 *
7920 * @bp: driver handle
7921 */
7922 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7923 {
7924 /* special handling for emulation and FPGA,
7925 wait 10 times longer */
7926 if (CHIP_REV_IS_SLOW(bp))
7927 msleep(MCP_ONE_TIMEOUT*10);
7928 else
7929 msleep(MCP_ONE_TIMEOUT);
7930 }
7931
7932 /*
7933 * initializes bp->common.shmem_base and waits for validity signature to appear
7934 */
7935 static int bnx2x_init_shmem(struct bnx2x *bp)
7936 {
7937 int cnt = 0;
7938 u32 val = 0;
7939
7940 do {
7941 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7942 if (bp->common.shmem_base) {
7943 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7944 if (val & SHR_MEM_VALIDITY_MB)
7945 return 0;
7946 }
7947
7948 bnx2x_mcp_wait_one(bp);
7949
7950 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7951
7952 BNX2X_ERR("BAD MCP validity signature\n");
7953
7954 return -ENODEV;
7955 }
7956
7957 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7958 {
7959 int rc = bnx2x_init_shmem(bp);
7960
7961 /* Restore the `magic' bit value */
7962 if (!CHIP_IS_E1(bp))
7963 bnx2x_clp_reset_done(bp, magic_val);
7964
7965 return rc;
7966 }
7967
7968 static void bnx2x_pxp_prep(struct bnx2x *bp)
7969 {
7970 if (!CHIP_IS_E1(bp)) {
7971 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7972 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7973 mmiowb();
7974 }
7975 }
7976
7977 /*
7978 * Reset the whole chip except for:
7979 * - PCIE core
7980 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7981 * one reset bit)
7982 * - IGU
7983 * - MISC (including AEU)
7984 * - GRC
7985 * - RBCN, RBCP
7986 */
7987 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7988 {
7989 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7990 u32 global_bits2, stay_reset2;
7991
7992 /*
7993 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7994 * (per chip) blocks.
7995 */
7996 global_bits2 =
7997 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7998 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7999
8000 /* Don't reset the following blocks */
8001 not_reset_mask1 =
8002 MISC_REGISTERS_RESET_REG_1_RST_HC |
8003 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8004 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8005
8006 not_reset_mask2 =
8007 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8008 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8009 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8010 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8011 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8012 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8013 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8014 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8015 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8016 MISC_REGISTERS_RESET_REG_2_PGLC;
8017
8018 /*
8019 * Keep the following blocks in reset:
8020 * - all xxMACs are handled by the bnx2x_link code.
8021 */
8022 stay_reset2 =
8023 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8024 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8025 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8026 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8027 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8028 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8029 MISC_REGISTERS_RESET_REG_2_XMAC |
8030 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8031
8032 /* Full reset masks according to the chip */
8033 reset_mask1 = 0xffffffff;
8034
8035 if (CHIP_IS_E1(bp))
8036 reset_mask2 = 0xffff;
8037 else if (CHIP_IS_E1H(bp))
8038 reset_mask2 = 0x1ffff;
8039 else if (CHIP_IS_E2(bp))
8040 reset_mask2 = 0xfffff;
8041 else /* CHIP_IS_E3 */
8042 reset_mask2 = 0x3ffffff;
8043
8044 /* Don't reset global blocks unless we need to */
8045 if (!global)
8046 reset_mask2 &= ~global_bits2;
8047
8048 /*
8049 * In case of attention in the QM, we need to reset PXP
8050 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8051 * because otherwise QM reset would release 'close the gates' shortly
8052 * before resetting the PXP, then the PSWRQ would send a write
8053 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8054 * read the payload data from PSWWR, but PSWWR would not
8055 * respond. The write queue in PGLUE would stuck, dmae commands
8056 * would not return. Therefore it's important to reset the second
8057 * reset register (containing the
8058 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8059 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8060 * bit).
8061 */
8062 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8063 reset_mask2 & (~not_reset_mask2));
8064
8065 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8066 reset_mask1 & (~not_reset_mask1));
8067
8068 barrier();
8069 mmiowb();
8070
8071 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8072 reset_mask2 & (~stay_reset2));
8073
8074 barrier();
8075 mmiowb();
8076
8077 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8078 mmiowb();
8079 }
8080
8081 /**
8082 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8083 * It should get cleared in no more than 1s.
8084 *
8085 * @bp: driver handle
8086 *
8087 * It should get cleared in no more than 1s. Returns 0 if
8088 * pending writes bit gets cleared.
8089 */
8090 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8091 {
8092 u32 cnt = 1000;
8093 u32 pend_bits = 0;
8094
8095 do {
8096 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8097
8098 if (pend_bits == 0)
8099 break;
8100
8101 usleep_range(1000, 1000);
8102 } while (cnt-- > 0);
8103
8104 if (cnt <= 0) {
8105 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8106 pend_bits);
8107 return -EBUSY;
8108 }
8109
8110 return 0;
8111 }
8112
8113 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8114 {
8115 int cnt = 1000;
8116 u32 val = 0;
8117 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8118
8119
8120 /* Empty the Tetris buffer, wait for 1s */
8121 do {
8122 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8123 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8124 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8125 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8126 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8127 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8128 ((port_is_idle_0 & 0x1) == 0x1) &&
8129 ((port_is_idle_1 & 0x1) == 0x1) &&
8130 (pgl_exp_rom2 == 0xffffffff))
8131 break;
8132 usleep_range(1000, 1000);
8133 } while (cnt-- > 0);
8134
8135 if (cnt <= 0) {
8136 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8137 " are still"
8138 " outstanding read requests after 1s!\n");
8139 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8140 " port_is_idle_0=0x%08x,"
8141 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8142 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8143 pgl_exp_rom2);
8144 return -EAGAIN;
8145 }
8146
8147 barrier();
8148
8149 /* Close gates #2, #3 and #4 */
8150 bnx2x_set_234_gates(bp, true);
8151
8152 /* Poll for IGU VQs for 57712 and newer chips */
8153 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8154 return -EAGAIN;
8155
8156
8157 /* TBD: Indicate that "process kill" is in progress to MCP */
8158
8159 /* Clear "unprepared" bit */
8160 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8161 barrier();
8162
8163 /* Make sure all is written to the chip before the reset */
8164 mmiowb();
8165
8166 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8167 * PSWHST, GRC and PSWRD Tetris buffer.
8168 */
8169 usleep_range(1000, 1000);
8170
8171 /* Prepare to chip reset: */
8172 /* MCP */
8173 if (global)
8174 bnx2x_reset_mcp_prep(bp, &val);
8175
8176 /* PXP */
8177 bnx2x_pxp_prep(bp);
8178 barrier();
8179
8180 /* reset the chip */
8181 bnx2x_process_kill_chip_reset(bp, global);
8182 barrier();
8183
8184 /* Recover after reset: */
8185 /* MCP */
8186 if (global && bnx2x_reset_mcp_comp(bp, val))
8187 return -EAGAIN;
8188
8189 /* TBD: Add resetting the NO_MCP mode DB here */
8190
8191 /* PXP */
8192 bnx2x_pxp_prep(bp);
8193
8194 /* Open the gates #2, #3 and #4 */
8195 bnx2x_set_234_gates(bp, false);
8196
8197 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8198 * reset state, re-enable attentions. */
8199
8200 return 0;
8201 }
8202
8203 int bnx2x_leader_reset(struct bnx2x *bp)
8204 {
8205 int rc = 0;
8206 bool global = bnx2x_reset_is_global(bp);
8207
8208 /* Try to recover after the failure */
8209 if (bnx2x_process_kill(bp, global)) {
8210 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8211 "Aii!\n", BP_PATH(bp));
8212 rc = -EAGAIN;
8213 goto exit_leader_reset;
8214 }
8215
8216 /*
8217 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8218 * state.
8219 */
8220 bnx2x_set_reset_done(bp);
8221 if (global)
8222 bnx2x_clear_reset_global(bp);
8223
8224 exit_leader_reset:
8225 bp->is_leader = 0;
8226 bnx2x_release_leader_lock(bp);
8227 smp_mb();
8228 return rc;
8229 }
8230
8231 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8232 {
8233 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8234
8235 /* Disconnect this device */
8236 netif_device_detach(bp->dev);
8237
8238 /*
8239 * Block ifup for all function on this engine until "process kill"
8240 * or power cycle.
8241 */
8242 bnx2x_set_reset_in_progress(bp);
8243
8244 /* Shut down the power */
8245 bnx2x_set_power_state(bp, PCI_D3hot);
8246
8247 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8248
8249 smp_mb();
8250 }
8251
8252 /*
8253 * Assumption: runs under rtnl lock. This together with the fact
8254 * that it's called only from bnx2x_sp_rtnl() ensure that it
8255 * will never be called when netif_running(bp->dev) is false.
8256 */
8257 static void bnx2x_parity_recover(struct bnx2x *bp)
8258 {
8259 bool global = false;
8260
8261 DP(NETIF_MSG_HW, "Handling parity\n");
8262 while (1) {
8263 switch (bp->recovery_state) {
8264 case BNX2X_RECOVERY_INIT:
8265 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8266 bnx2x_chk_parity_attn(bp, &global, false);
8267
8268 /* Try to get a LEADER_LOCK HW lock */
8269 if (bnx2x_trylock_leader_lock(bp)) {
8270 bnx2x_set_reset_in_progress(bp);
8271 /*
8272 * Check if there is a global attention and if
8273 * there was a global attention, set the global
8274 * reset bit.
8275 */
8276
8277 if (global)
8278 bnx2x_set_reset_global(bp);
8279
8280 bp->is_leader = 1;
8281 }
8282
8283 /* Stop the driver */
8284 /* If interface has been removed - break */
8285 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8286 return;
8287
8288 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8289
8290 /*
8291 * Reset MCP command sequence number and MCP mail box
8292 * sequence as we are going to reset the MCP.
8293 */
8294 if (global) {
8295 bp->fw_seq = 0;
8296 bp->fw_drv_pulse_wr_seq = 0;
8297 }
8298
8299 /* Ensure "is_leader", MCP command sequence and
8300 * "recovery_state" update values are seen on other
8301 * CPUs.
8302 */
8303 smp_mb();
8304 break;
8305
8306 case BNX2X_RECOVERY_WAIT:
8307 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8308 if (bp->is_leader) {
8309 int other_engine = BP_PATH(bp) ? 0 : 1;
8310 u32 other_load_counter =
8311 bnx2x_get_load_cnt(bp, other_engine);
8312 u32 load_counter =
8313 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8314 global = bnx2x_reset_is_global(bp);
8315
8316 /*
8317 * In case of a parity in a global block, let
8318 * the first leader that performs a
8319 * leader_reset() reset the global blocks in
8320 * order to clear global attentions. Otherwise
8321 * the the gates will remain closed for that
8322 * engine.
8323 */
8324 if (load_counter ||
8325 (global && other_load_counter)) {
8326 /* Wait until all other functions get
8327 * down.
8328 */
8329 schedule_delayed_work(&bp->sp_rtnl_task,
8330 HZ/10);
8331 return;
8332 } else {
8333 /* If all other functions got down -
8334 * try to bring the chip back to
8335 * normal. In any case it's an exit
8336 * point for a leader.
8337 */
8338 if (bnx2x_leader_reset(bp)) {
8339 bnx2x_recovery_failed(bp);
8340 return;
8341 }
8342
8343 /* If we are here, means that the
8344 * leader has succeeded and doesn't
8345 * want to be a leader any more. Try
8346 * to continue as a none-leader.
8347 */
8348 break;
8349 }
8350 } else { /* non-leader */
8351 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8352 /* Try to get a LEADER_LOCK HW lock as
8353 * long as a former leader may have
8354 * been unloaded by the user or
8355 * released a leadership by another
8356 * reason.
8357 */
8358 if (bnx2x_trylock_leader_lock(bp)) {
8359 /* I'm a leader now! Restart a
8360 * switch case.
8361 */
8362 bp->is_leader = 1;
8363 break;
8364 }
8365
8366 schedule_delayed_work(&bp->sp_rtnl_task,
8367 HZ/10);
8368 return;
8369
8370 } else {
8371 /*
8372 * If there was a global attention, wait
8373 * for it to be cleared.
8374 */
8375 if (bnx2x_reset_is_global(bp)) {
8376 schedule_delayed_work(
8377 &bp->sp_rtnl_task,
8378 HZ/10);
8379 return;
8380 }
8381
8382 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8383 bnx2x_recovery_failed(bp);
8384 else {
8385 bp->recovery_state =
8386 BNX2X_RECOVERY_DONE;
8387 smp_mb();
8388 }
8389
8390 return;
8391 }
8392 }
8393 default:
8394 return;
8395 }
8396 }
8397 }
8398
8399 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8400 * scheduled on a general queue in order to prevent a dead lock.
8401 */
8402 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8403 {
8404 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8405
8406 rtnl_lock();
8407
8408 if (!netif_running(bp->dev))
8409 goto sp_rtnl_exit;
8410
8411 /* if stop on error is defined no recovery flows should be executed */
8412 #ifdef BNX2X_STOP_ON_ERROR
8413 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8414 "so reset not done to allow debug dump,\n"
8415 "you will need to reboot when done\n");
8416 goto sp_rtnl_not_reset;
8417 #endif
8418
8419 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8420 /*
8421 * Clear all pending SP commands as we are going to reset the
8422 * function anyway.
8423 */
8424 bp->sp_rtnl_state = 0;
8425 smp_mb();
8426
8427 bnx2x_parity_recover(bp);
8428
8429 goto sp_rtnl_exit;
8430 }
8431
8432 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8433 /*
8434 * Clear all pending SP commands as we are going to reset the
8435 * function anyway.
8436 */
8437 bp->sp_rtnl_state = 0;
8438 smp_mb();
8439
8440 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8441 bnx2x_nic_load(bp, LOAD_NORMAL);
8442
8443 goto sp_rtnl_exit;
8444 }
8445 #ifdef BNX2X_STOP_ON_ERROR
8446 sp_rtnl_not_reset:
8447 #endif
8448 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8449 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8450
8451 sp_rtnl_exit:
8452 rtnl_unlock();
8453 }
8454
8455 /* end of nic load/unload */
8456
8457 static void bnx2x_period_task(struct work_struct *work)
8458 {
8459 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8460
8461 if (!netif_running(bp->dev))
8462 goto period_task_exit;
8463
8464 if (CHIP_REV_IS_SLOW(bp)) {
8465 BNX2X_ERR("period task called on emulation, ignoring\n");
8466 goto period_task_exit;
8467 }
8468
8469 bnx2x_acquire_phy_lock(bp);
8470 /*
8471 * The barrier is needed to ensure the ordering between the writing to
8472 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8473 * the reading here.
8474 */
8475 smp_mb();
8476 if (bp->port.pmf) {
8477 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8478
8479 /* Re-queue task in 1 sec */
8480 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8481 }
8482
8483 bnx2x_release_phy_lock(bp);
8484 period_task_exit:
8485 return;
8486 }
8487
8488 /*
8489 * Init service functions
8490 */
8491
8492 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8493 {
8494 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8495 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8496 return base + (BP_ABS_FUNC(bp)) * stride;
8497 }
8498
8499 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8500 {
8501 u32 reg = bnx2x_get_pretend_reg(bp);
8502
8503 /* Flush all outstanding writes */
8504 mmiowb();
8505
8506 /* Pretend to be function 0 */
8507 REG_WR(bp, reg, 0);
8508 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8509
8510 /* From now we are in the "like-E1" mode */
8511 bnx2x_int_disable(bp);
8512
8513 /* Flush all outstanding writes */
8514 mmiowb();
8515
8516 /* Restore the original function */
8517 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8518 REG_RD(bp, reg);
8519 }
8520
8521 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8522 {
8523 if (CHIP_IS_E1(bp))
8524 bnx2x_int_disable(bp);
8525 else
8526 bnx2x_undi_int_disable_e1h(bp);
8527 }
8528
8529 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8530 {
8531 u32 val;
8532
8533 /* Check if there is any driver already loaded */
8534 val = REG_RD(bp, MISC_REG_UNPREPARED);
8535 if (val == 0x1) {
8536 /* Check if it is the UNDI driver
8537 * UNDI driver initializes CID offset for normal bell to 0x7
8538 */
8539 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8540 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8541 if (val == 0x7) {
8542 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8543 /* save our pf_num */
8544 int orig_pf_num = bp->pf_num;
8545 int port;
8546 u32 swap_en, swap_val, value;
8547
8548 /* clear the UNDI indication */
8549 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8550
8551 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8552
8553 /* try unload UNDI on port 0 */
8554 bp->pf_num = 0;
8555 bp->fw_seq =
8556 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8557 DRV_MSG_SEQ_NUMBER_MASK);
8558 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8559
8560 /* if UNDI is loaded on the other port */
8561 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8562
8563 /* send "DONE" for previous unload */
8564 bnx2x_fw_command(bp,
8565 DRV_MSG_CODE_UNLOAD_DONE, 0);
8566
8567 /* unload UNDI on port 1 */
8568 bp->pf_num = 1;
8569 bp->fw_seq =
8570 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8571 DRV_MSG_SEQ_NUMBER_MASK);
8572 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8573
8574 bnx2x_fw_command(bp, reset_code, 0);
8575 }
8576
8577 /* now it's safe to release the lock */
8578 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8579
8580 bnx2x_undi_int_disable(bp);
8581 port = BP_PORT(bp);
8582
8583 /* close input traffic and wait for it */
8584 /* Do not rcv packets to BRB */
8585 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8586 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8587 /* Do not direct rcv packets that are not for MCP to
8588 * the BRB */
8589 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8590 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8591 /* clear AEU */
8592 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8593 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8594 msleep(10);
8595
8596 /* save NIG port swap info */
8597 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8598 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8599 /* reset device */
8600 REG_WR(bp,
8601 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8602 0xd3ffffff);
8603
8604 value = 0x1400;
8605 if (CHIP_IS_E3(bp)) {
8606 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8607 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8608 }
8609
8610 REG_WR(bp,
8611 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8612 value);
8613
8614 /* take the NIG out of reset and restore swap values */
8615 REG_WR(bp,
8616 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8617 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8618 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8619 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8620
8621 /* send unload done to the MCP */
8622 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8623
8624 /* restore our func and fw_seq */
8625 bp->pf_num = orig_pf_num;
8626 bp->fw_seq =
8627 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8628 DRV_MSG_SEQ_NUMBER_MASK);
8629 } else
8630 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8631 }
8632 }
8633
8634 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8635 {
8636 u32 val, val2, val3, val4, id;
8637 u16 pmc;
8638
8639 /* Get the chip revision id and number. */
8640 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8641 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8642 id = ((val & 0xffff) << 16);
8643 val = REG_RD(bp, MISC_REG_CHIP_REV);
8644 id |= ((val & 0xf) << 12);
8645 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8646 id |= ((val & 0xff) << 4);
8647 val = REG_RD(bp, MISC_REG_BOND_ID);
8648 id |= (val & 0xf);
8649 bp->common.chip_id = id;
8650
8651 /* Set doorbell size */
8652 bp->db_size = (1 << BNX2X_DB_SHIFT);
8653
8654 if (!CHIP_IS_E1x(bp)) {
8655 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8656 if ((val & 1) == 0)
8657 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8658 else
8659 val = (val >> 1) & 1;
8660 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8661 "2_PORT_MODE");
8662 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8663 CHIP_2_PORT_MODE;
8664
8665 if (CHIP_MODE_IS_4_PORT(bp))
8666 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8667 else
8668 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8669 } else {
8670 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8671 bp->pfid = bp->pf_num; /* 0..7 */
8672 }
8673
8674 bp->link_params.chip_id = bp->common.chip_id;
8675 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8676
8677 val = (REG_RD(bp, 0x2874) & 0x55);
8678 if ((bp->common.chip_id & 0x1) ||
8679 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8680 bp->flags |= ONE_PORT_FLAG;
8681 BNX2X_DEV_INFO("single port device\n");
8682 }
8683
8684 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8685 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8686 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8687 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8688 bp->common.flash_size, bp->common.flash_size);
8689
8690 bnx2x_init_shmem(bp);
8691
8692
8693
8694 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8695 MISC_REG_GENERIC_CR_1 :
8696 MISC_REG_GENERIC_CR_0));
8697
8698 bp->link_params.shmem_base = bp->common.shmem_base;
8699 bp->link_params.shmem2_base = bp->common.shmem2_base;
8700 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8701 bp->common.shmem_base, bp->common.shmem2_base);
8702
8703 if (!bp->common.shmem_base) {
8704 BNX2X_DEV_INFO("MCP not active\n");
8705 bp->flags |= NO_MCP_FLAG;
8706 return;
8707 }
8708
8709 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8710 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8711
8712 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8713 SHARED_HW_CFG_LED_MODE_MASK) >>
8714 SHARED_HW_CFG_LED_MODE_SHIFT);
8715
8716 bp->link_params.feature_config_flags = 0;
8717 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8718 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8719 bp->link_params.feature_config_flags |=
8720 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8721 else
8722 bp->link_params.feature_config_flags &=
8723 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8724
8725 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8726 bp->common.bc_ver = val;
8727 BNX2X_DEV_INFO("bc_ver %X\n", val);
8728 if (val < BNX2X_BC_VER) {
8729 /* for now only warn
8730 * later we might need to enforce this */
8731 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8732 "please upgrade BC\n", BNX2X_BC_VER, val);
8733 }
8734 bp->link_params.feature_config_flags |=
8735 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8736 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8737
8738 bp->link_params.feature_config_flags |=
8739 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8740 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8741
8742 bp->link_params.feature_config_flags |=
8743 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8744 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8745
8746 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8747 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8748
8749 BNX2X_DEV_INFO("%sWoL capable\n",
8750 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8751
8752 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8753 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8754 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8755 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8756
8757 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8758 val, val2, val3, val4);
8759 }
8760
8761 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8762 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8763
8764 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8765 {
8766 int pfid = BP_FUNC(bp);
8767 int vn = BP_E1HVN(bp);
8768 int igu_sb_id;
8769 u32 val;
8770 u8 fid, igu_sb_cnt = 0;
8771
8772 bp->igu_base_sb = 0xff;
8773 if (CHIP_INT_MODE_IS_BC(bp)) {
8774 igu_sb_cnt = bp->igu_sb_cnt;
8775 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8776 FP_SB_MAX_E1x;
8777
8778 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8779 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8780
8781 return;
8782 }
8783
8784 /* IGU in normal mode - read CAM */
8785 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8786 igu_sb_id++) {
8787 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8788 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8789 continue;
8790 fid = IGU_FID(val);
8791 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8792 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8793 continue;
8794 if (IGU_VEC(val) == 0)
8795 /* default status block */
8796 bp->igu_dsb_id = igu_sb_id;
8797 else {
8798 if (bp->igu_base_sb == 0xff)
8799 bp->igu_base_sb = igu_sb_id;
8800 igu_sb_cnt++;
8801 }
8802 }
8803 }
8804
8805 #ifdef CONFIG_PCI_MSI
8806 /*
8807 * It's expected that number of CAM entries for this functions is equal
8808 * to the number evaluated based on the MSI-X table size. We want a
8809 * harsh warning if these values are different!
8810 */
8811 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8812 #endif
8813
8814 if (igu_sb_cnt == 0)
8815 BNX2X_ERR("CAM configuration error\n");
8816 }
8817
8818 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8819 u32 switch_cfg)
8820 {
8821 int cfg_size = 0, idx, port = BP_PORT(bp);
8822
8823 /* Aggregation of supported attributes of all external phys */
8824 bp->port.supported[0] = 0;
8825 bp->port.supported[1] = 0;
8826 switch (bp->link_params.num_phys) {
8827 case 1:
8828 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8829 cfg_size = 1;
8830 break;
8831 case 2:
8832 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8833 cfg_size = 1;
8834 break;
8835 case 3:
8836 if (bp->link_params.multi_phy_config &
8837 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8838 bp->port.supported[1] =
8839 bp->link_params.phy[EXT_PHY1].supported;
8840 bp->port.supported[0] =
8841 bp->link_params.phy[EXT_PHY2].supported;
8842 } else {
8843 bp->port.supported[0] =
8844 bp->link_params.phy[EXT_PHY1].supported;
8845 bp->port.supported[1] =
8846 bp->link_params.phy[EXT_PHY2].supported;
8847 }
8848 cfg_size = 2;
8849 break;
8850 }
8851
8852 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8853 BNX2X_ERR("NVRAM config error. BAD phy config."
8854 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8855 SHMEM_RD(bp,
8856 dev_info.port_hw_config[port].external_phy_config),
8857 SHMEM_RD(bp,
8858 dev_info.port_hw_config[port].external_phy_config2));
8859 return;
8860 }
8861
8862 if (CHIP_IS_E3(bp))
8863 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8864 else {
8865 switch (switch_cfg) {
8866 case SWITCH_CFG_1G:
8867 bp->port.phy_addr = REG_RD(
8868 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8869 break;
8870 case SWITCH_CFG_10G:
8871 bp->port.phy_addr = REG_RD(
8872 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8873 break;
8874 default:
8875 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8876 bp->port.link_config[0]);
8877 return;
8878 }
8879 }
8880 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8881 /* mask what we support according to speed_cap_mask per configuration */
8882 for (idx = 0; idx < cfg_size; idx++) {
8883 if (!(bp->link_params.speed_cap_mask[idx] &
8884 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8885 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8886
8887 if (!(bp->link_params.speed_cap_mask[idx] &
8888 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8889 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8890
8891 if (!(bp->link_params.speed_cap_mask[idx] &
8892 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8893 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8894
8895 if (!(bp->link_params.speed_cap_mask[idx] &
8896 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8897 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8898
8899 if (!(bp->link_params.speed_cap_mask[idx] &
8900 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8901 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8902 SUPPORTED_1000baseT_Full);
8903
8904 if (!(bp->link_params.speed_cap_mask[idx] &
8905 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8906 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8907
8908 if (!(bp->link_params.speed_cap_mask[idx] &
8909 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8910 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8911
8912 }
8913
8914 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8915 bp->port.supported[1]);
8916 }
8917
8918 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8919 {
8920 u32 link_config, idx, cfg_size = 0;
8921 bp->port.advertising[0] = 0;
8922 bp->port.advertising[1] = 0;
8923 switch (bp->link_params.num_phys) {
8924 case 1:
8925 case 2:
8926 cfg_size = 1;
8927 break;
8928 case 3:
8929 cfg_size = 2;
8930 break;
8931 }
8932 for (idx = 0; idx < cfg_size; idx++) {
8933 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8934 link_config = bp->port.link_config[idx];
8935 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8936 case PORT_FEATURE_LINK_SPEED_AUTO:
8937 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8938 bp->link_params.req_line_speed[idx] =
8939 SPEED_AUTO_NEG;
8940 bp->port.advertising[idx] |=
8941 bp->port.supported[idx];
8942 } else {
8943 /* force 10G, no AN */
8944 bp->link_params.req_line_speed[idx] =
8945 SPEED_10000;
8946 bp->port.advertising[idx] |=
8947 (ADVERTISED_10000baseT_Full |
8948 ADVERTISED_FIBRE);
8949 continue;
8950 }
8951 break;
8952
8953 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8954 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8955 bp->link_params.req_line_speed[idx] =
8956 SPEED_10;
8957 bp->port.advertising[idx] |=
8958 (ADVERTISED_10baseT_Full |
8959 ADVERTISED_TP);
8960 } else {
8961 BNX2X_ERR("NVRAM config error. "
8962 "Invalid link_config 0x%x"
8963 " speed_cap_mask 0x%x\n",
8964 link_config,
8965 bp->link_params.speed_cap_mask[idx]);
8966 return;
8967 }
8968 break;
8969
8970 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8971 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8972 bp->link_params.req_line_speed[idx] =
8973 SPEED_10;
8974 bp->link_params.req_duplex[idx] =
8975 DUPLEX_HALF;
8976 bp->port.advertising[idx] |=
8977 (ADVERTISED_10baseT_Half |
8978 ADVERTISED_TP);
8979 } else {
8980 BNX2X_ERR("NVRAM config error. "
8981 "Invalid link_config 0x%x"
8982 " speed_cap_mask 0x%x\n",
8983 link_config,
8984 bp->link_params.speed_cap_mask[idx]);
8985 return;
8986 }
8987 break;
8988
8989 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8990 if (bp->port.supported[idx] &
8991 SUPPORTED_100baseT_Full) {
8992 bp->link_params.req_line_speed[idx] =
8993 SPEED_100;
8994 bp->port.advertising[idx] |=
8995 (ADVERTISED_100baseT_Full |
8996 ADVERTISED_TP);
8997 } else {
8998 BNX2X_ERR("NVRAM config error. "
8999 "Invalid link_config 0x%x"
9000 " speed_cap_mask 0x%x\n",
9001 link_config,
9002 bp->link_params.speed_cap_mask[idx]);
9003 return;
9004 }
9005 break;
9006
9007 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9008 if (bp->port.supported[idx] &
9009 SUPPORTED_100baseT_Half) {
9010 bp->link_params.req_line_speed[idx] =
9011 SPEED_100;
9012 bp->link_params.req_duplex[idx] =
9013 DUPLEX_HALF;
9014 bp->port.advertising[idx] |=
9015 (ADVERTISED_100baseT_Half |
9016 ADVERTISED_TP);
9017 } else {
9018 BNX2X_ERR("NVRAM config error. "
9019 "Invalid link_config 0x%x"
9020 " speed_cap_mask 0x%x\n",
9021 link_config,
9022 bp->link_params.speed_cap_mask[idx]);
9023 return;
9024 }
9025 break;
9026
9027 case PORT_FEATURE_LINK_SPEED_1G:
9028 if (bp->port.supported[idx] &
9029 SUPPORTED_1000baseT_Full) {
9030 bp->link_params.req_line_speed[idx] =
9031 SPEED_1000;
9032 bp->port.advertising[idx] |=
9033 (ADVERTISED_1000baseT_Full |
9034 ADVERTISED_TP);
9035 } else {
9036 BNX2X_ERR("NVRAM config error. "
9037 "Invalid link_config 0x%x"
9038 " speed_cap_mask 0x%x\n",
9039 link_config,
9040 bp->link_params.speed_cap_mask[idx]);
9041 return;
9042 }
9043 break;
9044
9045 case PORT_FEATURE_LINK_SPEED_2_5G:
9046 if (bp->port.supported[idx] &
9047 SUPPORTED_2500baseX_Full) {
9048 bp->link_params.req_line_speed[idx] =
9049 SPEED_2500;
9050 bp->port.advertising[idx] |=
9051 (ADVERTISED_2500baseX_Full |
9052 ADVERTISED_TP);
9053 } else {
9054 BNX2X_ERR("NVRAM config error. "
9055 "Invalid link_config 0x%x"
9056 " speed_cap_mask 0x%x\n",
9057 link_config,
9058 bp->link_params.speed_cap_mask[idx]);
9059 return;
9060 }
9061 break;
9062
9063 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9064 if (bp->port.supported[idx] &
9065 SUPPORTED_10000baseT_Full) {
9066 bp->link_params.req_line_speed[idx] =
9067 SPEED_10000;
9068 bp->port.advertising[idx] |=
9069 (ADVERTISED_10000baseT_Full |
9070 ADVERTISED_FIBRE);
9071 } else {
9072 BNX2X_ERR("NVRAM config error. "
9073 "Invalid link_config 0x%x"
9074 " speed_cap_mask 0x%x\n",
9075 link_config,
9076 bp->link_params.speed_cap_mask[idx]);
9077 return;
9078 }
9079 break;
9080 case PORT_FEATURE_LINK_SPEED_20G:
9081 bp->link_params.req_line_speed[idx] = SPEED_20000;
9082
9083 break;
9084 default:
9085 BNX2X_ERR("NVRAM config error. "
9086 "BAD link speed link_config 0x%x\n",
9087 link_config);
9088 bp->link_params.req_line_speed[idx] =
9089 SPEED_AUTO_NEG;
9090 bp->port.advertising[idx] =
9091 bp->port.supported[idx];
9092 break;
9093 }
9094
9095 bp->link_params.req_flow_ctrl[idx] = (link_config &
9096 PORT_FEATURE_FLOW_CONTROL_MASK);
9097 if ((bp->link_params.req_flow_ctrl[idx] ==
9098 BNX2X_FLOW_CTRL_AUTO) &&
9099 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9100 bp->link_params.req_flow_ctrl[idx] =
9101 BNX2X_FLOW_CTRL_NONE;
9102 }
9103
9104 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9105 " 0x%x advertising 0x%x\n",
9106 bp->link_params.req_line_speed[idx],
9107 bp->link_params.req_duplex[idx],
9108 bp->link_params.req_flow_ctrl[idx],
9109 bp->port.advertising[idx]);
9110 }
9111 }
9112
9113 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9114 {
9115 mac_hi = cpu_to_be16(mac_hi);
9116 mac_lo = cpu_to_be32(mac_lo);
9117 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9118 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9119 }
9120
9121 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9122 {
9123 int port = BP_PORT(bp);
9124 u32 config;
9125 u32 ext_phy_type, ext_phy_config;
9126
9127 bp->link_params.bp = bp;
9128 bp->link_params.port = port;
9129
9130 bp->link_params.lane_config =
9131 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9132
9133 bp->link_params.speed_cap_mask[0] =
9134 SHMEM_RD(bp,
9135 dev_info.port_hw_config[port].speed_capability_mask);
9136 bp->link_params.speed_cap_mask[1] =
9137 SHMEM_RD(bp,
9138 dev_info.port_hw_config[port].speed_capability_mask2);
9139 bp->port.link_config[0] =
9140 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9141
9142 bp->port.link_config[1] =
9143 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9144
9145 bp->link_params.multi_phy_config =
9146 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9147 /* If the device is capable of WoL, set the default state according
9148 * to the HW
9149 */
9150 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9151 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9152 (config & PORT_FEATURE_WOL_ENABLED));
9153
9154 BNX2X_DEV_INFO("lane_config 0x%08x "
9155 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9156 bp->link_params.lane_config,
9157 bp->link_params.speed_cap_mask[0],
9158 bp->port.link_config[0]);
9159
9160 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9161 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9162 bnx2x_phy_probe(&bp->link_params);
9163 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9164
9165 bnx2x_link_settings_requested(bp);
9166
9167 /*
9168 * If connected directly, work with the internal PHY, otherwise, work
9169 * with the external PHY
9170 */
9171 ext_phy_config =
9172 SHMEM_RD(bp,
9173 dev_info.port_hw_config[port].external_phy_config);
9174 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9175 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9176 bp->mdio.prtad = bp->port.phy_addr;
9177
9178 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9179 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9180 bp->mdio.prtad =
9181 XGXS_EXT_PHY_ADDR(ext_phy_config);
9182
9183 /*
9184 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9185 * In MF mode, it is set to cover self test cases
9186 */
9187 if (IS_MF(bp))
9188 bp->port.need_hw_lock = 1;
9189 else
9190 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9191 bp->common.shmem_base,
9192 bp->common.shmem2_base);
9193 }
9194
9195 #ifdef BCM_CNIC
9196 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9197 {
9198 int port = BP_PORT(bp);
9199 int func = BP_ABS_FUNC(bp);
9200
9201 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9202 drv_lic_key[port].max_iscsi_conn);
9203 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9204 drv_lic_key[port].max_fcoe_conn);
9205
9206 /* Get the number of maximum allowed iSCSI and FCoE connections */
9207 bp->cnic_eth_dev.max_iscsi_conn =
9208 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9209 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9210
9211 bp->cnic_eth_dev.max_fcoe_conn =
9212 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9213 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9214
9215 /* Read the WWN: */
9216 if (!IS_MF(bp)) {
9217 /* Port info */
9218 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9219 SHMEM_RD(bp,
9220 dev_info.port_hw_config[port].
9221 fcoe_wwn_port_name_upper);
9222 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9223 SHMEM_RD(bp,
9224 dev_info.port_hw_config[port].
9225 fcoe_wwn_port_name_lower);
9226
9227 /* Node info */
9228 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9229 SHMEM_RD(bp,
9230 dev_info.port_hw_config[port].
9231 fcoe_wwn_node_name_upper);
9232 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9233 SHMEM_RD(bp,
9234 dev_info.port_hw_config[port].
9235 fcoe_wwn_node_name_lower);
9236 } else if (!IS_MF_SD(bp)) {
9237 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9238
9239 /*
9240 * Read the WWN info only if the FCoE feature is enabled for
9241 * this function.
9242 */
9243 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9244 /* Port info */
9245 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9246 MF_CFG_RD(bp, func_ext_config[func].
9247 fcoe_wwn_port_name_upper);
9248 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9249 MF_CFG_RD(bp, func_ext_config[func].
9250 fcoe_wwn_port_name_lower);
9251
9252 /* Node info */
9253 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9254 MF_CFG_RD(bp, func_ext_config[func].
9255 fcoe_wwn_node_name_upper);
9256 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9257 MF_CFG_RD(bp, func_ext_config[func].
9258 fcoe_wwn_node_name_lower);
9259 }
9260 }
9261
9262 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9263 bp->cnic_eth_dev.max_iscsi_conn,
9264 bp->cnic_eth_dev.max_fcoe_conn);
9265
9266 /*
9267 * If maximum allowed number of connections is zero -
9268 * disable the feature.
9269 */
9270 if (!bp->cnic_eth_dev.max_iscsi_conn)
9271 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9272
9273 if (!bp->cnic_eth_dev.max_fcoe_conn)
9274 bp->flags |= NO_FCOE_FLAG;
9275 }
9276 #endif
9277
9278 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9279 {
9280 u32 val, val2;
9281 int func = BP_ABS_FUNC(bp);
9282 int port = BP_PORT(bp);
9283 #ifdef BCM_CNIC
9284 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9285 u8 *fip_mac = bp->fip_mac;
9286 #endif
9287
9288 /* Zero primary MAC configuration */
9289 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9290
9291 if (BP_NOMCP(bp)) {
9292 BNX2X_ERROR("warning: random MAC workaround active\n");
9293 random_ether_addr(bp->dev->dev_addr);
9294 } else if (IS_MF(bp)) {
9295 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9296 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9297 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9298 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9299 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9300
9301 #ifdef BCM_CNIC
9302 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9303 * FCoE MAC then the appropriate feature should be disabled.
9304 */
9305 if (IS_MF_SI(bp)) {
9306 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9307 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9308 val2 = MF_CFG_RD(bp, func_ext_config[func].
9309 iscsi_mac_addr_upper);
9310 val = MF_CFG_RD(bp, func_ext_config[func].
9311 iscsi_mac_addr_lower);
9312 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9313 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9314 iscsi_mac);
9315 } else
9316 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9317
9318 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9319 val2 = MF_CFG_RD(bp, func_ext_config[func].
9320 fcoe_mac_addr_upper);
9321 val = MF_CFG_RD(bp, func_ext_config[func].
9322 fcoe_mac_addr_lower);
9323 bnx2x_set_mac_buf(fip_mac, val, val2);
9324 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n",
9325 fip_mac);
9326
9327 } else
9328 bp->flags |= NO_FCOE_FLAG;
9329 }
9330 #endif
9331 } else {
9332 /* in SF read MACs from port configuration */
9333 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9334 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9335 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9336
9337 #ifdef BCM_CNIC
9338 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9339 iscsi_mac_upper);
9340 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9341 iscsi_mac_lower);
9342 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9343
9344 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9345 fcoe_fip_mac_upper);
9346 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9347 fcoe_fip_mac_lower);
9348 bnx2x_set_mac_buf(fip_mac, val, val2);
9349 #endif
9350 }
9351
9352 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9353 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9354
9355 #ifdef BCM_CNIC
9356 /* Set the FCoE MAC in MF_SD mode */
9357 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9358 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9359
9360 /* Disable iSCSI if MAC configuration is
9361 * invalid.
9362 */
9363 if (!is_valid_ether_addr(iscsi_mac)) {
9364 bp->flags |= NO_ISCSI_FLAG;
9365 memset(iscsi_mac, 0, ETH_ALEN);
9366 }
9367
9368 /* Disable FCoE if MAC configuration is
9369 * invalid.
9370 */
9371 if (!is_valid_ether_addr(fip_mac)) {
9372 bp->flags |= NO_FCOE_FLAG;
9373 memset(bp->fip_mac, 0, ETH_ALEN);
9374 }
9375 #endif
9376
9377 if (!is_valid_ether_addr(bp->dev->dev_addr))
9378 dev_err(&bp->pdev->dev,
9379 "bad Ethernet MAC address configuration: "
9380 "%pM, change it manually before bringing up "
9381 "the appropriate network interface\n",
9382 bp->dev->dev_addr);
9383 }
9384
9385 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9386 {
9387 int /*abs*/func = BP_ABS_FUNC(bp);
9388 int vn;
9389 u32 val = 0;
9390 int rc = 0;
9391
9392 bnx2x_get_common_hwinfo(bp);
9393
9394 /*
9395 * initialize IGU parameters
9396 */
9397 if (CHIP_IS_E1x(bp)) {
9398 bp->common.int_block = INT_BLOCK_HC;
9399
9400 bp->igu_dsb_id = DEF_SB_IGU_ID;
9401 bp->igu_base_sb = 0;
9402 } else {
9403 bp->common.int_block = INT_BLOCK_IGU;
9404 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9405
9406 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9407 int tout = 5000;
9408
9409 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9410
9411 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9412 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9413 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9414
9415 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9416 tout--;
9417 usleep_range(1000, 1000);
9418 }
9419
9420 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9421 dev_err(&bp->pdev->dev,
9422 "FORCING Normal Mode failed!!!\n");
9423 return -EPERM;
9424 }
9425 }
9426
9427 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9428 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9429 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9430 } else
9431 BNX2X_DEV_INFO("IGU Normal Mode\n");
9432
9433 bnx2x_get_igu_cam_info(bp);
9434
9435 }
9436
9437 /*
9438 * set base FW non-default (fast path) status block id, this value is
9439 * used to initialize the fw_sb_id saved on the fp/queue structure to
9440 * determine the id used by the FW.
9441 */
9442 if (CHIP_IS_E1x(bp))
9443 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9444 else /*
9445 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9446 * the same queue are indicated on the same IGU SB). So we prefer
9447 * FW and IGU SBs to be the same value.
9448 */
9449 bp->base_fw_ndsb = bp->igu_base_sb;
9450
9451 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9452 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9453 bp->igu_sb_cnt, bp->base_fw_ndsb);
9454
9455 /*
9456 * Initialize MF configuration
9457 */
9458
9459 bp->mf_ov = 0;
9460 bp->mf_mode = 0;
9461 vn = BP_E1HVN(bp);
9462
9463 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9464 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9465 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9466 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9467
9468 if (SHMEM2_HAS(bp, mf_cfg_addr))
9469 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9470 else
9471 bp->common.mf_cfg_base = bp->common.shmem_base +
9472 offsetof(struct shmem_region, func_mb) +
9473 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9474 /*
9475 * get mf configuration:
9476 * 1. existence of MF configuration
9477 * 2. MAC address must be legal (check only upper bytes)
9478 * for Switch-Independent mode;
9479 * OVLAN must be legal for Switch-Dependent mode
9480 * 3. SF_MODE configures specific MF mode
9481 */
9482 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9483 /* get mf configuration */
9484 val = SHMEM_RD(bp,
9485 dev_info.shared_feature_config.config);
9486 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9487
9488 switch (val) {
9489 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9490 val = MF_CFG_RD(bp, func_mf_config[func].
9491 mac_upper);
9492 /* check for legal mac (upper bytes)*/
9493 if (val != 0xffff) {
9494 bp->mf_mode = MULTI_FUNCTION_SI;
9495 bp->mf_config[vn] = MF_CFG_RD(bp,
9496 func_mf_config[func].config);
9497 } else
9498 BNX2X_DEV_INFO("illegal MAC address "
9499 "for SI\n");
9500 break;
9501 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9502 /* get OV configuration */
9503 val = MF_CFG_RD(bp,
9504 func_mf_config[FUNC_0].e1hov_tag);
9505 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9506
9507 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9508 bp->mf_mode = MULTI_FUNCTION_SD;
9509 bp->mf_config[vn] = MF_CFG_RD(bp,
9510 func_mf_config[func].config);
9511 } else
9512 BNX2X_DEV_INFO("illegal OV for SD\n");
9513 break;
9514 default:
9515 /* Unknown configuration: reset mf_config */
9516 bp->mf_config[vn] = 0;
9517 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9518 }
9519 }
9520
9521 BNX2X_DEV_INFO("%s function mode\n",
9522 IS_MF(bp) ? "multi" : "single");
9523
9524 switch (bp->mf_mode) {
9525 case MULTI_FUNCTION_SD:
9526 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9527 FUNC_MF_CFG_E1HOV_TAG_MASK;
9528 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9529 bp->mf_ov = val;
9530 bp->path_has_ovlan = true;
9531
9532 BNX2X_DEV_INFO("MF OV for func %d is %d "
9533 "(0x%04x)\n", func, bp->mf_ov,
9534 bp->mf_ov);
9535 } else {
9536 dev_err(&bp->pdev->dev,
9537 "No valid MF OV for func %d, "
9538 "aborting\n", func);
9539 return -EPERM;
9540 }
9541 break;
9542 case MULTI_FUNCTION_SI:
9543 BNX2X_DEV_INFO("func %d is in MF "
9544 "switch-independent mode\n", func);
9545 break;
9546 default:
9547 if (vn) {
9548 dev_err(&bp->pdev->dev,
9549 "VN %d is in a single function mode, "
9550 "aborting\n", vn);
9551 return -EPERM;
9552 }
9553 break;
9554 }
9555
9556 /* check if other port on the path needs ovlan:
9557 * Since MF configuration is shared between ports
9558 * Possible mixed modes are only
9559 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9560 */
9561 if (CHIP_MODE_IS_4_PORT(bp) &&
9562 !bp->path_has_ovlan &&
9563 !IS_MF(bp) &&
9564 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9565 u8 other_port = !BP_PORT(bp);
9566 u8 other_func = BP_PATH(bp) + 2*other_port;
9567 val = MF_CFG_RD(bp,
9568 func_mf_config[other_func].e1hov_tag);
9569 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9570 bp->path_has_ovlan = true;
9571 }
9572 }
9573
9574 /* adjust igu_sb_cnt to MF for E1x */
9575 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9576 bp->igu_sb_cnt /= E1HVN_MAX;
9577
9578 /* port info */
9579 bnx2x_get_port_hwinfo(bp);
9580
9581 if (!BP_NOMCP(bp)) {
9582 bp->fw_seq =
9583 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9584 DRV_MSG_SEQ_NUMBER_MASK);
9585 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9586 }
9587
9588 /* Get MAC addresses */
9589 bnx2x_get_mac_hwinfo(bp);
9590
9591 #ifdef BCM_CNIC
9592 bnx2x_get_cnic_info(bp);
9593 #endif
9594
9595 /* Get current FW pulse sequence */
9596 if (!BP_NOMCP(bp)) {
9597 int mb_idx = BP_FW_MB_IDX(bp);
9598
9599 bp->fw_drv_pulse_wr_seq =
9600 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9601 DRV_PULSE_SEQ_MASK);
9602 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9603 }
9604
9605 return rc;
9606 }
9607
9608 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9609 {
9610 int cnt, i, block_end, rodi;
9611 char vpd_data[BNX2X_VPD_LEN+1];
9612 char str_id_reg[VENDOR_ID_LEN+1];
9613 char str_id_cap[VENDOR_ID_LEN+1];
9614 u8 len;
9615
9616 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9617 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9618
9619 if (cnt < BNX2X_VPD_LEN)
9620 goto out_not_found;
9621
9622 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9623 PCI_VPD_LRDT_RO_DATA);
9624 if (i < 0)
9625 goto out_not_found;
9626
9627
9628 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9629 pci_vpd_lrdt_size(&vpd_data[i]);
9630
9631 i += PCI_VPD_LRDT_TAG_SIZE;
9632
9633 if (block_end > BNX2X_VPD_LEN)
9634 goto out_not_found;
9635
9636 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9637 PCI_VPD_RO_KEYWORD_MFR_ID);
9638 if (rodi < 0)
9639 goto out_not_found;
9640
9641 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9642
9643 if (len != VENDOR_ID_LEN)
9644 goto out_not_found;
9645
9646 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9647
9648 /* vendor specific info */
9649 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9650 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9651 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9652 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9653
9654 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9655 PCI_VPD_RO_KEYWORD_VENDOR0);
9656 if (rodi >= 0) {
9657 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9658
9659 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9660
9661 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9662 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9663 bp->fw_ver[len] = ' ';
9664 }
9665 }
9666 return;
9667 }
9668 out_not_found:
9669 return;
9670 }
9671
9672 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9673 {
9674 u32 flags = 0;
9675
9676 if (CHIP_REV_IS_FPGA(bp))
9677 SET_FLAGS(flags, MODE_FPGA);
9678 else if (CHIP_REV_IS_EMUL(bp))
9679 SET_FLAGS(flags, MODE_EMUL);
9680 else
9681 SET_FLAGS(flags, MODE_ASIC);
9682
9683 if (CHIP_MODE_IS_4_PORT(bp))
9684 SET_FLAGS(flags, MODE_PORT4);
9685 else
9686 SET_FLAGS(flags, MODE_PORT2);
9687
9688 if (CHIP_IS_E2(bp))
9689 SET_FLAGS(flags, MODE_E2);
9690 else if (CHIP_IS_E3(bp)) {
9691 SET_FLAGS(flags, MODE_E3);
9692 if (CHIP_REV(bp) == CHIP_REV_Ax)
9693 SET_FLAGS(flags, MODE_E3_A0);
9694 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9695 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9696 }
9697
9698 if (IS_MF(bp)) {
9699 SET_FLAGS(flags, MODE_MF);
9700 switch (bp->mf_mode) {
9701 case MULTI_FUNCTION_SD:
9702 SET_FLAGS(flags, MODE_MF_SD);
9703 break;
9704 case MULTI_FUNCTION_SI:
9705 SET_FLAGS(flags, MODE_MF_SI);
9706 break;
9707 }
9708 } else
9709 SET_FLAGS(flags, MODE_SF);
9710
9711 #if defined(__LITTLE_ENDIAN)
9712 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9713 #else /*(__BIG_ENDIAN)*/
9714 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9715 #endif
9716 INIT_MODE_FLAGS(bp) = flags;
9717 }
9718
9719 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9720 {
9721 int func;
9722 int timer_interval;
9723 int rc;
9724
9725 mutex_init(&bp->port.phy_mutex);
9726 mutex_init(&bp->fw_mb_mutex);
9727 spin_lock_init(&bp->stats_lock);
9728 #ifdef BCM_CNIC
9729 mutex_init(&bp->cnic_mutex);
9730 #endif
9731
9732 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9733 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9734 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9735 rc = bnx2x_get_hwinfo(bp);
9736 if (rc)
9737 return rc;
9738
9739 bnx2x_set_modes_bitmap(bp);
9740
9741 rc = bnx2x_alloc_mem_bp(bp);
9742 if (rc)
9743 return rc;
9744
9745 bnx2x_read_fwinfo(bp);
9746
9747 func = BP_FUNC(bp);
9748
9749 /* need to reset chip if undi was active */
9750 if (!BP_NOMCP(bp))
9751 bnx2x_undi_unload(bp);
9752
9753 if (CHIP_REV_IS_FPGA(bp))
9754 dev_err(&bp->pdev->dev, "FPGA detected\n");
9755
9756 if (BP_NOMCP(bp) && (func == 0))
9757 dev_err(&bp->pdev->dev, "MCP disabled, "
9758 "must load devices in order!\n");
9759
9760 bp->multi_mode = multi_mode;
9761
9762 /* Set TPA flags */
9763 if (disable_tpa) {
9764 bp->flags &= ~TPA_ENABLE_FLAG;
9765 bp->dev->features &= ~NETIF_F_LRO;
9766 } else {
9767 bp->flags |= TPA_ENABLE_FLAG;
9768 bp->dev->features |= NETIF_F_LRO;
9769 }
9770 bp->disable_tpa = disable_tpa;
9771
9772 if (CHIP_IS_E1(bp))
9773 bp->dropless_fc = 0;
9774 else
9775 bp->dropless_fc = dropless_fc;
9776
9777 bp->mrrs = mrrs;
9778
9779 bp->tx_ring_size = MAX_TX_AVAIL;
9780
9781 /* make sure that the numbers are in the right granularity */
9782 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9783 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9784
9785 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9786 bp->current_interval = (poll ? poll : timer_interval);
9787
9788 init_timer(&bp->timer);
9789 bp->timer.expires = jiffies + bp->current_interval;
9790 bp->timer.data = (unsigned long) bp;
9791 bp->timer.function = bnx2x_timer;
9792
9793 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9794 bnx2x_dcbx_init_params(bp);
9795
9796 #ifdef BCM_CNIC
9797 if (CHIP_IS_E1x(bp))
9798 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9799 else
9800 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9801 #endif
9802
9803 /* multiple tx priority */
9804 if (CHIP_IS_E1x(bp))
9805 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9806 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9807 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9808 if (CHIP_IS_E3B0(bp))
9809 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9810
9811 return rc;
9812 }
9813
9814
9815 /****************************************************************************
9816 * General service functions
9817 ****************************************************************************/
9818
9819 /*
9820 * net_device service functions
9821 */
9822
9823 /* called with rtnl_lock */
9824 static int bnx2x_open(struct net_device *dev)
9825 {
9826 struct bnx2x *bp = netdev_priv(dev);
9827 bool global = false;
9828 int other_engine = BP_PATH(bp) ? 0 : 1;
9829 u32 other_load_counter, load_counter;
9830
9831 netif_carrier_off(dev);
9832
9833 bnx2x_set_power_state(bp, PCI_D0);
9834
9835 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9836 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9837
9838 /*
9839 * If parity had happen during the unload, then attentions
9840 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9841 * want the first function loaded on the current engine to
9842 * complete the recovery.
9843 */
9844 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9845 bnx2x_chk_parity_attn(bp, &global, true))
9846 do {
9847 /*
9848 * If there are attentions and they are in a global
9849 * blocks, set the GLOBAL_RESET bit regardless whether
9850 * it will be this function that will complete the
9851 * recovery or not.
9852 */
9853 if (global)
9854 bnx2x_set_reset_global(bp);
9855
9856 /*
9857 * Only the first function on the current engine should
9858 * try to recover in open. In case of attentions in
9859 * global blocks only the first in the chip should try
9860 * to recover.
9861 */
9862 if ((!load_counter &&
9863 (!global || !other_load_counter)) &&
9864 bnx2x_trylock_leader_lock(bp) &&
9865 !bnx2x_leader_reset(bp)) {
9866 netdev_info(bp->dev, "Recovered in open\n");
9867 break;
9868 }
9869
9870 /* recovery has failed... */
9871 bnx2x_set_power_state(bp, PCI_D3hot);
9872 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9873
9874 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9875 " completed yet. Try again later. If u still see this"
9876 " message after a few retries then power cycle is"
9877 " required.\n");
9878
9879 return -EAGAIN;
9880 } while (0);
9881
9882 bp->recovery_state = BNX2X_RECOVERY_DONE;
9883 return bnx2x_nic_load(bp, LOAD_OPEN);
9884 }
9885
9886 /* called with rtnl_lock */
9887 static int bnx2x_close(struct net_device *dev)
9888 {
9889 struct bnx2x *bp = netdev_priv(dev);
9890
9891 /* Unload the driver, release IRQs */
9892 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9893
9894 /* Power off */
9895 bnx2x_set_power_state(bp, PCI_D3hot);
9896
9897 return 0;
9898 }
9899
9900 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9901 struct bnx2x_mcast_ramrod_params *p)
9902 {
9903 int mc_count = netdev_mc_count(bp->dev);
9904 struct bnx2x_mcast_list_elem *mc_mac =
9905 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9906 struct netdev_hw_addr *ha;
9907
9908 if (!mc_mac)
9909 return -ENOMEM;
9910
9911 INIT_LIST_HEAD(&p->mcast_list);
9912
9913 netdev_for_each_mc_addr(ha, bp->dev) {
9914 mc_mac->mac = bnx2x_mc_addr(ha);
9915 list_add_tail(&mc_mac->link, &p->mcast_list);
9916 mc_mac++;
9917 }
9918
9919 p->mcast_list_len = mc_count;
9920
9921 return 0;
9922 }
9923
9924 static inline void bnx2x_free_mcast_macs_list(
9925 struct bnx2x_mcast_ramrod_params *p)
9926 {
9927 struct bnx2x_mcast_list_elem *mc_mac =
9928 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9929 link);
9930
9931 WARN_ON(!mc_mac);
9932 kfree(mc_mac);
9933 }
9934
9935 /**
9936 * bnx2x_set_uc_list - configure a new unicast MACs list.
9937 *
9938 * @bp: driver handle
9939 *
9940 * We will use zero (0) as a MAC type for these MACs.
9941 */
9942 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9943 {
9944 int rc;
9945 struct net_device *dev = bp->dev;
9946 struct netdev_hw_addr *ha;
9947 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9948 unsigned long ramrod_flags = 0;
9949
9950 /* First schedule a cleanup up of old configuration */
9951 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9952 if (rc < 0) {
9953 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9954 return rc;
9955 }
9956
9957 netdev_for_each_uc_addr(ha, dev) {
9958 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9959 BNX2X_UC_LIST_MAC, &ramrod_flags);
9960 if (rc < 0) {
9961 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9962 rc);
9963 return rc;
9964 }
9965 }
9966
9967 /* Execute the pending commands */
9968 __set_bit(RAMROD_CONT, &ramrod_flags);
9969 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9970 BNX2X_UC_LIST_MAC, &ramrod_flags);
9971 }
9972
9973 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9974 {
9975 struct net_device *dev = bp->dev;
9976 struct bnx2x_mcast_ramrod_params rparam = {0};
9977 int rc = 0;
9978
9979 rparam.mcast_obj = &bp->mcast_obj;
9980
9981 /* first, clear all configured multicast MACs */
9982 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9983 if (rc < 0) {
9984 BNX2X_ERR("Failed to clear multicast "
9985 "configuration: %d\n", rc);
9986 return rc;
9987 }
9988
9989 /* then, configure a new MACs list */
9990 if (netdev_mc_count(dev)) {
9991 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9992 if (rc) {
9993 BNX2X_ERR("Failed to create multicast MACs "
9994 "list: %d\n", rc);
9995 return rc;
9996 }
9997
9998 /* Now add the new MACs */
9999 rc = bnx2x_config_mcast(bp, &rparam,
10000 BNX2X_MCAST_CMD_ADD);
10001 if (rc < 0)
10002 BNX2X_ERR("Failed to set a new multicast "
10003 "configuration: %d\n", rc);
10004
10005 bnx2x_free_mcast_macs_list(&rparam);
10006 }
10007
10008 return rc;
10009 }
10010
10011
10012 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10013 void bnx2x_set_rx_mode(struct net_device *dev)
10014 {
10015 struct bnx2x *bp = netdev_priv(dev);
10016 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10017
10018 if (bp->state != BNX2X_STATE_OPEN) {
10019 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10020 return;
10021 }
10022
10023 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10024
10025 if (dev->flags & IFF_PROMISC)
10026 rx_mode = BNX2X_RX_MODE_PROMISC;
10027 else if ((dev->flags & IFF_ALLMULTI) ||
10028 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10029 CHIP_IS_E1(bp)))
10030 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10031 else {
10032 /* some multicasts */
10033 if (bnx2x_set_mc_list(bp) < 0)
10034 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10035
10036 if (bnx2x_set_uc_list(bp) < 0)
10037 rx_mode = BNX2X_RX_MODE_PROMISC;
10038 }
10039
10040 bp->rx_mode = rx_mode;
10041
10042 /* Schedule the rx_mode command */
10043 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10044 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10045 return;
10046 }
10047
10048 bnx2x_set_storm_rx_mode(bp);
10049 }
10050
10051 /* called with rtnl_lock */
10052 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10053 int devad, u16 addr)
10054 {
10055 struct bnx2x *bp = netdev_priv(netdev);
10056 u16 value;
10057 int rc;
10058
10059 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10060 prtad, devad, addr);
10061
10062 /* The HW expects different devad if CL22 is used */
10063 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10064
10065 bnx2x_acquire_phy_lock(bp);
10066 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10067 bnx2x_release_phy_lock(bp);
10068 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10069
10070 if (!rc)
10071 rc = value;
10072 return rc;
10073 }
10074
10075 /* called with rtnl_lock */
10076 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10077 u16 addr, u16 value)
10078 {
10079 struct bnx2x *bp = netdev_priv(netdev);
10080 int rc;
10081
10082 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10083 " value 0x%x\n", prtad, devad, addr, value);
10084
10085 /* The HW expects different devad if CL22 is used */
10086 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10087
10088 bnx2x_acquire_phy_lock(bp);
10089 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10090 bnx2x_release_phy_lock(bp);
10091 return rc;
10092 }
10093
10094 /* called with rtnl_lock */
10095 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10096 {
10097 struct bnx2x *bp = netdev_priv(dev);
10098 struct mii_ioctl_data *mdio = if_mii(ifr);
10099
10100 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10101 mdio->phy_id, mdio->reg_num, mdio->val_in);
10102
10103 if (!netif_running(dev))
10104 return -EAGAIN;
10105
10106 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10107 }
10108
10109 #ifdef CONFIG_NET_POLL_CONTROLLER
10110 static void poll_bnx2x(struct net_device *dev)
10111 {
10112 struct bnx2x *bp = netdev_priv(dev);
10113
10114 disable_irq(bp->pdev->irq);
10115 bnx2x_interrupt(bp->pdev->irq, dev);
10116 enable_irq(bp->pdev->irq);
10117 }
10118 #endif
10119
10120 static const struct net_device_ops bnx2x_netdev_ops = {
10121 .ndo_open = bnx2x_open,
10122 .ndo_stop = bnx2x_close,
10123 .ndo_start_xmit = bnx2x_start_xmit,
10124 .ndo_select_queue = bnx2x_select_queue,
10125 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10126 .ndo_set_mac_address = bnx2x_change_mac_addr,
10127 .ndo_validate_addr = eth_validate_addr,
10128 .ndo_do_ioctl = bnx2x_ioctl,
10129 .ndo_change_mtu = bnx2x_change_mtu,
10130 .ndo_fix_features = bnx2x_fix_features,
10131 .ndo_set_features = bnx2x_set_features,
10132 .ndo_tx_timeout = bnx2x_tx_timeout,
10133 #ifdef CONFIG_NET_POLL_CONTROLLER
10134 .ndo_poll_controller = poll_bnx2x,
10135 #endif
10136 .ndo_setup_tc = bnx2x_setup_tc,
10137
10138 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10139 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10140 #endif
10141 };
10142
10143 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10144 {
10145 struct device *dev = &bp->pdev->dev;
10146
10147 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10148 bp->flags |= USING_DAC_FLAG;
10149 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10150 dev_err(dev, "dma_set_coherent_mask failed, "
10151 "aborting\n");
10152 return -EIO;
10153 }
10154 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10155 dev_err(dev, "System does not support DMA, aborting\n");
10156 return -EIO;
10157 }
10158
10159 return 0;
10160 }
10161
10162 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10163 struct net_device *dev,
10164 unsigned long board_type)
10165 {
10166 struct bnx2x *bp;
10167 int rc;
10168
10169 SET_NETDEV_DEV(dev, &pdev->dev);
10170 bp = netdev_priv(dev);
10171
10172 bp->dev = dev;
10173 bp->pdev = pdev;
10174 bp->flags = 0;
10175 bp->pf_num = PCI_FUNC(pdev->devfn);
10176
10177 rc = pci_enable_device(pdev);
10178 if (rc) {
10179 dev_err(&bp->pdev->dev,
10180 "Cannot enable PCI device, aborting\n");
10181 goto err_out;
10182 }
10183
10184 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10185 dev_err(&bp->pdev->dev,
10186 "Cannot find PCI device base address, aborting\n");
10187 rc = -ENODEV;
10188 goto err_out_disable;
10189 }
10190
10191 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10192 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10193 " base address, aborting\n");
10194 rc = -ENODEV;
10195 goto err_out_disable;
10196 }
10197
10198 if (atomic_read(&pdev->enable_cnt) == 1) {
10199 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10200 if (rc) {
10201 dev_err(&bp->pdev->dev,
10202 "Cannot obtain PCI resources, aborting\n");
10203 goto err_out_disable;
10204 }
10205
10206 pci_set_master(pdev);
10207 pci_save_state(pdev);
10208 }
10209
10210 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10211 if (bp->pm_cap == 0) {
10212 dev_err(&bp->pdev->dev,
10213 "Cannot find power management capability, aborting\n");
10214 rc = -EIO;
10215 goto err_out_release;
10216 }
10217
10218 if (!pci_is_pcie(pdev)) {
10219 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10220 rc = -EIO;
10221 goto err_out_release;
10222 }
10223
10224 rc = bnx2x_set_coherency_mask(bp);
10225 if (rc)
10226 goto err_out_release;
10227
10228 dev->mem_start = pci_resource_start(pdev, 0);
10229 dev->base_addr = dev->mem_start;
10230 dev->mem_end = pci_resource_end(pdev, 0);
10231
10232 dev->irq = pdev->irq;
10233
10234 bp->regview = pci_ioremap_bar(pdev, 0);
10235 if (!bp->regview) {
10236 dev_err(&bp->pdev->dev,
10237 "Cannot map register space, aborting\n");
10238 rc = -ENOMEM;
10239 goto err_out_release;
10240 }
10241
10242 bnx2x_set_power_state(bp, PCI_D0);
10243
10244 /* clean indirect addresses */
10245 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10246 PCICFG_VENDOR_ID_OFFSET);
10247 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10248 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10249 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10250 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
10251
10252 /*
10253 * Enable internal target-read (in case we are probed after PF FLR).
10254 * Must be done prior to any BAR read access. Only for 57712 and up
10255 */
10256 if (board_type != BCM57710 &&
10257 board_type != BCM57711 &&
10258 board_type != BCM57711E)
10259 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10260
10261 /* Reset the load counter */
10262 bnx2x_clear_load_cnt(bp);
10263
10264 dev->watchdog_timeo = TX_TIMEOUT;
10265
10266 dev->netdev_ops = &bnx2x_netdev_ops;
10267 bnx2x_set_ethtool_ops(dev);
10268
10269 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10270 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10271 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10272
10273 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10274 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10275
10276 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10277 if (bp->flags & USING_DAC_FLAG)
10278 dev->features |= NETIF_F_HIGHDMA;
10279
10280 /* Add Loopback capability to the device */
10281 dev->hw_features |= NETIF_F_LOOPBACK;
10282
10283 #ifdef BCM_DCBNL
10284 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10285 #endif
10286
10287 /* get_port_hwinfo() will set prtad and mmds properly */
10288 bp->mdio.prtad = MDIO_PRTAD_NONE;
10289 bp->mdio.mmds = 0;
10290 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10291 bp->mdio.dev = dev;
10292 bp->mdio.mdio_read = bnx2x_mdio_read;
10293 bp->mdio.mdio_write = bnx2x_mdio_write;
10294
10295 return 0;
10296
10297 err_out_release:
10298 if (atomic_read(&pdev->enable_cnt) == 1)
10299 pci_release_regions(pdev);
10300
10301 err_out_disable:
10302 pci_disable_device(pdev);
10303 pci_set_drvdata(pdev, NULL);
10304
10305 err_out:
10306 return rc;
10307 }
10308
10309 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10310 int *width, int *speed)
10311 {
10312 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10313
10314 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10315
10316 /* return value of 1=2.5GHz 2=5GHz */
10317 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10318 }
10319
10320 static int bnx2x_check_firmware(struct bnx2x *bp)
10321 {
10322 const struct firmware *firmware = bp->firmware;
10323 struct bnx2x_fw_file_hdr *fw_hdr;
10324 struct bnx2x_fw_file_section *sections;
10325 u32 offset, len, num_ops;
10326 u16 *ops_offsets;
10327 int i;
10328 const u8 *fw_ver;
10329
10330 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10331 return -EINVAL;
10332
10333 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10334 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10335
10336 /* Make sure none of the offsets and sizes make us read beyond
10337 * the end of the firmware data */
10338 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10339 offset = be32_to_cpu(sections[i].offset);
10340 len = be32_to_cpu(sections[i].len);
10341 if (offset + len > firmware->size) {
10342 dev_err(&bp->pdev->dev,
10343 "Section %d length is out of bounds\n", i);
10344 return -EINVAL;
10345 }
10346 }
10347
10348 /* Likewise for the init_ops offsets */
10349 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10350 ops_offsets = (u16 *)(firmware->data + offset);
10351 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10352
10353 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10354 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10355 dev_err(&bp->pdev->dev,
10356 "Section offset %d is out of bounds\n", i);
10357 return -EINVAL;
10358 }
10359 }
10360
10361 /* Check FW version */
10362 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10363 fw_ver = firmware->data + offset;
10364 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10365 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10366 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10367 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10368 dev_err(&bp->pdev->dev,
10369 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10370 fw_ver[0], fw_ver[1], fw_ver[2],
10371 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10372 BCM_5710_FW_MINOR_VERSION,
10373 BCM_5710_FW_REVISION_VERSION,
10374 BCM_5710_FW_ENGINEERING_VERSION);
10375 return -EINVAL;
10376 }
10377
10378 return 0;
10379 }
10380
10381 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10382 {
10383 const __be32 *source = (const __be32 *)_source;
10384 u32 *target = (u32 *)_target;
10385 u32 i;
10386
10387 for (i = 0; i < n/4; i++)
10388 target[i] = be32_to_cpu(source[i]);
10389 }
10390
10391 /*
10392 Ops array is stored in the following format:
10393 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10394 */
10395 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10396 {
10397 const __be32 *source = (const __be32 *)_source;
10398 struct raw_op *target = (struct raw_op *)_target;
10399 u32 i, j, tmp;
10400
10401 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10402 tmp = be32_to_cpu(source[j]);
10403 target[i].op = (tmp >> 24) & 0xff;
10404 target[i].offset = tmp & 0xffffff;
10405 target[i].raw_data = be32_to_cpu(source[j + 1]);
10406 }
10407 }
10408
10409 /**
10410 * IRO array is stored in the following format:
10411 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10412 */
10413 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10414 {
10415 const __be32 *source = (const __be32 *)_source;
10416 struct iro *target = (struct iro *)_target;
10417 u32 i, j, tmp;
10418
10419 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10420 target[i].base = be32_to_cpu(source[j]);
10421 j++;
10422 tmp = be32_to_cpu(source[j]);
10423 target[i].m1 = (tmp >> 16) & 0xffff;
10424 target[i].m2 = tmp & 0xffff;
10425 j++;
10426 tmp = be32_to_cpu(source[j]);
10427 target[i].m3 = (tmp >> 16) & 0xffff;
10428 target[i].size = tmp & 0xffff;
10429 j++;
10430 }
10431 }
10432
10433 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10434 {
10435 const __be16 *source = (const __be16 *)_source;
10436 u16 *target = (u16 *)_target;
10437 u32 i;
10438
10439 for (i = 0; i < n/2; i++)
10440 target[i] = be16_to_cpu(source[i]);
10441 }
10442
10443 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10444 do { \
10445 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10446 bp->arr = kmalloc(len, GFP_KERNEL); \
10447 if (!bp->arr) { \
10448 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10449 goto lbl; \
10450 } \
10451 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10452 (u8 *)bp->arr, len); \
10453 } while (0)
10454
10455 int bnx2x_init_firmware(struct bnx2x *bp)
10456 {
10457 const char *fw_file_name;
10458 struct bnx2x_fw_file_hdr *fw_hdr;
10459 int rc;
10460
10461 if (CHIP_IS_E1(bp))
10462 fw_file_name = FW_FILE_NAME_E1;
10463 else if (CHIP_IS_E1H(bp))
10464 fw_file_name = FW_FILE_NAME_E1H;
10465 else if (!CHIP_IS_E1x(bp))
10466 fw_file_name = FW_FILE_NAME_E2;
10467 else {
10468 BNX2X_ERR("Unsupported chip revision\n");
10469 return -EINVAL;
10470 }
10471
10472 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10473
10474 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10475 if (rc) {
10476 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10477 goto request_firmware_exit;
10478 }
10479
10480 rc = bnx2x_check_firmware(bp);
10481 if (rc) {
10482 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10483 goto request_firmware_exit;
10484 }
10485
10486 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10487
10488 /* Initialize the pointers to the init arrays */
10489 /* Blob */
10490 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10491
10492 /* Opcodes */
10493 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10494
10495 /* Offsets */
10496 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10497 be16_to_cpu_n);
10498
10499 /* STORMs firmware */
10500 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10501 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10502 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10503 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10504 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10505 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10506 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10507 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10508 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10509 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10510 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10511 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10512 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10513 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10514 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10515 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10516 /* IRO */
10517 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10518
10519 return 0;
10520
10521 iro_alloc_err:
10522 kfree(bp->init_ops_offsets);
10523 init_offsets_alloc_err:
10524 kfree(bp->init_ops);
10525 init_ops_alloc_err:
10526 kfree(bp->init_data);
10527 request_firmware_exit:
10528 release_firmware(bp->firmware);
10529
10530 return rc;
10531 }
10532
10533 static void bnx2x_release_firmware(struct bnx2x *bp)
10534 {
10535 kfree(bp->init_ops_offsets);
10536 kfree(bp->init_ops);
10537 kfree(bp->init_data);
10538 release_firmware(bp->firmware);
10539 }
10540
10541
10542 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10543 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10544 .init_hw_cmn = bnx2x_init_hw_common,
10545 .init_hw_port = bnx2x_init_hw_port,
10546 .init_hw_func = bnx2x_init_hw_func,
10547
10548 .reset_hw_cmn = bnx2x_reset_common,
10549 .reset_hw_port = bnx2x_reset_port,
10550 .reset_hw_func = bnx2x_reset_func,
10551
10552 .gunzip_init = bnx2x_gunzip_init,
10553 .gunzip_end = bnx2x_gunzip_end,
10554
10555 .init_fw = bnx2x_init_firmware,
10556 .release_fw = bnx2x_release_firmware,
10557 };
10558
10559 void bnx2x__init_func_obj(struct bnx2x *bp)
10560 {
10561 /* Prepare DMAE related driver resources */
10562 bnx2x_setup_dmae(bp);
10563
10564 bnx2x_init_func_obj(bp, &bp->func_obj,
10565 bnx2x_sp(bp, func_rdata),
10566 bnx2x_sp_mapping(bp, func_rdata),
10567 &bnx2x_func_sp_drv);
10568 }
10569
10570 /* must be called after sriov-enable */
10571 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10572 {
10573 int cid_count = BNX2X_L2_CID_COUNT(bp);
10574
10575 #ifdef BCM_CNIC
10576 cid_count += CNIC_CID_MAX;
10577 #endif
10578 return roundup(cid_count, QM_CID_ROUND);
10579 }
10580
10581 /**
10582 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10583 *
10584 * @dev: pci device
10585 *
10586 */
10587 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10588 {
10589 int pos;
10590 u16 control;
10591
10592 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10593
10594 /*
10595 * If MSI-X is not supported - return number of SBs needed to support
10596 * one fast path queue: one FP queue + SB for CNIC
10597 */
10598 if (!pos)
10599 return 1 + CNIC_PRESENT;
10600
10601 /*
10602 * The value in the PCI configuration space is the index of the last
10603 * entry, namely one less than the actual size of the table, which is
10604 * exactly what we want to return from this function: number of all SBs
10605 * without the default SB.
10606 */
10607 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10608 return control & PCI_MSIX_FLAGS_QSIZE;
10609 }
10610
10611 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10612 const struct pci_device_id *ent)
10613 {
10614 struct net_device *dev = NULL;
10615 struct bnx2x *bp;
10616 int pcie_width, pcie_speed;
10617 int rc, max_non_def_sbs;
10618 int rx_count, tx_count, rss_count;
10619 /*
10620 * An estimated maximum supported CoS number according to the chip
10621 * version.
10622 * We will try to roughly estimate the maximum number of CoSes this chip
10623 * may support in order to minimize the memory allocated for Tx
10624 * netdev_queue's. This number will be accurately calculated during the
10625 * initialization of bp->max_cos based on the chip versions AND chip
10626 * revision in the bnx2x_init_bp().
10627 */
10628 u8 max_cos_est = 0;
10629
10630 switch (ent->driver_data) {
10631 case BCM57710:
10632 case BCM57711:
10633 case BCM57711E:
10634 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10635 break;
10636
10637 case BCM57712:
10638 case BCM57712_MF:
10639 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10640 break;
10641
10642 case BCM57800:
10643 case BCM57800_MF:
10644 case BCM57810:
10645 case BCM57810_MF:
10646 case BCM57840:
10647 case BCM57840_MF:
10648 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10649 break;
10650
10651 default:
10652 pr_err("Unknown board_type (%ld), aborting\n",
10653 ent->driver_data);
10654 return -ENODEV;
10655 }
10656
10657 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10658
10659 /* !!! FIXME !!!
10660 * Do not allow the maximum SB count to grow above 16
10661 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10662 * We will use the FP_SB_MAX_E1x macro for this matter.
10663 */
10664 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10665
10666 WARN_ON(!max_non_def_sbs);
10667
10668 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10669 rss_count = max_non_def_sbs - CNIC_PRESENT;
10670
10671 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10672 rx_count = rss_count + FCOE_PRESENT;
10673
10674 /*
10675 * Maximum number of netdev Tx queues:
10676 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10677 */
10678 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10679
10680 /* dev zeroed in init_etherdev */
10681 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10682 if (!dev) {
10683 dev_err(&pdev->dev, "Cannot allocate net device\n");
10684 return -ENOMEM;
10685 }
10686
10687 bp = netdev_priv(dev);
10688
10689 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10690 tx_count, rx_count);
10691
10692 bp->igu_sb_cnt = max_non_def_sbs;
10693 bp->msg_enable = debug;
10694 pci_set_drvdata(pdev, dev);
10695
10696 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10697 if (rc < 0) {
10698 free_netdev(dev);
10699 return rc;
10700 }
10701
10702 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
10703
10704 rc = bnx2x_init_bp(bp);
10705 if (rc)
10706 goto init_one_exit;
10707
10708 /*
10709 * Map doorbels here as we need the real value of bp->max_cos which
10710 * is initialized in bnx2x_init_bp().
10711 */
10712 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10713 min_t(u64, BNX2X_DB_SIZE(bp),
10714 pci_resource_len(pdev, 2)));
10715 if (!bp->doorbells) {
10716 dev_err(&bp->pdev->dev,
10717 "Cannot map doorbell space, aborting\n");
10718 rc = -ENOMEM;
10719 goto init_one_exit;
10720 }
10721
10722 /* calc qm_cid_count */
10723 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10724
10725 #ifdef BCM_CNIC
10726 /* disable FCOE L2 queue for E1x and E3*/
10727 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10728 bp->flags |= NO_FCOE_FLAG;
10729
10730 #endif
10731
10732 /* Configure interrupt mode: try to enable MSI-X/MSI if
10733 * needed, set bp->num_queues appropriately.
10734 */
10735 bnx2x_set_int_mode(bp);
10736
10737 /* Add all NAPI objects */
10738 bnx2x_add_all_napi(bp);
10739
10740 rc = register_netdev(dev);
10741 if (rc) {
10742 dev_err(&pdev->dev, "Cannot register net device\n");
10743 goto init_one_exit;
10744 }
10745
10746 #ifdef BCM_CNIC
10747 if (!NO_FCOE(bp)) {
10748 /* Add storage MAC address */
10749 rtnl_lock();
10750 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10751 rtnl_unlock();
10752 }
10753 #endif
10754
10755 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10756
10757 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10758 board_info[ent->driver_data].name,
10759 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10760 pcie_width,
10761 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10762 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10763 "5GHz (Gen2)" : "2.5GHz",
10764 dev->base_addr, bp->pdev->irq, dev->dev_addr);
10765
10766 return 0;
10767
10768 init_one_exit:
10769 if (bp->regview)
10770 iounmap(bp->regview);
10771
10772 if (bp->doorbells)
10773 iounmap(bp->doorbells);
10774
10775 free_netdev(dev);
10776
10777 if (atomic_read(&pdev->enable_cnt) == 1)
10778 pci_release_regions(pdev);
10779
10780 pci_disable_device(pdev);
10781 pci_set_drvdata(pdev, NULL);
10782
10783 return rc;
10784 }
10785
10786 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10787 {
10788 struct net_device *dev = pci_get_drvdata(pdev);
10789 struct bnx2x *bp;
10790
10791 if (!dev) {
10792 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10793 return;
10794 }
10795 bp = netdev_priv(dev);
10796
10797 #ifdef BCM_CNIC
10798 /* Delete storage MAC address */
10799 if (!NO_FCOE(bp)) {
10800 rtnl_lock();
10801 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10802 rtnl_unlock();
10803 }
10804 #endif
10805
10806 #ifdef BCM_DCBNL
10807 /* Delete app tlvs from dcbnl */
10808 bnx2x_dcbnl_update_applist(bp, true);
10809 #endif
10810
10811 unregister_netdev(dev);
10812
10813 /* Delete all NAPI objects */
10814 bnx2x_del_all_napi(bp);
10815
10816 /* Power on: we can't let PCI layer write to us while we are in D3 */
10817 bnx2x_set_power_state(bp, PCI_D0);
10818
10819 /* Disable MSI/MSI-X */
10820 bnx2x_disable_msi(bp);
10821
10822 /* Power off */
10823 bnx2x_set_power_state(bp, PCI_D3hot);
10824
10825 /* Make sure RESET task is not scheduled before continuing */
10826 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10827
10828 if (bp->regview)
10829 iounmap(bp->regview);
10830
10831 if (bp->doorbells)
10832 iounmap(bp->doorbells);
10833
10834 bnx2x_free_mem_bp(bp);
10835
10836 free_netdev(dev);
10837
10838 if (atomic_read(&pdev->enable_cnt) == 1)
10839 pci_release_regions(pdev);
10840
10841 pci_disable_device(pdev);
10842 pci_set_drvdata(pdev, NULL);
10843 }
10844
10845 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10846 {
10847 int i;
10848
10849 bp->state = BNX2X_STATE_ERROR;
10850
10851 bp->rx_mode = BNX2X_RX_MODE_NONE;
10852
10853 #ifdef BCM_CNIC
10854 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10855 #endif
10856 /* Stop Tx */
10857 bnx2x_tx_disable(bp);
10858
10859 bnx2x_netif_stop(bp, 0);
10860
10861 del_timer_sync(&bp->timer);
10862
10863 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10864
10865 /* Release IRQs */
10866 bnx2x_free_irq(bp);
10867
10868 /* Free SKBs, SGEs, TPA pool and driver internals */
10869 bnx2x_free_skbs(bp);
10870
10871 for_each_rx_queue(bp, i)
10872 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10873
10874 bnx2x_free_mem(bp);
10875
10876 bp->state = BNX2X_STATE_CLOSED;
10877
10878 netif_carrier_off(bp->dev);
10879
10880 return 0;
10881 }
10882
10883 static void bnx2x_eeh_recover(struct bnx2x *bp)
10884 {
10885 u32 val;
10886
10887 mutex_init(&bp->port.phy_mutex);
10888
10889 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10890 bp->link_params.shmem_base = bp->common.shmem_base;
10891 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10892
10893 if (!bp->common.shmem_base ||
10894 (bp->common.shmem_base < 0xA0000) ||
10895 (bp->common.shmem_base >= 0xC0000)) {
10896 BNX2X_DEV_INFO("MCP not active\n");
10897 bp->flags |= NO_MCP_FLAG;
10898 return;
10899 }
10900
10901 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10902 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10903 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10904 BNX2X_ERR("BAD MCP validity signature\n");
10905
10906 if (!BP_NOMCP(bp)) {
10907 bp->fw_seq =
10908 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10909 DRV_MSG_SEQ_NUMBER_MASK);
10910 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10911 }
10912 }
10913
10914 /**
10915 * bnx2x_io_error_detected - called when PCI error is detected
10916 * @pdev: Pointer to PCI device
10917 * @state: The current pci connection state
10918 *
10919 * This function is called after a PCI bus error affecting
10920 * this device has been detected.
10921 */
10922 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10923 pci_channel_state_t state)
10924 {
10925 struct net_device *dev = pci_get_drvdata(pdev);
10926 struct bnx2x *bp = netdev_priv(dev);
10927
10928 rtnl_lock();
10929
10930 netif_device_detach(dev);
10931
10932 if (state == pci_channel_io_perm_failure) {
10933 rtnl_unlock();
10934 return PCI_ERS_RESULT_DISCONNECT;
10935 }
10936
10937 if (netif_running(dev))
10938 bnx2x_eeh_nic_unload(bp);
10939
10940 pci_disable_device(pdev);
10941
10942 rtnl_unlock();
10943
10944 /* Request a slot reset */
10945 return PCI_ERS_RESULT_NEED_RESET;
10946 }
10947
10948 /**
10949 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10950 * @pdev: Pointer to PCI device
10951 *
10952 * Restart the card from scratch, as if from a cold-boot.
10953 */
10954 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10955 {
10956 struct net_device *dev = pci_get_drvdata(pdev);
10957 struct bnx2x *bp = netdev_priv(dev);
10958
10959 rtnl_lock();
10960
10961 if (pci_enable_device(pdev)) {
10962 dev_err(&pdev->dev,
10963 "Cannot re-enable PCI device after reset\n");
10964 rtnl_unlock();
10965 return PCI_ERS_RESULT_DISCONNECT;
10966 }
10967
10968 pci_set_master(pdev);
10969 pci_restore_state(pdev);
10970
10971 if (netif_running(dev))
10972 bnx2x_set_power_state(bp, PCI_D0);
10973
10974 rtnl_unlock();
10975
10976 return PCI_ERS_RESULT_RECOVERED;
10977 }
10978
10979 /**
10980 * bnx2x_io_resume - called when traffic can start flowing again
10981 * @pdev: Pointer to PCI device
10982 *
10983 * This callback is called when the error recovery driver tells us that
10984 * its OK to resume normal operation.
10985 */
10986 static void bnx2x_io_resume(struct pci_dev *pdev)
10987 {
10988 struct net_device *dev = pci_get_drvdata(pdev);
10989 struct bnx2x *bp = netdev_priv(dev);
10990
10991 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10992 netdev_err(bp->dev, "Handling parity error recovery. "
10993 "Try again later\n");
10994 return;
10995 }
10996
10997 rtnl_lock();
10998
10999 bnx2x_eeh_recover(bp);
11000
11001 if (netif_running(dev))
11002 bnx2x_nic_load(bp, LOAD_NORMAL);
11003
11004 netif_device_attach(dev);
11005
11006 rtnl_unlock();
11007 }
11008
11009 static struct pci_error_handlers bnx2x_err_handler = {
11010 .error_detected = bnx2x_io_error_detected,
11011 .slot_reset = bnx2x_io_slot_reset,
11012 .resume = bnx2x_io_resume,
11013 };
11014
11015 static struct pci_driver bnx2x_pci_driver = {
11016 .name = DRV_MODULE_NAME,
11017 .id_table = bnx2x_pci_tbl,
11018 .probe = bnx2x_init_one,
11019 .remove = __devexit_p(bnx2x_remove_one),
11020 .suspend = bnx2x_suspend,
11021 .resume = bnx2x_resume,
11022 .err_handler = &bnx2x_err_handler,
11023 };
11024
11025 static int __init bnx2x_init(void)
11026 {
11027 int ret;
11028
11029 pr_info("%s", version);
11030
11031 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11032 if (bnx2x_wq == NULL) {
11033 pr_err("Cannot create workqueue\n");
11034 return -ENOMEM;
11035 }
11036
11037 ret = pci_register_driver(&bnx2x_pci_driver);
11038 if (ret) {
11039 pr_err("Cannot register driver\n");
11040 destroy_workqueue(bnx2x_wq);
11041 }
11042 return ret;
11043 }
11044
11045 static void __exit bnx2x_cleanup(void)
11046 {
11047 pci_unregister_driver(&bnx2x_pci_driver);
11048
11049 destroy_workqueue(bnx2x_wq);
11050 }
11051
11052 void bnx2x_notify_link_changed(struct bnx2x *bp)
11053 {
11054 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11055 }
11056
11057 module_init(bnx2x_init);
11058 module_exit(bnx2x_cleanup);
11059
11060 #ifdef BCM_CNIC
11061 /**
11062 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11063 *
11064 * @bp: driver handle
11065 * @set: set or clear the CAM entry
11066 *
11067 * This function will wait until the ramdord completion returns.
11068 * Return 0 if success, -ENODEV if ramrod doesn't return.
11069 */
11070 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11071 {
11072 unsigned long ramrod_flags = 0;
11073
11074 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11075 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11076 &bp->iscsi_l2_mac_obj, true,
11077 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11078 }
11079
11080 /* count denotes the number of new completions we have seen */
11081 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11082 {
11083 struct eth_spe *spe;
11084
11085 #ifdef BNX2X_STOP_ON_ERROR
11086 if (unlikely(bp->panic))
11087 return;
11088 #endif
11089
11090 spin_lock_bh(&bp->spq_lock);
11091 BUG_ON(bp->cnic_spq_pending < count);
11092 bp->cnic_spq_pending -= count;
11093
11094
11095 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11096 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11097 & SPE_HDR_CONN_TYPE) >>
11098 SPE_HDR_CONN_TYPE_SHIFT;
11099 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11100 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11101
11102 /* Set validation for iSCSI L2 client before sending SETUP
11103 * ramrod
11104 */
11105 if (type == ETH_CONNECTION_TYPE) {
11106 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11107 bnx2x_set_ctx_validation(bp, &bp->context.
11108 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11109 BNX2X_ISCSI_ETH_CID);
11110 }
11111
11112 /*
11113 * There may be not more than 8 L2, not more than 8 L5 SPEs
11114 * and in the air. We also check that number of outstanding
11115 * COMMON ramrods is not more than the EQ and SPQ can
11116 * accommodate.
11117 */
11118 if (type == ETH_CONNECTION_TYPE) {
11119 if (!atomic_read(&bp->cq_spq_left))
11120 break;
11121 else
11122 atomic_dec(&bp->cq_spq_left);
11123 } else if (type == NONE_CONNECTION_TYPE) {
11124 if (!atomic_read(&bp->eq_spq_left))
11125 break;
11126 else
11127 atomic_dec(&bp->eq_spq_left);
11128 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11129 (type == FCOE_CONNECTION_TYPE)) {
11130 if (bp->cnic_spq_pending >=
11131 bp->cnic_eth_dev.max_kwqe_pending)
11132 break;
11133 else
11134 bp->cnic_spq_pending++;
11135 } else {
11136 BNX2X_ERR("Unknown SPE type: %d\n", type);
11137 bnx2x_panic();
11138 break;
11139 }
11140
11141 spe = bnx2x_sp_get_next(bp);
11142 *spe = *bp->cnic_kwq_cons;
11143
11144 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11145 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11146
11147 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11148 bp->cnic_kwq_cons = bp->cnic_kwq;
11149 else
11150 bp->cnic_kwq_cons++;
11151 }
11152 bnx2x_sp_prod_update(bp);
11153 spin_unlock_bh(&bp->spq_lock);
11154 }
11155
11156 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11157 struct kwqe_16 *kwqes[], u32 count)
11158 {
11159 struct bnx2x *bp = netdev_priv(dev);
11160 int i;
11161
11162 #ifdef BNX2X_STOP_ON_ERROR
11163 if (unlikely(bp->panic))
11164 return -EIO;
11165 #endif
11166
11167 spin_lock_bh(&bp->spq_lock);
11168
11169 for (i = 0; i < count; i++) {
11170 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11171
11172 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11173 break;
11174
11175 *bp->cnic_kwq_prod = *spe;
11176
11177 bp->cnic_kwq_pending++;
11178
11179 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11180 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11181 spe->data.update_data_addr.hi,
11182 spe->data.update_data_addr.lo,
11183 bp->cnic_kwq_pending);
11184
11185 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11186 bp->cnic_kwq_prod = bp->cnic_kwq;
11187 else
11188 bp->cnic_kwq_prod++;
11189 }
11190
11191 spin_unlock_bh(&bp->spq_lock);
11192
11193 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11194 bnx2x_cnic_sp_post(bp, 0);
11195
11196 return i;
11197 }
11198
11199 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11200 {
11201 struct cnic_ops *c_ops;
11202 int rc = 0;
11203
11204 mutex_lock(&bp->cnic_mutex);
11205 c_ops = rcu_dereference_protected(bp->cnic_ops,
11206 lockdep_is_held(&bp->cnic_mutex));
11207 if (c_ops)
11208 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11209 mutex_unlock(&bp->cnic_mutex);
11210
11211 return rc;
11212 }
11213
11214 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11215 {
11216 struct cnic_ops *c_ops;
11217 int rc = 0;
11218
11219 rcu_read_lock();
11220 c_ops = rcu_dereference(bp->cnic_ops);
11221 if (c_ops)
11222 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11223 rcu_read_unlock();
11224
11225 return rc;
11226 }
11227
11228 /*
11229 * for commands that have no data
11230 */
11231 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11232 {
11233 struct cnic_ctl_info ctl = {0};
11234
11235 ctl.cmd = cmd;
11236
11237 return bnx2x_cnic_ctl_send(bp, &ctl);
11238 }
11239
11240 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11241 {
11242 struct cnic_ctl_info ctl = {0};
11243
11244 /* first we tell CNIC and only then we count this as a completion */
11245 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11246 ctl.data.comp.cid = cid;
11247 ctl.data.comp.error = err;
11248
11249 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11250 bnx2x_cnic_sp_post(bp, 0);
11251 }
11252
11253
11254 /* Called with netif_addr_lock_bh() taken.
11255 * Sets an rx_mode config for an iSCSI ETH client.
11256 * Doesn't block.
11257 * Completion should be checked outside.
11258 */
11259 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11260 {
11261 unsigned long accept_flags = 0, ramrod_flags = 0;
11262 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11263 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11264
11265 if (start) {
11266 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11267 * because it's the only way for UIO Queue to accept
11268 * multicasts (in non-promiscuous mode only one Queue per
11269 * function will receive multicast packets (leading in our
11270 * case).
11271 */
11272 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11273 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11274 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11275 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11276
11277 /* Clear STOP_PENDING bit if START is requested */
11278 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11279
11280 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11281 } else
11282 /* Clear START_PENDING bit if STOP is requested */
11283 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11284
11285 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11286 set_bit(sched_state, &bp->sp_state);
11287 else {
11288 __set_bit(RAMROD_RX, &ramrod_flags);
11289 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11290 ramrod_flags);
11291 }
11292 }
11293
11294
11295 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11296 {
11297 struct bnx2x *bp = netdev_priv(dev);
11298 int rc = 0;
11299
11300 switch (ctl->cmd) {
11301 case DRV_CTL_CTXTBL_WR_CMD: {
11302 u32 index = ctl->data.io.offset;
11303 dma_addr_t addr = ctl->data.io.dma_addr;
11304
11305 bnx2x_ilt_wr(bp, index, addr);
11306 break;
11307 }
11308
11309 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11310 int count = ctl->data.credit.credit_count;
11311
11312 bnx2x_cnic_sp_post(bp, count);
11313 break;
11314 }
11315
11316 /* rtnl_lock is held. */
11317 case DRV_CTL_START_L2_CMD: {
11318 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11319 unsigned long sp_bits = 0;
11320
11321 /* Configure the iSCSI classification object */
11322 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11323 cp->iscsi_l2_client_id,
11324 cp->iscsi_l2_cid, BP_FUNC(bp),
11325 bnx2x_sp(bp, mac_rdata),
11326 bnx2x_sp_mapping(bp, mac_rdata),
11327 BNX2X_FILTER_MAC_PENDING,
11328 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11329 &bp->macs_pool);
11330
11331 /* Set iSCSI MAC address */
11332 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11333 if (rc)
11334 break;
11335
11336 mmiowb();
11337 barrier();
11338
11339 /* Start accepting on iSCSI L2 ring */
11340
11341 netif_addr_lock_bh(dev);
11342 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11343 netif_addr_unlock_bh(dev);
11344
11345 /* bits to wait on */
11346 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11347 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11348
11349 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11350 BNX2X_ERR("rx_mode completion timed out!\n");
11351
11352 break;
11353 }
11354
11355 /* rtnl_lock is held. */
11356 case DRV_CTL_STOP_L2_CMD: {
11357 unsigned long sp_bits = 0;
11358
11359 /* Stop accepting on iSCSI L2 ring */
11360 netif_addr_lock_bh(dev);
11361 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11362 netif_addr_unlock_bh(dev);
11363
11364 /* bits to wait on */
11365 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11366 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11367
11368 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11369 BNX2X_ERR("rx_mode completion timed out!\n");
11370
11371 mmiowb();
11372 barrier();
11373
11374 /* Unset iSCSI L2 MAC */
11375 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11376 BNX2X_ISCSI_ETH_MAC, true);
11377 break;
11378 }
11379 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11380 int count = ctl->data.credit.credit_count;
11381
11382 smp_mb__before_atomic_inc();
11383 atomic_add(count, &bp->cq_spq_left);
11384 smp_mb__after_atomic_inc();
11385 break;
11386 }
11387
11388 default:
11389 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11390 rc = -EINVAL;
11391 }
11392
11393 return rc;
11394 }
11395
11396 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11397 {
11398 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11399
11400 if (bp->flags & USING_MSIX_FLAG) {
11401 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11402 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11403 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11404 } else {
11405 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11406 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11407 }
11408 if (!CHIP_IS_E1x(bp))
11409 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11410 else
11411 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11412
11413 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11414 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11415 cp->irq_arr[1].status_blk = bp->def_status_blk;
11416 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11417 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11418
11419 cp->num_irq = 2;
11420 }
11421
11422 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11423 void *data)
11424 {
11425 struct bnx2x *bp = netdev_priv(dev);
11426 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11427
11428 if (ops == NULL)
11429 return -EINVAL;
11430
11431 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11432 if (!bp->cnic_kwq)
11433 return -ENOMEM;
11434
11435 bp->cnic_kwq_cons = bp->cnic_kwq;
11436 bp->cnic_kwq_prod = bp->cnic_kwq;
11437 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11438
11439 bp->cnic_spq_pending = 0;
11440 bp->cnic_kwq_pending = 0;
11441
11442 bp->cnic_data = data;
11443
11444 cp->num_irq = 0;
11445 cp->drv_state |= CNIC_DRV_STATE_REGD;
11446 cp->iro_arr = bp->iro_arr;
11447
11448 bnx2x_setup_cnic_irq_info(bp);
11449
11450 rcu_assign_pointer(bp->cnic_ops, ops);
11451
11452 return 0;
11453 }
11454
11455 static int bnx2x_unregister_cnic(struct net_device *dev)
11456 {
11457 struct bnx2x *bp = netdev_priv(dev);
11458 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11459
11460 mutex_lock(&bp->cnic_mutex);
11461 cp->drv_state = 0;
11462 rcu_assign_pointer(bp->cnic_ops, NULL);
11463 mutex_unlock(&bp->cnic_mutex);
11464 synchronize_rcu();
11465 kfree(bp->cnic_kwq);
11466 bp->cnic_kwq = NULL;
11467
11468 return 0;
11469 }
11470
11471 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11472 {
11473 struct bnx2x *bp = netdev_priv(dev);
11474 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11475
11476 /* If both iSCSI and FCoE are disabled - return NULL in
11477 * order to indicate CNIC that it should not try to work
11478 * with this device.
11479 */
11480 if (NO_ISCSI(bp) && NO_FCOE(bp))
11481 return NULL;
11482
11483 cp->drv_owner = THIS_MODULE;
11484 cp->chip_id = CHIP_ID(bp);
11485 cp->pdev = bp->pdev;
11486 cp->io_base = bp->regview;
11487 cp->io_base2 = bp->doorbells;
11488 cp->max_kwqe_pending = 8;
11489 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11490 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11491 bnx2x_cid_ilt_lines(bp);
11492 cp->ctx_tbl_len = CNIC_ILT_LINES;
11493 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11494 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11495 cp->drv_ctl = bnx2x_drv_ctl;
11496 cp->drv_register_cnic = bnx2x_register_cnic;
11497 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11498 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11499 cp->iscsi_l2_client_id =
11500 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11501 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11502
11503 if (NO_ISCSI_OOO(bp))
11504 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11505
11506 if (NO_ISCSI(bp))
11507 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11508
11509 if (NO_FCOE(bp))
11510 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11511
11512 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11513 "starting cid %d\n",
11514 cp->ctx_blk_size,
11515 cp->ctx_tbl_offset,
11516 cp->ctx_tbl_len,
11517 cp->starting_cid);
11518 return cp;
11519 }
11520 EXPORT_SYMBOL(bnx2x_cnic_probe);
11521
11522 #endif /* BCM_CNIC */
11523
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree