arch/arm/mach-tegra/clock.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/clock.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #ifndef __MACH_TEGRA_CLOCK_H
  21 #define __MACH_TEGRA_CLOCK_H
  22
  23 #include <linux/list.h>
  24 #include <linux/clkdev.h>
  25
  26 #define DIV_BUS                 (1 << 0)
  27 #define DIV_U71                 (1 << 1)
  28 #define DIV_U71_FIXED           (1 << 2)
  29 #define DIV_2                   (1 << 3)
  30 #define DIV_U16                 (1 << 4)
  31 #define PLL_FIXED               (1 << 5)
  32 #define PLL_HAS_CPCON           (1 << 6)
  33 #define MUX                     (1 << 7)
  34 #define PLLD                    (1 << 8)
  35 #define PERIPH_NO_RESET         (1 << 9)
  36 #define PERIPH_NO_ENB           (1 << 10)
  37 #define PERIPH_EMC_ENB          (1 << 11)
  38 #define PERIPH_MANUAL_RESET     (1 << 12)
  39 #define PLL_ALT_MISC_REG        (1 << 13)
  40 #define PLLU                    (1 << 14)
  41 #define ENABLE_ON_INIT          (1 << 28)
  42
  43 struct clk;
  44
  45 struct clk_mux_sel {
  46         struct clk      *input;
  47         u32             value;
  48 };
  49
  50 struct clk_pll_freq_table {
  51         unsigned long   input_rate;
  52         unsigned long   output_rate;
  53         u16             n;
  54         u16             m;
  55         u8              p;
  56         u8              cpcon;
  57 };
  58
  59 struct clk_ops {
  60         void            (*init)(struct clk *);
  61         int             (*enable)(struct clk *);
  62         void            (*disable)(struct clk *);
  63         int             (*set_parent)(struct clk *, struct clk *);
  64         int             (*set_rate)(struct clk *, unsigned long);
  65         long            (*round_rate)(struct clk *, unsigned long);
  66         void            (*reset)(struct clk *, bool);
  67 };
  68
  69 enum clk_state {
  70         UNINITIALIZED = 0,
  71         ON,
  72         OFF,
  73 };
  74
  75 struct clk {
  76         /* node for master clocks list */
  77         struct list_head        node;           /* node for list of all clocks */
  78         struct list_head        children;       /* list of children */
  79         struct list_head        sibling;        /* node for children */
  80         struct clk_lookup       lookup;
  81
  82 #ifdef CONFIG_DEBUG_FS
  83         struct dentry           *dent;
  84         bool                    set;
  85 #endif
  86         struct clk_ops          *ops;
  87         unsigned long           rate;
  88         unsigned long           max_rate;
  89         u32                     flags;
  90         const char              *name;
  91
  92         u32                     refcnt;
  93         enum clk_state          state;
  94         struct clk              *parent;
  95         u32                     div;
  96         u32                     mul;
  97
  98         const struct clk_mux_sel        *inputs;
  99         u32                             reg;
 100         u32                             reg_shift;
 101
 102         union {
 103                 struct {
 104                         unsigned int                    clk_num;
 105                 } periph;
 106                 struct {
 107                         unsigned long                   input_min;
 108                         unsigned long                   input_max;
 109                         unsigned long                   cf_min;
 110                         unsigned long                   cf_max;
 111                         unsigned long                   vco_min;
 112                         unsigned long                   vco_max;
 113                         const struct clk_pll_freq_table *freq_table;
 114                         int                             lock_delay;
 115                 } pll;
 116                 struct {
 117                         u32                             sel;
 118                         u32                             reg_mask;
 119                 } mux;
 120                 struct {
 121                         struct clk                      *main;
 122                         struct clk                      *backup;
 123                 } cpu;
 124         } u;
 125 };
 126
 127
 128 struct clk_duplicate {
 129         const char *name;
 130         struct clk_lookup lookup;
 131 };
 132
 133 struct tegra_clk_init_table {
 134         const char *name;
 135         const char *parent;
 136         unsigned long rate;
 137         bool enabled;
 138 };
 139
 140 void tegra2_init_clocks(void);
 141 void tegra2_periph_reset_deassert(struct clk *c);
 142 void tegra2_periph_reset_assert(struct clk *c);
 143 void clk_init(struct clk *clk);
 144 struct clk *tegra_get_clock_by_name(const char *name);
 145 unsigned long clk_measure_input_freq(void);
 146 void clk_disable_locked(struct clk *c);
 147 int clk_enable_locked(struct clk *c);
 148 int clk_set_parent_locked(struct clk *c, struct clk *parent);
 149 int clk_set_rate_locked(struct clk *c, unsigned long rate);
 150 int clk_reparent(struct clk *c, struct clk *parent);
 151 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 152
 153 #endif