drivers/pci/pci.h

   1 #ifndef DRIVERS_PCI_H
   2 #define DRIVERS_PCI_H
   3
   4 #include <linux/workqueue.h>
   5
   6 #define PCI_CFG_SPACE_SIZE      256
   7 #define PCI_CFG_SPACE_EXP_SIZE  4096
   8
   9 /* Functions internal to the PCI core code */
  10
  11 extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
  12 extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  13 extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  14 #ifndef CONFIG_DMI
  15 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  16 { return; }
  17 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  18 { return; }
  19 #else
  20 extern void pci_create_firmware_label_files(struct pci_dev *pdev);
  21 extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
  22 #endif
  23 extern void pci_cleanup_rom(struct pci_dev *dev);
  24 #ifdef HAVE_PCI_MMAP
  25 enum pci_mmap_api {
  26         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  27         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  28 };
  29 extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
  30                          struct vm_area_struct *vmai,
  31                          enum pci_mmap_api mmap_api);
  32 #endif
  33 int pci_probe_reset_function(struct pci_dev *dev);
  34
  35 /**
  36  * struct pci_platform_pm_ops - Firmware PM callbacks
  37  *
  38  * @is_manageable: returns 'true' if given device is power manageable by the
  39  *                 platform firmware
  40  *
  41  * @set_state: invokes the platform firmware to set the device's power state
  42  *
  43  * @choose_state: returns PCI power state of given device preferred by the
  44  *                platform; to be used during system-wide transitions from a
  45  *                sleeping state to the working state and vice versa
  46  *
  47  * @can_wakeup: returns 'true' if given device is capable of waking up the
  48  *              system from a sleeping state
  49  *
  50  * @sleep_wake: enables/disables the system wake up capability of given device
  51  *
  52  * @run_wake: enables/disables the platform to generate run-time wake-up events
  53  *              for given device (the device's wake-up capability has to be
  54  *              enabled by @sleep_wake for this feature to work)
  55  *
  56  * If given platform is generally capable of power managing PCI devices, all of
  57  * these callbacks are mandatory.
  58  */
  59 struct pci_platform_pm_ops {
  60         bool (*is_manageable)(struct pci_dev *dev);
  61         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  62         pci_power_t (*choose_state)(struct pci_dev *dev);
  63         bool (*can_wakeup)(struct pci_dev *dev);
  64         int (*sleep_wake)(struct pci_dev *dev, bool enable);
  65         int (*run_wake)(struct pci_dev *dev, bool enable);
  66 };
  67
  68 extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
  69 extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  70 extern void pci_disable_enabled_device(struct pci_dev *dev);
  71 extern int pci_finish_runtime_suspend(struct pci_dev *dev);
  72 extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  73 extern void pci_pm_init(struct pci_dev *dev);
  74 extern void platform_pci_wakeup_init(struct pci_dev *dev);
  75 extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  76
  77 static inline bool pci_is_bridge(struct pci_dev *pci_dev)
  78 {
  79         return !!(pci_dev->subordinate);
  80 }
  81
  82 extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
  83 extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
  84 extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
  85 extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
  86 extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
  87 extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
  88
  89 struct pci_vpd_ops {
  90         ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  91         ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  92         void (*release)(struct pci_dev *dev);
  93 };
  94
  95 struct pci_vpd {
  96         unsigned int len;
  97         const struct pci_vpd_ops *ops;
  98         struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
  99 };
 100
 101 extern int pci_vpd_pci22_init(struct pci_dev *dev);
 102 static inline void pci_vpd_release(struct pci_dev *dev)
 103 {
 104         if (dev->vpd)
 105                 dev->vpd->ops->release(dev);
 106 }
 107
 108 /* PCI /proc functions */
 109 #ifdef CONFIG_PROC_FS
 110 extern int pci_proc_attach_device(struct pci_dev *dev);
 111 extern int pci_proc_detach_device(struct pci_dev *dev);
 112 extern int pci_proc_detach_bus(struct pci_bus *bus);
 113 #else
 114 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 115 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 116 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 117 #endif
 118
 119 /* Functions for PCI Hotplug drivers to use */
 120 extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
 121
 122 #ifdef HAVE_PCI_LEGACY
 123 extern void pci_create_legacy_files(struct pci_bus *bus);
 124 extern void pci_remove_legacy_files(struct pci_bus *bus);
 125 #else
 126 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 127 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 128 #endif
 129
 130 /* Lock for read/write access to pci device and bus lists */
 131 extern struct rw_semaphore pci_bus_sem;
 132
 133 extern unsigned int pci_pm_d3_delay;
 134
 135 #ifdef CONFIG_PCI_MSI
 136 void pci_no_msi(void);
 137 extern void pci_msi_init_pci_dev(struct pci_dev *dev);
 138 #else
 139 static inline void pci_no_msi(void) { }
 140 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
 141 #endif
 142
 143 #ifdef CONFIG_PCIEAER
 144 void pci_no_aer(void);
 145 bool pci_aer_available(void);
 146 #else
 147 static inline void pci_no_aer(void) { }
 148 static inline bool pci_aer_available(void) { return false; }
 149 #endif
 150
 151 static inline int pci_no_d1d2(struct pci_dev *dev)
 152 {
 153         unsigned int parent_dstates = 0;
 154
 155         if (dev->bus->self)
 156                 parent_dstates = dev->bus->self->no_d1d2;
 157         return (dev->no_d1d2 || parent_dstates);
 158
 159 }
 160 extern struct device_attribute pci_dev_attrs[];
 161 extern struct device_attribute dev_attr_cpuaffinity;
 162 extern struct device_attribute dev_attr_cpulistaffinity;
 163 #ifdef CONFIG_HOTPLUG
 164 extern struct bus_attribute pci_bus_attrs[];
 165 #else
 166 #define pci_bus_attrs   NULL
 167 #endif
 168
 169
 170 /**
 171  * pci_match_one_device - Tell if a PCI device structure has a matching
 172  *                        PCI device id structure
 173  * @id: single PCI device id structure to match
 174  * @dev: the PCI device structure to match against
 175  *
 176  * Returns the matching pci_device_id structure or %NULL if there is no match.
 177  */
 178 static inline const struct pci_device_id *
 179 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 180 {
 181         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 182             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 183             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 184             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 185             !((id->class ^ dev->class) & id->class_mask))
 186                 return id;
 187         return NULL;
 188 }
 189
 190 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
 191
 192 /* PCI slot sysfs helper code */
 193 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 194
 195 extern struct kset *pci_slots_kset;
 196
 197 struct pci_slot_attribute {
 198         struct attribute attr;
 199         ssize_t (*show)(struct pci_slot *, char *);
 200         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 201 };
 202 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 203
 204 enum pci_bar_type {
 205         pci_bar_unknown,        /* Standard PCI BAR probe */
 206         pci_bar_io,             /* An io port BAR */
 207         pci_bar_mem32,          /* A 32-bit memory BAR */
 208         pci_bar_mem64,          /* A 64-bit memory BAR */
 209 };
 210
 211 extern int pci_setup_device(struct pci_dev *dev);
 212 extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 213                                 struct resource *res, unsigned int reg);
 214 extern int pci_resource_bar(struct pci_dev *dev, int resno,
 215                             enum pci_bar_type *type);
 216 extern int pci_bus_add_child(struct pci_bus *bus);
 217 extern void pci_enable_ari(struct pci_dev *dev);
 218 /**
 219  * pci_ari_enabled - query ARI forwarding status
 220  * @bus: the PCI bus
 221  *
 222  * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 223  */
 224 static inline int pci_ari_enabled(struct pci_bus *bus)
 225 {
 226         return bus->self && bus->self->ari_enabled;
 227 }
 228
 229 #ifdef CONFIG_PCI_QUIRKS
 230 extern int pci_is_reassigndev(struct pci_dev *dev);
 231 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
 232 extern void pci_disable_bridge_window(struct pci_dev *dev);
 233 #endif
 234
 235 /* Single Root I/O Virtualization */
 236 struct pci_sriov {
 237         int pos;                /* capability position */
 238         int nres;               /* number of resources */
 239         u32 cap;                /* SR-IOV Capabilities */
 240         u16 ctrl;               /* SR-IOV Control */
 241         u16 total;              /* total VFs associated with the PF */
 242         u16 initial;            /* initial VFs associated with the PF */
 243         u16 nr_virtfn;          /* number of VFs available */
 244         u16 offset;             /* first VF Routing ID offset */
 245         u16 stride;             /* following VF stride */
 246         u32 pgsz;               /* page size for BAR alignment */
 247         u8 link;                /* Function Dependency Link */
 248         struct pci_dev *dev;    /* lowest numbered PF */
 249         struct pci_dev *self;   /* this PF */
 250         struct mutex lock;      /* lock for VF bus */
 251         struct work_struct mtask; /* VF Migration task */
 252         u8 __iomem *mstate;     /* VF Migration State Array */
 253 };
 254
 255 /* Address Translation Service */
 256 struct pci_ats {
 257         int pos;        /* capability position */
 258         int stu;        /* Smallest Translation Unit */
 259         int qdep;       /* Invalidate Queue Depth */
 260         int ref_cnt;    /* Physical Function reference count */
 261         unsigned int is_enabled:1;      /* Enable bit is set */
 262 };
 263
 264 #ifdef CONFIG_PCI_IOV
 265 extern int pci_iov_init(struct pci_dev *dev);
 266 extern void pci_iov_release(struct pci_dev *dev);
 267 extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 268                                 enum pci_bar_type *type);
 269 extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
 270                                                     int resno);
 271 extern void pci_restore_iov_state(struct pci_dev *dev);
 272 extern int pci_iov_bus_range(struct pci_bus *bus);
 273
 274 extern int pci_enable_ats(struct pci_dev *dev, int ps);
 275 extern void pci_disable_ats(struct pci_dev *dev);
 276 extern int pci_ats_queue_depth(struct pci_dev *dev);
 277 /**
 278  * pci_ats_enabled - query the ATS status
 279  * @dev: the PCI device
 280  *
 281  * Returns 1 if ATS capability is enabled, or 0 if not.
 282  */
 283 static inline int pci_ats_enabled(struct pci_dev *dev)
 284 {
 285         return dev->ats && dev->ats->is_enabled;
 286 }
 287 #else
 288 static inline int pci_iov_init(struct pci_dev *dev)
 289 {
 290         return -ENODEV;
 291 }
 292 static inline void pci_iov_release(struct pci_dev *dev)
 293
 294 {
 295 }
 296 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
 297                                        enum pci_bar_type *type)
 298 {
 299         return 0;
 300 }
 301 static inline void pci_restore_iov_state(struct pci_dev *dev)
 302 {
 303 }
 304 static inline int pci_iov_bus_range(struct pci_bus *bus)
 305 {
 306         return 0;
 307 }
 308
 309 static inline int pci_enable_ats(struct pci_dev *dev, int ps)
 310 {
 311         return -ENODEV;
 312 }
 313 static inline void pci_disable_ats(struct pci_dev *dev)
 314 {
 315 }
 316 static inline int pci_ats_queue_depth(struct pci_dev *dev)
 317 {
 318         return -ENODEV;
 319 }
 320 static inline int pci_ats_enabled(struct pci_dev *dev)
 321 {
 322         return 0;
 323 }
 324 #endif /* CONFIG_PCI_IOV */
 325
 326 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 327                                          struct resource *res)
 328 {
 329 #ifdef CONFIG_PCI_IOV
 330         int resno = res - dev->resource;
 331
 332         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 333                 return pci_sriov_resource_alignment(dev, resno);
 334 #endif
 335         return resource_alignment(res);
 336 }
 337
 338 extern void pci_enable_acs(struct pci_dev *dev);
 339
 340 struct pci_dev_reset_methods {
 341         u16 vendor;
 342         u16 device;
 343         int (*reset)(struct pci_dev *dev, int probe);
 344 };
 345
 346 #ifdef CONFIG_PCI_QUIRKS
 347 extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 348 #else
 349 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 350 {
 351         return -ENOTTY;
 352 }
 353 #endif
 354
 355 #endif /* DRIVERS_PCI_H */