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ath9k: sync the dma buffer after changing the retry flag
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobfa3dcfdf71743255771dd4c6f314687ff2ca0b0b
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35
36 static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 };
47
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb);
68
69 enum {
70 MCS_HT20,
71 MCS_HT20_SGI,
72 MCS_HT40,
73 MCS_HT40_SGI,
74 };
75
76 static int ath_max_4ms_framelen[4][32] = {
77 [MCS_HT20] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
82 },
83 [MCS_HT20_SGI] = {
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
88 },
89 [MCS_HT40] = {
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
94 },
95 [MCS_HT40_SGI] = {
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
100 }
101 };
102
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
106
107 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
108 {
109 struct ath_atx_ac *ac = tid->ac;
110
111 if (tid->paused)
112 return;
113
114 if (tid->sched)
115 return;
116
117 tid->sched = true;
118 list_add_tail(&tid->list, &ac->tid_q);
119
120 if (ac->sched)
121 return;
122
123 ac->sched = true;
124 list_add_tail(&ac->list, &txq->axq_acq);
125 }
126
127 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128 {
129 struct ath_txq *txq = tid->ac->txq;
130
131 WARN_ON(!tid->paused);
132
133 spin_lock_bh(&txq->axq_lock);
134 tid->paused = false;
135
136 if (skb_queue_empty(&tid->buf_q))
137 goto unlock;
138
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
141 unlock:
142 spin_unlock_bh(&txq->axq_lock);
143 }
144
145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
146 {
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
151 }
152
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
154 {
155 struct ath_txq *txq = tid->ac->txq;
156 struct sk_buff *skb;
157 struct ath_buf *bf;
158 struct list_head bf_head;
159 struct ath_tx_status ts;
160 struct ath_frame_info *fi;
161
162 INIT_LIST_HEAD(&bf_head);
163
164 memset(&ts, 0, sizeof(ts));
165 spin_lock_bh(&txq->axq_lock);
166
167 while ((skb = __skb_dequeue(&tid->buf_q))) {
168 fi = get_frame_info(skb);
169 bf = fi->bf;
170
171 spin_unlock_bh(&txq->axq_lock);
172 if (bf && fi->retries) {
173 list_add_tail(&bf->list, &bf_head);
174 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
175 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
176 } else {
177 ath_tx_send_normal(sc, txq, NULL, skb);
178 }
179 spin_lock_bh(&txq->axq_lock);
180 }
181
182 spin_unlock_bh(&txq->axq_lock);
183 }
184
185 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
186 int seqno)
187 {
188 int index, cindex;
189
190 index = ATH_BA_INDEX(tid->seq_start, seqno);
191 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
192
193 __clear_bit(cindex, tid->tx_buf);
194
195 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
196 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
197 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
198 }
199 }
200
201 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
202 u16 seqno)
203 {
204 int index, cindex;
205
206 index = ATH_BA_INDEX(tid->seq_start, seqno);
207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
208 __set_bit(cindex, tid->tx_buf);
209
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
214 }
215 }
216
217 /*
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
221 * forward.
222 */
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
225
226 {
227 struct sk_buff *skb;
228 struct ath_buf *bf;
229 struct list_head bf_head;
230 struct ath_tx_status ts;
231 struct ath_frame_info *fi;
232
233 memset(&ts, 0, sizeof(ts));
234 INIT_LIST_HEAD(&bf_head);
235
236 while ((skb = __skb_dequeue(&tid->buf_q))) {
237 fi = get_frame_info(skb);
238 bf = fi->bf;
239
240 if (!bf) {
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
243 spin_lock(&txq->axq_lock);
244 continue;
245 }
246
247 list_add_tail(&bf->list, &bf_head);
248
249 if (fi->retries)
250 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
251
252 spin_unlock(&txq->axq_lock);
253 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
254 spin_lock(&txq->axq_lock);
255 }
256
257 tid->seq_next = tid->seq_start;
258 tid->baw_tail = tid->baw_head;
259 }
260
261 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
262 struct sk_buff *skb)
263 {
264 struct ath_frame_info *fi = get_frame_info(skb);
265 struct ath_buf *bf = fi->bf;
266 struct ieee80211_hdr *hdr;
267
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
270 return;
271
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
274 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
275 sizeof(*hdr), DMA_TO_DEVICE);
276 }
277
278 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
279 {
280 struct ath_buf *bf = NULL;
281
282 spin_lock_bh(&sc->tx.txbuflock);
283
284 if (unlikely(list_empty(&sc->tx.txbuf))) {
285 spin_unlock_bh(&sc->tx.txbuflock);
286 return NULL;
287 }
288
289 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
290 list_del(&bf->list);
291
292 spin_unlock_bh(&sc->tx.txbuflock);
293
294 return bf;
295 }
296
297 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
298 {
299 spin_lock_bh(&sc->tx.txbuflock);
300 list_add_tail(&bf->list, &sc->tx.txbuf);
301 spin_unlock_bh(&sc->tx.txbuflock);
302 }
303
304 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
305 {
306 struct ath_buf *tbf;
307
308 tbf = ath_tx_get_buffer(sc);
309 if (WARN_ON(!tbf))
310 return NULL;
311
312 ATH_TXBUF_RESET(tbf);
313
314 tbf->bf_mpdu = bf->bf_mpdu;
315 tbf->bf_buf_addr = bf->bf_buf_addr;
316 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
317 tbf->bf_state = bf->bf_state;
318
319 return tbf;
320 }
321
322 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
323 struct ath_tx_status *ts, int txok,
324 int *nframes, int *nbad)
325 {
326 struct ath_frame_info *fi;
327 u16 seq_st = 0;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
329 int ba_index;
330 int isaggr = 0;
331
332 *nbad = 0;
333 *nframes = 0;
334
335 isaggr = bf_isaggr(bf);
336 if (isaggr) {
337 seq_st = ts->ts_seqnum;
338 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
339 }
340
341 while (bf) {
342 fi = get_frame_info(bf->bf_mpdu);
343 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
344
345 (*nframes)++;
346 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
347 (*nbad)++;
348
349 bf = bf->bf_next;
350 }
351 }
352
353
354 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
355 struct ath_buf *bf, struct list_head *bf_q,
356 struct ath_tx_status *ts, int txok, bool retry)
357 {
358 struct ath_node *an = NULL;
359 struct sk_buff *skb;
360 struct ieee80211_sta *sta;
361 struct ieee80211_hw *hw = sc->hw;
362 struct ieee80211_hdr *hdr;
363 struct ieee80211_tx_info *tx_info;
364 struct ath_atx_tid *tid = NULL;
365 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
366 struct list_head bf_head;
367 struct sk_buff_head bf_pending;
368 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
370 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
371 bool rc_update = true;
372 struct ieee80211_tx_rate rates[4];
373 struct ath_frame_info *fi;
374 int nframes;
375 u8 tidno;
376 bool clear_filter;
377
378 skb = bf->bf_mpdu;
379 hdr = (struct ieee80211_hdr *)skb->data;
380
381 tx_info = IEEE80211_SKB_CB(skb);
382
383 memcpy(rates, tx_info->control.rates, sizeof(rates));
384
385 rcu_read_lock();
386
387 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
388 if (!sta) {
389 rcu_read_unlock();
390
391 INIT_LIST_HEAD(&bf_head);
392 while (bf) {
393 bf_next = bf->bf_next;
394
395 if (!bf->bf_stale || bf_next != NULL)
396 list_move_tail(&bf->list, &bf_head);
397
398 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
399 0, 0);
400
401 bf = bf_next;
402 }
403 return;
404 }
405
406 an = (struct ath_node *)sta->drv_priv;
407 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
408 tid = ATH_AN_2_TID(an, tidno);
409
410 /*
411 * The hardware occasionally sends a tx status for the wrong TID.
412 * In this case, the BA status cannot be considered valid and all
413 * subframes need to be retransmitted
414 */
415 if (tidno != ts->tid)
416 txok = false;
417
418 isaggr = bf_isaggr(bf);
419 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
420
421 if (isaggr && txok) {
422 if (ts->ts_flags & ATH9K_TX_BA) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
425 } else {
426 /*
427 * AR5416 can become deaf/mute when BA
428 * issue happens. Chip needs to be reset.
429 * But AP code may have sychronization issues
430 * when perform internal reset in this routine.
431 * Only enable reset in STA mode for now.
432 */
433 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
434 needreset = 1;
435 }
436 }
437
438 __skb_queue_head_init(&bf_pending);
439
440 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
441 while (bf) {
442 u16 seqno = bf->bf_state.seqno;
443
444 txfail = txpending = sendbar = 0;
445 bf_next = bf->bf_next;
446
447 skb = bf->bf_mpdu;
448 tx_info = IEEE80211_SKB_CB(skb);
449 fi = get_frame_info(skb);
450
451 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
452 /* transmit completion, subframe is
453 * acked by block ack */
454 acked_cnt++;
455 } else if (!isaggr && txok) {
456 /* transmit completion */
457 acked_cnt++;
458 } else {
459 if ((tid->state & AGGR_CLEANUP) || !retry) {
460 /*
461 * cleanup in progress, just fail
462 * the un-acked sub-frames
463 */
464 txfail = 1;
465 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
466 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
467 !an->sleeping)
468 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
469
470 clear_filter = true;
471 txpending = 1;
472 } else {
473 txfail = 1;
474 sendbar = 1;
475 txfail_cnt++;
476 }
477 }
478
479 /*
480 * Make sure the last desc is reclaimed if it
481 * not a holding desc.
482 */
483 INIT_LIST_HEAD(&bf_head);
484 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
485 bf_next != NULL || !bf_last->bf_stale)
486 list_move_tail(&bf->list, &bf_head);
487
488 if (!txpending || (tid->state & AGGR_CLEANUP)) {
489 /*
490 * complete the acked-ones/xretried ones; update
491 * block-ack window
492 */
493 spin_lock_bh(&txq->axq_lock);
494 ath_tx_update_baw(sc, tid, seqno);
495 spin_unlock_bh(&txq->axq_lock);
496
497 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
498 memcpy(tx_info->control.rates, rates, sizeof(rates));
499 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
500 rc_update = false;
501 }
502
503 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
504 !txfail, sendbar);
505 } else {
506 /* retry the un-acked ones */
507 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
508 if (bf->bf_next == NULL && bf_last->bf_stale) {
509 struct ath_buf *tbf;
510
511 tbf = ath_clone_txbuf(sc, bf_last);
512 /*
513 * Update tx baw and complete the
514 * frame with failed status if we
515 * run out of tx buf.
516 */
517 if (!tbf) {
518 spin_lock_bh(&txq->axq_lock);
519 ath_tx_update_baw(sc, tid, seqno);
520 spin_unlock_bh(&txq->axq_lock);
521
522 ath_tx_complete_buf(sc, bf, txq,
523 &bf_head,
524 ts, 0, 1);
525 break;
526 }
527
528 fi->bf = tbf;
529 }
530 }
531
532 /*
533 * Put this buffer to the temporary pending
534 * queue to retain ordering
535 */
536 __skb_queue_tail(&bf_pending, skb);
537 }
538
539 bf = bf_next;
540 }
541
542 /* prepend un-acked frames to the beginning of the pending frame queue */
543 if (!skb_queue_empty(&bf_pending)) {
544 if (an->sleeping)
545 ieee80211_sta_set_tim(sta);
546
547 spin_lock_bh(&txq->axq_lock);
548 if (clear_filter)
549 tid->ac->clear_ps_filter = true;
550 skb_queue_splice(&bf_pending, &tid->buf_q);
551 if (!an->sleeping)
552 ath_tx_queue_tid(txq, tid);
553 spin_unlock_bh(&txq->axq_lock);
554 }
555
556 if (tid->state & AGGR_CLEANUP) {
557 ath_tx_flush_tid(sc, tid);
558
559 if (tid->baw_head == tid->baw_tail) {
560 tid->state &= ~AGGR_ADDBA_COMPLETE;
561 tid->state &= ~AGGR_CLEANUP;
562 }
563 }
564
565 rcu_read_unlock();
566
567 if (needreset)
568 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
569 }
570
571 static bool ath_lookup_legacy(struct ath_buf *bf)
572 {
573 struct sk_buff *skb;
574 struct ieee80211_tx_info *tx_info;
575 struct ieee80211_tx_rate *rates;
576 int i;
577
578 skb = bf->bf_mpdu;
579 tx_info = IEEE80211_SKB_CB(skb);
580 rates = tx_info->control.rates;
581
582 for (i = 0; i < 4; i++) {
583 if (!rates[i].count || rates[i].idx < 0)
584 break;
585
586 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
587 return true;
588 }
589
590 return false;
591 }
592
593 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
594 struct ath_atx_tid *tid)
595 {
596 struct sk_buff *skb;
597 struct ieee80211_tx_info *tx_info;
598 struct ieee80211_tx_rate *rates;
599 u32 max_4ms_framelen, frmlen;
600 u16 aggr_limit, legacy = 0;
601 int i;
602
603 skb = bf->bf_mpdu;
604 tx_info = IEEE80211_SKB_CB(skb);
605 rates = tx_info->control.rates;
606
607 /*
608 * Find the lowest frame length among the rate series that will have a
609 * 4ms transmit duration.
610 * TODO - TXOP limit needs to be considered.
611 */
612 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
613
614 for (i = 0; i < 4; i++) {
615 if (rates[i].count) {
616 int modeidx;
617 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
618 legacy = 1;
619 break;
620 }
621
622 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
623 modeidx = MCS_HT40;
624 else
625 modeidx = MCS_HT20;
626
627 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
628 modeidx++;
629
630 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
631 max_4ms_framelen = min(max_4ms_framelen, frmlen);
632 }
633 }
634
635 /*
636 * limit aggregate size by the minimum rate if rate selected is
637 * not a probe rate, if rate selected is a probe rate then
638 * avoid aggregation of this packet.
639 */
640 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
641 return 0;
642
643 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
644 aggr_limit = min((max_4ms_framelen * 3) / 8,
645 (u32)ATH_AMPDU_LIMIT_MAX);
646 else
647 aggr_limit = min(max_4ms_framelen,
648 (u32)ATH_AMPDU_LIMIT_MAX);
649
650 /*
651 * h/w can accept aggregates up to 16 bit lengths (65535).
652 * The IE, however can hold up to 65536, which shows up here
653 * as zero. Ignore 65536 since we are constrained by hw.
654 */
655 if (tid->an->maxampdu)
656 aggr_limit = min(aggr_limit, tid->an->maxampdu);
657
658 return aggr_limit;
659 }
660
661 /*
662 * Returns the number of delimiters to be added to
663 * meet the minimum required mpdudensity.
664 */
665 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
666 struct ath_buf *bf, u16 frmlen,
667 bool first_subfrm)
668 {
669 #define FIRST_DESC_NDELIMS 60
670 struct sk_buff *skb = bf->bf_mpdu;
671 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
672 u32 nsymbits, nsymbols;
673 u16 minlen;
674 u8 flags, rix;
675 int width, streams, half_gi, ndelim, mindelim;
676 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
677
678 /* Select standard number of delimiters based on frame length alone */
679 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
680
681 /*
682 * If encryption enabled, hardware requires some more padding between
683 * subframes.
684 * TODO - this could be improved to be dependent on the rate.
685 * The hardware can keep up at lower rates, but not higher rates
686 */
687 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
688 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
689 ndelim += ATH_AGGR_ENCRYPTDELIM;
690
691 /*
692 * Add delimiter when using RTS/CTS with aggregation
693 * and non enterprise AR9003 card
694 */
695 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
696 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
697 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
698
699 /*
700 * Convert desired mpdu density from microeconds to bytes based
701 * on highest rate in rate series (i.e. first rate) to determine
702 * required minimum length for subframe. Take into account
703 * whether high rate is 20 or 40Mhz and half or full GI.
704 *
705 * If there is no mpdu density restriction, no further calculation
706 * is needed.
707 */
708
709 if (tid->an->mpdudensity == 0)
710 return ndelim;
711
712 rix = tx_info->control.rates[0].idx;
713 flags = tx_info->control.rates[0].flags;
714 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
715 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
716
717 if (half_gi)
718 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
719 else
720 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
721
722 if (nsymbols == 0)
723 nsymbols = 1;
724
725 streams = HT_RC_2_STREAMS(rix);
726 nsymbits = bits_per_symbol[rix % 8][width] * streams;
727 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
728
729 if (frmlen < minlen) {
730 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
731 ndelim = max(mindelim, ndelim);
732 }
733
734 return ndelim;
735 }
736
737 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
738 struct ath_txq *txq,
739 struct ath_atx_tid *tid,
740 struct list_head *bf_q,
741 int *aggr_len)
742 {
743 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
744 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
745 int rl = 0, nframes = 0, ndelim, prev_al = 0;
746 u16 aggr_limit = 0, al = 0, bpad = 0,
747 al_delta, h_baw = tid->baw_size / 2;
748 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
749 struct ieee80211_tx_info *tx_info;
750 struct ath_frame_info *fi;
751 struct sk_buff *skb;
752 u16 seqno;
753
754 do {
755 skb = skb_peek(&tid->buf_q);
756 fi = get_frame_info(skb);
757 bf = fi->bf;
758 if (!fi->bf)
759 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
760
761 if (!bf)
762 continue;
763
764 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
765 seqno = bf->bf_state.seqno;
766 if (!bf_first)
767 bf_first = bf;
768
769 /* do not step over block-ack window */
770 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
771 status = ATH_AGGR_BAW_CLOSED;
772 break;
773 }
774
775 if (!rl) {
776 aggr_limit = ath_lookup_rate(sc, bf, tid);
777 rl = 1;
778 }
779
780 /* do not exceed aggregation limit */
781 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
782
783 if (nframes &&
784 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
785 ath_lookup_legacy(bf))) {
786 status = ATH_AGGR_LIMITED;
787 break;
788 }
789
790 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
791 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
792 break;
793
794 /* do not exceed subframe limit */
795 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
796 status = ATH_AGGR_LIMITED;
797 break;
798 }
799
800 /* add padding for previous frame to aggregation length */
801 al += bpad + al_delta;
802
803 /*
804 * Get the delimiters needed to meet the MPDU
805 * density for this node.
806 */
807 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
808 !nframes);
809 bpad = PADBYTES(al_delta) + (ndelim << 2);
810
811 nframes++;
812 bf->bf_next = NULL;
813
814 /* link buffers of this frame to the aggregate */
815 if (!fi->retries)
816 ath_tx_addto_baw(sc, tid, seqno);
817 bf->bf_state.ndelim = ndelim;
818
819 __skb_unlink(skb, &tid->buf_q);
820 list_add_tail(&bf->list, bf_q);
821 if (bf_prev)
822 bf_prev->bf_next = bf;
823
824 bf_prev = bf;
825
826 } while (!skb_queue_empty(&tid->buf_q));
827
828 *aggr_len = al;
829
830 return status;
831 #undef PADBYTES
832 }
833
834 /*
835 * rix - rate index
836 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
837 * width - 0 for 20 MHz, 1 for 40 MHz
838 * half_gi - to use 4us v/s 3.6 us for symbol time
839 */
840 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
841 int width, int half_gi, bool shortPreamble)
842 {
843 u32 nbits, nsymbits, duration, nsymbols;
844 int streams;
845
846 /* find number of symbols: PLCP + data */
847 streams = HT_RC_2_STREAMS(rix);
848 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
849 nsymbits = bits_per_symbol[rix % 8][width] * streams;
850 nsymbols = (nbits + nsymbits - 1) / nsymbits;
851
852 if (!half_gi)
853 duration = SYMBOL_TIME(nsymbols);
854 else
855 duration = SYMBOL_TIME_HALFGI(nsymbols);
856
857 /* addup duration for legacy/ht training and signal fields */
858 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
859
860 return duration;
861 }
862
863 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
864 struct ath_tx_info *info, int len)
865 {
866 struct ath_hw *ah = sc->sc_ah;
867 struct sk_buff *skb;
868 struct ieee80211_tx_info *tx_info;
869 struct ieee80211_tx_rate *rates;
870 const struct ieee80211_rate *rate;
871 struct ieee80211_hdr *hdr;
872 int i;
873 u8 rix = 0;
874
875 skb = bf->bf_mpdu;
876 tx_info = IEEE80211_SKB_CB(skb);
877 rates = tx_info->control.rates;
878 hdr = (struct ieee80211_hdr *)skb->data;
879
880 /* set dur_update_en for l-sig computation except for PS-Poll frames */
881 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
882
883 /*
884 * We check if Short Preamble is needed for the CTS rate by
885 * checking the BSS's global flag.
886 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
887 */
888 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
889 info->rtscts_rate = rate->hw_value;
890 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
891 info->rtscts_rate |= rate->hw_value_short;
892
893 for (i = 0; i < 4; i++) {
894 bool is_40, is_sgi, is_sp;
895 int phy;
896
897 if (!rates[i].count || (rates[i].idx < 0))
898 continue;
899
900 rix = rates[i].idx;
901 info->rates[i].Tries = rates[i].count;
902
903 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
904 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
905 info->flags |= ATH9K_TXDESC_RTSENA;
906 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
907 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
908 info->flags |= ATH9K_TXDESC_CTSENA;
909 }
910
911 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
912 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
913 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
914 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
915
916 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
917 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
918 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
919
920 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
921 /* MCS rates */
922 info->rates[i].Rate = rix | 0x80;
923 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
924 ah->txchainmask, info->rates[i].Rate);
925 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
926 is_40, is_sgi, is_sp);
927 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
928 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
929 continue;
930 }
931
932 /* legacy rates */
933 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
934 !(rate->flags & IEEE80211_RATE_ERP_G))
935 phy = WLAN_RC_PHY_CCK;
936 else
937 phy = WLAN_RC_PHY_OFDM;
938
939 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
940 info->rates[i].Rate = rate->hw_value;
941 if (rate->hw_value_short) {
942 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
943 info->rates[i].Rate |= rate->hw_value_short;
944 } else {
945 is_sp = false;
946 }
947
948 if (bf->bf_state.bfs_paprd)
949 info->rates[i].ChSel = ah->txchainmask;
950 else
951 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
952 ah->txchainmask, info->rates[i].Rate);
953
954 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
955 phy, rate->bitrate * 100, len, rix, is_sp);
956 }
957
958 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
959 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
960 info->flags &= ~ATH9K_TXDESC_RTSENA;
961
962 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
963 if (info->flags & ATH9K_TXDESC_RTSENA)
964 info->flags &= ~ATH9K_TXDESC_CTSENA;
965 }
966
967 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
968 {
969 struct ieee80211_hdr *hdr;
970 enum ath9k_pkt_type htype;
971 __le16 fc;
972
973 hdr = (struct ieee80211_hdr *)skb->data;
974 fc = hdr->frame_control;
975
976 if (ieee80211_is_beacon(fc))
977 htype = ATH9K_PKT_TYPE_BEACON;
978 else if (ieee80211_is_probe_resp(fc))
979 htype = ATH9K_PKT_TYPE_PROBE_RESP;
980 else if (ieee80211_is_atim(fc))
981 htype = ATH9K_PKT_TYPE_ATIM;
982 else if (ieee80211_is_pspoll(fc))
983 htype = ATH9K_PKT_TYPE_PSPOLL;
984 else
985 htype = ATH9K_PKT_TYPE_NORMAL;
986
987 return htype;
988 }
989
990 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
991 struct ath_txq *txq, int len)
992 {
993 struct ath_hw *ah = sc->sc_ah;
994 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
995 struct ath_buf *bf_first = bf;
996 struct ath_tx_info info;
997 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
998
999 memset(&info, 0, sizeof(info));
1000 info.is_first = true;
1001 info.is_last = true;
1002 info.txpower = MAX_RATE_POWER;
1003 info.qcu = txq->axq_qnum;
1004
1005 info.flags = ATH9K_TXDESC_INTREQ;
1006 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1007 info.flags |= ATH9K_TXDESC_NOACK;
1008 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1009 info.flags |= ATH9K_TXDESC_LDPC;
1010
1011 ath_buf_set_rate(sc, bf, &info, len);
1012
1013 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1014 info.flags |= ATH9K_TXDESC_CLRDMASK;
1015
1016 if (bf->bf_state.bfs_paprd)
1017 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1018
1019
1020 while (bf) {
1021 struct sk_buff *skb = bf->bf_mpdu;
1022 struct ath_frame_info *fi = get_frame_info(skb);
1023
1024 info.type = get_hw_packet_type(skb);
1025 if (bf->bf_next)
1026 info.link = bf->bf_next->bf_daddr;
1027 else
1028 info.link = 0;
1029
1030 info.buf_addr[0] = bf->bf_buf_addr;
1031 info.buf_len[0] = skb->len;
1032 info.pkt_len = fi->framelen;
1033 info.keyix = fi->keyix;
1034 info.keytype = fi->keytype;
1035
1036 if (aggr) {
1037 if (bf == bf_first)
1038 info.aggr = AGGR_BUF_FIRST;
1039 else if (!bf->bf_next)
1040 info.aggr = AGGR_BUF_LAST;
1041 else
1042 info.aggr = AGGR_BUF_MIDDLE;
1043
1044 info.ndelim = bf->bf_state.ndelim;
1045 info.aggr_len = len;
1046 }
1047
1048 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1049 bf = bf->bf_next;
1050 }
1051 }
1052
1053 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1054 struct ath_atx_tid *tid)
1055 {
1056 struct ath_buf *bf;
1057 enum ATH_AGGR_STATUS status;
1058 struct ieee80211_tx_info *tx_info;
1059 struct list_head bf_q;
1060 int aggr_len;
1061
1062 do {
1063 if (skb_queue_empty(&tid->buf_q))
1064 return;
1065
1066 INIT_LIST_HEAD(&bf_q);
1067
1068 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1069
1070 /*
1071 * no frames picked up to be aggregated;
1072 * block-ack window is not open.
1073 */
1074 if (list_empty(&bf_q))
1075 break;
1076
1077 bf = list_first_entry(&bf_q, struct ath_buf, list);
1078 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1079 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1080
1081 if (tid->ac->clear_ps_filter) {
1082 tid->ac->clear_ps_filter = false;
1083 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1084 } else {
1085 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1086 }
1087
1088 /* if only one frame, send as non-aggregate */
1089 if (bf == bf->bf_lastbf) {
1090 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1091 bf->bf_state.bf_type = BUF_AMPDU;
1092 } else {
1093 TX_STAT_INC(txq->axq_qnum, a_aggr);
1094 }
1095
1096 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1097 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1098 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1099 status != ATH_AGGR_BAW_CLOSED);
1100 }
1101
1102 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1103 u16 tid, u16 *ssn)
1104 {
1105 struct ath_atx_tid *txtid;
1106 struct ath_node *an;
1107
1108 an = (struct ath_node *)sta->drv_priv;
1109 txtid = ATH_AN_2_TID(an, tid);
1110
1111 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1112 return -EAGAIN;
1113
1114 txtid->state |= AGGR_ADDBA_PROGRESS;
1115 txtid->paused = true;
1116 *ssn = txtid->seq_start = txtid->seq_next;
1117
1118 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1119 txtid->baw_head = txtid->baw_tail = 0;
1120
1121 return 0;
1122 }
1123
1124 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1125 {
1126 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1127 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1128 struct ath_txq *txq = txtid->ac->txq;
1129
1130 if (txtid->state & AGGR_CLEANUP)
1131 return;
1132
1133 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1134 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1135 return;
1136 }
1137
1138 spin_lock_bh(&txq->axq_lock);
1139 txtid->paused = true;
1140
1141 /*
1142 * If frames are still being transmitted for this TID, they will be
1143 * cleaned up during tx completion. To prevent race conditions, this
1144 * TID can only be reused after all in-progress subframes have been
1145 * completed.
1146 */
1147 if (txtid->baw_head != txtid->baw_tail)
1148 txtid->state |= AGGR_CLEANUP;
1149 else
1150 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1151 spin_unlock_bh(&txq->axq_lock);
1152
1153 ath_tx_flush_tid(sc, txtid);
1154 }
1155
1156 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
1157 {
1158 struct ath_atx_tid *tid;
1159 struct ath_atx_ac *ac;
1160 struct ath_txq *txq;
1161 bool buffered = false;
1162 int tidno;
1163
1164 for (tidno = 0, tid = &an->tid[tidno];
1165 tidno < WME_NUM_TID; tidno++, tid++) {
1166
1167 if (!tid->sched)
1168 continue;
1169
1170 ac = tid->ac;
1171 txq = ac->txq;
1172
1173 spin_lock_bh(&txq->axq_lock);
1174
1175 if (!skb_queue_empty(&tid->buf_q))
1176 buffered = true;
1177
1178 tid->sched = false;
1179 list_del(&tid->list);
1180
1181 if (ac->sched) {
1182 ac->sched = false;
1183 list_del(&ac->list);
1184 }
1185
1186 spin_unlock_bh(&txq->axq_lock);
1187 }
1188
1189 return buffered;
1190 }
1191
1192 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1193 {
1194 struct ath_atx_tid *tid;
1195 struct ath_atx_ac *ac;
1196 struct ath_txq *txq;
1197 int tidno;
1198
1199 for (tidno = 0, tid = &an->tid[tidno];
1200 tidno < WME_NUM_TID; tidno++, tid++) {
1201
1202 ac = tid->ac;
1203 txq = ac->txq;
1204
1205 spin_lock_bh(&txq->axq_lock);
1206 ac->clear_ps_filter = true;
1207
1208 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1209 ath_tx_queue_tid(txq, tid);
1210 ath_txq_schedule(sc, txq);
1211 }
1212
1213 spin_unlock_bh(&txq->axq_lock);
1214 }
1215 }
1216
1217 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1218 {
1219 struct ath_atx_tid *txtid;
1220 struct ath_node *an;
1221
1222 an = (struct ath_node *)sta->drv_priv;
1223
1224 if (sc->sc_flags & SC_OP_TXAGGR) {
1225 txtid = ATH_AN_2_TID(an, tid);
1226 txtid->baw_size =
1227 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1228 txtid->state |= AGGR_ADDBA_COMPLETE;
1229 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1230 ath_tx_resume_tid(sc, txtid);
1231 }
1232 }
1233
1234 /********************/
1235 /* Queue Management */
1236 /********************/
1237
1238 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1239 struct ath_txq *txq)
1240 {
1241 struct ath_atx_ac *ac, *ac_tmp;
1242 struct ath_atx_tid *tid, *tid_tmp;
1243
1244 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1245 list_del(&ac->list);
1246 ac->sched = false;
1247 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1248 list_del(&tid->list);
1249 tid->sched = false;
1250 ath_tid_drain(sc, txq, tid);
1251 }
1252 }
1253 }
1254
1255 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1256 {
1257 struct ath_hw *ah = sc->sc_ah;
1258 struct ath_common *common = ath9k_hw_common(ah);
1259 struct ath9k_tx_queue_info qi;
1260 static const int subtype_txq_to_hwq[] = {
1261 [WME_AC_BE] = ATH_TXQ_AC_BE,
1262 [WME_AC_BK] = ATH_TXQ_AC_BK,
1263 [WME_AC_VI] = ATH_TXQ_AC_VI,
1264 [WME_AC_VO] = ATH_TXQ_AC_VO,
1265 };
1266 int axq_qnum, i;
1267
1268 memset(&qi, 0, sizeof(qi));
1269 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1270 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1271 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1272 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1273 qi.tqi_physCompBuf = 0;
1274
1275 /*
1276 * Enable interrupts only for EOL and DESC conditions.
1277 * We mark tx descriptors to receive a DESC interrupt
1278 * when a tx queue gets deep; otherwise waiting for the
1279 * EOL to reap descriptors. Note that this is done to
1280 * reduce interrupt load and this only defers reaping
1281 * descriptors, never transmitting frames. Aside from
1282 * reducing interrupts this also permits more concurrency.
1283 * The only potential downside is if the tx queue backs
1284 * up in which case the top half of the kernel may backup
1285 * due to a lack of tx descriptors.
1286 *
1287 * The UAPSD queue is an exception, since we take a desc-
1288 * based intr on the EOSP frames.
1289 */
1290 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1291 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1292 TXQ_FLAG_TXERRINT_ENABLE;
1293 } else {
1294 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1295 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1296 else
1297 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1298 TXQ_FLAG_TXDESCINT_ENABLE;
1299 }
1300 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1301 if (axq_qnum == -1) {
1302 /*
1303 * NB: don't print a message, this happens
1304 * normally on parts with too few tx queues
1305 */
1306 return NULL;
1307 }
1308 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1309 ath_err(common, "qnum %u out of range, max %zu!\n",
1310 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1311 ath9k_hw_releasetxqueue(ah, axq_qnum);
1312 return NULL;
1313 }
1314 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1315 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1316
1317 txq->axq_qnum = axq_qnum;
1318 txq->mac80211_qnum = -1;
1319 txq->axq_link = NULL;
1320 INIT_LIST_HEAD(&txq->axq_q);
1321 INIT_LIST_HEAD(&txq->axq_acq);
1322 spin_lock_init(&txq->axq_lock);
1323 txq->axq_depth = 0;
1324 txq->axq_ampdu_depth = 0;
1325 txq->axq_tx_inprogress = false;
1326 sc->tx.txqsetup |= 1<<axq_qnum;
1327
1328 txq->txq_headidx = txq->txq_tailidx = 0;
1329 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1330 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1331 }
1332 return &sc->tx.txq[axq_qnum];
1333 }
1334
1335 int ath_txq_update(struct ath_softc *sc, int qnum,
1336 struct ath9k_tx_queue_info *qinfo)
1337 {
1338 struct ath_hw *ah = sc->sc_ah;
1339 int error = 0;
1340 struct ath9k_tx_queue_info qi;
1341
1342 if (qnum == sc->beacon.beaconq) {
1343 /*
1344 * XXX: for beacon queue, we just save the parameter.
1345 * It will be picked up by ath_beaconq_config when
1346 * it's necessary.
1347 */
1348 sc->beacon.beacon_qi = *qinfo;
1349 return 0;
1350 }
1351
1352 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1353
1354 ath9k_hw_get_txq_props(ah, qnum, &qi);
1355 qi.tqi_aifs = qinfo->tqi_aifs;
1356 qi.tqi_cwmin = qinfo->tqi_cwmin;
1357 qi.tqi_cwmax = qinfo->tqi_cwmax;
1358 qi.tqi_burstTime = qinfo->tqi_burstTime;
1359 qi.tqi_readyTime = qinfo->tqi_readyTime;
1360
1361 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1362 ath_err(ath9k_hw_common(sc->sc_ah),
1363 "Unable to update hardware queue %u!\n", qnum);
1364 error = -EIO;
1365 } else {
1366 ath9k_hw_resettxqueue(ah, qnum);
1367 }
1368
1369 return error;
1370 }
1371
1372 int ath_cabq_update(struct ath_softc *sc)
1373 {
1374 struct ath9k_tx_queue_info qi;
1375 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1376 int qnum = sc->beacon.cabq->axq_qnum;
1377
1378 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1379 /*
1380 * Ensure the readytime % is within the bounds.
1381 */
1382 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1383 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1384 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1385 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1386
1387 qi.tqi_readyTime = (cur_conf->beacon_interval *
1388 sc->config.cabqReadytime) / 100;
1389 ath_txq_update(sc, qnum, &qi);
1390
1391 return 0;
1392 }
1393
1394 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1395 {
1396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1397 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1398 }
1399
1400 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1401 struct list_head *list, bool retry_tx)
1402 __releases(txq->axq_lock)
1403 __acquires(txq->axq_lock)
1404 {
1405 struct ath_buf *bf, *lastbf;
1406 struct list_head bf_head;
1407 struct ath_tx_status ts;
1408
1409 memset(&ts, 0, sizeof(ts));
1410 INIT_LIST_HEAD(&bf_head);
1411
1412 while (!list_empty(list)) {
1413 bf = list_first_entry(list, struct ath_buf, list);
1414
1415 if (bf->bf_stale) {
1416 list_del(&bf->list);
1417
1418 ath_tx_return_buffer(sc, bf);
1419 continue;
1420 }
1421
1422 lastbf = bf->bf_lastbf;
1423 list_cut_position(&bf_head, list, &lastbf->list);
1424
1425 txq->axq_depth--;
1426 if (bf_is_ampdu_not_probing(bf))
1427 txq->axq_ampdu_depth--;
1428
1429 spin_unlock_bh(&txq->axq_lock);
1430 if (bf_isampdu(bf))
1431 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1432 retry_tx);
1433 else
1434 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1435 spin_lock_bh(&txq->axq_lock);
1436 }
1437 }
1438
1439 /*
1440 * Drain a given TX queue (could be Beacon or Data)
1441 *
1442 * This assumes output has been stopped and
1443 * we do not need to block ath_tx_tasklet.
1444 */
1445 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1446 {
1447 spin_lock_bh(&txq->axq_lock);
1448 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1449 int idx = txq->txq_tailidx;
1450
1451 while (!list_empty(&txq->txq_fifo[idx])) {
1452 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1453 retry_tx);
1454
1455 INCR(idx, ATH_TXFIFO_DEPTH);
1456 }
1457 txq->txq_tailidx = idx;
1458 }
1459
1460 txq->axq_link = NULL;
1461 txq->axq_tx_inprogress = false;
1462 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1463
1464 /* flush any pending frames if aggregation is enabled */
1465 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1466 ath_txq_drain_pending_buffers(sc, txq);
1467
1468 spin_unlock_bh(&txq->axq_lock);
1469 }
1470
1471 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1472 {
1473 struct ath_hw *ah = sc->sc_ah;
1474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1475 struct ath_txq *txq;
1476 int i, npend = 0;
1477
1478 if (sc->sc_flags & SC_OP_INVALID)
1479 return true;
1480
1481 ath9k_hw_abort_tx_dma(ah);
1482
1483 /* Check if any queue remains active */
1484 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1485 if (!ATH_TXQ_SETUP(sc, i))
1486 continue;
1487
1488 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1489 }
1490
1491 if (npend)
1492 ath_err(common, "Failed to stop TX DMA!\n");
1493
1494 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1495 if (!ATH_TXQ_SETUP(sc, i))
1496 continue;
1497
1498 /*
1499 * The caller will resume queues with ieee80211_wake_queues.
1500 * Mark the queue as not stopped to prevent ath_tx_complete
1501 * from waking the queue too early.
1502 */
1503 txq = &sc->tx.txq[i];
1504 txq->stopped = false;
1505 ath_draintxq(sc, txq, retry_tx);
1506 }
1507
1508 return !npend;
1509 }
1510
1511 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1512 {
1513 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1514 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1515 }
1516
1517 /* For each axq_acq entry, for each tid, try to schedule packets
1518 * for transmit until ampdu_depth has reached min Q depth.
1519 */
1520 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1521 {
1522 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1523 struct ath_atx_tid *tid, *last_tid;
1524
1525 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1526 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1527 return;
1528
1529 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1530 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1531
1532 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1533 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1534 list_del(&ac->list);
1535 ac->sched = false;
1536
1537 while (!list_empty(&ac->tid_q)) {
1538 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1539 list);
1540 list_del(&tid->list);
1541 tid->sched = false;
1542
1543 if (tid->paused)
1544 continue;
1545
1546 ath_tx_sched_aggr(sc, txq, tid);
1547
1548 /*
1549 * add tid to round-robin queue if more frames
1550 * are pending for the tid
1551 */
1552 if (!skb_queue_empty(&tid->buf_q))
1553 ath_tx_queue_tid(txq, tid);
1554
1555 if (tid == last_tid ||
1556 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1557 break;
1558 }
1559
1560 if (!list_empty(&ac->tid_q)) {
1561 if (!ac->sched) {
1562 ac->sched = true;
1563 list_add_tail(&ac->list, &txq->axq_acq);
1564 }
1565 }
1566
1567 if (ac == last_ac ||
1568 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1569 return;
1570 }
1571 }
1572
1573 /***********/
1574 /* TX, DMA */
1575 /***********/
1576
1577 /*
1578 * Insert a chain of ath_buf (descriptors) on a txq and
1579 * assume the descriptors are already chained together by caller.
1580 */
1581 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1582 struct list_head *head, bool internal)
1583 {
1584 struct ath_hw *ah = sc->sc_ah;
1585 struct ath_common *common = ath9k_hw_common(ah);
1586 struct ath_buf *bf, *bf_last;
1587 bool puttxbuf = false;
1588 bool edma;
1589
1590 /*
1591 * Insert the frame on the outbound list and
1592 * pass it on to the hardware.
1593 */
1594
1595 if (list_empty(head))
1596 return;
1597
1598 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1599 bf = list_first_entry(head, struct ath_buf, list);
1600 bf_last = list_entry(head->prev, struct ath_buf, list);
1601
1602 ath_dbg(common, ATH_DBG_QUEUE,
1603 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1604
1605 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1606 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1607 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1608 puttxbuf = true;
1609 } else {
1610 list_splice_tail_init(head, &txq->axq_q);
1611
1612 if (txq->axq_link) {
1613 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1614 ath_dbg(common, ATH_DBG_XMIT,
1615 "link[%u] (%p)=%llx (%p)\n",
1616 txq->axq_qnum, txq->axq_link,
1617 ito64(bf->bf_daddr), bf->bf_desc);
1618 } else if (!edma)
1619 puttxbuf = true;
1620
1621 txq->axq_link = bf_last->bf_desc;
1622 }
1623
1624 if (puttxbuf) {
1625 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1626 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1627 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1628 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1629 }
1630
1631 if (!edma) {
1632 TX_STAT_INC(txq->axq_qnum, txstart);
1633 ath9k_hw_txstart(ah, txq->axq_qnum);
1634 }
1635
1636 if (!internal) {
1637 txq->axq_depth++;
1638 if (bf_is_ampdu_not_probing(bf))
1639 txq->axq_ampdu_depth++;
1640 }
1641 }
1642
1643 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1644 struct sk_buff *skb, struct ath_tx_control *txctl)
1645 {
1646 struct ath_frame_info *fi = get_frame_info(skb);
1647 struct list_head bf_head;
1648 struct ath_buf *bf;
1649
1650 /*
1651 * Do not queue to h/w when any of the following conditions is true:
1652 * - there are pending frames in software queue
1653 * - the TID is currently paused for ADDBA/BAR request
1654 * - seqno is not within block-ack window
1655 * - h/w queue depth exceeds low water mark
1656 */
1657 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1658 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1659 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1660 /*
1661 * Add this frame to software queue for scheduling later
1662 * for aggregation.
1663 */
1664 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1665 __skb_queue_tail(&tid->buf_q, skb);
1666 if (!txctl->an || !txctl->an->sleeping)
1667 ath_tx_queue_tid(txctl->txq, tid);
1668 return;
1669 }
1670
1671 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1672 if (!bf)
1673 return;
1674
1675 bf->bf_state.bf_type = BUF_AMPDU;
1676 INIT_LIST_HEAD(&bf_head);
1677 list_add(&bf->list, &bf_head);
1678
1679 /* Add sub-frame to BAW */
1680 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1681
1682 /* Queue to h/w without aggregation */
1683 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1684 bf->bf_lastbf = bf;
1685 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1686 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1687 }
1688
1689 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1690 struct ath_atx_tid *tid, struct sk_buff *skb)
1691 {
1692 struct ath_frame_info *fi = get_frame_info(skb);
1693 struct list_head bf_head;
1694 struct ath_buf *bf;
1695
1696 bf = fi->bf;
1697 if (!bf)
1698 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1699
1700 if (!bf)
1701 return;
1702
1703 INIT_LIST_HEAD(&bf_head);
1704 list_add_tail(&bf->list, &bf_head);
1705 bf->bf_state.bf_type = 0;
1706
1707 /* update starting sequence number for subsequent ADDBA request */
1708 if (tid)
1709 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1710
1711 bf->bf_lastbf = bf;
1712 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1713 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1714 TX_STAT_INC(txq->axq_qnum, queued);
1715 }
1716
1717 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1718 int framelen)
1719 {
1720 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1721 struct ieee80211_sta *sta = tx_info->control.sta;
1722 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1723 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1724 struct ath_frame_info *fi = get_frame_info(skb);
1725 struct ath_node *an = NULL;
1726 enum ath9k_key_type keytype;
1727
1728 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1729
1730 if (sta)
1731 an = (struct ath_node *) sta->drv_priv;
1732
1733 memset(fi, 0, sizeof(*fi));
1734 if (hw_key)
1735 fi->keyix = hw_key->hw_key_idx;
1736 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1737 fi->keyix = an->ps_key;
1738 else
1739 fi->keyix = ATH9K_TXKEYIX_INVALID;
1740 fi->keytype = keytype;
1741 fi->framelen = framelen;
1742 }
1743
1744 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1745 {
1746 struct ath_hw *ah = sc->sc_ah;
1747 struct ath9k_channel *curchan = ah->curchan;
1748 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1749 (curchan->channelFlags & CHANNEL_5GHZ) &&
1750 (chainmask == 0x7) && (rate < 0x90))
1751 return 0x3;
1752 else
1753 return chainmask;
1754 }
1755
1756 /*
1757 * Assign a descriptor (and sequence number if necessary,
1758 * and map buffer for DMA. Frees skb on error
1759 */
1760 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1761 struct ath_txq *txq,
1762 struct ath_atx_tid *tid,
1763 struct sk_buff *skb)
1764 {
1765 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1766 struct ath_frame_info *fi = get_frame_info(skb);
1767 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1768 struct ath_buf *bf;
1769 u16 seqno;
1770
1771 bf = ath_tx_get_buffer(sc);
1772 if (!bf) {
1773 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1774 goto error;
1775 }
1776
1777 ATH_TXBUF_RESET(bf);
1778
1779 if (tid) {
1780 seqno = tid->seq_next;
1781 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1782 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1783 bf->bf_state.seqno = seqno;
1784 }
1785
1786 bf->bf_mpdu = skb;
1787
1788 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1789 skb->len, DMA_TO_DEVICE);
1790 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1791 bf->bf_mpdu = NULL;
1792 bf->bf_buf_addr = 0;
1793 ath_err(ath9k_hw_common(sc->sc_ah),
1794 "dma_mapping_error() on TX\n");
1795 ath_tx_return_buffer(sc, bf);
1796 goto error;
1797 }
1798
1799 fi->bf = bf;
1800
1801 return bf;
1802
1803 error:
1804 dev_kfree_skb_any(skb);
1805 return NULL;
1806 }
1807
1808 /* FIXME: tx power */
1809 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1810 struct ath_tx_control *txctl)
1811 {
1812 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1813 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1814 struct ath_atx_tid *tid = NULL;
1815 struct ath_buf *bf;
1816 u8 tidno;
1817
1818 spin_lock_bh(&txctl->txq->axq_lock);
1819 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1820 ieee80211_is_data_qos(hdr->frame_control)) {
1821 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1822 IEEE80211_QOS_CTL_TID_MASK;
1823 tid = ATH_AN_2_TID(txctl->an, tidno);
1824
1825 WARN_ON(tid->ac->txq != txctl->txq);
1826 }
1827
1828 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1829 /*
1830 * Try aggregation if it's a unicast data frame
1831 * and the destination is HT capable.
1832 */
1833 ath_tx_send_ampdu(sc, tid, skb, txctl);
1834 } else {
1835 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1836 if (!bf)
1837 goto out;
1838
1839 bf->bf_state.bfs_paprd = txctl->paprd;
1840
1841 if (txctl->paprd)
1842 bf->bf_state.bfs_paprd_timestamp = jiffies;
1843
1844 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1845 }
1846
1847 out:
1848 spin_unlock_bh(&txctl->txq->axq_lock);
1849 }
1850
1851 /* Upon failure caller should free skb */
1852 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1853 struct ath_tx_control *txctl)
1854 {
1855 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1856 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1857 struct ieee80211_sta *sta = info->control.sta;
1858 struct ieee80211_vif *vif = info->control.vif;
1859 struct ath_softc *sc = hw->priv;
1860 struct ath_txq *txq = txctl->txq;
1861 int padpos, padsize;
1862 int frmlen = skb->len + FCS_LEN;
1863 int q;
1864
1865 /* NOTE: sta can be NULL according to net/mac80211.h */
1866 if (sta)
1867 txctl->an = (struct ath_node *)sta->drv_priv;
1868
1869 if (info->control.hw_key)
1870 frmlen += info->control.hw_key->icv_len;
1871
1872 /*
1873 * As a temporary workaround, assign seq# here; this will likely need
1874 * to be cleaned up to work better with Beacon transmission and virtual
1875 * BSSes.
1876 */
1877 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1878 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1879 sc->tx.seq_no += 0x10;
1880 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1881 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1882 }
1883
1884 /* Add the padding after the header if this is not already done */
1885 padpos = ath9k_cmn_padpos(hdr->frame_control);
1886 padsize = padpos & 3;
1887 if (padsize && skb->len > padpos) {
1888 if (skb_headroom(skb) < padsize)
1889 return -ENOMEM;
1890
1891 skb_push(skb, padsize);
1892 memmove(skb->data, skb->data + padsize, padpos);
1893 hdr = (struct ieee80211_hdr *) skb->data;
1894 }
1895
1896 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1897 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1898 !ieee80211_is_data(hdr->frame_control))
1899 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1900
1901 setup_frame_info(hw, skb, frmlen);
1902
1903 /*
1904 * At this point, the vif, hw_key and sta pointers in the tx control
1905 * info are no longer valid (overwritten by the ath_frame_info data.
1906 */
1907
1908 q = skb_get_queue_mapping(skb);
1909 spin_lock_bh(&txq->axq_lock);
1910 if (txq == sc->tx.txq_map[q] &&
1911 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1912 ieee80211_stop_queue(sc->hw, q);
1913 txq->stopped = 1;
1914 }
1915 spin_unlock_bh(&txq->axq_lock);
1916
1917 ath_tx_start_dma(sc, skb, txctl);
1918 return 0;
1919 }
1920
1921 /*****************/
1922 /* TX Completion */
1923 /*****************/
1924
1925 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1926 int tx_flags, struct ath_txq *txq)
1927 {
1928 struct ieee80211_hw *hw = sc->hw;
1929 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1930 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1931 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1932 int q, padpos, padsize;
1933
1934 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1935
1936 if (tx_flags & ATH_TX_BAR)
1937 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1938
1939 if (!(tx_flags & ATH_TX_ERROR))
1940 /* Frame was ACKed */
1941 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1942
1943 padpos = ath9k_cmn_padpos(hdr->frame_control);
1944 padsize = padpos & 3;
1945 if (padsize && skb->len>padpos+padsize) {
1946 /*
1947 * Remove MAC header padding before giving the frame back to
1948 * mac80211.
1949 */
1950 memmove(skb->data + padsize, skb->data, padpos);
1951 skb_pull(skb, padsize);
1952 }
1953
1954 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1955 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1956 ath_dbg(common, ATH_DBG_PS,
1957 "Going back to sleep after having received TX status (0x%lx)\n",
1958 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1959 PS_WAIT_FOR_CAB |
1960 PS_WAIT_FOR_PSPOLL_DATA |
1961 PS_WAIT_FOR_TX_ACK));
1962 }
1963
1964 q = skb_get_queue_mapping(skb);
1965 if (txq == sc->tx.txq_map[q]) {
1966 spin_lock_bh(&txq->axq_lock);
1967 if (WARN_ON(--txq->pending_frames < 0))
1968 txq->pending_frames = 0;
1969
1970 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1971 ieee80211_wake_queue(sc->hw, q);
1972 txq->stopped = 0;
1973 }
1974 spin_unlock_bh(&txq->axq_lock);
1975 }
1976
1977 ieee80211_tx_status(hw, skb);
1978 }
1979
1980 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1981 struct ath_txq *txq, struct list_head *bf_q,
1982 struct ath_tx_status *ts, int txok, int sendbar)
1983 {
1984 struct sk_buff *skb = bf->bf_mpdu;
1985 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1986 unsigned long flags;
1987 int tx_flags = 0;
1988
1989 if (sendbar)
1990 tx_flags = ATH_TX_BAR;
1991
1992 if (!txok)
1993 tx_flags |= ATH_TX_ERROR;
1994
1995 if (ts->ts_status & ATH9K_TXERR_FILT)
1996 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1997
1998 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1999 bf->bf_buf_addr = 0;
2000
2001 if (bf->bf_state.bfs_paprd) {
2002 if (time_after(jiffies,
2003 bf->bf_state.bfs_paprd_timestamp +
2004 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2005 dev_kfree_skb_any(skb);
2006 else
2007 complete(&sc->paprd_complete);
2008 } else {
2009 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2010 ath_tx_complete(sc, skb, tx_flags, txq);
2011 }
2012 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2013 * accidentally reference it later.
2014 */
2015 bf->bf_mpdu = NULL;
2016
2017 /*
2018 * Return the list of ath_buf of this mpdu to free queue
2019 */
2020 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2021 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2022 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2023 }
2024
2025 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2026 struct ath_tx_status *ts, int nframes, int nbad,
2027 int txok)
2028 {
2029 struct sk_buff *skb = bf->bf_mpdu;
2030 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2031 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2032 struct ieee80211_hw *hw = sc->hw;
2033 struct ath_hw *ah = sc->sc_ah;
2034 u8 i, tx_rateindex;
2035
2036 if (txok)
2037 tx_info->status.ack_signal = ts->ts_rssi;
2038
2039 tx_rateindex = ts->ts_rateindex;
2040 WARN_ON(tx_rateindex >= hw->max_rates);
2041
2042 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2043 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2044
2045 BUG_ON(nbad > nframes);
2046
2047 tx_info->status.ampdu_len = nframes;
2048 tx_info->status.ampdu_ack_len = nframes - nbad;
2049 }
2050
2051 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2052 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2053 /*
2054 * If an underrun error is seen assume it as an excessive
2055 * retry only if max frame trigger level has been reached
2056 * (2 KB for single stream, and 4 KB for dual stream).
2057 * Adjust the long retry as if the frame was tried
2058 * hw->max_rate_tries times to affect how rate control updates
2059 * PER for the failed rate.
2060 * In case of congestion on the bus penalizing this type of
2061 * underruns should help hardware actually transmit new frames
2062 * successfully by eventually preferring slower rates.
2063 * This itself should also alleviate congestion on the bus.
2064 */
2065 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2066 ATH9K_TX_DELIM_UNDERRUN)) &&
2067 ieee80211_is_data(hdr->frame_control) &&
2068 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2069 tx_info->status.rates[tx_rateindex].count =
2070 hw->max_rate_tries;
2071 }
2072
2073 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2074 tx_info->status.rates[i].count = 0;
2075 tx_info->status.rates[i].idx = -1;
2076 }
2077
2078 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2079 }
2080
2081 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2082 struct ath_tx_status *ts, struct ath_buf *bf,
2083 struct list_head *bf_head)
2084 __releases(txq->axq_lock)
2085 __acquires(txq->axq_lock)
2086 {
2087 int txok;
2088
2089 txq->axq_depth--;
2090 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2091 txq->axq_tx_inprogress = false;
2092 if (bf_is_ampdu_not_probing(bf))
2093 txq->axq_ampdu_depth--;
2094
2095 spin_unlock_bh(&txq->axq_lock);
2096
2097 if (!bf_isampdu(bf)) {
2098 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2099 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2100 } else
2101 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2102
2103 spin_lock_bh(&txq->axq_lock);
2104
2105 if (sc->sc_flags & SC_OP_TXAGGR)
2106 ath_txq_schedule(sc, txq);
2107 }
2108
2109 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2110 {
2111 struct ath_hw *ah = sc->sc_ah;
2112 struct ath_common *common = ath9k_hw_common(ah);
2113 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2114 struct list_head bf_head;
2115 struct ath_desc *ds;
2116 struct ath_tx_status ts;
2117 int status;
2118
2119 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2120 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2121 txq->axq_link);
2122
2123 spin_lock_bh(&txq->axq_lock);
2124 for (;;) {
2125 if (work_pending(&sc->hw_reset_work))
2126 break;
2127
2128 if (list_empty(&txq->axq_q)) {
2129 txq->axq_link = NULL;
2130 if (sc->sc_flags & SC_OP_TXAGGR)
2131 ath_txq_schedule(sc, txq);
2132 break;
2133 }
2134 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2135
2136 /*
2137 * There is a race condition that a BH gets scheduled
2138 * after sw writes TxE and before hw re-load the last
2139 * descriptor to get the newly chained one.
2140 * Software must keep the last DONE descriptor as a
2141 * holding descriptor - software does so by marking
2142 * it with the STALE flag.
2143 */
2144 bf_held = NULL;
2145 if (bf->bf_stale) {
2146 bf_held = bf;
2147 if (list_is_last(&bf_held->list, &txq->axq_q))
2148 break;
2149
2150 bf = list_entry(bf_held->list.next, struct ath_buf,
2151 list);
2152 }
2153
2154 lastbf = bf->bf_lastbf;
2155 ds = lastbf->bf_desc;
2156
2157 memset(&ts, 0, sizeof(ts));
2158 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2159 if (status == -EINPROGRESS)
2160 break;
2161
2162 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2163
2164 /*
2165 * Remove ath_buf's of the same transmit unit from txq,
2166 * however leave the last descriptor back as the holding
2167 * descriptor for hw.
2168 */
2169 lastbf->bf_stale = true;
2170 INIT_LIST_HEAD(&bf_head);
2171 if (!list_is_singular(&lastbf->list))
2172 list_cut_position(&bf_head,
2173 &txq->axq_q, lastbf->list.prev);
2174
2175 if (bf_held) {
2176 list_del(&bf_held->list);
2177 ath_tx_return_buffer(sc, bf_held);
2178 }
2179
2180 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2181 }
2182 spin_unlock_bh(&txq->axq_lock);
2183 }
2184
2185 static void ath_tx_complete_poll_work(struct work_struct *work)
2186 {
2187 struct ath_softc *sc = container_of(work, struct ath_softc,
2188 tx_complete_work.work);
2189 struct ath_txq *txq;
2190 int i;
2191 bool needreset = false;
2192 #ifdef CONFIG_ATH9K_DEBUGFS
2193 sc->tx_complete_poll_work_seen++;
2194 #endif
2195
2196 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2197 if (ATH_TXQ_SETUP(sc, i)) {
2198 txq = &sc->tx.txq[i];
2199 spin_lock_bh(&txq->axq_lock);
2200 if (txq->axq_depth) {
2201 if (txq->axq_tx_inprogress) {
2202 needreset = true;
2203 spin_unlock_bh(&txq->axq_lock);
2204 break;
2205 } else {
2206 txq->axq_tx_inprogress = true;
2207 }
2208 }
2209 spin_unlock_bh(&txq->axq_lock);
2210 }
2211
2212 if (needreset) {
2213 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2214 "tx hung, resetting the chip\n");
2215 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2216 }
2217
2218 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2219 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2220 }
2221
2222
2223
2224 void ath_tx_tasklet(struct ath_softc *sc)
2225 {
2226 int i;
2227 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2228
2229 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2230
2231 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2232 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2233 ath_tx_processq(sc, &sc->tx.txq[i]);
2234 }
2235 }
2236
2237 void ath_tx_edma_tasklet(struct ath_softc *sc)
2238 {
2239 struct ath_tx_status ts;
2240 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2241 struct ath_hw *ah = sc->sc_ah;
2242 struct ath_txq *txq;
2243 struct ath_buf *bf, *lastbf;
2244 struct list_head bf_head;
2245 int status;
2246
2247 for (;;) {
2248 if (work_pending(&sc->hw_reset_work))
2249 break;
2250
2251 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2252 if (status == -EINPROGRESS)
2253 break;
2254 if (status == -EIO) {
2255 ath_dbg(common, ATH_DBG_XMIT,
2256 "Error processing tx status\n");
2257 break;
2258 }
2259
2260 /* Skip beacon completions */
2261 if (ts.qid == sc->beacon.beaconq)
2262 continue;
2263
2264 txq = &sc->tx.txq[ts.qid];
2265
2266 spin_lock_bh(&txq->axq_lock);
2267
2268 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2269 spin_unlock_bh(&txq->axq_lock);
2270 return;
2271 }
2272
2273 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2274 struct ath_buf, list);
2275 lastbf = bf->bf_lastbf;
2276
2277 INIT_LIST_HEAD(&bf_head);
2278 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2279 &lastbf->list);
2280
2281 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2282 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2283
2284 if (!list_empty(&txq->axq_q)) {
2285 struct list_head bf_q;
2286
2287 INIT_LIST_HEAD(&bf_q);
2288 txq->axq_link = NULL;
2289 list_splice_tail_init(&txq->axq_q, &bf_q);
2290 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2291 }
2292 }
2293
2294 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2295 spin_unlock_bh(&txq->axq_lock);
2296 }
2297 }
2298
2299 /*****************/
2300 /* Init, Cleanup */
2301 /*****************/
2302
2303 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2304 {
2305 struct ath_descdma *dd = &sc->txsdma;
2306 u8 txs_len = sc->sc_ah->caps.txs_len;
2307
2308 dd->dd_desc_len = size * txs_len;
2309 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2310 &dd->dd_desc_paddr, GFP_KERNEL);
2311 if (!dd->dd_desc)
2312 return -ENOMEM;
2313
2314 return 0;
2315 }
2316
2317 static int ath_tx_edma_init(struct ath_softc *sc)
2318 {
2319 int err;
2320
2321 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2322 if (!err)
2323 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2324 sc->txsdma.dd_desc_paddr,
2325 ATH_TXSTATUS_RING_SIZE);
2326
2327 return err;
2328 }
2329
2330 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2331 {
2332 struct ath_descdma *dd = &sc->txsdma;
2333
2334 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2335 dd->dd_desc_paddr);
2336 }
2337
2338 int ath_tx_init(struct ath_softc *sc, int nbufs)
2339 {
2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2341 int error = 0;
2342
2343 spin_lock_init(&sc->tx.txbuflock);
2344
2345 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2346 "tx", nbufs, 1, 1);
2347 if (error != 0) {
2348 ath_err(common,
2349 "Failed to allocate tx descriptors: %d\n", error);
2350 goto err;
2351 }
2352
2353 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2354 "beacon", ATH_BCBUF, 1, 1);
2355 if (error != 0) {
2356 ath_err(common,
2357 "Failed to allocate beacon descriptors: %d\n", error);
2358 goto err;
2359 }
2360
2361 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2362
2363 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2364 error = ath_tx_edma_init(sc);
2365 if (error)
2366 goto err;
2367 }
2368
2369 err:
2370 if (error != 0)
2371 ath_tx_cleanup(sc);
2372
2373 return error;
2374 }
2375
2376 void ath_tx_cleanup(struct ath_softc *sc)
2377 {
2378 if (sc->beacon.bdma.dd_desc_len != 0)
2379 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2380
2381 if (sc->tx.txdma.dd_desc_len != 0)
2382 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2383
2384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2385 ath_tx_edma_cleanup(sc);
2386 }
2387
2388 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2389 {
2390 struct ath_atx_tid *tid;
2391 struct ath_atx_ac *ac;
2392 int tidno, acno;
2393
2394 for (tidno = 0, tid = &an->tid[tidno];
2395 tidno < WME_NUM_TID;
2396 tidno++, tid++) {
2397 tid->an = an;
2398 tid->tidno = tidno;
2399 tid->seq_start = tid->seq_next = 0;
2400 tid->baw_size = WME_MAX_BA;
2401 tid->baw_head = tid->baw_tail = 0;
2402 tid->sched = false;
2403 tid->paused = false;
2404 tid->state &= ~AGGR_CLEANUP;
2405 __skb_queue_head_init(&tid->buf_q);
2406 acno = TID_TO_WME_AC(tidno);
2407 tid->ac = &an->ac[acno];
2408 tid->state &= ~AGGR_ADDBA_COMPLETE;
2409 tid->state &= ~AGGR_ADDBA_PROGRESS;
2410 }
2411
2412 for (acno = 0, ac = &an->ac[acno];
2413 acno < WME_NUM_AC; acno++, ac++) {
2414 ac->sched = false;
2415 ac->txq = sc->tx.txq_map[acno];
2416 INIT_LIST_HEAD(&ac->tid_q);
2417 }
2418 }
2419
2420 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2421 {
2422 struct ath_atx_ac *ac;
2423 struct ath_atx_tid *tid;
2424 struct ath_txq *txq;
2425 int tidno;
2426
2427 for (tidno = 0, tid = &an->tid[tidno];
2428 tidno < WME_NUM_TID; tidno++, tid++) {
2429
2430 ac = tid->ac;
2431 txq = ac->txq;
2432
2433 spin_lock_bh(&txq->axq_lock);
2434
2435 if (tid->sched) {
2436 list_del(&tid->list);
2437 tid->sched = false;
2438 }
2439
2440 if (ac->sched) {
2441 list_del(&ac->list);
2442 tid->ac->sched = false;
2443 }
2444
2445 ath_tid_drain(sc, txq, tid);
2446 tid->state &= ~AGGR_ADDBA_COMPLETE;
2447 tid->state &= ~AGGR_CLEANUP;
2448
2449 spin_unlock_bh(&txq->axq_lock);
2450 }
2451 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree