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[PATCH] I2O: new sysfs attributes and Adaptec specific block device access and 64...
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / linux / i2o.h
blob497ea574f96bf5e773bd79695a0585874e961147
1 /*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18 #ifndef _I2O_H
19 #define _I2O_H
20
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
22
23 #include <linux/i2o-dev.h>
24
25 /* How many different OSM's are we allowing */
26 #define I2O_MAX_DRIVERS 8
27
28 #include <asm/io.h>
29 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32
33 /* message queue empty */
34 #define I2O_QUEUE_EMPTY 0xffffffff
35
36 /*
37 * Message structures
38 */
39 struct i2o_message {
40 union {
41 struct {
42 u8 version_offset;
43 u8 flags;
44 u16 size;
45 u32 target_tid:12;
46 u32 init_tid:12;
47 u32 function:8;
48 u32 icntxt; /* initiator context */
49 u32 tcntxt; /* transaction context */
50 } s;
51 u32 head[4];
52 } u;
53 /* List follows */
54 u32 body[0];
55 };
56
57 /*
58 * Each I2O device entity has one of these. There is one per device.
59 */
60 struct i2o_device {
61 i2o_lct_entry lct_data; /* Device LCT information */
62
63 struct i2o_controller *iop; /* Controlling IOP */
64 struct list_head list; /* node in IOP devices list */
65
66 struct device device;
67
68 struct semaphore lock; /* device lock */
69
70 struct class_device classdev; /* i2o device class */
71 };
72
73 /*
74 * Event structure provided to the event handling function
75 */
76 struct i2o_event {
77 struct work_struct work;
78 struct i2o_device *i2o_dev; /* I2O device pointer from which the
79 event reply was initiated */
80 u16 size; /* Size of data in 32-bit words */
81 u32 tcntxt; /* Transaction context used at
82 registration */
83 u32 event_indicator; /* Event indicator from reply */
84 u32 data[0]; /* Event data from reply */
85 };
86
87 /*
88 * I2O classes which could be handled by the OSM
89 */
90 struct i2o_class_id {
91 u16 class_id:12;
92 };
93
94 /*
95 * I2O driver structure for OSMs
96 */
97 struct i2o_driver {
98 char *name; /* OSM name */
99 int context; /* Low 8 bits of the transaction info */
100 struct i2o_class_id *classes; /* I2O classes that this OSM handles */
101
102 /* Message reply handler */
103 int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
104
105 /* Event handler */
106 void (*event) (struct i2o_event *);
107
108 struct workqueue_struct *event_queue; /* Event queue */
109
110 struct device_driver driver;
111
112 /* notification of changes */
113 void (*notify_controller_add) (struct i2o_controller *);
114 void (*notify_controller_remove) (struct i2o_controller *);
115 void (*notify_device_add) (struct i2o_device *);
116 void (*notify_device_remove) (struct i2o_device *);
117
118 struct semaphore lock;
119 };
120
121 /*
122 * Contains all information which are necessary for DMA operations
123 */
124 struct i2o_dma {
125 void *virt;
126 dma_addr_t phys;
127 u32 len;
128 };
129
130 /*
131 * Context queue entry, used for 32-bit context on 64-bit systems
132 */
133 struct i2o_context_list_element {
134 struct list_head list;
135 u32 context;
136 void *ptr;
137 unsigned long timestamp;
138 };
139
140 /*
141 * Each I2O controller has one of these objects
142 */
143 struct i2o_controller {
144 char name[16];
145 int unit;
146 int type;
147
148 struct pci_dev *pdev; /* PCI device */
149
150 unsigned int short_req:1; /* use small block sizes */
151 unsigned int no_quiesce:1; /* dont quiesce before reset */
152 unsigned int raptor:1; /* split bar */
153 unsigned int promise:1; /* Promise controller */
154
155 struct list_head devices; /* list of I2O devices */
156 struct list_head list; /* Controller list */
157
158 void __iomem *in_port; /* Inbout port address */
159 void __iomem *out_port; /* Outbound port address */
160 void __iomem *irq_status; /* Interrupt status register address */
161 void __iomem *irq_mask; /* Interrupt mask register address */
162
163 /* Dynamic LCT related data */
164
165 struct i2o_dma status; /* status of IOP */
166
167 struct i2o_dma hrt; /* HW Resource Table */
168 i2o_lct *lct; /* Logical Config Table */
169 struct i2o_dma dlct; /* Temp LCT */
170 struct semaphore lct_lock; /* Lock for LCT updates */
171 struct i2o_dma status_block; /* IOP status block */
172
173 struct i2o_dma base; /* controller messaging unit */
174 struct i2o_dma in_queue; /* inbound message queue Host->IOP */
175 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
176
177 unsigned int battery:1; /* Has a battery backup */
178 unsigned int io_alloc:1; /* An I/O resource was allocated */
179 unsigned int mem_alloc:1; /* A memory resource was allocated */
180
181 struct resource io_resource; /* I/O resource allocated to the IOP */
182 struct resource mem_resource; /* Mem resource allocated to the IOP */
183
184 struct device device;
185 struct i2o_device *exec; /* Executive */
186 #if BITS_PER_LONG == 64
187 spinlock_t context_list_lock; /* lock for context_list */
188 atomic_t context_list_counter; /* needed for unique contexts */
189 struct list_head context_list; /* list of context id's
190 and pointers */
191 #endif
192 spinlock_t lock; /* lock for controller
193 configuration */
194
195 void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
196 };
197
198 /*
199 * I2O System table entry
200 *
201 * The system table contains information about all the IOPs in the
202 * system. It is sent to all IOPs so that they can create peer2peer
203 * connections between them.
204 */
205 struct i2o_sys_tbl_entry {
206 u16 org_id;
207 u16 reserved1;
208 u32 iop_id:12;
209 u32 reserved2:20;
210 u16 seg_num:12;
211 u16 i2o_version:4;
212 u8 iop_state;
213 u8 msg_type;
214 u16 frame_size;
215 u16 reserved3;
216 u32 last_changed;
217 u32 iop_capabilities;
218 u32 inbound_low;
219 u32 inbound_high;
220 };
221
222 struct i2o_sys_tbl {
223 u8 num_entries;
224 u8 version;
225 u16 reserved1;
226 u32 change_ind;
227 u32 reserved2;
228 u32 reserved3;
229 struct i2o_sys_tbl_entry iops[0];
230 };
231
232 extern struct list_head i2o_controllers;
233
234 /* Message functions */
235 static inline u32 i2o_msg_get(struct i2o_controller *, struct i2o_message __iomem **);
236 extern u32 i2o_msg_get_wait(struct i2o_controller *, struct i2o_message __iomem **,
237 int);
238 static inline void i2o_msg_post(struct i2o_controller *, u32);
239 static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
240 unsigned long);
241 extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
242 struct i2o_dma *);
243 extern void i2o_msg_nop(struct i2o_controller *, u32);
244 static inline void i2o_flush_reply(struct i2o_controller *, u32);
245
246 /* IOP functions */
247 extern int i2o_status_get(struct i2o_controller *);
248
249 extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
250 u32);
251 extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
252 extern struct i2o_controller *i2o_find_iop(int);
253
254 /* Functions needed for handling 64-bit pointers in 32-bit context */
255 #if BITS_PER_LONG == 64
256 extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
257 extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
258 extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
259 extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);
260
261 static inline u32 i2o_ptr_low(void *ptr)
262 {
263 return (u32) (u64) ptr;
264 };
265
266 static inline u32 i2o_ptr_high(void *ptr)
267 {
268 return (u32) ((u64) ptr >> 32);
269 };
270
271 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
272 {
273 return (u32) (u64) dma_addr;
274 };
275
276 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
277 {
278 return (u32) ((u64) dma_addr >> 32);
279 };
280 #else
281 static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
282 {
283 return (u32) ptr;
284 };
285
286 static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
287 {
288 return (void *)context;
289 };
290
291 static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
292 {
293 return (u32) ptr;
294 };
295
296 static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
297 {
298 return (u32) ptr;
299 };
300
301 static inline u32 i2o_ptr_low(void *ptr)
302 {
303 return (u32) ptr;
304 };
305
306 static inline u32 i2o_ptr_high(void *ptr)
307 {
308 return 0;
309 };
310
311 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
312 {
313 return (u32) dma_addr;
314 };
315
316 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
317 {
318 return 0;
319 };
320 #endif
321
322 /**
323 * i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
324 * @c: I2O controller for which the calculation should be done
325 * @body_size: maximum body size used for message in 32-bit words.
326 *
327 * Return the maximum number of SG elements in a SG list.
328 */
329 static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
330 {
331 i2o_status_block *sb = c->status_block.virt;
332 u16 sg_count =
333 (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
334 body_size;
335
336 if (c->pae_support) {
337 /*
338 * for 64-bit a SG attribute element must be added and each
339 * SG element needs 12 bytes instead of 8.
340 */
341 sg_count -= 2;
342 sg_count /= 3;
343 } else
344 sg_count /= 2;
345
346 if (c->short_req && (sg_count > 8))
347 sg_count = 8;
348
349 return sg_count;
350 };
351
352 /**
353 * i2o_dma_map_single - Map pointer to controller and fill in I2O message.
354 * @c: I2O controller
355 * @ptr: pointer to the data which should be mapped
356 * @size: size of data in bytes
357 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
358 * @sg_ptr: pointer to the SG list inside the I2O message
359 *
360 * This function does all necessary DMA handling and also writes the I2O
361 * SGL elements into the I2O message. For details on DMA handling see also
362 * dma_map_single(). The pointer sg_ptr will only be set to the end of the
363 * SG list if the allocation was successful.
364 *
365 * Returns DMA address which must be checked for failures using
366 * dma_mapping_error().
367 */
368 static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
369 size_t size,
370 enum dma_data_direction direction,
371 u32 __iomem ** sg_ptr)
372 {
373 u32 sg_flags;
374 u32 __iomem *mptr = *sg_ptr;
375 dma_addr_t dma_addr;
376
377 switch (direction) {
378 case DMA_TO_DEVICE:
379 sg_flags = 0xd4000000;
380 break;
381 case DMA_FROM_DEVICE:
382 sg_flags = 0xd0000000;
383 break;
384 default:
385 return 0;
386 }
387
388 dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
389 if (!dma_mapping_error(dma_addr)) {
390 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
391 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
392 writel(0x7C020002, mptr++);
393 writel(PAGE_SIZE, mptr++);
394 }
395 #endif
396
397 writel(sg_flags | size, mptr++);
398 writel(i2o_dma_low(dma_addr), mptr++);
399 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
400 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
401 writel(i2o_dma_high(dma_addr), mptr++);
402 #endif
403 *sg_ptr = mptr;
404 }
405 return dma_addr;
406 };
407
408 /**
409 * i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
410 * @c: I2O controller
411 * @sg: SG list to be mapped
412 * @sg_count: number of elements in the SG list
413 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
414 * @sg_ptr: pointer to the SG list inside the I2O message
415 *
416 * This function does all necessary DMA handling and also writes the I2O
417 * SGL elements into the I2O message. For details on DMA handling see also
418 * dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
419 * list if the allocation was successful.
420 *
421 * Returns 0 on failure or 1 on success.
422 */
423 static inline int i2o_dma_map_sg(struct i2o_controller *c,
424 struct scatterlist *sg, int sg_count,
425 enum dma_data_direction direction,
426 u32 __iomem ** sg_ptr)
427 {
428 u32 sg_flags;
429 u32 __iomem *mptr = *sg_ptr;
430
431 switch (direction) {
432 case DMA_TO_DEVICE:
433 sg_flags = 0x14000000;
434 break;
435 case DMA_FROM_DEVICE:
436 sg_flags = 0x10000000;
437 break;
438 default:
439 return 0;
440 }
441
442 sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
443 if (!sg_count)
444 return 0;
445
446 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
447 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
448 writel(0x7C020002, mptr++);
449 writel(PAGE_SIZE, mptr++);
450 }
451 #endif
452
453 while (sg_count-- > 0) {
454 if (!sg_count)
455 sg_flags |= 0xC0000000;
456 writel(sg_flags | sg_dma_len(sg), mptr++);
457 writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
458 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
459 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
460 writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
461 #endif
462 sg++;
463 }
464 *sg_ptr = mptr;
465
466 return 1;
467 };
468
469 /**
470 * i2o_dma_alloc - Allocate DMA memory
471 * @dev: struct device pointer to the PCI device of the I2O controller
472 * @addr: i2o_dma struct which should get the DMA buffer
473 * @len: length of the new DMA memory
474 * @gfp_mask: GFP mask
475 *
476 * Allocate a coherent DMA memory and write the pointers into addr.
477 *
478 * Returns 0 on success or -ENOMEM on failure.
479 */
480 static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
481 size_t len, unsigned int gfp_mask)
482 {
483 struct pci_dev *pdev = to_pci_dev(dev);
484 int dma_64 = 0;
485
486 if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
487 dma_64 = 1;
488 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
489 return -ENOMEM;
490 }
491
492 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
493
494 if ((sizeof(dma_addr_t) > 4) && dma_64)
495 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
496 printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
497
498 if (!addr->virt)
499 return -ENOMEM;
500
501 memset(addr->virt, 0, len);
502 addr->len = len;
503
504 return 0;
505 };
506
507 /**
508 * i2o_dma_free - Free DMA memory
509 * @dev: struct device pointer to the PCI device of the I2O controller
510 * @addr: i2o_dma struct which contains the DMA buffer
511 *
512 * Free a coherent DMA memory and set virtual address of addr to NULL.
513 */
514 static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
515 {
516 if (addr->virt) {
517 if (addr->phys)
518 dma_free_coherent(dev, addr->len, addr->virt,
519 addr->phys);
520 else
521 kfree(addr->virt);
522 addr->virt = NULL;
523 }
524 };
525
526 /**
527 * i2o_dma_realloc - Realloc DMA memory
528 * @dev: struct device pointer to the PCI device of the I2O controller
529 * @addr: pointer to a i2o_dma struct DMA buffer
530 * @len: new length of memory
531 * @gfp_mask: GFP mask
532 *
533 * If there was something allocated in the addr, free it first. If len > 0
534 * than try to allocate it and write the addresses back to the addr
535 * structure. If len == 0 set the virtual address to NULL.
536 *
537 * Returns the 0 on success or negative error code on failure.
538 */
539 static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
540 size_t len, unsigned int gfp_mask)
541 {
542 i2o_dma_free(dev, addr);
543
544 if (len)
545 return i2o_dma_alloc(dev, addr, len, gfp_mask);
546
547 return 0;
548 };
549
550 /* I2O driver (OSM) functions */
551 extern int i2o_driver_register(struct i2o_driver *);
552 extern void i2o_driver_unregister(struct i2o_driver *);
553
554 /**
555 * i2o_driver_notify_controller_add - Send notification of added controller
556 * to a single I2O driver
557 *
558 * Send notification of added controller to a single registered driver.
559 */
560 static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv,
561 struct i2o_controller *c)
562 {
563 if (drv->notify_controller_add)
564 drv->notify_controller_add(c);
565 };
566
567 /**
568 * i2o_driver_notify_controller_remove - Send notification of removed
569 * controller to a single I2O driver
570 *
571 * Send notification of removed controller to a single registered driver.
572 */
573 static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv,
574 struct i2o_controller *c)
575 {
576 if (drv->notify_controller_remove)
577 drv->notify_controller_remove(c);
578 };
579
580 /**
581 * i2o_driver_notify_device_add - Send notification of added device to a
582 * single I2O driver
583 *
584 * Send notification of added device to a single registered driver.
585 */
586 static inline void i2o_driver_notify_device_add(struct i2o_driver *drv,
587 struct i2o_device *i2o_dev)
588 {
589 if (drv->notify_device_add)
590 drv->notify_device_add(i2o_dev);
591 };
592
593 /**
594 * i2o_driver_notify_device_remove - Send notification of removed device
595 * to a single I2O driver
596 *
597 * Send notification of removed device to a single registered driver.
598 */
599 static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv,
600 struct i2o_device *i2o_dev)
601 {
602 if (drv->notify_device_remove)
603 drv->notify_device_remove(i2o_dev);
604 };
605
606 extern void i2o_driver_notify_controller_add_all(struct i2o_controller *);
607 extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *);
608 extern void i2o_driver_notify_device_add_all(struct i2o_device *);
609 extern void i2o_driver_notify_device_remove_all(struct i2o_device *);
610
611 /* I2O device functions */
612 extern int i2o_device_claim(struct i2o_device *);
613 extern int i2o_device_claim_release(struct i2o_device *);
614
615 /* Exec OSM functions */
616 extern int i2o_exec_lct_get(struct i2o_controller *);
617
618 /* device / driver / kobject conversion functions */
619 #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
620 #define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
621 #define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
622 #define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
623
624 /**
625 * i2o_msg_get - obtain an I2O message from the IOP
626 * @c: I2O controller
627 * @msg: pointer to a I2O message pointer
628 *
629 * This function tries to get a message slot. If no message slot is
630 * available do not wait until one is availabe (see also i2o_msg_get_wait).
631 *
632 * On a success the message is returned and the pointer to the message is
633 * set in msg. The returned message is the physical page frame offset
634 * address from the read port (see the i2o spec). If no message is
635 * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
636 */
637 static inline u32 i2o_msg_get(struct i2o_controller *c,
638 struct i2o_message __iomem **msg)
639 {
640 u32 m = readl(c->in_port);
641
642 if (m != I2O_QUEUE_EMPTY) {
643 *msg = c->in_queue.virt + m;
644 rmb();
645 }
646
647 return m;
648 };
649
650 /**
651 * i2o_msg_post - Post I2O message to I2O controller
652 * @c: I2O controller to which the message should be send
653 * @m: the message identifier
654 *
655 * Post the message to the I2O controller.
656 */
657 static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
658 {
659 wmb();
660 writel(m, c->in_port);
661 };
662
663 /**
664 * i2o_msg_post_wait - Post and wait a message and wait until return
665 * @c: controller
666 * @m: message to post
667 * @timeout: time in seconds to wait
668 *
669 * This API allows an OSM to post a message and then be told whether or
670 * not the system received a successful reply. If the message times out
671 * then the value '-ETIMEDOUT' is returned.
672 *
673 * Returns 0 on success or negative error code on failure.
674 */
675 static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
676 unsigned long timeout)
677 {
678 return i2o_msg_post_wait_mem(c, m, timeout, NULL);
679 };
680
681 /**
682 * i2o_flush_reply - Flush reply from I2O controller
683 * @c: I2O controller
684 * @m: the message identifier
685 *
686 * The I2O controller must be informed that the reply message is not needed
687 * anymore. If you forget to flush the reply, the message frame can't be
688 * used by the controller anymore and is therefore lost.
689 */
690 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
691 {
692 writel(m, c->out_port);
693 };
694
695 /**
696 * i2o_out_to_virt - Turn an I2O message to a virtual address
697 * @c: controller
698 * @m: message engine value
699 *
700 * Turn a receive message from an I2O controller bus address into
701 * a Linux virtual address. The shared page frame is a linear block
702 * so we simply have to shift the offset. This function does not
703 * work for sender side messages as they are ioremap objects
704 * provided by the I2O controller.
705 */
706 static inline struct i2o_message __iomem *i2o_msg_out_to_virt(struct
707 i2o_controller *c,
708 u32 m)
709 {
710 if (unlikely
711 (m < c->out_queue.phys
712 || m >= c->out_queue.phys + c->out_queue.len))
713 return NULL;
714
715 return c->out_queue.virt + (m - c->out_queue.phys);
716 };
717
718 /**
719 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
720 * @c: controller
721 * @m: message engine value
722 *
723 * Turn a send message from an I2O controller bus address into
724 * a Linux virtual address. The shared page frame is a linear block
725 * so we simply have to shift the offset. This function does not
726 * work for receive side messages as they are kmalloc objects
727 * in a different pool.
728 */
729 static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct i2o_controller *c,
730 u32 m)
731 {
732 return c->in_queue.virt + m;
733 };
734
735 /**
736 * i2o_dma_alloc - Allocate DMA memory
737 * @dev: struct device pointer to the PCI device of the I2O controller
738 * @addr: i2o_dma struct which should get the DMA buffer
739 * @len: length of the new DMA memory
740 * @gfp_mask: GFP mask
741 *
742 * Allocate a coherent DMA memory and write the pointers into addr.
743 *
744 * Returns 0 on success or -ENOMEM on failure.
745 */
746 static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
747 size_t len, unsigned int gfp_mask)
748 {
749 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
750 if (!addr->virt)
751 return -ENOMEM;
752
753 memset(addr->virt, 0, len);
754 addr->len = len;
755
756 return 0;
757 };
758
759 /**
760 * i2o_dma_free - Free DMA memory
761 * @dev: struct device pointer to the PCI device of the I2O controller
762 * @addr: i2o_dma struct which contains the DMA buffer
763 *
764 * Free a coherent DMA memory and set virtual address of addr to NULL.
765 */
766 static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
767 {
768 if (addr->virt) {
769 if (addr->phys)
770 dma_free_coherent(dev, addr->len, addr->virt,
771 addr->phys);
772 else
773 kfree(addr->virt);
774 addr->virt = NULL;
775 }
776 };
777
778 /*
779 * Endian handling wrapped into the macro - keeps the core code
780 * cleaner.
781 */
782
783 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
784
785 extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int);
786 extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int,
787 void *, int);
788
789 /* debugging and troubleshooting/diagnostic helpers. */
790 #define osm_printk(level, format, arg...) \
791 printk(level "%s: " format, OSM_NAME , ## arg)
792
793 #ifdef DEBUG
794 #define osm_debug(format, arg...) \
795 osm_printk(KERN_DEBUG, format , ## arg)
796 #else
797 #define osm_debug(format, arg...) \
798 do { } while (0)
799 #endif
800
801 #define osm_err(format, arg...) \
802 osm_printk(KERN_ERR, format , ## arg)
803 #define osm_info(format, arg...) \
804 osm_printk(KERN_INFO, format , ## arg)
805 #define osm_warn(format, arg...) \
806 osm_printk(KERN_WARNING, format , ## arg)
807
808 /* debugging functions */
809 extern void i2o_report_status(const char *, const char *, struct i2o_message *);
810 extern void i2o_dump_message(struct i2o_message *);
811 extern void i2o_dump_hrt(struct i2o_controller *c);
812 extern void i2o_debug_state(struct i2o_controller *c);
813
814 /*
815 * Cache strategies
816 */
817
818 /* The NULL strategy leaves everything up to the controller. This tends to be a
819 * pessimal but functional choice.
820 */
821 #define CACHE_NULL 0
822 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
823 * into the controller cache.
824 */
825 #define CACHE_PREFETCH 1
826 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
827 * into the controller cache. When an I/O is less <= 8K we assume its probably
828 * not sequential and don't prefetch (default)
829 */
830 #define CACHE_SMARTFETCH 2
831 /* Data is written to the cache and then out on to the disk. The I/O must be
832 * physically on the medium before the write is acknowledged (default without
833 * NVRAM)
834 */
835 #define CACHE_WRITETHROUGH 17
836 /* Data is written to the cache and then out on to the disk. The controller
837 * is permitted to write back the cache any way it wants. (default if battery
838 * backed NVRAM is present). It can be useful to set this for swap regardless of
839 * battery state.
840 */
841 #define CACHE_WRITEBACK 18
842 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
843 * write large I/O's directly to disk bypassing the cache to avoid the extra
844 * memory copy hits. Small writes are writeback cached
845 */
846 #define CACHE_SMARTBACK 19
847 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
848 * write large I/O's directly to disk bypassing the cache to avoid the extra
849 * memory copy hits. Small writes are writethrough cached. Suitable for devices
850 * lacking battery backup
851 */
852 #define CACHE_SMARTTHROUGH 20
853
854 /*
855 * Ioctl structures
856 */
857
858 #define BLKI2OGRSTRAT _IOR('2', 1, int)
859 #define BLKI2OGWSTRAT _IOR('2', 2, int)
860 #define BLKI2OSRSTRAT _IOW('2', 3, int)
861 #define BLKI2OSWSTRAT _IOW('2', 4, int)
862
863 /*
864 * I2O Function codes
865 */
866
867 /*
868 * Executive Class
869 */
870 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
871 #define I2O_CMD_ADAPTER_READ 0xB2
872 #define I2O_CMD_ADAPTER_RELEASE 0xB5
873 #define I2O_CMD_BIOS_INFO_SET 0xA5
874 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
875 #define I2O_CMD_CONFIG_VALIDATE 0xBB
876 #define I2O_CMD_CONN_SETUP 0xCA
877 #define I2O_CMD_DDM_DESTROY 0xB1
878 #define I2O_CMD_DDM_ENABLE 0xD5
879 #define I2O_CMD_DDM_QUIESCE 0xC7
880 #define I2O_CMD_DDM_RESET 0xD9
881 #define I2O_CMD_DDM_SUSPEND 0xAF
882 #define I2O_CMD_DEVICE_ASSIGN 0xB7
883 #define I2O_CMD_DEVICE_RELEASE 0xB9
884 #define I2O_CMD_HRT_GET 0xA8
885 #define I2O_CMD_ADAPTER_CLEAR 0xBE
886 #define I2O_CMD_ADAPTER_CONNECT 0xC9
887 #define I2O_CMD_ADAPTER_RESET 0xBD
888 #define I2O_CMD_LCT_NOTIFY 0xA2
889 #define I2O_CMD_OUTBOUND_INIT 0xA1
890 #define I2O_CMD_PATH_ENABLE 0xD3
891 #define I2O_CMD_PATH_QUIESCE 0xC5
892 #define I2O_CMD_PATH_RESET 0xD7
893 #define I2O_CMD_STATIC_MF_CREATE 0xDD
894 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
895 #define I2O_CMD_STATUS_GET 0xA0
896 #define I2O_CMD_SW_DOWNLOAD 0xA9
897 #define I2O_CMD_SW_UPLOAD 0xAB
898 #define I2O_CMD_SW_REMOVE 0xAD
899 #define I2O_CMD_SYS_ENABLE 0xD1
900 #define I2O_CMD_SYS_MODIFY 0xC1
901 #define I2O_CMD_SYS_QUIESCE 0xC3
902 #define I2O_CMD_SYS_TAB_SET 0xA3
903
904 /*
905 * Utility Class
906 */
907 #define I2O_CMD_UTIL_NOP 0x00
908 #define I2O_CMD_UTIL_ABORT 0x01
909 #define I2O_CMD_UTIL_CLAIM 0x09
910 #define I2O_CMD_UTIL_RELEASE 0x0B
911 #define I2O_CMD_UTIL_PARAMS_GET 0x06
912 #define I2O_CMD_UTIL_PARAMS_SET 0x05
913 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
914 #define I2O_CMD_UTIL_EVT_ACK 0x14
915 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
916 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
917 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
918 #define I2O_CMD_UTIL_LOCK 0x17
919 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
920 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
921
922 /*
923 * SCSI Host Bus Adapter Class
924 */
925 #define I2O_CMD_SCSI_EXEC 0x81
926 #define I2O_CMD_SCSI_ABORT 0x83
927 #define I2O_CMD_SCSI_BUSRESET 0x27
928
929 /*
930 * Bus Adapter Class
931 */
932 #define I2O_CMD_BUS_ADAPTER_RESET 0x85
933 #define I2O_CMD_BUS_RESET 0x87
934 #define I2O_CMD_BUS_SCAN 0x89
935 #define I2O_CMD_BUS_QUIESCE 0x8b
936
937 /*
938 * Random Block Storage Class
939 */
940 #define I2O_CMD_BLOCK_READ 0x30
941 #define I2O_CMD_BLOCK_WRITE 0x31
942 #define I2O_CMD_BLOCK_CFLUSH 0x37
943 #define I2O_CMD_BLOCK_MLOCK 0x49
944 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
945 #define I2O_CMD_BLOCK_MMOUNT 0x41
946 #define I2O_CMD_BLOCK_MEJECT 0x43
947 #define I2O_CMD_BLOCK_POWER 0x70
948
949 #define I2O_PRIVATE_MSG 0xFF
950
951 /* Command status values */
952
953 #define I2O_CMD_IN_PROGRESS 0x01
954 #define I2O_CMD_REJECTED 0x02
955 #define I2O_CMD_FAILED 0x03
956 #define I2O_CMD_COMPLETED 0x04
957
958 /* I2O API function return values */
959
960 #define I2O_RTN_NO_ERROR 0
961 #define I2O_RTN_NOT_INIT 1
962 #define I2O_RTN_FREE_Q_EMPTY 2
963 #define I2O_RTN_TCB_ERROR 3
964 #define I2O_RTN_TRANSACTION_ERROR 4
965 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
966 #define I2O_RTN_MALLOC_ERROR 6
967 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
968 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
969 #define I2O_RTN_NO_STATUS 9
970 #define I2O_RTN_NO_FIRM_VER 10
971 #define I2O_RTN_NO_LINK_SPEED 11
972
973 /* Reply message status defines for all messages */
974
975 #define I2O_REPLY_STATUS_SUCCESS 0x00
976 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
977 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
978 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
979 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
980 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
981 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
982 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
983 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
984 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
985 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
986 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
987
988 /* Status codes and Error Information for Parameter functions */
989
990 #define I2O_PARAMS_STATUS_SUCCESS 0x00
991 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
992 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
993 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
994 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
995 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
996 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
997 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
998 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
999 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
1000 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
1001 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
1002 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
1003 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
1004 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
1005 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
1006 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
1007
1008 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
1009 * messages: Table 3-2 Detailed Status Codes.*/
1010
1011 #define I2O_DSC_SUCCESS 0x0000
1012 #define I2O_DSC_BAD_KEY 0x0002
1013 #define I2O_DSC_TCL_ERROR 0x0003
1014 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
1015 #define I2O_DSC_NO_SUCH_PAGE 0x0005
1016 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
1017 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
1018 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
1019 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
1020 #define I2O_DSC_DEVICE_LOCKED 0x000B
1021 #define I2O_DSC_DEVICE_RESET 0x000C
1022 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
1023 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
1024 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
1025 #define I2O_DSC_INVALID_OFFSET 0x0010
1026 #define I2O_DSC_INVALID_PARAMETER 0x0011
1027 #define I2O_DSC_INVALID_REQUEST 0x0012
1028 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
1029 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
1030 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
1031 #define I2O_DSC_MISSING_PARAMETER 0x0016
1032 #define I2O_DSC_TIMEOUT 0x0017
1033 #define I2O_DSC_UNKNOWN_ERROR 0x0018
1034 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
1035 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
1036 #define I2O_DSC_DEVICE_BUSY 0x001B
1037 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
1038
1039 /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
1040 Status Codes.*/
1041
1042 #define I2O_BSA_DSC_SUCCESS 0x0000
1043 #define I2O_BSA_DSC_MEDIA_ERROR 0x0001
1044 #define I2O_BSA_DSC_ACCESS_ERROR 0x0002
1045 #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
1046 #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
1047 #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
1048 #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
1049 #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
1050 #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
1051 #define I2O_BSA_DSC_BUS_FAILURE 0x0009
1052 #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
1053 #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
1054 #define I2O_BSA_DSC_DEVICE_RESET 0x000C
1055 #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
1056 #define I2O_BSA_DSC_TIMEOUT 0x000E
1057
1058 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
1059
1060 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
1061 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
1062 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
1063 #define I2O_FSC_TRANSPORT_FAILURE 0x84
1064 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
1065 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
1066 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
1067 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
1068 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
1069 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
1070 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
1071 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
1072 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
1073 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
1074 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
1075 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
1076
1077 /* Device Claim Types */
1078 #define I2O_CLAIM_PRIMARY 0x01000000
1079 #define I2O_CLAIM_MANAGEMENT 0x02000000
1080 #define I2O_CLAIM_AUTHORIZED 0x03000000
1081 #define I2O_CLAIM_SECONDARY 0x04000000
1082
1083 /* Message header defines for VersionOffset */
1084 #define I2OVER15 0x0001
1085 #define I2OVER20 0x0002
1086
1087 /* Default is 1.5 */
1088 #define I2OVERSION I2OVER15
1089
1090 #define SGL_OFFSET_0 I2OVERSION
1091 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
1092 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
1093 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
1094 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
1095 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
1096 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
1097 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
1098
1099 #define TRL_OFFSET_5 (0x0050 | I2OVERSION)
1100 #define TRL_OFFSET_6 (0x0060 | I2OVERSION)
1101
1102 /* Transaction Reply Lists (TRL) Control Word structure */
1103 #define TRL_SINGLE_FIXED_LENGTH 0x00
1104 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
1105 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
1106
1107 /* msg header defines for MsgFlags */
1108 #define MSG_STATIC 0x0100
1109 #define MSG_64BIT_CNTXT 0x0200
1110 #define MSG_MULTI_TRANS 0x1000
1111 #define MSG_FAIL 0x2000
1112 #define MSG_FINAL 0x4000
1113 #define MSG_REPLY 0x8000
1114
1115 /* minimum size msg */
1116 #define THREE_WORD_MSG_SIZE 0x00030000
1117 #define FOUR_WORD_MSG_SIZE 0x00040000
1118 #define FIVE_WORD_MSG_SIZE 0x00050000
1119 #define SIX_WORD_MSG_SIZE 0x00060000
1120 #define SEVEN_WORD_MSG_SIZE 0x00070000
1121 #define EIGHT_WORD_MSG_SIZE 0x00080000
1122 #define NINE_WORD_MSG_SIZE 0x00090000
1123 #define TEN_WORD_MSG_SIZE 0x000A0000
1124 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
1125 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
1126
1127 /* Special TID Assignments */
1128
1129 #define ADAPTER_TID 0
1130 #define HOST_TID 1
1131
1132 #define MSG_FRAME_SIZE 128 /* i2o_scsi assumes >= 32 */
1133 #define REPLY_FRAME_SIZE 17
1134 #define SG_TABLESIZE 30
1135 #define NMBR_MSG_FRAMES 128
1136
1137 #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
1138
1139 #define I2O_POST_WAIT_OK 0
1140 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
1141
1142 #define I2O_CONTEXT_LIST_MIN_LENGTH 15
1143 #define I2O_CONTEXT_LIST_USED 0x01
1144 #define I2O_CONTEXT_LIST_DELETED 0x02
1145
1146 /* timeouts */
1147 #define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
1148 #define I2O_TIMEOUT_MESSAGE_GET 5
1149 #define I2O_TIMEOUT_RESET 30
1150 #define I2O_TIMEOUT_STATUS_GET 5
1151 #define I2O_TIMEOUT_LCT_GET 360
1152 #define I2O_TIMEOUT_SCSI_SCB_ABORT 240
1153
1154 /* retries */
1155 #define I2O_HRT_GET_TRIES 3
1156 #define I2O_LCT_GET_TRIES 3
1157
1158 /* request queue sizes */
1159 #define I2O_MAX_SECTORS 1024
1160 #define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
1161
1162 #define I2O_REQ_MEMPOOL_SIZE 32
1163
1164 #endif /* __KERNEL__ */
1165 #endif /* _I2O_H */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree