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ASoC: multi-component - ASoC Multi-Component Support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / codecs / wm8990.c
blobb252433829663db482396d4032f89afe764e9c7f
1 /*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <asm/div64.h>
30
31 #include "wm8990.h"
32
33 /* codec private data */
34 struct wm8990_priv {
35 enum snd_soc_control_type control_type;
36 void *control_data;
37 unsigned int sysclk;
38 unsigned int pcmclk;
39 };
40
41 /*
42 * wm8990 register cache. Note that register 0 is not included in the
43 * cache.
44 */
45 static const u16 wm8990_reg[] = {
46 0x8990, /* R0 - Reset */
47 0x0000, /* R1 - Power Management (1) */
48 0x6000, /* R2 - Power Management (2) */
49 0x0000, /* R3 - Power Management (3) */
50 0x4050, /* R4 - Audio Interface (1) */
51 0x4000, /* R5 - Audio Interface (2) */
52 0x01C8, /* R6 - Clocking (1) */
53 0x0000, /* R7 - Clocking (2) */
54 0x0040, /* R8 - Audio Interface (3) */
55 0x0040, /* R9 - Audio Interface (4) */
56 0x0004, /* R10 - DAC CTRL */
57 0x00C0, /* R11 - Left DAC Digital Volume */
58 0x00C0, /* R12 - Right DAC Digital Volume */
59 0x0000, /* R13 - Digital Side Tone */
60 0x0100, /* R14 - ADC CTRL */
61 0x00C0, /* R15 - Left ADC Digital Volume */
62 0x00C0, /* R16 - Right ADC Digital Volume */
63 0x0000, /* R17 */
64 0x0000, /* R18 - GPIO CTRL 1 */
65 0x1000, /* R19 - GPIO1 & GPIO2 */
66 0x1010, /* R20 - GPIO3 & GPIO4 */
67 0x1010, /* R21 - GPIO5 & GPIO6 */
68 0x8000, /* R22 - GPIOCTRL 2 */
69 0x0800, /* R23 - GPIO_POL */
70 0x008B, /* R24 - Left Line Input 1&2 Volume */
71 0x008B, /* R25 - Left Line Input 3&4 Volume */
72 0x008B, /* R26 - Right Line Input 1&2 Volume */
73 0x008B, /* R27 - Right Line Input 3&4 Volume */
74 0x0000, /* R28 - Left Output Volume */
75 0x0000, /* R29 - Right Output Volume */
76 0x0066, /* R30 - Line Outputs Volume */
77 0x0022, /* R31 - Out3/4 Volume */
78 0x0079, /* R32 - Left OPGA Volume */
79 0x0079, /* R33 - Right OPGA Volume */
80 0x0003, /* R34 - Speaker Volume */
81 0x0003, /* R35 - ClassD1 */
82 0x0000, /* R36 */
83 0x0100, /* R37 - ClassD3 */
84 0x0079, /* R38 - ClassD4 */
85 0x0000, /* R39 - Input Mixer1 */
86 0x0000, /* R40 - Input Mixer2 */
87 0x0000, /* R41 - Input Mixer3 */
88 0x0000, /* R42 - Input Mixer4 */
89 0x0000, /* R43 - Input Mixer5 */
90 0x0000, /* R44 - Input Mixer6 */
91 0x0000, /* R45 - Output Mixer1 */
92 0x0000, /* R46 - Output Mixer2 */
93 0x0000, /* R47 - Output Mixer3 */
94 0x0000, /* R48 - Output Mixer4 */
95 0x0000, /* R49 - Output Mixer5 */
96 0x0000, /* R50 - Output Mixer6 */
97 0x0180, /* R51 - Out3/4 Mixer */
98 0x0000, /* R52 - Line Mixer1 */
99 0x0000, /* R53 - Line Mixer2 */
100 0x0000, /* R54 - Speaker Mixer */
101 0x0000, /* R55 - Additional Control */
102 0x0000, /* R56 - AntiPOP1 */
103 0x0000, /* R57 - AntiPOP2 */
104 0x0000, /* R58 - MICBIAS */
105 0x0000, /* R59 */
106 0x0008, /* R60 - PLL1 */
107 0x0031, /* R61 - PLL2 */
108 0x0026, /* R62 - PLL3 */
109 0x0000, /* R63 - Driver internal */
110 };
111
112 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
113
114 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
115
116 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
117
118 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
119
120 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
121
122 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
123
124 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
125
126 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
127
128 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
129
130 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
131 struct snd_ctl_elem_value *ucontrol)
132 {
133 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
134 struct soc_mixer_control *mc =
135 (struct soc_mixer_control *)kcontrol->private_value;
136 int reg = mc->reg;
137 int ret;
138 u16 val;
139
140 ret = snd_soc_put_volsw(kcontrol, ucontrol);
141 if (ret < 0)
142 return ret;
143
144 /* now hit the volume update bits (always bit 8) */
145 val = snd_soc_read(codec, reg);
146 return snd_soc_write(codec, reg, val | 0x0100);
147 }
148
149 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
150 tlv_array) {\
151 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
152 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
153 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
154 .tlv.p = (tlv_array), \
155 .info = snd_soc_info_volsw, \
156 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
157 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
158
159
160 static const char *wm8990_digital_sidetone[] =
161 {"None", "Left ADC", "Right ADC", "Reserved"};
162
163 static const struct soc_enum wm8990_left_digital_sidetone_enum =
164 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
165 WM8990_ADC_TO_DACL_SHIFT,
166 WM8990_ADC_TO_DACL_MASK,
167 wm8990_digital_sidetone);
168
169 static const struct soc_enum wm8990_right_digital_sidetone_enum =
170 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
171 WM8990_ADC_TO_DACR_SHIFT,
172 WM8990_ADC_TO_DACR_MASK,
173 wm8990_digital_sidetone);
174
175 static const char *wm8990_adcmode[] =
176 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
177
178 static const struct soc_enum wm8990_right_adcmode_enum =
179 SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
180 WM8990_ADC_HPF_CUT_SHIFT,
181 WM8990_ADC_HPF_CUT_MASK,
182 wm8990_adcmode);
183
184 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
185 /* INMIXL */
186 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
187 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
188 /* INMIXR */
189 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
190 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
191
192 /* LOMIX */
193 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
194 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
195 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
196 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
197 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
198 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
199 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
200 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
201 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
202 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
203 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
204 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
205
206 /* ROMIX */
207 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
208 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
209 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
210 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
211 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
212 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
213 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
214 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
215 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
216 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
217 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
218 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
219
220 /* LOUT */
221 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
222 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
223 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
224
225 /* ROUT */
226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
227 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
228 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
229
230 /* LOPGA */
231 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
232 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
233 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
234 WM8990_LOPGAZC_BIT, 1, 0),
235
236 /* ROPGA */
237 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
238 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
239 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
240 WM8990_ROPGAZC_BIT, 1, 0),
241
242 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
243 WM8990_LONMUTE_BIT, 1, 0),
244 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
245 WM8990_LOPMUTE_BIT, 1, 0),
246 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
247 WM8990_LOATTN_BIT, 1, 0),
248 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
249 WM8990_RONMUTE_BIT, 1, 0),
250 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
251 WM8990_ROPMUTE_BIT, 1, 0),
252 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
253 WM8990_ROATTN_BIT, 1, 0),
254
255 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
256 WM8990_OUT3MUTE_BIT, 1, 0),
257 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
258 WM8990_OUT3ATTN_BIT, 1, 0),
259
260 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
261 WM8990_OUT4MUTE_BIT, 1, 0),
262 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
263 WM8990_OUT4ATTN_BIT, 1, 0),
264
265 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
266 WM8990_CDMODE_BIT, 1, 0),
267
268 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
269 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
270 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
271 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
272 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
273 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
274 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
275 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
276 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
277 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
278
279 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
280 WM8990_LEFT_DAC_DIGITAL_VOLUME,
281 WM8990_DACL_VOL_SHIFT,
282 WM8990_DACL_VOL_MASK,
283 0,
284 out_dac_tlv),
285
286 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
287 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
288 WM8990_DACR_VOL_SHIFT,
289 WM8990_DACR_VOL_MASK,
290 0,
291 out_dac_tlv),
292
293 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
294 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
295
296 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
297 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
298 out_sidetone_tlv),
299 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
300 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
301 out_sidetone_tlv),
302
303 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
304 WM8990_ADC_HPF_ENA_BIT, 1, 0),
305
306 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
307
308 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
309 WM8990_LEFT_ADC_DIGITAL_VOLUME,
310 WM8990_ADCL_VOL_SHIFT,
311 WM8990_ADCL_VOL_MASK,
312 0,
313 in_adc_tlv),
314
315 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
316 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
317 WM8990_ADCR_VOL_SHIFT,
318 WM8990_ADCR_VOL_MASK,
319 0,
320 in_adc_tlv),
321
322 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
323 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
324 WM8990_LIN12VOL_SHIFT,
325 WM8990_LIN12VOL_MASK,
326 0,
327 in_pga_tlv),
328
329 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
330 WM8990_LI12ZC_BIT, 1, 0),
331
332 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
333 WM8990_LI12MUTE_BIT, 1, 0),
334
335 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
336 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
337 WM8990_LIN34VOL_SHIFT,
338 WM8990_LIN34VOL_MASK,
339 0,
340 in_pga_tlv),
341
342 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
343 WM8990_LI34ZC_BIT, 1, 0),
344
345 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
346 WM8990_LI34MUTE_BIT, 1, 0),
347
348 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
349 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
350 WM8990_RIN12VOL_SHIFT,
351 WM8990_RIN12VOL_MASK,
352 0,
353 in_pga_tlv),
354
355 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
356 WM8990_RI12ZC_BIT, 1, 0),
357
358 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
359 WM8990_RI12MUTE_BIT, 1, 0),
360
361 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
362 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
363 WM8990_RIN34VOL_SHIFT,
364 WM8990_RIN34VOL_MASK,
365 0,
366 in_pga_tlv),
367
368 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
369 WM8990_RI34ZC_BIT, 1, 0),
370
371 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
372 WM8990_RI34MUTE_BIT, 1, 0),
373
374 };
375
376 /*
377 * _DAPM_ Controls
378 */
379
380 static int inmixer_event(struct snd_soc_dapm_widget *w,
381 struct snd_kcontrol *kcontrol, int event)
382 {
383 u16 reg, fakepower;
384
385 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
386 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
387
388 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
389 (1 << WM8990_AINLMUX_PWR_BIT))) {
390 reg |= WM8990_AINL_ENA;
391 } else {
392 reg &= ~WM8990_AINL_ENA;
393 }
394
395 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
396 (1 << WM8990_AINRMUX_PWR_BIT))) {
397 reg |= WM8990_AINR_ENA;
398 } else {
399 reg &= ~WM8990_AINL_ENA;
400 }
401 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
402
403 return 0;
404 }
405
406 static int outmixer_event(struct snd_soc_dapm_widget *w,
407 struct snd_kcontrol *kcontrol, int event)
408 {
409 u32 reg_shift = kcontrol->private_value & 0xfff;
410 int ret = 0;
411 u16 reg;
412
413 switch (reg_shift) {
414 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
415 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
416 if (reg & WM8990_LDLO) {
417 printk(KERN_WARNING
418 "Cannot set as Output Mixer 1 LDLO Set\n");
419 ret = -1;
420 }
421 break;
422 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
423 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
424 if (reg & WM8990_RDRO) {
425 printk(KERN_WARNING
426 "Cannot set as Output Mixer 2 RDRO Set\n");
427 ret = -1;
428 }
429 break;
430 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
431 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
432 if (reg & WM8990_LDSPK) {
433 printk(KERN_WARNING
434 "Cannot set as Speaker Mixer LDSPK Set\n");
435 ret = -1;
436 }
437 break;
438 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
439 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
440 if (reg & WM8990_RDSPK) {
441 printk(KERN_WARNING
442 "Cannot set as Speaker Mixer RDSPK Set\n");
443 ret = -1;
444 }
445 break;
446 }
447
448 return ret;
449 }
450
451 /* INMIX dB values */
452 static const unsigned int in_mix_tlv[] = {
453 TLV_DB_RANGE_HEAD(1),
454 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
455 };
456
457 /* Left In PGA Connections */
458 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
459 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
460 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
461 };
462
463 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
464 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
465 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
466 };
467
468 /* Right In PGA Connections */
469 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
470 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
471 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
472 };
473
474 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
475 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
476 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
477 };
478
479 /* INMIXL */
480 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
481 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
482 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
483 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
484 7, 0, in_mix_tlv),
485 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
486 1, 0),
487 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
488 1, 0),
489 };
490
491 /* INMIXR */
492 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
493 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
494 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
495 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
496 7, 0, in_mix_tlv),
497 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
498 1, 0),
499 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
500 1, 0),
501 };
502
503 /* AINLMUX */
504 static const char *wm8990_ainlmux[] =
505 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
506
507 static const struct soc_enum wm8990_ainlmux_enum =
508 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
509 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
510
511 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
512 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
513
514 /* DIFFINL */
515
516 /* AINRMUX */
517 static const char *wm8990_ainrmux[] =
518 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
519
520 static const struct soc_enum wm8990_ainrmux_enum =
521 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
522 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
523
524 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
525 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
526
527 /* RXVOICE */
528 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
529 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
530 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
531 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
532 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
533 };
534
535 /* LOMIX */
536 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
537 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
538 WM8990_LRBLO_BIT, 1, 0),
539 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
540 WM8990_LLBLO_BIT, 1, 0),
541 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
542 WM8990_LRI3LO_BIT, 1, 0),
543 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
544 WM8990_LLI3LO_BIT, 1, 0),
545 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
546 WM8990_LR12LO_BIT, 1, 0),
547 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
548 WM8990_LL12LO_BIT, 1, 0),
549 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
550 WM8990_LDLO_BIT, 1, 0),
551 };
552
553 /* ROMIX */
554 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
555 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
556 WM8990_RLBRO_BIT, 1, 0),
557 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
558 WM8990_RRBRO_BIT, 1, 0),
559 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
560 WM8990_RLI3RO_BIT, 1, 0),
561 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
562 WM8990_RRI3RO_BIT, 1, 0),
563 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
564 WM8990_RL12RO_BIT, 1, 0),
565 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
566 WM8990_RR12RO_BIT, 1, 0),
567 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
568 WM8990_RDRO_BIT, 1, 0),
569 };
570
571 /* LONMIX */
572 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
573 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
574 WM8990_LLOPGALON_BIT, 1, 0),
575 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
576 WM8990_LROPGALON_BIT, 1, 0),
577 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
578 WM8990_LOPLON_BIT, 1, 0),
579 };
580
581 /* LOPMIX */
582 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
583 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
584 WM8990_LR12LOP_BIT, 1, 0),
585 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
586 WM8990_LL12LOP_BIT, 1, 0),
587 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
588 WM8990_LLOPGALOP_BIT, 1, 0),
589 };
590
591 /* RONMIX */
592 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
593 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
594 WM8990_RROPGARON_BIT, 1, 0),
595 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
596 WM8990_RLOPGARON_BIT, 1, 0),
597 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
598 WM8990_ROPRON_BIT, 1, 0),
599 };
600
601 /* ROPMIX */
602 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
603 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
604 WM8990_RL12ROP_BIT, 1, 0),
605 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
606 WM8990_RR12ROP_BIT, 1, 0),
607 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
608 WM8990_RROPGAROP_BIT, 1, 0),
609 };
610
611 /* OUT3MIX */
612 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
613 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
614 WM8990_LI4O3_BIT, 1, 0),
615 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
616 WM8990_LPGAO3_BIT, 1, 0),
617 };
618
619 /* OUT4MIX */
620 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
621 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
622 WM8990_RPGAO4_BIT, 1, 0),
623 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
624 WM8990_RI4O4_BIT, 1, 0),
625 };
626
627 /* SPKMIX */
628 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
629 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
630 WM8990_LI2SPK_BIT, 1, 0),
631 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
632 WM8990_LB2SPK_BIT, 1, 0),
633 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
634 WM8990_LOPGASPK_BIT, 1, 0),
635 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
636 WM8990_LDSPK_BIT, 1, 0),
637 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
638 WM8990_RDSPK_BIT, 1, 0),
639 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
640 WM8990_ROPGASPK_BIT, 1, 0),
641 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
642 WM8990_RL12ROP_BIT, 1, 0),
643 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
644 WM8990_RI2SPK_BIT, 1, 0),
645 };
646
647 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
648 /* Input Side */
649 /* Input Lines */
650 SND_SOC_DAPM_INPUT("LIN1"),
651 SND_SOC_DAPM_INPUT("LIN2"),
652 SND_SOC_DAPM_INPUT("LIN3"),
653 SND_SOC_DAPM_INPUT("LIN4/RXN"),
654 SND_SOC_DAPM_INPUT("RIN3"),
655 SND_SOC_DAPM_INPUT("RIN4/RXP"),
656 SND_SOC_DAPM_INPUT("RIN1"),
657 SND_SOC_DAPM_INPUT("RIN2"),
658 SND_SOC_DAPM_INPUT("Internal ADC Source"),
659
660 /* DACs */
661 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
662 WM8990_ADCL_ENA_BIT, 0),
663 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
664 WM8990_ADCR_ENA_BIT, 0),
665
666 /* Input PGAs */
667 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
668 0, &wm8990_dapm_lin12_pga_controls[0],
669 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
670 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
671 0, &wm8990_dapm_lin34_pga_controls[0],
672 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
673 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
674 0, &wm8990_dapm_rin12_pga_controls[0],
675 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
676 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
677 0, &wm8990_dapm_rin34_pga_controls[0],
678 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
679
680 /* INMIXL */
681 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
682 &wm8990_dapm_inmixl_controls[0],
683 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
684 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
685
686 /* AINLMUX */
687 SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
688 &wm8990_dapm_ainlmux_controls, inmixer_event,
689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
690
691 /* INMIXR */
692 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
693 &wm8990_dapm_inmixr_controls[0],
694 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
695 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
696
697 /* AINRMUX */
698 SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
699 &wm8990_dapm_ainrmux_controls, inmixer_event,
700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
701
702 /* Output Side */
703 /* DACs */
704 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
705 WM8990_DACL_ENA_BIT, 0),
706 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
707 WM8990_DACR_ENA_BIT, 0),
708
709 /* LOMIX */
710 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
711 0, &wm8990_dapm_lomix_controls[0],
712 ARRAY_SIZE(wm8990_dapm_lomix_controls),
713 outmixer_event, SND_SOC_DAPM_PRE_REG),
714
715 /* LONMIX */
716 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
717 &wm8990_dapm_lonmix_controls[0],
718 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
719
720 /* LOPMIX */
721 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
722 &wm8990_dapm_lopmix_controls[0],
723 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
724
725 /* OUT3MIX */
726 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
727 &wm8990_dapm_out3mix_controls[0],
728 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
729
730 /* SPKMIX */
731 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
732 &wm8990_dapm_spkmix_controls[0],
733 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
734 SND_SOC_DAPM_PRE_REG),
735
736 /* OUT4MIX */
737 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
738 &wm8990_dapm_out4mix_controls[0],
739 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
740
741 /* ROPMIX */
742 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
743 &wm8990_dapm_ropmix_controls[0],
744 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
745
746 /* RONMIX */
747 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
748 &wm8990_dapm_ronmix_controls[0],
749 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
750
751 /* ROMIX */
752 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
753 0, &wm8990_dapm_romix_controls[0],
754 ARRAY_SIZE(wm8990_dapm_romix_controls),
755 outmixer_event, SND_SOC_DAPM_PRE_REG),
756
757 /* LOUT PGA */
758 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
759 NULL, 0),
760
761 /* ROUT PGA */
762 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
763 NULL, 0),
764
765 /* LOPGA */
766 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
767 NULL, 0),
768
769 /* ROPGA */
770 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
771 NULL, 0),
772
773 /* MICBIAS */
774 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
775 WM8990_MICBIAS_ENA_BIT, 0),
776
777 SND_SOC_DAPM_OUTPUT("LON"),
778 SND_SOC_DAPM_OUTPUT("LOP"),
779 SND_SOC_DAPM_OUTPUT("OUT3"),
780 SND_SOC_DAPM_OUTPUT("LOUT"),
781 SND_SOC_DAPM_OUTPUT("SPKN"),
782 SND_SOC_DAPM_OUTPUT("SPKP"),
783 SND_SOC_DAPM_OUTPUT("ROUT"),
784 SND_SOC_DAPM_OUTPUT("OUT4"),
785 SND_SOC_DAPM_OUTPUT("ROP"),
786 SND_SOC_DAPM_OUTPUT("RON"),
787
788 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
789 };
790
791 static const struct snd_soc_dapm_route audio_map[] = {
792 /* Make DACs turn on when playing even if not mixed into any outputs */
793 {"Internal DAC Sink", NULL, "Left DAC"},
794 {"Internal DAC Sink", NULL, "Right DAC"},
795
796 /* Make ADCs turn on when recording even if not mixed from any inputs */
797 {"Left ADC", NULL, "Internal ADC Source"},
798 {"Right ADC", NULL, "Internal ADC Source"},
799
800 /* Input Side */
801 /* LIN12 PGA */
802 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
803 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
804 /* LIN34 PGA */
805 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
806 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
807 /* INMIXL */
808 {"INMIXL", "Record Left Volume", "LOMIX"},
809 {"INMIXL", "LIN2 Volume", "LIN2"},
810 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
811 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
812 /* AINLMUX */
813 {"AINLMUX", "INMIXL Mix", "INMIXL"},
814 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
815 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
816 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
817 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
818 /* ADC */
819 {"Left ADC", NULL, "AINLMUX"},
820
821 /* RIN12 PGA */
822 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
823 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
824 /* RIN34 PGA */
825 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
826 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
827 /* INMIXL */
828 {"INMIXR", "Record Right Volume", "ROMIX"},
829 {"INMIXR", "RIN2 Volume", "RIN2"},
830 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
831 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
832 /* AINRMUX */
833 {"AINRMUX", "INMIXR Mix", "INMIXR"},
834 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
835 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
836 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
837 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
838 /* ADC */
839 {"Right ADC", NULL, "AINRMUX"},
840
841 /* LOMIX */
842 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
843 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
844 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
845 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
846 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
847 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
848 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
849
850 /* ROMIX */
851 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
852 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
853 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
854 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
855 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
856 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
857 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
858
859 /* SPKMIX */
860 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
861 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
862 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
863 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
864 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
865 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
866 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
867 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
868
869 /* LONMIX */
870 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
871 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
872 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
873
874 /* LOPMIX */
875 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
876 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
877 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
878
879 /* OUT3MIX */
880 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
881 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
882
883 /* OUT4MIX */
884 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
885 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
886
887 /* RONMIX */
888 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
889 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
890 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
891
892 /* ROPMIX */
893 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
894 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
895 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
896
897 /* Out Mixer PGAs */
898 {"LOPGA", NULL, "LOMIX"},
899 {"ROPGA", NULL, "ROMIX"},
900
901 {"LOUT PGA", NULL, "LOMIX"},
902 {"ROUT PGA", NULL, "ROMIX"},
903
904 /* Output Pins */
905 {"LON", NULL, "LONMIX"},
906 {"LOP", NULL, "LOPMIX"},
907 {"OUT3", NULL, "OUT3MIX"},
908 {"LOUT", NULL, "LOUT PGA"},
909 {"SPKN", NULL, "SPKMIX"},
910 {"ROUT", NULL, "ROUT PGA"},
911 {"OUT4", NULL, "OUT4MIX"},
912 {"ROP", NULL, "ROPMIX"},
913 {"RON", NULL, "RONMIX"},
914 };
915
916 static int wm8990_add_widgets(struct snd_soc_codec *codec)
917 {
918 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
919 ARRAY_SIZE(wm8990_dapm_widgets));
920
921 /* set up the WM8990 audio map */
922 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
923
924 return 0;
925 }
926
927 /* PLL divisors */
928 struct _pll_div {
929 u32 div2;
930 u32 n;
931 u32 k;
932 };
933
934 /* The size in bits of the pll divide multiplied by 10
935 * to allow rounding later */
936 #define FIXED_PLL_SIZE ((1 << 16) * 10)
937
938 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
939 unsigned int source)
940 {
941 u64 Kpart;
942 unsigned int K, Ndiv, Nmod;
943
944
945 Ndiv = target / source;
946 if (Ndiv < 6) {
947 source >>= 1;
948 pll_div->div2 = 1;
949 Ndiv = target / source;
950 } else
951 pll_div->div2 = 0;
952
953 if ((Ndiv < 6) || (Ndiv > 12))
954 printk(KERN_WARNING
955 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
956
957 pll_div->n = Ndiv;
958 Nmod = target % source;
959 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
960
961 do_div(Kpart, source);
962
963 K = Kpart & 0xFFFFFFFF;
964
965 /* Check if we need to round */
966 if ((K % 10) >= 5)
967 K += 5;
968
969 /* Move down to proper range now rounding is done */
970 K /= 10;
971
972 pll_div->k = K;
973 }
974
975 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
976 int source, unsigned int freq_in, unsigned int freq_out)
977 {
978 u16 reg;
979 struct snd_soc_codec *codec = codec_dai->codec;
980 struct _pll_div pll_div;
981
982 if (freq_in && freq_out) {
983 pll_factors(&pll_div, freq_out * 4, freq_in);
984
985 /* Turn on PLL */
986 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
987 reg |= WM8990_PLL_ENA;
988 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
989
990 /* sysclk comes from PLL */
991 reg = snd_soc_read(codec, WM8990_CLOCKING_2);
992 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
993
994 /* set up N , fractional mode and pre-divisor if necessary */
995 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
996 (pll_div.div2?WM8990_PRESCALE:0));
997 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
998 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
999 } else {
1000 /* Turn on PLL */
1001 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1002 reg &= ~WM8990_PLL_ENA;
1003 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1004 }
1005 return 0;
1006 }
1007
1008 /*
1009 * Clock after PLL and dividers
1010 */
1011 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1012 int clk_id, unsigned int freq, int dir)
1013 {
1014 struct snd_soc_codec *codec = codec_dai->codec;
1015 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1016
1017 wm8990->sysclk = freq;
1018 return 0;
1019 }
1020
1021 /*
1022 * Set's ADC and Voice DAC format.
1023 */
1024 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1025 unsigned int fmt)
1026 {
1027 struct snd_soc_codec *codec = codec_dai->codec;
1028 u16 audio1, audio3;
1029
1030 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1031 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
1032
1033 /* set master/slave audio interface */
1034 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1035 case SND_SOC_DAIFMT_CBS_CFS:
1036 audio3 &= ~WM8990_AIF_MSTR1;
1037 break;
1038 case SND_SOC_DAIFMT_CBM_CFM:
1039 audio3 |= WM8990_AIF_MSTR1;
1040 break;
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 audio1 &= ~WM8990_AIF_FMT_MASK;
1046
1047 /* interface format */
1048 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1049 case SND_SOC_DAIFMT_I2S:
1050 audio1 |= WM8990_AIF_TMF_I2S;
1051 audio1 &= ~WM8990_AIF_LRCLK_INV;
1052 break;
1053 case SND_SOC_DAIFMT_RIGHT_J:
1054 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1055 audio1 &= ~WM8990_AIF_LRCLK_INV;
1056 break;
1057 case SND_SOC_DAIFMT_LEFT_J:
1058 audio1 |= WM8990_AIF_TMF_LEFTJ;
1059 audio1 &= ~WM8990_AIF_LRCLK_INV;
1060 break;
1061 case SND_SOC_DAIFMT_DSP_A:
1062 audio1 |= WM8990_AIF_TMF_DSP;
1063 audio1 &= ~WM8990_AIF_LRCLK_INV;
1064 break;
1065 case SND_SOC_DAIFMT_DSP_B:
1066 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1067 break;
1068 default:
1069 return -EINVAL;
1070 }
1071
1072 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1073 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1074 return 0;
1075 }
1076
1077 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1078 int div_id, int div)
1079 {
1080 struct snd_soc_codec *codec = codec_dai->codec;
1081 u16 reg;
1082
1083 switch (div_id) {
1084 case WM8990_MCLK_DIV:
1085 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1086 ~WM8990_MCLK_DIV_MASK;
1087 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1088 break;
1089 case WM8990_DACCLK_DIV:
1090 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1091 ~WM8990_DAC_CLKDIV_MASK;
1092 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1093 break;
1094 case WM8990_ADCCLK_DIV:
1095 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1096 ~WM8990_ADC_CLKDIV_MASK;
1097 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1098 break;
1099 case WM8990_BCLK_DIV:
1100 reg = snd_soc_read(codec, WM8990_CLOCKING_1) &
1101 ~WM8990_BCLK_DIV_MASK;
1102 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div);
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 return 0;
1109 }
1110
1111 /*
1112 * Set PCM DAI bit size and sample rate.
1113 */
1114 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1115 struct snd_pcm_hw_params *params,
1116 struct snd_soc_dai *dai)
1117 {
1118 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1119 struct snd_soc_codec *codec = rtd->codec;
1120 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1121
1122 audio1 &= ~WM8990_AIF_WL_MASK;
1123 /* bit size */
1124 switch (params_format(params)) {
1125 case SNDRV_PCM_FORMAT_S16_LE:
1126 break;
1127 case SNDRV_PCM_FORMAT_S20_3LE:
1128 audio1 |= WM8990_AIF_WL_20BITS;
1129 break;
1130 case SNDRV_PCM_FORMAT_S24_LE:
1131 audio1 |= WM8990_AIF_WL_24BITS;
1132 break;
1133 case SNDRV_PCM_FORMAT_S32_LE:
1134 audio1 |= WM8990_AIF_WL_32BITS;
1135 break;
1136 }
1137
1138 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1139 return 0;
1140 }
1141
1142 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1143 {
1144 struct snd_soc_codec *codec = dai->codec;
1145 u16 val;
1146
1147 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1148
1149 if (mute)
1150 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1151 else
1152 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1153
1154 return 0;
1155 }
1156
1157 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1158 enum snd_soc_bias_level level)
1159 {
1160 u16 val;
1161
1162 switch (level) {
1163 case SND_SOC_BIAS_ON:
1164 break;
1165
1166 case SND_SOC_BIAS_PREPARE:
1167 /* VMID=2*50k */
1168 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1169 ~WM8990_VMID_MODE_MASK;
1170 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
1171 break;
1172
1173 case SND_SOC_BIAS_STANDBY:
1174 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1175 /* Enable all output discharge bits */
1176 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1177 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1178 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1179 WM8990_DIS_ROUT);
1180
1181 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1182 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1183 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1184 WM8990_VMIDTOG);
1185
1186 /* Delay to allow output caps to discharge */
1187 msleep(msecs_to_jiffies(300));
1188
1189 /* Disable VMIDTOG */
1190 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1191 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1192
1193 /* disable all output discharge bits */
1194 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1195
1196 /* Enable outputs */
1197 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1198
1199 msleep(msecs_to_jiffies(50));
1200
1201 /* Enable VMID at 2x50k */
1202 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1203
1204 msleep(msecs_to_jiffies(100));
1205
1206 /* Enable VREF */
1207 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1208
1209 msleep(msecs_to_jiffies(600));
1210
1211 /* Enable BUFIOEN */
1212 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1213 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1214 WM8990_BUFIOEN);
1215
1216 /* Disable outputs */
1217 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1218
1219 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1220 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1221
1222 /* Enable workaround for ADC clocking issue. */
1223 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1224 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1225 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1226 }
1227
1228 /* VMID=2*250k */
1229 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1230 ~WM8990_VMID_MODE_MASK;
1231 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
1232 break;
1233
1234 case SND_SOC_BIAS_OFF:
1235 /* Enable POBCTRL and SOFT_ST */
1236 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1237 WM8990_POBCTRL | WM8990_BUFIOEN);
1238
1239 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1240 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1241 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1242 WM8990_BUFIOEN);
1243
1244 /* mute DAC */
1245 val = snd_soc_read(codec, WM8990_DAC_CTRL);
1246 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1247
1248 /* Enable any disabled outputs */
1249 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1250
1251 /* Disable VMID */
1252 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1253
1254 msleep(msecs_to_jiffies(300));
1255
1256 /* Enable all output discharge bits */
1257 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1258 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1259 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1260 WM8990_DIS_ROUT);
1261
1262 /* Disable VREF */
1263 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1264
1265 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1266 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1267 break;
1268 }
1269
1270 codec->bias_level = level;
1271 return 0;
1272 }
1273
1274 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1275 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1276 SNDRV_PCM_RATE_48000)
1277
1278 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1279 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1280
1281 /*
1282 * The WM8990 supports 2 different and mutually exclusive DAI
1283 * configurations.
1284 *
1285 * 1. ADC/DAC on Primary Interface
1286 * 2. ADC on Primary Interface/DAC on secondary
1287 */
1288 static struct snd_soc_dai_ops wm8990_dai_ops = {
1289 .hw_params = wm8990_hw_params,
1290 .digital_mute = wm8990_mute,
1291 .set_fmt = wm8990_set_dai_fmt,
1292 .set_clkdiv = wm8990_set_dai_clkdiv,
1293 .set_pll = wm8990_set_dai_pll,
1294 .set_sysclk = wm8990_set_dai_sysclk,
1295 };
1296
1297 static struct snd_soc_dai_driver wm8990_dai = {
1298 /* ADC/DAC on primary */
1299 .name = "wm8990-hifi",
1300 .playback = {
1301 .stream_name = "Playback",
1302 .channels_min = 1,
1303 .channels_max = 2,
1304 .rates = WM8990_RATES,
1305 .formats = WM8990_FORMATS,},
1306 .capture = {
1307 .stream_name = "Capture",
1308 .channels_min = 1,
1309 .channels_max = 2,
1310 .rates = WM8990_RATES,
1311 .formats = WM8990_FORMATS,},
1312 .ops = &wm8990_dai_ops,
1313 };
1314
1315 static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state)
1316 {
1317 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1318 return 0;
1319 }
1320
1321 static int wm8990_resume(struct snd_soc_codec *codec)
1322 {
1323 int i;
1324 u8 data[2];
1325 u16 *cache = codec->reg_cache;
1326
1327 /* Sync reg_cache with the hardware */
1328 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1329 if (i + 1 == WM8990_RESET)
1330 continue;
1331 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1332 data[1] = cache[i] & 0x00ff;
1333 codec->hw_write(codec->control_data, data, 2);
1334 }
1335
1336 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1337 return 0;
1338 }
1339
1340 /*
1341 * initialise the WM8990 driver
1342 * register the mixer and dsp interfaces with the kernel
1343 */
1344 static int wm8990_probe(struct snd_soc_codec *codec)
1345 {
1346 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1347 int ret;
1348 u16 reg;
1349
1350 codec->control_data = wm8990->control_data;
1351 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1352 if (ret < 0) {
1353 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1354 return ret;
1355 }
1356
1357 wm8990_reset(codec);
1358
1359 /* charge output caps */
1360 codec->bias_level = SND_SOC_BIAS_OFF;
1361 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1362
1363 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
1364 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1365
1366 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) &
1367 ~WM8990_GPIO1_SEL_MASK;
1368 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1369
1370 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1371 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1372
1373 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1374 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1375
1376 snd_soc_add_controls(codec, wm8990_snd_controls,
1377 ARRAY_SIZE(wm8990_snd_controls));
1378 wm8990_add_widgets(codec);
1379
1380 return 0;
1381 }
1382
1383 /* power down chip */
1384 static int wm8990_remove(struct snd_soc_codec *codec)
1385 {
1386 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1387 return 0;
1388 }
1389
1390 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1391 .probe = wm8990_probe,
1392 .remove = wm8990_remove,
1393 .suspend = wm8990_suspend,
1394 .resume = wm8990_resume,
1395 .set_bias_level = wm8990_set_bias_level,
1396 .reg_cache_size = ARRAY_SIZE(wm8990_reg),
1397 .reg_word_size = sizeof(u16),
1398 .reg_cache_default = wm8990_reg,
1399 };
1400
1401 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1402 static __devinit int wm8990_i2c_probe(struct i2c_client *i2c,
1403 const struct i2c_device_id *id)
1404 {
1405 struct wm8990_priv *wm8990;
1406 int ret;
1407
1408 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1409 if (wm8990 == NULL)
1410 return -ENOMEM;
1411
1412 i2c_set_clientdata(i2c, wm8990);
1413 wm8990->control_data = i2c;
1414
1415 ret = snd_soc_register_codec(&i2c->dev,
1416 &soc_codec_dev_wm8990, &wm8990_dai, 1);
1417 if (ret < 0)
1418 kfree(wm8990);
1419 return ret;
1420 }
1421
1422 static __devexit int wm8990_i2c_remove(struct i2c_client *client)
1423 {
1424 snd_soc_unregister_codec(&client->dev);
1425 kfree(i2c_get_clientdata(client));
1426 return 0;
1427 }
1428
1429 static const struct i2c_device_id wm8990_i2c_id[] = {
1430 { "wm8990", 0 },
1431 { }
1432 };
1433 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1434
1435 static struct i2c_driver wm8990_i2c_driver = {
1436 .driver = {
1437 .name = "wm8990-codec",
1438 .owner = THIS_MODULE,
1439 },
1440 .probe = wm8990_i2c_probe,
1441 .remove = __devexit_p(wm8990_i2c_remove),
1442 .id_table = wm8990_i2c_id,
1443 };
1444 #endif
1445
1446 static int __init wm8990_modinit(void)
1447 {
1448 int ret = 0;
1449 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1450 ret = i2c_add_driver(&wm8990_i2c_driver);
1451 if (ret != 0) {
1452 printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n",
1453 ret);
1454 }
1455 #endif
1456 return ret;
1457 }
1458 module_init(wm8990_modinit);
1459
1460 static void __exit wm8990_exit(void)
1461 {
1462 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1463 i2c_del_driver(&wm8990_i2c_driver);
1464 #endif
1465 }
1466 module_exit(wm8990_exit);
1467
1468 MODULE_DESCRIPTION("ASoC WM8990 driver");
1469 MODULE_AUTHOR("Liam Girdwood");
1470 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree