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bnx2x: remove some dead code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blob28bde1610ffba31487bfe0ec0b1c7405301dabfd
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if.h>
43 #include <linux/if_vlan.h>
44 #include <net/ip.h>
45 #include <net/ipv6.h>
46 #include <net/tcp.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
54 #include <linux/io.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
79
80 static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2);
94
95 static int multi_mode = 1;
96 module_param(multi_mode, int, 0);
97 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
100 int num_queues;
101 module_param(num_queues, int, 0);
102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
104
105 static int disable_tpa;
106 module_param(disable_tpa, int, 0);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
111 static int int_mode;
112 module_param(int_mode, int, 0);
113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)");
115
116 static int dropless_fc;
117 module_param(dropless_fc, int, 0);
118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
120 static int poll;
121 module_param(poll, int, 0);
122 MODULE_PARM_DESC(poll, " Use polling (for debug)");
123
124 static int mrrs = -1;
125 module_param(mrrs, int, 0);
126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127
128 static int debug;
129 module_param(debug, int, 0);
130 MODULE_PARM_DESC(debug, " Default debug msglevel");
131
132
133
134 struct workqueue_struct *bnx2x_wq;
135
136 enum bnx2x_board_type {
137 BCM57710 = 0,
138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
142 BCM57800,
143 BCM57800_MF,
144 BCM57810,
145 BCM57810_MF,
146 BCM57840,
147 BCM57840_MF
148 };
149
150 /* indexed by board_type, above */
151 static struct {
152 char *name;
153 } board_info[] __devinitdata = {
154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
166 };
167
168 #ifndef PCI_DEVICE_ID_NX2_57710
169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170 #endif
171 #ifndef PCI_DEVICE_ID_NX2_57711
172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711E
175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57712
178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712_MF
181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57800
184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800_MF
187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57810
190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810_MF
193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57840
196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_MF
199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200 #endif
201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 { 0 }
214 };
215
216 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217
218 /****************************************************************************
219 * General service functions
220 ****************************************************************************/
221
222 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping)
224 {
225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping));
227 }
228
229 static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid)
231 {
232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234
235 __storm_memset_dma_mapping(bp, addr, mapping);
236 }
237
238 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id)
240 {
241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id);
249 }
250
251 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable)
253 {
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable);
262 }
263
264 static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data,
266 u16 pfid)
267 {
268 size_t size = sizeof(struct event_ring_data);
269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273 }
274
275 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid)
277 {
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod);
280 }
281
282 /* used only at init
283 * locking is done by mcp
284 */
285 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
286 {
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET);
291 }
292
293 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 {
295 u32 val;
296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET);
301
302 return val;
303 }
304
305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309 #define DMAE_DP_DST_NONE "dst_addr [none]"
310
311 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl)
313 {
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315
316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val);
326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val);
334 break;
335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val);
344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val);
352 break;
353 default:
354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n"
356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val);
361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n"
363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val);
368 break;
369 }
370
371 }
372
373 /* copy command into DMAE command memory and set DMAE command go */
374 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
375 {
376 u32 cmd_offset;
377 int i;
378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382
383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387 }
388
389 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 {
391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE);
393 }
394
395 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 {
397 return opcode & ~DMAE_CMD_SRC_RESET;
398 }
399
400 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type)
402 {
403 u32 opcode = 0;
404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT));
407
408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
414
415 #ifdef __BIG_ENDIAN
416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 #else
418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
419 #endif
420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode;
423 }
424
425 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type)
428 {
429 memset(dmae, 0, sizeof(struct dmae_command));
430
431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI);
434
435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL;
439 }
440
441 /* issue a dmae command over the init-channel and wailt for completion */
442 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae)
444 {
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
447 int rc = 0;
448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
452
453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */
458 spin_lock_bh(&bp->dmae_lock);
459
460 /* reset completion */
461 *wb_comp = 0;
462
463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465
466 /* wait for completion */
467 udelay(5);
468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470
471 if (!cnt) {
472 BNX2X_ERR("DMAE timeout!\n");
473 rc = DMAE_TIMEOUT;
474 goto unlock;
475 }
476 cnt--;
477 udelay(50);
478 }
479 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
480 BNX2X_ERR("DMAE PCI error!\n");
481 rc = DMAE_PCI_ERROR;
482 }
483
484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
487
488 unlock:
489 spin_unlock_bh(&bp->dmae_lock);
490 return rc;
491 }
492
493 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 u32 len32)
495 {
496 struct dmae_command dmae;
497
498 if (!bp->dmae_ready) {
499 u32 *data = bnx2x_sp(bp, wb_data[0]);
500
501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
502 " using indirect\n", dst_addr, len32);
503 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
504 return;
505 }
506
507 /* set opcode and fixed command fields */
508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509
510 /* fill in addresses and len */
511 dmae.src_addr_lo = U64_LO(dma_addr);
512 dmae.src_addr_hi = U64_HI(dma_addr);
513 dmae.dst_addr_lo = dst_addr >> 2;
514 dmae.dst_addr_hi = 0;
515 dmae.len = len32;
516
517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518
519 /* issue the command and wait for completion */
520 bnx2x_issue_dmae_with_comp(bp, &dmae);
521 }
522
523 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 {
525 struct dmae_command dmae;
526
527 if (!bp->dmae_ready) {
528 u32 *data = bnx2x_sp(bp, wb_data[0]);
529 int i;
530
531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
532 " using indirect\n", src_addr, len32);
533 for (i = 0; i < len32; i++)
534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
535 return;
536 }
537
538 /* set opcode and fixed command fields */
539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540
541 /* fill in addresses and len */
542 dmae.src_addr_lo = src_addr >> 2;
543 dmae.src_addr_hi = 0;
544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
546 dmae.len = len32;
547
548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549
550 /* issue the command and wait for completion */
551 bnx2x_issue_dmae_with_comp(bp, &dmae);
552 }
553
554 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
555 u32 addr, u32 len)
556 {
557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
558 int offset = 0;
559
560 while (len > dmae_wr_max) {
561 bnx2x_write_dmae(bp, phys_addr + offset,
562 addr + offset, dmae_wr_max);
563 offset += dmae_wr_max * 4;
564 len -= dmae_wr_max;
565 }
566
567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
568 }
569
570 /* used only for slowpath so not inlined */
571 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
572 {
573 u32 wb_write[2];
574
575 wb_write[0] = val_hi;
576 wb_write[1] = val_lo;
577 REG_WR_DMAE(bp, reg, wb_write, 2);
578 }
579
580 #ifdef USE_WB_RD
581 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
582 {
583 u32 wb_data[2];
584
585 REG_RD_DMAE(bp, reg, wb_data, 2);
586
587 return HILO_U64(wb_data[0], wb_data[1]);
588 }
589 #endif
590
591 static int bnx2x_mc_assert(struct bnx2x *bp)
592 {
593 char last_idx;
594 int i, rc = 0;
595 u32 row0, row1, row2, row3;
596
597 /* XSTORM */
598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
599 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 if (last_idx)
601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602
603 /* print the asserts */
604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605
606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i));
608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
613 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614
615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617 " 0x%08x 0x%08x 0x%08x\n",
618 i, row3, row2, row1, row0);
619 rc++;
620 } else {
621 break;
622 }
623 }
624
625 /* TSTORM */
626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
627 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 if (last_idx)
629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630
631 /* print the asserts */
632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633
634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i));
636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642
643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645 " 0x%08x 0x%08x 0x%08x\n",
646 i, row3, row2, row1, row0);
647 rc++;
648 } else {
649 break;
650 }
651 }
652
653 /* CSTORM */
654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
655 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 if (last_idx)
657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658
659 /* print the asserts */
660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661
662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i));
664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
669 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670
671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673 " 0x%08x 0x%08x 0x%08x\n",
674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* USTORM */
682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
683 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701 " 0x%08x 0x%08x 0x%08x\n",
702 i, row3, row2, row1, row0);
703 rc++;
704 } else {
705 break;
706 }
707 }
708
709 return rc;
710 }
711
712 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
713 {
714 u32 addr, val;
715 u32 mark, offset;
716 __be32 data[9];
717 int word;
718 u32 trace_shmem_base;
719 if (BP_NOMCP(bp)) {
720 BNX2X_ERR("NO MCP - can not dump\n");
721 return;
722 }
723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
724 (bp->common.bc_ver & 0xff0000) >> 16,
725 (bp->common.bc_ver & 0xff00) >> 8,
726 (bp->common.bc_ver & 0xff));
727
728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
730 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731
732 if (BP_PATH(bp) == 0)
733 trace_shmem_base = bp->common.shmem_base;
734 else
735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
736 addr = trace_shmem_base - 0x0800 + 4;
737 mark = REG_RD(bp, addr);
738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
739 + ((mark + 0x3) & ~0x3) - 0x08000000;
740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
741
742 printk("%s", lvl);
743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
744 for (word = 0; word < 8; word++)
745 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 data[8] = 0x0;
747 pr_cont("%s", (char *)data);
748 }
749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
750 for (word = 0; word < 8; word++)
751 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 data[8] = 0x0;
753 pr_cont("%s", (char *)data);
754 }
755 printk("%s" "end of fw dump\n", lvl);
756 }
757
758 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 {
760 bnx2x_fw_dump_lvl(bp, KERN_ERR);
761 }
762
763 void bnx2x_panic_dump(struct bnx2x *bp)
764 {
765 int i;
766 u16 j;
767 struct hc_sp_status_block_data sp_sb_data;
768 int func = BP_FUNC(bp);
769 #ifdef BNX2X_STOP_ON_ERROR
770 u16 start = 0, end = 0;
771 u8 cos;
772 #endif
773
774 bp->stats_state = STATS_STATE_DISABLED;
775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776
777 BNX2X_ERR("begin crash dump -----------------\n");
778
779 /* Indices */
780 /* Common */
781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783 bp->def_idx, bp->def_att_idx, bp->attn_state,
784 bp->spq_prod_idx, bp->stats_counter);
785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786 bp->def_status_blk->atten_status_block.attn_bits,
787 bp->def_status_blk->atten_status_block.attn_bits_ack,
788 bp->def_status_blk->atten_status_block.status_block_id,
789 bp->def_status_blk->atten_status_block.attn_bits_index);
790 BNX2X_ERR(" def (");
791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 pr_cont("0x%x%s",
793 bp->def_status_blk->sp_sb.index_values[i],
794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795
796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
799 i*sizeof(u32));
800
801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state);
809
810
811 for_each_eth_queue(bp, i) {
812 struct bnx2x_fastpath *fp = &bp->fp[i];
813 int loop;
814 struct hc_status_block_data_e2 sb_data_e2;
815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
820 struct hc_index_data *hc_index_p =
821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
824 u8 data_size, cos;
825 u32 *sb_data_p;
826 struct bnx2x_fp_txdata txdata;
827
828 /* Rx */
829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
830 " rx_comp_prod(0x%x)"
831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
832 i, fp->rx_bd_prod, fp->rx_bd_cons,
833 fp->rx_comp_prod,
834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
836 " fp_hc_idx(0x%x)\n",
837 fp->rx_sge_prod, fp->last_max_sge,
838 le16_to_cpu(fp->fp_hc_idx));
839
840 /* Tx */
841 for_each_cos_in_tx_queue(fp, cos)
842 {
843 txdata = fp->txdata[cos];
844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846 " *tx_cons_sb(0x%x)\n",
847 i, txdata.tx_pkt_prod,
848 txdata.tx_pkt_cons, txdata.tx_bd_prod,
849 txdata.tx_bd_cons,
850 le16_to_cpu(*txdata.tx_cons_sb));
851 }
852
853 loop = CHIP_IS_E1x(bp) ?
854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
855
856 /* host sb data */
857
858 #ifdef BCM_CNIC
859 if (IS_FCOE_FP(fp))
860 continue;
861 #endif
862 BNX2X_ERR(" run indexes (");
863 for (j = 0; j < HC_SB_MAX_SM; j++)
864 pr_cont("0x%x%s",
865 fp->sb_running_index[j],
866 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
867
868 BNX2X_ERR(" indexes (");
869 for (j = 0; j < loop; j++)
870 pr_cont("0x%x%s",
871 fp->sb_index_values[j],
872 (j == loop - 1) ? ")" : " ");
873 /* fw sb data */
874 data_size = CHIP_IS_E1x(bp) ?
875 sizeof(struct hc_status_block_data_e1x) :
876 sizeof(struct hc_status_block_data_e2);
877 data_size /= sizeof(u32);
878 sb_data_p = CHIP_IS_E1x(bp) ?
879 (u32 *)&sb_data_e1x :
880 (u32 *)&sb_data_e2;
881 /* copy sb data in here */
882 for (j = 0; j < data_size; j++)
883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
885 j * sizeof(u32));
886
887 if (!CHIP_IS_E1x(bp)) {
888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
890 "state(0x%x)\n",
891 sb_data_e2.common.p_func.pf_id,
892 sb_data_e2.common.p_func.vf_id,
893 sb_data_e2.common.p_func.vf_valid,
894 sb_data_e2.common.p_func.vnic_id,
895 sb_data_e2.common.same_igu_sb_1b,
896 sb_data_e2.common.state);
897 } else {
898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
900 "state(0x%x)\n",
901 sb_data_e1x.common.p_func.pf_id,
902 sb_data_e1x.common.p_func.vf_id,
903 sb_data_e1x.common.p_func.vf_valid,
904 sb_data_e1x.common.p_func.vnic_id,
905 sb_data_e1x.common.same_igu_sb_1b,
906 sb_data_e1x.common.state);
907 }
908
909 /* SB_SMs data */
910 for (j = 0; j < HC_SB_MAX_SM; j++) {
911 pr_cont("SM[%d] __flags (0x%x) "
912 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
913 "time_to_expire (0x%x) "
914 "timer_value(0x%x)\n", j,
915 hc_sm_p[j].__flags,
916 hc_sm_p[j].igu_sb_id,
917 hc_sm_p[j].igu_seg_id,
918 hc_sm_p[j].time_to_expire,
919 hc_sm_p[j].timer_value);
920 }
921
922 /* Indecies data */
923 for (j = 0; j < loop; j++) {
924 pr_cont("INDEX[%d] flags (0x%x) "
925 "timeout (0x%x)\n", j,
926 hc_index_p[j].flags,
927 hc_index_p[j].timeout);
928 }
929 }
930
931 #ifdef BNX2X_STOP_ON_ERROR
932 /* Rings */
933 /* Rx */
934 for_each_rx_queue(bp, i) {
935 struct bnx2x_fastpath *fp = &bp->fp[i];
936
937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
939 for (j = start; j != end; j = RX_BD(j + 1)) {
940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
942
943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
945 }
946
947 start = RX_SGE(fp->rx_sge_prod);
948 end = RX_SGE(fp->last_max_sge);
949 for (j = start; j != end; j = RX_SGE(j + 1)) {
950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
952
953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954 i, j, rx_sge[1], rx_sge[0], sw_page->page);
955 }
956
957 start = RCQ_BD(fp->rx_comp_cons - 10);
958 end = RCQ_BD(fp->rx_comp_cons + 503);
959 for (j = start; j != end; j = RCQ_BD(j + 1)) {
960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
961
962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
964 }
965 }
966
967 /* Tx */
968 for_each_tx_queue(bp, i) {
969 struct bnx2x_fastpath *fp = &bp->fp[i];
970 for_each_cos_in_tx_queue(fp, cos) {
971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
972
973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 struct sw_tx_bd *sw_bd =
977 &txdata->tx_buf_ring[j];
978
979 BNX2X_ERR("fp%d: txdata %d, "
980 "packet[%x]=[%p,%x]\n",
981 i, cos, j, sw_bd->skb,
982 sw_bd->first_bd);
983 }
984
985 start = TX_BD(txdata->tx_bd_cons - 10);
986 end = TX_BD(txdata->tx_bd_cons + 254);
987 for (j = start; j != end; j = TX_BD(j + 1)) {
988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
989
990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
991 "[%x:%x:%x:%x]\n",
992 i, cos, j, tx_bd[0], tx_bd[1],
993 tx_bd[2], tx_bd[3]);
994 }
995 }
996 }
997 #endif
998 bnx2x_fw_dump(bp);
999 bnx2x_mc_assert(bp);
1000 BNX2X_ERR("end crash dump -----------------\n");
1001 }
1002
1003 /*
1004 * FLR Support for E2
1005 *
1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1007 * initialization.
1008 */
1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010 #define FLR_WAIT_INTERAVAL 50 /* usec */
1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1012
1013 struct pbf_pN_buf_regs {
1014 int pN;
1015 u32 init_crd;
1016 u32 crd;
1017 u32 crd_freed;
1018 };
1019
1020 struct pbf_pN_cmd_regs {
1021 int pN;
1022 u32 lines_occup;
1023 u32 lines_freed;
1024 };
1025
1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1027 struct pbf_pN_buf_regs *regs,
1028 u32 poll_count)
1029 {
1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1031 u32 cur_cnt = poll_count;
1032
1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1034 crd = crd_start = REG_RD(bp, regs->crd);
1035 init_crd = REG_RD(bp, regs->init_crd);
1036
1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1040
1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1042 (init_crd - crd_start))) {
1043 if (cur_cnt--) {
1044 udelay(FLR_WAIT_INTERAVAL);
1045 crd = REG_RD(bp, regs->crd);
1046 crd_freed = REG_RD(bp, regs->crd_freed);
1047 } else {
1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1049 regs->pN);
1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1051 regs->pN, crd);
1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1053 regs->pN, crd_freed);
1054 break;
1055 }
1056 }
1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1059 }
1060
1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1062 struct pbf_pN_cmd_regs *regs,
1063 u32 poll_count)
1064 {
1065 u32 occup, to_free, freed, freed_start;
1066 u32 cur_cnt = poll_count;
1067
1068 occup = to_free = REG_RD(bp, regs->lines_occup);
1069 freed = freed_start = REG_RD(bp, regs->lines_freed);
1070
1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1073
1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1075 if (cur_cnt--) {
1076 udelay(FLR_WAIT_INTERAVAL);
1077 occup = REG_RD(bp, regs->lines_occup);
1078 freed = REG_RD(bp, regs->lines_freed);
1079 } else {
1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1081 regs->pN);
1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1083 regs->pN, occup);
1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1085 regs->pN, freed);
1086 break;
1087 }
1088 }
1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1091 }
1092
1093 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1094 u32 expected, u32 poll_count)
1095 {
1096 u32 cur_cnt = poll_count;
1097 u32 val;
1098
1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1100 udelay(FLR_WAIT_INTERAVAL);
1101
1102 return val;
1103 }
1104
1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1106 char *msg, u32 poll_cnt)
1107 {
1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1109 if (val != 0) {
1110 BNX2X_ERR("%s usage count=%d\n", msg, val);
1111 return 1;
1112 }
1113 return 0;
1114 }
1115
1116 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1117 {
1118 /* adjust polling timeout */
1119 if (CHIP_REV_IS_EMUL(bp))
1120 return FLR_POLL_CNT * 2000;
1121
1122 if (CHIP_REV_IS_FPGA(bp))
1123 return FLR_POLL_CNT * 120;
1124
1125 return FLR_POLL_CNT;
1126 }
1127
1128 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1129 {
1130 struct pbf_pN_cmd_regs cmd_regs[] = {
1131 {0, (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_OCCUPANCY_Q0 :
1133 PBF_REG_P0_TQ_OCCUPANCY,
1134 (CHIP_IS_E3B0(bp)) ?
1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1136 PBF_REG_P0_TQ_LINES_FREED_CNT},
1137 {1, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_TQ_OCCUPANCY_Q1 :
1139 PBF_REG_P1_TQ_OCCUPANCY,
1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1142 PBF_REG_P1_TQ_LINES_FREED_CNT},
1143 {4, (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_TQ_OCCUPANCY_LB_Q :
1145 PBF_REG_P4_TQ_OCCUPANCY,
1146 (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1148 PBF_REG_P4_TQ_LINES_FREED_CNT}
1149 };
1150
1151 struct pbf_pN_buf_regs buf_regs[] = {
1152 {0, (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INIT_CRD_Q0 :
1154 PBF_REG_P0_INIT_CRD ,
1155 (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_CREDIT_Q0 :
1157 PBF_REG_P0_CREDIT,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1161 {1, (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INIT_CRD_Q1 :
1163 PBF_REG_P1_INIT_CRD,
1164 (CHIP_IS_E3B0(bp)) ?
1165 PBF_REG_CREDIT_Q1 :
1166 PBF_REG_P1_CREDIT,
1167 (CHIP_IS_E3B0(bp)) ?
1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1170 {4, (CHIP_IS_E3B0(bp)) ?
1171 PBF_REG_INIT_CRD_LB_Q :
1172 PBF_REG_P4_INIT_CRD,
1173 (CHIP_IS_E3B0(bp)) ?
1174 PBF_REG_CREDIT_LB_Q :
1175 PBF_REG_P4_CREDIT,
1176 (CHIP_IS_E3B0(bp)) ?
1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1179 };
1180
1181 int i;
1182
1183 /* Verify the command queues are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1186
1187
1188 /* Verify the transmission buffers are flushed P0, P1, P4 */
1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1191 }
1192
1193 #define OP_GEN_PARAM(param) \
1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1195
1196 #define OP_GEN_TYPE(type) \
1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1198
1199 #define OP_GEN_AGG_VECT(index) \
1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1201
1202
1203 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1204 u32 poll_cnt)
1205 {
1206 struct sdm_op_gen op_gen = {0};
1207
1208 u32 comp_addr = BAR_CSTRORM_INTMEM +
1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1210 int ret = 0;
1211
1212 if (REG_RD(bp, comp_addr)) {
1213 BNX2X_ERR("Cleanup complete is not 0\n");
1214 return 1;
1215 }
1216
1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1221
1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1224
1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1226 BNX2X_ERR("FW final cleanup did not succeed\n");
1227 ret = 1;
1228 }
1229 /* Zero completion for nxt FLR */
1230 REG_WR(bp, comp_addr, 0);
1231
1232 return ret;
1233 }
1234
1235 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1236 {
1237 int pos;
1238 u16 status;
1239
1240 pos = pci_pcie_cap(dev);
1241 if (!pos)
1242 return false;
1243
1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1245 return status & PCI_EXP_DEVSTA_TRPND;
1246 }
1247
1248 /* PF FLR specific routines
1249 */
1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1251 {
1252
1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 CFC_REG_NUM_LCIDS_INSIDE_PF,
1256 "CFC PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260
1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1263 DORQ_REG_PF_USAGE_CNT,
1264 "DQ PF usage counter timed out",
1265 poll_cnt))
1266 return 1;
1267
1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1271 "QM PF usage counter timed out",
1272 poll_cnt))
1273 return 1;
1274
1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1278 "Timers VNIC usage counter timed out",
1279 poll_cnt))
1280 return 1;
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1283 "Timers NUM_SCANS usage counter timed out",
1284 poll_cnt))
1285 return 1;
1286
1287 /* Wait DMAE PF usage counter to zero */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289 dmae_reg_go_c[INIT_DMAE_C(bp)],
1290 "DMAE dommand register timed out",
1291 poll_cnt))
1292 return 1;
1293
1294 return 0;
1295 }
1296
1297 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1298 {
1299 u32 val;
1300
1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1303
1304 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1306
1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1309
1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1312
1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1315
1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1318
1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1321
1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1324 val);
1325 }
1326
1327 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1328 {
1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1330
1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1332
1333 /* Re-enable PF target read access */
1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1335
1336 /* Poll HW usage counters */
1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1338 return -EBUSY;
1339
1340 /* Zero the igu 'trailing edge' and 'leading edge' */
1341
1342 /* Send the FW cleanup command */
1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1344 return -EBUSY;
1345
1346 /* ATC cleanup */
1347
1348 /* Verify TX hw is flushed */
1349 bnx2x_tx_hw_flushed(bp, poll_cnt);
1350
1351 /* Wait 100ms (not adjusted according to platform) */
1352 msleep(100);
1353
1354 /* Verify no pending pci transactions */
1355 if (bnx2x_is_pcie_pending(bp->pdev))
1356 BNX2X_ERR("PCIE Transactions still pending\n");
1357
1358 /* Debug */
1359 bnx2x_hw_enable_status(bp);
1360
1361 /*
1362 * Master enable - Due to WB DMAE writes performed before this
1363 * register is re-initialized as part of the regular function init
1364 */
1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1366
1367 return 0;
1368 }
1369
1370 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1371 {
1372 int port = BP_PORT(bp);
1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1374 u32 val = REG_RD(bp, addr);
1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1377
1378 if (msix) {
1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1380 HC_CONFIG_0_REG_INT_LINE_EN_0);
1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1383 } else if (msi) {
1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1388 } else {
1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1391 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1393
1394 if (!CHIP_IS_E1(bp)) {
1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1396 val, port, addr);
1397
1398 REG_WR(bp, addr, val);
1399
1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1401 }
1402 }
1403
1404 if (CHIP_IS_E1(bp))
1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1406
1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1409
1410 REG_WR(bp, addr, val);
1411 /*
1412 * Ensure that HC_CONFIG is written before leading/trailing edge config
1413 */
1414 mmiowb();
1415 barrier();
1416
1417 if (!CHIP_IS_E1(bp)) {
1418 /* init leading/trailing edge */
1419 if (IS_MF(bp)) {
1420 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1421 if (bp->port.pmf)
1422 /* enable nig and gpio3 attention */
1423 val |= 0x1100;
1424 } else
1425 val = 0xffff;
1426
1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1429 }
1430
1431 /* Make sure that interrupts are indeed enabled from here on */
1432 mmiowb();
1433 }
1434
1435 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1436 {
1437 u32 val;
1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1440
1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1442
1443 if (msix) {
1444 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 val |= (IGU_PF_CONF_FUNC_EN |
1447 IGU_PF_CONF_MSI_MSIX_EN |
1448 IGU_PF_CONF_ATTN_BIT_EN);
1449 } else if (msi) {
1450 val &= ~IGU_PF_CONF_INT_LINE_EN;
1451 val |= (IGU_PF_CONF_FUNC_EN |
1452 IGU_PF_CONF_MSI_MSIX_EN |
1453 IGU_PF_CONF_ATTN_BIT_EN |
1454 IGU_PF_CONF_SINGLE_ISR_EN);
1455 } else {
1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1457 val |= (IGU_PF_CONF_FUNC_EN |
1458 IGU_PF_CONF_INT_LINE_EN |
1459 IGU_PF_CONF_ATTN_BIT_EN |
1460 IGU_PF_CONF_SINGLE_ISR_EN);
1461 }
1462
1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1465
1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1467
1468 barrier();
1469
1470 /* init leading/trailing edge */
1471 if (IS_MF(bp)) {
1472 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1473 if (bp->port.pmf)
1474 /* enable nig and gpio3 attention */
1475 val |= 0x1100;
1476 } else
1477 val = 0xffff;
1478
1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1481
1482 /* Make sure that interrupts are indeed enabled from here on */
1483 mmiowb();
1484 }
1485
1486 void bnx2x_int_enable(struct bnx2x *bp)
1487 {
1488 if (bp->common.int_block == INT_BLOCK_HC)
1489 bnx2x_hc_int_enable(bp);
1490 else
1491 bnx2x_igu_int_enable(bp);
1492 }
1493
1494 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1495 {
1496 int port = BP_PORT(bp);
1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1498 u32 val = REG_RD(bp, addr);
1499
1500 /*
1501 * in E1 we must use only PCI configuration space to disable
1502 * MSI/MSIX capablility
1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1504 */
1505 if (CHIP_IS_E1(bp)) {
1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507 * Use mask register to prevent from HC sending interrupts
1508 * after we exit the function
1509 */
1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1511
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1515 } else
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1520
1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1522 val, port, addr);
1523
1524 /* flush all outstanding writes */
1525 mmiowb();
1526
1527 REG_WR(bp, addr, val);
1528 if (REG_RD(bp, addr) != val)
1529 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1530 }
1531
1532 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1533 {
1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1535
1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1537 IGU_PF_CONF_INT_LINE_EN |
1538 IGU_PF_CONF_ATTN_BIT_EN);
1539
1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1541
1542 /* flush all outstanding writes */
1543 mmiowb();
1544
1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1547 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1548 }
1549
1550 void bnx2x_int_disable(struct bnx2x *bp)
1551 {
1552 if (bp->common.int_block == INT_BLOCK_HC)
1553 bnx2x_hc_int_disable(bp);
1554 else
1555 bnx2x_igu_int_disable(bp);
1556 }
1557
1558 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1559 {
1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1561 int i, offset;
1562
1563 if (disable_hw)
1564 /* prevent the HW from sending interrupts */
1565 bnx2x_int_disable(bp);
1566
1567 /* make sure all ISRs are done */
1568 if (msix) {
1569 synchronize_irq(bp->msix_table[0].vector);
1570 offset = 1;
1571 #ifdef BCM_CNIC
1572 offset++;
1573 #endif
1574 for_each_eth_queue(bp, i)
1575 synchronize_irq(bp->msix_table[offset++].vector);
1576 } else
1577 synchronize_irq(bp->pdev->irq);
1578
1579 /* make sure sp_task is not running */
1580 cancel_delayed_work(&bp->sp_task);
1581 cancel_delayed_work(&bp->period_task);
1582 flush_workqueue(bnx2x_wq);
1583 }
1584
1585 /* fast path */
1586
1587 /*
1588 * General service functions
1589 */
1590
1591 /* Return true if succeeded to acquire the lock */
1592 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1593 {
1594 u32 lock_status;
1595 u32 resource_bit = (1 << resource);
1596 int func = BP_FUNC(bp);
1597 u32 hw_lock_control_reg;
1598
1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1600
1601 /* Validating that the resource is within range */
1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1603 DP(NETIF_MSG_HW,
1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1606 return false;
1607 }
1608
1609 if (func <= 5)
1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1611 else
1612 hw_lock_control_reg =
1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1614
1615 /* Try to acquire the lock */
1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1617 lock_status = REG_RD(bp, hw_lock_control_reg);
1618 if (lock_status & resource_bit)
1619 return true;
1620
1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1622 return false;
1623 }
1624
1625 /**
1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1627 *
1628 * @bp: driver handle
1629 *
1630 * Returns the recovery leader resource id according to the engine this function
1631 * belongs to. Currently only only 2 engines is supported.
1632 */
1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1634 {
1635 if (BP_PATH(bp))
1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1637 else
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1639 }
1640
1641 /**
1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1643 *
1644 * @bp: driver handle
1645 *
1646 * Tries to aquire a leader lock for cuurent engine.
1647 */
1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1649 {
1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1651 }
1652
1653 #ifdef BCM_CNIC
1654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1655 #endif
1656
1657 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1658 {
1659 struct bnx2x *bp = fp->bp;
1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1664
1665 DP(BNX2X_MSG_SP,
1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1667 fp->index, cid, command, bp->state,
1668 rr_cqe->ramrod_cqe.ramrod_type);
1669
1670 switch (command) {
1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1673 drv_cmd = BNX2X_Q_CMD_UPDATE;
1674 break;
1675
1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1678 drv_cmd = BNX2X_Q_CMD_SETUP;
1679 break;
1680
1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1684 break;
1685
1686 case (RAMROD_CMD_ID_ETH_HALT):
1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1688 drv_cmd = BNX2X_Q_CMD_HALT;
1689 break;
1690
1691 case (RAMROD_CMD_ID_ETH_TERMINATE):
1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1693 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1694 break;
1695
1696 case (RAMROD_CMD_ID_ETH_EMPTY):
1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1698 drv_cmd = BNX2X_Q_CMD_EMPTY;
1699 break;
1700
1701 default:
1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703 command, fp->index);
1704 return;
1705 }
1706
1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1708 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1709 /* q_obj->complete_cmd() failure means that this was
1710 * an unexpected completion.
1711 *
1712 * In this case we don't want to increase the bp->spq_left
1713 * because apparently we haven't sent this command the first
1714 * place.
1715 */
1716 #ifdef BNX2X_STOP_ON_ERROR
1717 bnx2x_panic();
1718 #else
1719 return;
1720 #endif
1721
1722 smp_mb__before_atomic_inc();
1723 atomic_inc(&bp->cq_spq_left);
1724 /* push the change in bp->spq_left and towards the memory */
1725 smp_mb__after_atomic_inc();
1726
1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1728
1729 return;
1730 }
1731
1732 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734 {
1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736
1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1738 start);
1739 }
1740
1741 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1742 {
1743 struct bnx2x *bp = netdev_priv(dev_instance);
1744 u16 status = bnx2x_ack_int(bp);
1745 u16 mask;
1746 int i;
1747 u8 cos;
1748
1749 /* Return here if interrupt is shared and it's not for us */
1750 if (unlikely(status == 0)) {
1751 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1752 return IRQ_NONE;
1753 }
1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1755
1756 #ifdef BNX2X_STOP_ON_ERROR
1757 if (unlikely(bp->panic))
1758 return IRQ_HANDLED;
1759 #endif
1760
1761 for_each_eth_queue(bp, i) {
1762 struct bnx2x_fastpath *fp = &bp->fp[i];
1763
1764 mask = 0x2 << (fp->index + CNIC_PRESENT);
1765 if (status & mask) {
1766 /* Handle Rx or Tx according to SB id */
1767 prefetch(fp->rx_cons_sb);
1768 for_each_cos_in_tx_queue(fp, cos)
1769 prefetch(fp->txdata[cos].tx_cons_sb);
1770 prefetch(&fp->sb_running_index[SM_RX_ID]);
1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1772 status &= ~mask;
1773 }
1774 }
1775
1776 #ifdef BCM_CNIC
1777 mask = 0x2;
1778 if (status & (mask | 0x1)) {
1779 struct cnic_ops *c_ops = NULL;
1780
1781 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 rcu_read_lock();
1783 c_ops = rcu_dereference(bp->cnic_ops);
1784 if (c_ops)
1785 c_ops->cnic_handler(bp->cnic_data, NULL);
1786 rcu_read_unlock();
1787 }
1788
1789 status &= ~mask;
1790 }
1791 #endif
1792
1793 if (unlikely(status & 0x1)) {
1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795
1796 status &= ~0x1;
1797 if (!status)
1798 return IRQ_HANDLED;
1799 }
1800
1801 if (unlikely(status))
1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1803 status);
1804
1805 return IRQ_HANDLED;
1806 }
1807
1808 /* Link */
1809
1810 /*
1811 * General service functions
1812 */
1813
1814 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1815 {
1816 u32 lock_status;
1817 u32 resource_bit = (1 << resource);
1818 int func = BP_FUNC(bp);
1819 u32 hw_lock_control_reg;
1820 int cnt;
1821
1822 /* Validating that the resource is within range */
1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 DP(NETIF_MSG_HW,
1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1827 return -EINVAL;
1828 }
1829
1830 if (func <= 5) {
1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 } else {
1833 hw_lock_control_reg =
1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1835 }
1836
1837 /* Validating that the resource is not already taken */
1838 lock_status = REG_RD(bp, hw_lock_control_reg);
1839 if (lock_status & resource_bit) {
1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1841 lock_status, resource_bit);
1842 return -EEXIST;
1843 }
1844
1845 /* Try for 5 second every 5ms */
1846 for (cnt = 0; cnt < 1000; cnt++) {
1847 /* Try to acquire the lock */
1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (lock_status & resource_bit)
1851 return 0;
1852
1853 msleep(5);
1854 }
1855 DP(NETIF_MSG_HW, "Timeout\n");
1856 return -EAGAIN;
1857 }
1858
1859 int bnx2x_release_leader_lock(struct bnx2x *bp)
1860 {
1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1862 }
1863
1864 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1865 {
1866 u32 lock_status;
1867 u32 resource_bit = (1 << resource);
1868 int func = BP_FUNC(bp);
1869 u32 hw_lock_control_reg;
1870
1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872
1873 /* Validating that the resource is within range */
1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 DP(NETIF_MSG_HW,
1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1878 return -EINVAL;
1879 }
1880
1881 if (func <= 5) {
1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 } else {
1884 hw_lock_control_reg =
1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1886 }
1887
1888 /* Validating that the resource is currently taken */
1889 lock_status = REG_RD(bp, hw_lock_control_reg);
1890 if (!(lock_status & resource_bit)) {
1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1892 lock_status, resource_bit);
1893 return -EFAULT;
1894 }
1895
1896 REG_WR(bp, hw_lock_control_reg, resource_bit);
1897 return 0;
1898 }
1899
1900
1901 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902 {
1903 /* The GPIO should be swapped if swap register is set and active */
1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1906 int gpio_shift = gpio_num +
1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1908 u32 gpio_mask = (1 << gpio_shift);
1909 u32 gpio_reg;
1910 int value;
1911
1912 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1914 return -EINVAL;
1915 }
1916
1917 /* read GPIO value */
1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919
1920 /* get the requested pin value */
1921 if ((gpio_reg & gpio_mask) == gpio_mask)
1922 value = 1;
1923 else
1924 value = 0;
1925
1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1927
1928 return value;
1929 }
1930
1931 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1932 {
1933 /* The GPIO should be swapped if swap register is set and active */
1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1936 int gpio_shift = gpio_num +
1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1938 u32 gpio_mask = (1 << gpio_shift);
1939 u32 gpio_reg;
1940
1941 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1943 return -EINVAL;
1944 }
1945
1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947 /* read GPIO and mask except the float bits */
1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1949
1950 switch (mode) {
1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1953 gpio_num, gpio_shift);
1954 /* clear FLOAT and set CLR */
1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1957 break;
1958
1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1961 gpio_num, gpio_shift);
1962 /* clear FLOAT and set SET */
1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1965 break;
1966
1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1969 gpio_num, gpio_shift);
1970 /* set FLOAT */
1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 break;
1973
1974 default:
1975 break;
1976 }
1977
1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1980
1981 return 0;
1982 }
1983
1984 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1985 {
1986 u32 gpio_reg = 0;
1987 int rc = 0;
1988
1989 /* Any port swapping should be handled by caller. */
1990
1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1997
1998 switch (mode) {
1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 /* set CLR */
2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2003 break;
2004
2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 /* set SET */
2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2009 break;
2010
2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 /* set FLOAT */
2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2015 break;
2016
2017 default:
2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2019 rc = -EINVAL;
2020 break;
2021 }
2022
2023 if (rc == 0)
2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025
2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2027
2028 return rc;
2029 }
2030
2031 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 {
2033 /* The GPIO should be swapped if swap register is set and active */
2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2036 int gpio_shift = gpio_num +
2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2038 u32 gpio_mask = (1 << gpio_shift);
2039 u32 gpio_reg;
2040
2041 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2043 return -EINVAL;
2044 }
2045
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 /* read GPIO int */
2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2049
2050 switch (mode) {
2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2053 "output low\n", gpio_num, gpio_shift);
2054 /* clear SET and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2057 break;
2058
2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2061 "output high\n", gpio_num, gpio_shift);
2062 /* clear CLR and set SET */
2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2065 break;
2066
2067 default:
2068 break;
2069 }
2070
2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2073
2074 return 0;
2075 }
2076
2077 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2078 {
2079 u32 spio_mask = (1 << spio_num);
2080 u32 spio_reg;
2081
2082 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2083 (spio_num > MISC_REGISTERS_SPIO_7)) {
2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2085 return -EINVAL;
2086 }
2087
2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2089 /* read SPIO and mask except the float bits */
2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2091
2092 switch (mode) {
2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2095 /* clear FLOAT and set CLR */
2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2098 break;
2099
2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2102 /* clear FLOAT and set SET */
2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2105 break;
2106
2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 /* set FLOAT */
2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2111 break;
2112
2113 default:
2114 break;
2115 }
2116
2117 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2119
2120 return 0;
2121 }
2122
2123 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2124 {
2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2126 switch (bp->link_vars.ieee_fc &
2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2130 ADVERTISED_Pause);
2131 break;
2132
2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2135 ADVERTISED_Pause);
2136 break;
2137
2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2140 break;
2141
2142 default:
2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2144 ADVERTISED_Pause);
2145 break;
2146 }
2147 }
2148
2149 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2150 {
2151 if (!BP_NOMCP(bp)) {
2152 u8 rc;
2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2155 /*
2156 * Initialize link parameters structure variables
2157 * It is recommended to turn off RX FC for jumbo frames
2158 * for better performance
2159 */
2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2162 else
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2164
2165 bnx2x_acquire_phy_lock(bp);
2166
2167 if (load_mode == LOAD_DIAG) {
2168 struct link_params *lp = &bp->link_params;
2169 lp->loopback_mode = LOOPBACK_XGXS;
2170 /* do PHY loopback at 10G speed, if possible */
2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2172 if (lp->speed_cap_mask[cfx_idx] &
2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2174 lp->req_line_speed[cfx_idx] =
2175 SPEED_10000;
2176 else
2177 lp->req_line_speed[cfx_idx] =
2178 SPEED_1000;
2179 }
2180 }
2181
2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2183
2184 bnx2x_release_phy_lock(bp);
2185
2186 bnx2x_calc_fc_adv(bp);
2187
2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2190 bnx2x_link_report(bp);
2191 } else
2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2194 return rc;
2195 }
2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2197 return -EINVAL;
2198 }
2199
2200 void bnx2x_link_set(struct bnx2x *bp)
2201 {
2202 if (!BP_NOMCP(bp)) {
2203 bnx2x_acquire_phy_lock(bp);
2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2206 bnx2x_release_phy_lock(bp);
2207
2208 bnx2x_calc_fc_adv(bp);
2209 } else
2210 BNX2X_ERR("Bootcode is missing - can not set link\n");
2211 }
2212
2213 static void bnx2x__link_reset(struct bnx2x *bp)
2214 {
2215 if (!BP_NOMCP(bp)) {
2216 bnx2x_acquire_phy_lock(bp);
2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2218 bnx2x_release_phy_lock(bp);
2219 } else
2220 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2221 }
2222
2223 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2224 {
2225 u8 rc = 0;
2226
2227 if (!BP_NOMCP(bp)) {
2228 bnx2x_acquire_phy_lock(bp);
2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2230 is_serdes);
2231 bnx2x_release_phy_lock(bp);
2232 } else
2233 BNX2X_ERR("Bootcode is missing - can not test link\n");
2234
2235 return rc;
2236 }
2237
2238 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2239 {
2240 u32 r_param = bp->link_vars.line_speed / 8;
2241 u32 fair_periodic_timeout_usec;
2242 u32 t_fair;
2243
2244 memset(&(bp->cmng.rs_vars), 0,
2245 sizeof(struct rate_shaping_vars_per_port));
2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2247
2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2250
2251 /* this is the threshold below which no timer arming will occur
2252 1.25 coefficient is for the threshold to be a little bigger
2253 than the real time, to compensate for timer in-accuracy */
2254 bp->cmng.rs_vars.rs_threshold =
2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2256
2257 /* resolution of fairness timer */
2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2261
2262 /* this is the threshold below which we won't arm the timer anymore */
2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2264
2265 /* we multiply by 1e3/8 to get bytes/msec.
2266 We don't want the credits to pass a credit
2267 of the t_fair*FAIR_MEM (algorithm resolution) */
2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2269 /* since each tick is 4 usec */
2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2271 }
2272
2273 /* Calculates the sum of vn_min_rates.
2274 It's needed for further normalizing of the min_rates.
2275 Returns:
2276 sum of vn_min_rates.
2277 or
2278 0 - if all the min_rates are 0.
2279 In the later case fainess algorithm should be deactivated.
2280 If not all min_rates are zero then those that are zeroes will be set to 1.
2281 */
2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2283 {
2284 int all_zero = 1;
2285 int vn;
2286
2287 bp->vn_weight_sum = 0;
2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2289 u32 vn_cfg = bp->mf_config[vn];
2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2292
2293 /* Skip hidden vns */
2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2295 continue;
2296
2297 /* If min rate is zero - set it to 1 */
2298 if (!vn_min_rate)
2299 vn_min_rate = DEF_MIN_RATE;
2300 else
2301 all_zero = 0;
2302
2303 bp->vn_weight_sum += vn_min_rate;
2304 }
2305
2306 /* if ETS or all min rates are zeros - disable fairness */
2307 if (BNX2X_IS_ETS_ENABLED(bp)) {
2308 bp->cmng.flags.cmng_enables &=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2311 } else if (all_zero) {
2312 bp->cmng.flags.cmng_enables &=
2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2315 " fairness will be disabled\n");
2316 } else
2317 bp->cmng.flags.cmng_enables |=
2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2319 }
2320
2321 /* returns func by VN for current port */
2322 static inline int func_by_vn(struct bnx2x *bp, int vn)
2323 {
2324 return 2 * vn + BP_PORT(bp);
2325 }
2326
2327 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2328 {
2329 struct rate_shaping_vars_per_vn m_rs_vn;
2330 struct fairness_vars_per_vn m_fair_vn;
2331 u32 vn_cfg = bp->mf_config[vn];
2332 int func = func_by_vn(bp, vn);
2333 u16 vn_min_rate, vn_max_rate;
2334 int i;
2335
2336 /* If function is hidden - set min and max to zeroes */
2337 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2338 vn_min_rate = 0;
2339 vn_max_rate = 0;
2340
2341 } else {
2342 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2343
2344 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2345 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2346 /* If fairness is enabled (not all min rates are zeroes) and
2347 if current min rate is zero - set it to 1.
2348 This is a requirement of the algorithm. */
2349 if (bp->vn_weight_sum && (vn_min_rate == 0))
2350 vn_min_rate = DEF_MIN_RATE;
2351
2352 if (IS_MF_SI(bp))
2353 /* maxCfg in percents of linkspeed */
2354 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2355 else
2356 /* maxCfg is absolute in 100Mb units */
2357 vn_max_rate = maxCfg * 100;
2358 }
2359
2360 DP(NETIF_MSG_IFUP,
2361 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2362 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2363
2364 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2365 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2366
2367 /* global vn counter - maximal Mbps for this vn */
2368 m_rs_vn.vn_counter.rate = vn_max_rate;
2369
2370 /* quota - number of bytes transmitted in this period */
2371 m_rs_vn.vn_counter.quota =
2372 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2373
2374 if (bp->vn_weight_sum) {
2375 /* credit for each period of the fairness algorithm:
2376 number of bytes in T_FAIR (the vn share the port rate).
2377 vn_weight_sum should not be larger than 10000, thus
2378 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2379 than zero */
2380 m_fair_vn.vn_credit_delta =
2381 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2382 (8 * bp->vn_weight_sum))),
2383 (bp->cmng.fair_vars.fair_threshold +
2384 MIN_ABOVE_THRESH));
2385 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2386 m_fair_vn.vn_credit_delta);
2387 }
2388
2389 /* Store it to internal memory */
2390 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2391 REG_WR(bp, BAR_XSTRORM_INTMEM +
2392 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2393 ((u32 *)(&m_rs_vn))[i]);
2394
2395 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2396 REG_WR(bp, BAR_XSTRORM_INTMEM +
2397 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2398 ((u32 *)(&m_fair_vn))[i]);
2399 }
2400
2401 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2402 {
2403 if (CHIP_REV_IS_SLOW(bp))
2404 return CMNG_FNS_NONE;
2405 if (IS_MF(bp))
2406 return CMNG_FNS_MINMAX;
2407
2408 return CMNG_FNS_NONE;
2409 }
2410
2411 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2412 {
2413 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2414
2415 if (BP_NOMCP(bp))
2416 return; /* what should be the default bvalue in this case */
2417
2418 /* For 2 port configuration the absolute function number formula
2419 * is:
2420 * abs_func = 2 * vn + BP_PORT + BP_PATH
2421 *
2422 * and there are 4 functions per port
2423 *
2424 * For 4 port configuration it is
2425 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2426 *
2427 * and there are 2 functions per port
2428 */
2429 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2430 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2431
2432 if (func >= E1H_FUNC_MAX)
2433 break;
2434
2435 bp->mf_config[vn] =
2436 MF_CFG_RD(bp, func_mf_config[func].config);
2437 }
2438 }
2439
2440 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2441 {
2442
2443 if (cmng_type == CMNG_FNS_MINMAX) {
2444 int vn;
2445
2446 /* clear cmng_enables */
2447 bp->cmng.flags.cmng_enables = 0;
2448
2449 /* read mf conf from shmem */
2450 if (read_cfg)
2451 bnx2x_read_mf_cfg(bp);
2452
2453 /* Init rate shaping and fairness contexts */
2454 bnx2x_init_port_minmax(bp);
2455
2456 /* vn_weight_sum and enable fairness if not 0 */
2457 bnx2x_calc_vn_weight_sum(bp);
2458
2459 /* calculate and set min-max rate for each vn */
2460 if (bp->port.pmf)
2461 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2462 bnx2x_init_vn_minmax(bp, vn);
2463
2464 /* always enable rate shaping and fairness */
2465 bp->cmng.flags.cmng_enables |=
2466 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2467 if (!bp->vn_weight_sum)
2468 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2469 " fairness will be disabled\n");
2470 return;
2471 }
2472
2473 /* rate shaping and fairness are disabled */
2474 DP(NETIF_MSG_IFUP,
2475 "rate shaping and fairness are disabled\n");
2476 }
2477
2478 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2479 {
2480 int func;
2481 int vn;
2482
2483 /* Set the attention towards other drivers on the same port */
2484 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2485 if (vn == BP_VN(bp))
2486 continue;
2487
2488 func = func_by_vn(bp, vn);
2489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2490 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2491 }
2492 }
2493
2494 /* This function is called upon link interrupt */
2495 static void bnx2x_link_attn(struct bnx2x *bp)
2496 {
2497 /* Make sure that we are synced with the current statistics */
2498 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2499
2500 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2501
2502 if (bp->link_vars.link_up) {
2503
2504 /* dropless flow control */
2505 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2506 int port = BP_PORT(bp);
2507 u32 pause_enabled = 0;
2508
2509 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2510 pause_enabled = 1;
2511
2512 REG_WR(bp, BAR_USTRORM_INTMEM +
2513 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2514 pause_enabled);
2515 }
2516
2517 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2518 struct host_port_stats *pstats;
2519
2520 pstats = bnx2x_sp(bp, port_stats);
2521 /* reset old mac stats */
2522 memset(&(pstats->mac_stx[0]), 0,
2523 sizeof(struct mac_stx));
2524 }
2525 if (bp->state == BNX2X_STATE_OPEN)
2526 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2527 }
2528
2529 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2530 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2531
2532 if (cmng_fns != CMNG_FNS_NONE) {
2533 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2534 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2535 } else
2536 /* rate shaping and fairness are disabled */
2537 DP(NETIF_MSG_IFUP,
2538 "single function mode without fairness\n");
2539 }
2540
2541 __bnx2x_link_report(bp);
2542
2543 if (IS_MF(bp))
2544 bnx2x_link_sync_notify(bp);
2545 }
2546
2547 void bnx2x__link_status_update(struct bnx2x *bp)
2548 {
2549 if (bp->state != BNX2X_STATE_OPEN)
2550 return;
2551
2552 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2553
2554 if (bp->link_vars.link_up)
2555 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2556 else
2557 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2558
2559 /* indicate link status */
2560 bnx2x_link_report(bp);
2561 }
2562
2563 static void bnx2x_pmf_update(struct bnx2x *bp)
2564 {
2565 int port = BP_PORT(bp);
2566 u32 val;
2567
2568 bp->port.pmf = 1;
2569 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2570
2571 /*
2572 * We need the mb() to ensure the ordering between the writing to
2573 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2574 */
2575 smp_mb();
2576
2577 /* queue a periodic task */
2578 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2579
2580 bnx2x_dcbx_pmf_update(bp);
2581
2582 /* enable nig attention */
2583 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2584 if (bp->common.int_block == INT_BLOCK_HC) {
2585 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2586 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2587 } else if (!CHIP_IS_E1x(bp)) {
2588 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2589 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2590 }
2591
2592 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2593 }
2594
2595 /* end of Link */
2596
2597 /* slow path */
2598
2599 /*
2600 * General service functions
2601 */
2602
2603 /* send the MCP a request, block until there is a reply */
2604 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2605 {
2606 int mb_idx = BP_FW_MB_IDX(bp);
2607 u32 seq;
2608 u32 rc = 0;
2609 u32 cnt = 1;
2610 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2611
2612 mutex_lock(&bp->fw_mb_mutex);
2613 seq = ++bp->fw_seq;
2614 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2615 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2616
2617 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2618 (command | seq), param);
2619
2620 do {
2621 /* let the FW do it's magic ... */
2622 msleep(delay);
2623
2624 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2625
2626 /* Give the FW up to 5 second (500*10ms) */
2627 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2628
2629 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2630 cnt*delay, rc, seq);
2631
2632 /* is this a reply to our command? */
2633 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2634 rc &= FW_MSG_CODE_MASK;
2635 else {
2636 /* FW BUG! */
2637 BNX2X_ERR("FW failed to respond!\n");
2638 bnx2x_fw_dump(bp);
2639 rc = 0;
2640 }
2641 mutex_unlock(&bp->fw_mb_mutex);
2642
2643 return rc;
2644 }
2645
2646 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2647 {
2648 #ifdef BCM_CNIC
2649 /* Statistics are not supported for CNIC Clients at the moment */
2650 if (IS_FCOE_FP(fp))
2651 return false;
2652 #endif
2653 return true;
2654 }
2655
2656 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2657 {
2658 if (CHIP_IS_E1x(bp)) {
2659 struct tstorm_eth_function_common_config tcfg = {0};
2660
2661 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2662 }
2663
2664 /* Enable the function in the FW */
2665 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2666 storm_memset_func_en(bp, p->func_id, 1);
2667
2668 /* spq */
2669 if (p->func_flgs & FUNC_FLG_SPQ) {
2670 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2671 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2672 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2673 }
2674 }
2675
2676 /**
2677 * bnx2x_get_tx_only_flags - Return common flags
2678 *
2679 * @bp device handle
2680 * @fp queue handle
2681 * @zero_stats TRUE if statistics zeroing is needed
2682 *
2683 * Return the flags that are common for the Tx-only and not normal connections.
2684 */
2685 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2686 struct bnx2x_fastpath *fp,
2687 bool zero_stats)
2688 {
2689 unsigned long flags = 0;
2690
2691 /* PF driver will always initialize the Queue to an ACTIVE state */
2692 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2693
2694 /* tx only connections collect statistics (on the same index as the
2695 * parent connection). The statistics are zeroed when the parent
2696 * connection is initialized.
2697 */
2698 if (stat_counter_valid(bp, fp)) {
2699 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2700 if (zero_stats)
2701 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2702 }
2703
2704 return flags;
2705 }
2706
2707 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2708 struct bnx2x_fastpath *fp,
2709 bool leading)
2710 {
2711 unsigned long flags = 0;
2712
2713 /* calculate other queue flags */
2714 if (IS_MF_SD(bp))
2715 __set_bit(BNX2X_Q_FLG_OV, &flags);
2716
2717 if (IS_FCOE_FP(fp))
2718 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2719
2720 if (!fp->disable_tpa) {
2721 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2722 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2723 }
2724
2725 if (leading) {
2726 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2727 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2728 }
2729
2730 /* Always set HW VLAN stripping */
2731 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2732
2733
2734 return flags | bnx2x_get_common_flags(bp, fp, true);
2735 }
2736
2737 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2738 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2739 u8 cos)
2740 {
2741 gen_init->stat_id = bnx2x_stats_id(fp);
2742 gen_init->spcl_id = fp->cl_id;
2743
2744 /* Always use mini-jumbo MTU for FCoE L2 ring */
2745 if (IS_FCOE_FP(fp))
2746 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2747 else
2748 gen_init->mtu = bp->dev->mtu;
2749
2750 gen_init->cos = cos;
2751 }
2752
2753 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2754 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2755 struct bnx2x_rxq_setup_params *rxq_init)
2756 {
2757 u8 max_sge = 0;
2758 u16 sge_sz = 0;
2759 u16 tpa_agg_size = 0;
2760
2761 if (!fp->disable_tpa) {
2762 pause->sge_th_lo = SGE_TH_LO(bp);
2763 pause->sge_th_hi = SGE_TH_HI(bp);
2764
2765 /* validate SGE ring has enough to cross high threshold */
2766 WARN_ON(bp->dropless_fc &&
2767 pause->sge_th_hi + FW_PREFETCH_CNT >
2768 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2769
2770 tpa_agg_size = min_t(u32,
2771 (min_t(u32, 8, MAX_SKB_FRAGS) *
2772 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2773 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2774 SGE_PAGE_SHIFT;
2775 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2776 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2777 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2778 0xffff);
2779 }
2780
2781 /* pause - not for e1 */
2782 if (!CHIP_IS_E1(bp)) {
2783 pause->bd_th_lo = BD_TH_LO(bp);
2784 pause->bd_th_hi = BD_TH_HI(bp);
2785
2786 pause->rcq_th_lo = RCQ_TH_LO(bp);
2787 pause->rcq_th_hi = RCQ_TH_HI(bp);
2788 /*
2789 * validate that rings have enough entries to cross
2790 * high thresholds
2791 */
2792 WARN_ON(bp->dropless_fc &&
2793 pause->bd_th_hi + FW_PREFETCH_CNT >
2794 bp->rx_ring_size);
2795 WARN_ON(bp->dropless_fc &&
2796 pause->rcq_th_hi + FW_PREFETCH_CNT >
2797 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2798
2799 pause->pri_map = 1;
2800 }
2801
2802 /* rxq setup */
2803 rxq_init->dscr_map = fp->rx_desc_mapping;
2804 rxq_init->sge_map = fp->rx_sge_mapping;
2805 rxq_init->rcq_map = fp->rx_comp_mapping;
2806 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2807
2808 /* This should be a maximum number of data bytes that may be
2809 * placed on the BD (not including paddings).
2810 */
2811 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2812 IP_HEADER_ALIGNMENT_PADDING;
2813
2814 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2815 rxq_init->tpa_agg_sz = tpa_agg_size;
2816 rxq_init->sge_buf_sz = sge_sz;
2817 rxq_init->max_sges_pkt = max_sge;
2818 rxq_init->rss_engine_id = BP_FUNC(bp);
2819
2820 /* Maximum number or simultaneous TPA aggregation for this Queue.
2821 *
2822 * For PF Clients it should be the maximum avaliable number.
2823 * VF driver(s) may want to define it to a smaller value.
2824 */
2825 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2826
2827 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2828 rxq_init->fw_sb_id = fp->fw_sb_id;
2829
2830 if (IS_FCOE_FP(fp))
2831 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2832 else
2833 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2834 }
2835
2836 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2837 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2838 u8 cos)
2839 {
2840 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2841 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2842 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2843 txq_init->fw_sb_id = fp->fw_sb_id;
2844
2845 /*
2846 * set the tss leading client id for TX classfication ==
2847 * leading RSS client id
2848 */
2849 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2850
2851 if (IS_FCOE_FP(fp)) {
2852 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2853 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2854 }
2855 }
2856
2857 static void bnx2x_pf_init(struct bnx2x *bp)
2858 {
2859 struct bnx2x_func_init_params func_init = {0};
2860 struct event_ring_data eq_data = { {0} };
2861 u16 flags;
2862
2863 if (!CHIP_IS_E1x(bp)) {
2864 /* reset IGU PF statistics: MSIX + ATTN */
2865 /* PF */
2866 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2867 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2868 (CHIP_MODE_IS_4_PORT(bp) ?
2869 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2870 /* ATTN */
2871 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2872 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2873 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2874 (CHIP_MODE_IS_4_PORT(bp) ?
2875 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2876 }
2877
2878 /* function setup flags */
2879 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2880
2881 /* This flag is relevant for E1x only.
2882 * E2 doesn't have a TPA configuration in a function level.
2883 */
2884 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2885
2886 func_init.func_flgs = flags;
2887 func_init.pf_id = BP_FUNC(bp);
2888 func_init.func_id = BP_FUNC(bp);
2889 func_init.spq_map = bp->spq_mapping;
2890 func_init.spq_prod = bp->spq_prod_idx;
2891
2892 bnx2x_func_init(bp, &func_init);
2893
2894 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2895
2896 /*
2897 * Congestion management values depend on the link rate
2898 * There is no active link so initial link rate is set to 10 Gbps.
2899 * When the link comes up The congestion management values are
2900 * re-calculated according to the actual link rate.
2901 */
2902 bp->link_vars.line_speed = SPEED_10000;
2903 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2904
2905 /* Only the PMF sets the HW */
2906 if (bp->port.pmf)
2907 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2908
2909 /* init Event Queue */
2910 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2911 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2912 eq_data.producer = bp->eq_prod;
2913 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2914 eq_data.sb_id = DEF_SB_ID;
2915 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2916 }
2917
2918
2919 static void bnx2x_e1h_disable(struct bnx2x *bp)
2920 {
2921 int port = BP_PORT(bp);
2922
2923 bnx2x_tx_disable(bp);
2924
2925 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2926 }
2927
2928 static void bnx2x_e1h_enable(struct bnx2x *bp)
2929 {
2930 int port = BP_PORT(bp);
2931
2932 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2933
2934 /* Tx queue should be only reenabled */
2935 netif_tx_wake_all_queues(bp->dev);
2936
2937 /*
2938 * Should not call netif_carrier_on since it will be called if the link
2939 * is up when checking for link state
2940 */
2941 }
2942
2943 /* called due to MCP event (on pmf):
2944 * reread new bandwidth configuration
2945 * configure FW
2946 * notify others function about the change
2947 */
2948 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2949 {
2950 if (bp->link_vars.link_up) {
2951 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2952 bnx2x_link_sync_notify(bp);
2953 }
2954 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2955 }
2956
2957 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2958 {
2959 bnx2x_config_mf_bw(bp);
2960 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2961 }
2962
2963 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2964 {
2965 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2966
2967 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2968
2969 /*
2970 * This is the only place besides the function initialization
2971 * where the bp->flags can change so it is done without any
2972 * locks
2973 */
2974 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2975 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2976 bp->flags |= MF_FUNC_DIS;
2977
2978 bnx2x_e1h_disable(bp);
2979 } else {
2980 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2981 bp->flags &= ~MF_FUNC_DIS;
2982
2983 bnx2x_e1h_enable(bp);
2984 }
2985 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2986 }
2987 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2988 bnx2x_config_mf_bw(bp);
2989 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2990 }
2991
2992 /* Report results to MCP */
2993 if (dcc_event)
2994 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2995 else
2996 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2997 }
2998
2999 /* must be called under the spq lock */
3000 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3001 {
3002 struct eth_spe *next_spe = bp->spq_prod_bd;
3003
3004 if (bp->spq_prod_bd == bp->spq_last_bd) {
3005 bp->spq_prod_bd = bp->spq;
3006 bp->spq_prod_idx = 0;
3007 DP(NETIF_MSG_TIMER, "end of spq\n");
3008 } else {
3009 bp->spq_prod_bd++;
3010 bp->spq_prod_idx++;
3011 }
3012 return next_spe;
3013 }
3014
3015 /* must be called under the spq lock */
3016 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3017 {
3018 int func = BP_FUNC(bp);
3019
3020 /*
3021 * Make sure that BD data is updated before writing the producer:
3022 * BD data is written to the memory, the producer is read from the
3023 * memory, thus we need a full memory barrier to ensure the ordering.
3024 */
3025 mb();
3026
3027 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3028 bp->spq_prod_idx);
3029 mmiowb();
3030 }
3031
3032 /**
3033 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3034 *
3035 * @cmd: command to check
3036 * @cmd_type: command type
3037 */
3038 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3039 {
3040 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3041 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3042 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3043 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3044 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3045 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3046 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3047 return true;
3048 else
3049 return false;
3050
3051 }
3052
3053
3054 /**
3055 * bnx2x_sp_post - place a single command on an SP ring
3056 *
3057 * @bp: driver handle
3058 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3059 * @cid: SW CID the command is related to
3060 * @data_hi: command private data address (high 32 bits)
3061 * @data_lo: command private data address (low 32 bits)
3062 * @cmd_type: command type (e.g. NONE, ETH)
3063 *
3064 * SP data is handled as if it's always an address pair, thus data fields are
3065 * not swapped to little endian in upper functions. Instead this function swaps
3066 * data as if it's two u32 fields.
3067 */
3068 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3069 u32 data_hi, u32 data_lo, int cmd_type)
3070 {
3071 struct eth_spe *spe;
3072 u16 type;
3073 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3074
3075 #ifdef BNX2X_STOP_ON_ERROR
3076 if (unlikely(bp->panic))
3077 return -EIO;
3078 #endif
3079
3080 spin_lock_bh(&bp->spq_lock);
3081
3082 if (common) {
3083 if (!atomic_read(&bp->eq_spq_left)) {
3084 BNX2X_ERR("BUG! EQ ring full!\n");
3085 spin_unlock_bh(&bp->spq_lock);
3086 bnx2x_panic();
3087 return -EBUSY;
3088 }
3089 } else if (!atomic_read(&bp->cq_spq_left)) {
3090 BNX2X_ERR("BUG! SPQ ring full!\n");
3091 spin_unlock_bh(&bp->spq_lock);
3092 bnx2x_panic();
3093 return -EBUSY;
3094 }
3095
3096 spe = bnx2x_sp_get_next(bp);
3097
3098 /* CID needs port number to be encoded int it */
3099 spe->hdr.conn_and_cmd_data =
3100 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3101 HW_CID(bp, cid));
3102
3103 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3104
3105 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3106 SPE_HDR_FUNCTION_ID);
3107
3108 spe->hdr.type = cpu_to_le16(type);
3109
3110 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3111 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3112
3113 /*
3114 * It's ok if the actual decrement is issued towards the memory
3115 * somewhere between the spin_lock and spin_unlock. Thus no
3116 * more explict memory barrier is needed.
3117 */
3118 if (common)
3119 atomic_dec(&bp->eq_spq_left);
3120 else
3121 atomic_dec(&bp->cq_spq_left);
3122
3123
3124 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3125 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3126 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3127 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3128 (u32)(U64_LO(bp->spq_mapping) +
3129 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3130 HW_CID(bp, cid), data_hi, data_lo, type,
3131 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3132
3133 bnx2x_sp_prod_update(bp);
3134 spin_unlock_bh(&bp->spq_lock);
3135 return 0;
3136 }
3137
3138 /* acquire split MCP access lock register */
3139 static int bnx2x_acquire_alr(struct bnx2x *bp)
3140 {
3141 u32 j, val;
3142 int rc = 0;
3143
3144 might_sleep();
3145 for (j = 0; j < 1000; j++) {
3146 val = (1UL << 31);
3147 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3148 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3149 if (val & (1L << 31))
3150 break;
3151
3152 msleep(5);
3153 }
3154 if (!(val & (1L << 31))) {
3155 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3156 rc = -EBUSY;
3157 }
3158
3159 return rc;
3160 }
3161
3162 /* release split MCP access lock register */
3163 static void bnx2x_release_alr(struct bnx2x *bp)
3164 {
3165 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3166 }
3167
3168 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3169 #define BNX2X_DEF_SB_IDX 0x0002
3170
3171 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3172 {
3173 struct host_sp_status_block *def_sb = bp->def_status_blk;
3174 u16 rc = 0;
3175
3176 barrier(); /* status block is written to by the chip */
3177 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3178 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3179 rc |= BNX2X_DEF_SB_ATT_IDX;
3180 }
3181
3182 if (bp->def_idx != def_sb->sp_sb.running_index) {
3183 bp->def_idx = def_sb->sp_sb.running_index;
3184 rc |= BNX2X_DEF_SB_IDX;
3185 }
3186
3187 /* Do not reorder: indecies reading should complete before handling */
3188 barrier();
3189 return rc;
3190 }
3191
3192 /*
3193 * slow path service functions
3194 */
3195
3196 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3197 {
3198 int port = BP_PORT(bp);
3199 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3200 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3201 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3202 NIG_REG_MASK_INTERRUPT_PORT0;
3203 u32 aeu_mask;
3204 u32 nig_mask = 0;
3205 u32 reg_addr;
3206
3207 if (bp->attn_state & asserted)
3208 BNX2X_ERR("IGU ERROR\n");
3209
3210 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3211 aeu_mask = REG_RD(bp, aeu_addr);
3212
3213 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3214 aeu_mask, asserted);
3215 aeu_mask &= ~(asserted & 0x3ff);
3216 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3217
3218 REG_WR(bp, aeu_addr, aeu_mask);
3219 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3220
3221 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3222 bp->attn_state |= asserted;
3223 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3224
3225 if (asserted & ATTN_HARD_WIRED_MASK) {
3226 if (asserted & ATTN_NIG_FOR_FUNC) {
3227
3228 bnx2x_acquire_phy_lock(bp);
3229
3230 /* save nig interrupt mask */
3231 nig_mask = REG_RD(bp, nig_int_mask_addr);
3232
3233 /* If nig_mask is not set, no need to call the update
3234 * function.
3235 */
3236 if (nig_mask) {
3237 REG_WR(bp, nig_int_mask_addr, 0);
3238
3239 bnx2x_link_attn(bp);
3240 }
3241
3242 /* handle unicore attn? */
3243 }
3244 if (asserted & ATTN_SW_TIMER_4_FUNC)
3245 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3246
3247 if (asserted & GPIO_2_FUNC)
3248 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3249
3250 if (asserted & GPIO_3_FUNC)
3251 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3252
3253 if (asserted & GPIO_4_FUNC)
3254 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3255
3256 if (port == 0) {
3257 if (asserted & ATTN_GENERAL_ATTN_1) {
3258 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3259 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3260 }
3261 if (asserted & ATTN_GENERAL_ATTN_2) {
3262 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3263 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3264 }
3265 if (asserted & ATTN_GENERAL_ATTN_3) {
3266 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3267 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3268 }
3269 } else {
3270 if (asserted & ATTN_GENERAL_ATTN_4) {
3271 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3272 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3273 }
3274 if (asserted & ATTN_GENERAL_ATTN_5) {
3275 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3276 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3277 }
3278 if (asserted & ATTN_GENERAL_ATTN_6) {
3279 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3280 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3281 }
3282 }
3283
3284 } /* if hardwired */
3285
3286 if (bp->common.int_block == INT_BLOCK_HC)
3287 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3288 COMMAND_REG_ATTN_BITS_SET);
3289 else
3290 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3291
3292 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3293 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3294 REG_WR(bp, reg_addr, asserted);
3295
3296 /* now set back the mask */
3297 if (asserted & ATTN_NIG_FOR_FUNC) {
3298 REG_WR(bp, nig_int_mask_addr, nig_mask);
3299 bnx2x_release_phy_lock(bp);
3300 }
3301 }
3302
3303 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3304 {
3305 int port = BP_PORT(bp);
3306 u32 ext_phy_config;
3307 /* mark the failure */
3308 ext_phy_config =
3309 SHMEM_RD(bp,
3310 dev_info.port_hw_config[port].external_phy_config);
3311
3312 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3313 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3314 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3315 ext_phy_config);
3316
3317 /* log the failure */
3318 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3319 " the driver to shutdown the card to prevent permanent"
3320 " damage. Please contact OEM Support for assistance\n");
3321 }
3322
3323 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3324 {
3325 int port = BP_PORT(bp);
3326 int reg_offset;
3327 u32 val;
3328
3329 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3330 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3331
3332 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3333
3334 val = REG_RD(bp, reg_offset);
3335 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3336 REG_WR(bp, reg_offset, val);
3337
3338 BNX2X_ERR("SPIO5 hw attention\n");
3339
3340 /* Fan failure attention */
3341 bnx2x_hw_reset_phy(&bp->link_params);
3342 bnx2x_fan_failure(bp);
3343 }
3344
3345 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3346 bnx2x_acquire_phy_lock(bp);
3347 bnx2x_handle_module_detect_int(&bp->link_params);
3348 bnx2x_release_phy_lock(bp);
3349 }
3350
3351 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3352
3353 val = REG_RD(bp, reg_offset);
3354 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3355 REG_WR(bp, reg_offset, val);
3356
3357 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3358 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3359 bnx2x_panic();
3360 }
3361 }
3362
3363 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3364 {
3365 u32 val;
3366
3367 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3368
3369 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3370 BNX2X_ERR("DB hw attention 0x%x\n", val);
3371 /* DORQ discard attention */
3372 if (val & 0x2)
3373 BNX2X_ERR("FATAL error from DORQ\n");
3374 }
3375
3376 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3377
3378 int port = BP_PORT(bp);
3379 int reg_offset;
3380
3381 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3382 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3383
3384 val = REG_RD(bp, reg_offset);
3385 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3386 REG_WR(bp, reg_offset, val);
3387
3388 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3389 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3390 bnx2x_panic();
3391 }
3392 }
3393
3394 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3395 {
3396 u32 val;
3397
3398 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3399
3400 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3401 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3402 /* CFC error attention */
3403 if (val & 0x2)
3404 BNX2X_ERR("FATAL error from CFC\n");
3405 }
3406
3407 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3408 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3409 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3410 /* RQ_USDMDP_FIFO_OVERFLOW */
3411 if (val & 0x18000)
3412 BNX2X_ERR("FATAL error from PXP\n");
3413
3414 if (!CHIP_IS_E1x(bp)) {
3415 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3416 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3417 }
3418 }
3419
3420 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3421
3422 int port = BP_PORT(bp);
3423 int reg_offset;
3424
3425 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3426 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3427
3428 val = REG_RD(bp, reg_offset);
3429 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3430 REG_WR(bp, reg_offset, val);
3431
3432 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3433 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3434 bnx2x_panic();
3435 }
3436 }
3437
3438 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3439 {
3440 u32 val;
3441
3442 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3443
3444 if (attn & BNX2X_PMF_LINK_ASSERT) {
3445 int func = BP_FUNC(bp);
3446
3447 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3448 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3449 func_mf_config[BP_ABS_FUNC(bp)].config);
3450 val = SHMEM_RD(bp,
3451 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3452 if (val & DRV_STATUS_DCC_EVENT_MASK)
3453 bnx2x_dcc_event(bp,
3454 (val & DRV_STATUS_DCC_EVENT_MASK));
3455
3456 if (val & DRV_STATUS_SET_MF_BW)
3457 bnx2x_set_mf_bw(bp);
3458
3459 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3460 bnx2x_pmf_update(bp);
3461
3462 if (bp->port.pmf &&
3463 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3464 bp->dcbx_enabled > 0)
3465 /* start dcbx state machine */
3466 bnx2x_dcbx_set_params(bp,
3467 BNX2X_DCBX_STATE_NEG_RECEIVED);
3468 if (bp->link_vars.periodic_flags &
3469 PERIODIC_FLAGS_LINK_EVENT) {
3470 /* sync with link */
3471 bnx2x_acquire_phy_lock(bp);
3472 bp->link_vars.periodic_flags &=
3473 ~PERIODIC_FLAGS_LINK_EVENT;
3474 bnx2x_release_phy_lock(bp);
3475 if (IS_MF(bp))
3476 bnx2x_link_sync_notify(bp);
3477 bnx2x_link_report(bp);
3478 }
3479 /* Always call it here: bnx2x_link_report() will
3480 * prevent the link indication duplication.
3481 */
3482 bnx2x__link_status_update(bp);
3483 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3484
3485 BNX2X_ERR("MC assert!\n");
3486 bnx2x_mc_assert(bp);
3487 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3488 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3491 bnx2x_panic();
3492
3493 } else if (attn & BNX2X_MCP_ASSERT) {
3494
3495 BNX2X_ERR("MCP assert!\n");
3496 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3497 bnx2x_fw_dump(bp);
3498
3499 } else
3500 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3501 }
3502
3503 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3504 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3505 if (attn & BNX2X_GRC_TIMEOUT) {
3506 val = CHIP_IS_E1(bp) ? 0 :
3507 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3508 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3509 }
3510 if (attn & BNX2X_GRC_RSV) {
3511 val = CHIP_IS_E1(bp) ? 0 :
3512 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3513 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3514 }
3515 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3516 }
3517 }
3518
3519 /*
3520 * Bits map:
3521 * 0-7 - Engine0 load counter.
3522 * 8-15 - Engine1 load counter.
3523 * 16 - Engine0 RESET_IN_PROGRESS bit.
3524 * 17 - Engine1 RESET_IN_PROGRESS bit.
3525 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3526 * on the engine
3527 * 19 - Engine1 ONE_IS_LOADED.
3528 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3529 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3530 * just the one belonging to its engine).
3531 *
3532 */
3533 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3534
3535 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3536 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3537 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3538 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3539 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3540 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3541 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3542
3543 /*
3544 * Set the GLOBAL_RESET bit.
3545 *
3546 * Should be run under rtnl lock
3547 */
3548 void bnx2x_set_reset_global(struct bnx2x *bp)
3549 {
3550 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3551
3552 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3553 barrier();
3554 mmiowb();
3555 }
3556
3557 /*
3558 * Clear the GLOBAL_RESET bit.
3559 *
3560 * Should be run under rtnl lock
3561 */
3562 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3563 {
3564 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3565
3566 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3567 barrier();
3568 mmiowb();
3569 }
3570
3571 /*
3572 * Checks the GLOBAL_RESET bit.
3573 *
3574 * should be run under rtnl lock
3575 */
3576 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3577 {
3578 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3579
3580 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3581 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3582 }
3583
3584 /*
3585 * Clear RESET_IN_PROGRESS bit for the current engine.
3586 *
3587 * Should be run under rtnl lock
3588 */
3589 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3590 {
3591 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3592 u32 bit = BP_PATH(bp) ?
3593 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3594
3595 /* Clear the bit */
3596 val &= ~bit;
3597 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3598 barrier();
3599 mmiowb();
3600 }
3601
3602 /*
3603 * Set RESET_IN_PROGRESS for the current engine.
3604 *
3605 * should be run under rtnl lock
3606 */
3607 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3608 {
3609 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3610 u32 bit = BP_PATH(bp) ?
3611 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3612
3613 /* Set the bit */
3614 val |= bit;
3615 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3616 barrier();
3617 mmiowb();
3618 }
3619
3620 /*
3621 * Checks the RESET_IN_PROGRESS bit for the given engine.
3622 * should be run under rtnl lock
3623 */
3624 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3625 {
3626 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3627 u32 bit = engine ?
3628 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3629
3630 /* return false if bit is set */
3631 return (val & bit) ? false : true;
3632 }
3633
3634 /*
3635 * Increment the load counter for the current engine.
3636 *
3637 * should be run under rtnl lock
3638 */
3639 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3640 {
3641 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3642 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3643 BNX2X_PATH0_LOAD_CNT_MASK;
3644 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3645 BNX2X_PATH0_LOAD_CNT_SHIFT;
3646
3647 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3648
3649 /* get the current counter value */
3650 val1 = (val & mask) >> shift;
3651
3652 /* increment... */
3653 val1++;
3654
3655 /* clear the old value */
3656 val &= ~mask;
3657
3658 /* set the new one */
3659 val |= ((val1 << shift) & mask);
3660
3661 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3662 barrier();
3663 mmiowb();
3664 }
3665
3666 /**
3667 * bnx2x_dec_load_cnt - decrement the load counter
3668 *
3669 * @bp: driver handle
3670 *
3671 * Should be run under rtnl lock.
3672 * Decrements the load counter for the current engine. Returns
3673 * the new counter value.
3674 */
3675 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3676 {
3677 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3678 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3679 BNX2X_PATH0_LOAD_CNT_MASK;
3680 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3681 BNX2X_PATH0_LOAD_CNT_SHIFT;
3682
3683 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3684
3685 /* get the current counter value */
3686 val1 = (val & mask) >> shift;
3687
3688 /* decrement... */
3689 val1--;
3690
3691 /* clear the old value */
3692 val &= ~mask;
3693
3694 /* set the new one */
3695 val |= ((val1 << shift) & mask);
3696
3697 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3698 barrier();
3699 mmiowb();
3700
3701 return val1;
3702 }
3703
3704 /*
3705 * Read the load counter for the current engine.
3706 *
3707 * should be run under rtnl lock
3708 */
3709 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3710 {
3711 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3712 BNX2X_PATH0_LOAD_CNT_MASK);
3713 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3714 BNX2X_PATH0_LOAD_CNT_SHIFT);
3715 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3716
3717 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3718
3719 val = (val & mask) >> shift;
3720
3721 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3722
3723 return val;
3724 }
3725
3726 /*
3727 * Reset the load counter for the current engine.
3728 *
3729 * should be run under rtnl lock
3730 */
3731 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3732 {
3733 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3734 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3735 BNX2X_PATH0_LOAD_CNT_MASK);
3736
3737 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3738 }
3739
3740 static inline void _print_next_block(int idx, const char *blk)
3741 {
3742 pr_cont("%s%s", idx ? ", " : "", blk);
3743 }
3744
3745 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3746 bool print)
3747 {
3748 int i = 0;
3749 u32 cur_bit = 0;
3750 for (i = 0; sig; i++) {
3751 cur_bit = ((u32)0x1 << i);
3752 if (sig & cur_bit) {
3753 switch (cur_bit) {
3754 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3755 if (print)
3756 _print_next_block(par_num++, "BRB");
3757 break;
3758 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3759 if (print)
3760 _print_next_block(par_num++, "PARSER");
3761 break;
3762 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3763 if (print)
3764 _print_next_block(par_num++, "TSDM");
3765 break;
3766 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3767 if (print)
3768 _print_next_block(par_num++,
3769 "SEARCHER");
3770 break;
3771 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3772 if (print)
3773 _print_next_block(par_num++, "TCM");
3774 break;
3775 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3776 if (print)
3777 _print_next_block(par_num++, "TSEMI");
3778 break;
3779 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3780 if (print)
3781 _print_next_block(par_num++, "XPB");
3782 break;
3783 }
3784
3785 /* Clear the bit */
3786 sig &= ~cur_bit;
3787 }
3788 }
3789
3790 return par_num;
3791 }
3792
3793 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3794 bool *global, bool print)
3795 {
3796 int i = 0;
3797 u32 cur_bit = 0;
3798 for (i = 0; sig; i++) {
3799 cur_bit = ((u32)0x1 << i);
3800 if (sig & cur_bit) {
3801 switch (cur_bit) {
3802 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3803 if (print)
3804 _print_next_block(par_num++, "PBF");
3805 break;
3806 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3807 if (print)
3808 _print_next_block(par_num++, "QM");
3809 break;
3810 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3811 if (print)
3812 _print_next_block(par_num++, "TM");
3813 break;
3814 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3815 if (print)
3816 _print_next_block(par_num++, "XSDM");
3817 break;
3818 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3819 if (print)
3820 _print_next_block(par_num++, "XCM");
3821 break;
3822 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3823 if (print)
3824 _print_next_block(par_num++, "XSEMI");
3825 break;
3826 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3827 if (print)
3828 _print_next_block(par_num++,
3829 "DOORBELLQ");
3830 break;
3831 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3832 if (print)
3833 _print_next_block(par_num++, "NIG");
3834 break;
3835 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3836 if (print)
3837 _print_next_block(par_num++,
3838 "VAUX PCI CORE");
3839 *global = true;
3840 break;
3841 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3842 if (print)
3843 _print_next_block(par_num++, "DEBUG");
3844 break;
3845 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3846 if (print)
3847 _print_next_block(par_num++, "USDM");
3848 break;
3849 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3850 if (print)
3851 _print_next_block(par_num++, "UCM");
3852 break;
3853 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3854 if (print)
3855 _print_next_block(par_num++, "USEMI");
3856 break;
3857 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3858 if (print)
3859 _print_next_block(par_num++, "UPB");
3860 break;
3861 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3862 if (print)
3863 _print_next_block(par_num++, "CSDM");
3864 break;
3865 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3866 if (print)
3867 _print_next_block(par_num++, "CCM");
3868 break;
3869 }
3870
3871 /* Clear the bit */
3872 sig &= ~cur_bit;
3873 }
3874 }
3875
3876 return par_num;
3877 }
3878
3879 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3880 bool print)
3881 {
3882 int i = 0;
3883 u32 cur_bit = 0;
3884 for (i = 0; sig; i++) {
3885 cur_bit = ((u32)0x1 << i);
3886 if (sig & cur_bit) {
3887 switch (cur_bit) {
3888 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3889 if (print)
3890 _print_next_block(par_num++, "CSEMI");
3891 break;
3892 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3893 if (print)
3894 _print_next_block(par_num++, "PXP");
3895 break;
3896 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3897 if (print)
3898 _print_next_block(par_num++,
3899 "PXPPCICLOCKCLIENT");
3900 break;
3901 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3902 if (print)
3903 _print_next_block(par_num++, "CFC");
3904 break;
3905 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3906 if (print)
3907 _print_next_block(par_num++, "CDU");
3908 break;
3909 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3910 if (print)
3911 _print_next_block(par_num++, "DMAE");
3912 break;
3913 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3914 if (print)
3915 _print_next_block(par_num++, "IGU");
3916 break;
3917 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3918 if (print)
3919 _print_next_block(par_num++, "MISC");
3920 break;
3921 }
3922
3923 /* Clear the bit */
3924 sig &= ~cur_bit;
3925 }
3926 }
3927
3928 return par_num;
3929 }
3930
3931 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3932 bool *global, bool print)
3933 {
3934 int i = 0;
3935 u32 cur_bit = 0;
3936 for (i = 0; sig; i++) {
3937 cur_bit = ((u32)0x1 << i);
3938 if (sig & cur_bit) {
3939 switch (cur_bit) {
3940 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3941 if (print)
3942 _print_next_block(par_num++, "MCP ROM");
3943 *global = true;
3944 break;
3945 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3946 if (print)
3947 _print_next_block(par_num++,
3948 "MCP UMP RX");
3949 *global = true;
3950 break;
3951 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3952 if (print)
3953 _print_next_block(par_num++,
3954 "MCP UMP TX");
3955 *global = true;
3956 break;
3957 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3958 if (print)
3959 _print_next_block(par_num++,
3960 "MCP SCPAD");
3961 *global = true;
3962 break;
3963 }
3964
3965 /* Clear the bit */
3966 sig &= ~cur_bit;
3967 }
3968 }
3969
3970 return par_num;
3971 }
3972
3973 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3974 bool print)
3975 {
3976 int i = 0;
3977 u32 cur_bit = 0;
3978 for (i = 0; sig; i++) {
3979 cur_bit = ((u32)0x1 << i);
3980 if (sig & cur_bit) {
3981 switch (cur_bit) {
3982 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3983 if (print)
3984 _print_next_block(par_num++, "PGLUE_B");
3985 break;
3986 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3987 if (print)
3988 _print_next_block(par_num++, "ATC");
3989 break;
3990 }
3991
3992 /* Clear the bit */
3993 sig &= ~cur_bit;
3994 }
3995 }
3996
3997 return par_num;
3998 }
3999
4000 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4001 u32 *sig)
4002 {
4003 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4004 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4005 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4006 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4007 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4008 int par_num = 0;
4009 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4010 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4011 "[4]:0x%08x\n",
4012 sig[0] & HW_PRTY_ASSERT_SET_0,
4013 sig[1] & HW_PRTY_ASSERT_SET_1,
4014 sig[2] & HW_PRTY_ASSERT_SET_2,
4015 sig[3] & HW_PRTY_ASSERT_SET_3,
4016 sig[4] & HW_PRTY_ASSERT_SET_4);
4017 if (print)
4018 netdev_err(bp->dev,
4019 "Parity errors detected in blocks: ");
4020 par_num = bnx2x_check_blocks_with_parity0(
4021 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4022 par_num = bnx2x_check_blocks_with_parity1(
4023 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4024 par_num = bnx2x_check_blocks_with_parity2(
4025 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4026 par_num = bnx2x_check_blocks_with_parity3(
4027 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4028 par_num = bnx2x_check_blocks_with_parity4(
4029 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4030
4031 if (print)
4032 pr_cont("\n");
4033
4034 return true;
4035 } else
4036 return false;
4037 }
4038
4039 /**
4040 * bnx2x_chk_parity_attn - checks for parity attentions.
4041 *
4042 * @bp: driver handle
4043 * @global: true if there was a global attention
4044 * @print: show parity attention in syslog
4045 */
4046 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4047 {
4048 struct attn_route attn = { {0} };
4049 int port = BP_PORT(bp);
4050
4051 attn.sig[0] = REG_RD(bp,
4052 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4053 port*4);
4054 attn.sig[1] = REG_RD(bp,
4055 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4056 port*4);
4057 attn.sig[2] = REG_RD(bp,
4058 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4059 port*4);
4060 attn.sig[3] = REG_RD(bp,
4061 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4062 port*4);
4063
4064 if (!CHIP_IS_E1x(bp))
4065 attn.sig[4] = REG_RD(bp,
4066 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4067 port*4);
4068
4069 return bnx2x_parity_attn(bp, global, print, attn.sig);
4070 }
4071
4072
4073 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4074 {
4075 u32 val;
4076 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4077
4078 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4079 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4080 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4082 "ADDRESS_ERROR\n");
4083 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4084 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4085 "INCORRECT_RCV_BEHAVIOR\n");
4086 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4087 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4088 "WAS_ERROR_ATTN\n");
4089 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4090 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4091 "VF_LENGTH_VIOLATION_ATTN\n");
4092 if (val &
4093 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4094 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4095 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4096 if (val &
4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4099 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4100 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4101 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4102 "TCPL_ERROR_ATTN\n");
4103 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4104 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4105 "TCPL_IN_TWO_RCBS_ATTN\n");
4106 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4107 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4108 "CSSNOOP_FIFO_OVERFLOW\n");
4109 }
4110 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4111 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4112 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4113 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4114 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4115 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4116 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4117 "_ATC_TCPL_TO_NOT_PEND\n");
4118 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4119 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4120 "ATC_GPA_MULTIPLE_HITS\n");
4121 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4122 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4123 "ATC_RCPL_TO_EMPTY_CNT\n");
4124 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4125 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4126 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4127 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4128 "ATC_IREQ_LESS_THAN_STU\n");
4129 }
4130
4131 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4132 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4133 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4134 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4135 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4136 }
4137
4138 }
4139
4140 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4141 {
4142 struct attn_route attn, *group_mask;
4143 int port = BP_PORT(bp);
4144 int index;
4145 u32 reg_addr;
4146 u32 val;
4147 u32 aeu_mask;
4148 bool global = false;
4149
4150 /* need to take HW lock because MCP or other port might also
4151 try to handle this event */
4152 bnx2x_acquire_alr(bp);
4153
4154 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4155 #ifndef BNX2X_STOP_ON_ERROR
4156 bp->recovery_state = BNX2X_RECOVERY_INIT;
4157 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4158 /* Disable HW interrupts */
4159 bnx2x_int_disable(bp);
4160 /* In case of parity errors don't handle attentions so that
4161 * other function would "see" parity errors.
4162 */
4163 #else
4164 bnx2x_panic();
4165 #endif
4166 bnx2x_release_alr(bp);
4167 return;
4168 }
4169
4170 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4171 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4172 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4173 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4174 if (!CHIP_IS_E1x(bp))
4175 attn.sig[4] =
4176 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4177 else
4178 attn.sig[4] = 0;
4179
4180 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4181 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4182
4183 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4184 if (deasserted & (1 << index)) {
4185 group_mask = &bp->attn_group[index];
4186
4187 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4188 "%08x %08x %08x\n",
4189 index,
4190 group_mask->sig[0], group_mask->sig[1],
4191 group_mask->sig[2], group_mask->sig[3],
4192 group_mask->sig[4]);
4193
4194 bnx2x_attn_int_deasserted4(bp,
4195 attn.sig[4] & group_mask->sig[4]);
4196 bnx2x_attn_int_deasserted3(bp,
4197 attn.sig[3] & group_mask->sig[3]);
4198 bnx2x_attn_int_deasserted1(bp,
4199 attn.sig[1] & group_mask->sig[1]);
4200 bnx2x_attn_int_deasserted2(bp,
4201 attn.sig[2] & group_mask->sig[2]);
4202 bnx2x_attn_int_deasserted0(bp,
4203 attn.sig[0] & group_mask->sig[0]);
4204 }
4205 }
4206
4207 bnx2x_release_alr(bp);
4208
4209 if (bp->common.int_block == INT_BLOCK_HC)
4210 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4211 COMMAND_REG_ATTN_BITS_CLR);
4212 else
4213 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4214
4215 val = ~deasserted;
4216 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4217 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4218 REG_WR(bp, reg_addr, val);
4219
4220 if (~bp->attn_state & deasserted)
4221 BNX2X_ERR("IGU ERROR\n");
4222
4223 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4224 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4225
4226 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4227 aeu_mask = REG_RD(bp, reg_addr);
4228
4229 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4230 aeu_mask, deasserted);
4231 aeu_mask |= (deasserted & 0x3ff);
4232 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4233
4234 REG_WR(bp, reg_addr, aeu_mask);
4235 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4236
4237 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4238 bp->attn_state &= ~deasserted;
4239 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4240 }
4241
4242 static void bnx2x_attn_int(struct bnx2x *bp)
4243 {
4244 /* read local copy of bits */
4245 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4246 attn_bits);
4247 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4248 attn_bits_ack);
4249 u32 attn_state = bp->attn_state;
4250
4251 /* look for changed bits */
4252 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4253 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4254
4255 DP(NETIF_MSG_HW,
4256 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4257 attn_bits, attn_ack, asserted, deasserted);
4258
4259 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4260 BNX2X_ERR("BAD attention state\n");
4261
4262 /* handle bits that were raised */
4263 if (asserted)
4264 bnx2x_attn_int_asserted(bp, asserted);
4265
4266 if (deasserted)
4267 bnx2x_attn_int_deasserted(bp, deasserted);
4268 }
4269
4270 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4271 u16 index, u8 op, u8 update)
4272 {
4273 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4274
4275 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4276 igu_addr);
4277 }
4278
4279 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4280 {
4281 /* No memory barriers */
4282 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4283 mmiowb(); /* keep prod updates ordered */
4284 }
4285
4286 #ifdef BCM_CNIC
4287 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4288 union event_ring_elem *elem)
4289 {
4290 u8 err = elem->message.error;
4291
4292 if (!bp->cnic_eth_dev.starting_cid ||
4293 (cid < bp->cnic_eth_dev.starting_cid &&
4294 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4295 return 1;
4296
4297 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4298
4299 if (unlikely(err)) {
4300
4301 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4302 cid);
4303 bnx2x_panic_dump(bp);
4304 }
4305 bnx2x_cnic_cfc_comp(bp, cid, err);
4306 return 0;
4307 }
4308 #endif
4309
4310 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4311 {
4312 struct bnx2x_mcast_ramrod_params rparam;
4313 int rc;
4314
4315 memset(&rparam, 0, sizeof(rparam));
4316
4317 rparam.mcast_obj = &bp->mcast_obj;
4318
4319 netif_addr_lock_bh(bp->dev);
4320
4321 /* Clear pending state for the last command */
4322 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4323
4324 /* If there are pending mcast commands - send them */
4325 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4326 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4327 if (rc < 0)
4328 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4329 rc);
4330 }
4331
4332 netif_addr_unlock_bh(bp->dev);
4333 }
4334
4335 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4336 union event_ring_elem *elem)
4337 {
4338 unsigned long ramrod_flags = 0;
4339 int rc = 0;
4340 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4341 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4342
4343 /* Always push next commands out, don't wait here */
4344 __set_bit(RAMROD_CONT, &ramrod_flags);
4345
4346 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4347 case BNX2X_FILTER_MAC_PENDING:
4348 #ifdef BCM_CNIC
4349 if (cid == BNX2X_ISCSI_ETH_CID)
4350 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4351 else
4352 #endif
4353 vlan_mac_obj = &bp->fp[cid].mac_obj;
4354
4355 break;
4356 case BNX2X_FILTER_MCAST_PENDING:
4357 /* This is only relevant for 57710 where multicast MACs are
4358 * configured as unicast MACs using the same ramrod.
4359 */
4360 bnx2x_handle_mcast_eqe(bp);
4361 return;
4362 default:
4363 BNX2X_ERR("Unsupported classification command: %d\n",
4364 elem->message.data.eth_event.echo);
4365 return;
4366 }
4367
4368 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4369
4370 if (rc < 0)
4371 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4372 else if (rc > 0)
4373 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4374
4375 }
4376
4377 #ifdef BCM_CNIC
4378 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4379 #endif
4380
4381 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4382 {
4383 netif_addr_lock_bh(bp->dev);
4384
4385 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4386
4387 /* Send rx_mode command again if was requested */
4388 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4389 bnx2x_set_storm_rx_mode(bp);
4390 #ifdef BCM_CNIC
4391 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4392 &bp->sp_state))
4393 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4394 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4395 &bp->sp_state))
4396 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4397 #endif
4398
4399 netif_addr_unlock_bh(bp->dev);
4400 }
4401
4402 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4403 struct bnx2x *bp, u32 cid)
4404 {
4405 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4406 #ifdef BCM_CNIC
4407 if (cid == BNX2X_FCOE_ETH_CID)
4408 return &bnx2x_fcoe(bp, q_obj);
4409 else
4410 #endif
4411 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4412 }
4413
4414 static void bnx2x_eq_int(struct bnx2x *bp)
4415 {
4416 u16 hw_cons, sw_cons, sw_prod;
4417 union event_ring_elem *elem;
4418 u32 cid;
4419 u8 opcode;
4420 int spqe_cnt = 0;
4421 struct bnx2x_queue_sp_obj *q_obj;
4422 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4423 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4424
4425 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4426
4427 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4428 * when we get the the next-page we nned to adjust so the loop
4429 * condition below will be met. The next element is the size of a
4430 * regular element and hence incrementing by 1
4431 */
4432 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4433 hw_cons++;
4434
4435 /* This function may never run in parallel with itself for a
4436 * specific bp, thus there is no need in "paired" read memory
4437 * barrier here.
4438 */
4439 sw_cons = bp->eq_cons;
4440 sw_prod = bp->eq_prod;
4441
4442 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4443 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4444
4445 for (; sw_cons != hw_cons;
4446 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4447
4448
4449 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4450
4451 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4452 opcode = elem->message.opcode;
4453
4454
4455 /* handle eq element */
4456 switch (opcode) {
4457 case EVENT_RING_OPCODE_STAT_QUERY:
4458 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4459 bp->stats_comp++);
4460 /* nothing to do with stats comp */
4461 goto next_spqe;
4462
4463 case EVENT_RING_OPCODE_CFC_DEL:
4464 /* handle according to cid range */
4465 /*
4466 * we may want to verify here that the bp state is
4467 * HALTING
4468 */
4469 DP(BNX2X_MSG_SP,
4470 "got delete ramrod for MULTI[%d]\n", cid);
4471 #ifdef BCM_CNIC
4472 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4473 goto next_spqe;
4474 #endif
4475 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4476
4477 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4478 break;
4479
4480
4481
4482 goto next_spqe;
4483
4484 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4485 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4486 if (f_obj->complete_cmd(bp, f_obj,
4487 BNX2X_F_CMD_TX_STOP))
4488 break;
4489 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4490 goto next_spqe;
4491
4492 case EVENT_RING_OPCODE_START_TRAFFIC:
4493 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4494 if (f_obj->complete_cmd(bp, f_obj,
4495 BNX2X_F_CMD_TX_START))
4496 break;
4497 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4498 goto next_spqe;
4499 case EVENT_RING_OPCODE_FUNCTION_START:
4500 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4501 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4502 break;
4503
4504 goto next_spqe;
4505
4506 case EVENT_RING_OPCODE_FUNCTION_STOP:
4507 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4508 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4509 break;
4510
4511 goto next_spqe;
4512 }
4513
4514 switch (opcode | bp->state) {
4515 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4516 BNX2X_STATE_OPEN):
4517 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4518 BNX2X_STATE_OPENING_WAIT4_PORT):
4519 cid = elem->message.data.eth_event.echo &
4520 BNX2X_SWCID_MASK;
4521 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4522 cid);
4523 rss_raw->clear_pending(rss_raw);
4524 break;
4525
4526 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4527 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4528 case (EVENT_RING_OPCODE_SET_MAC |
4529 BNX2X_STATE_CLOSING_WAIT4_HALT):
4530 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4531 BNX2X_STATE_OPEN):
4532 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4533 BNX2X_STATE_DIAG):
4534 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4535 BNX2X_STATE_CLOSING_WAIT4_HALT):
4536 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4537 bnx2x_handle_classification_eqe(bp, elem);
4538 break;
4539
4540 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4541 BNX2X_STATE_OPEN):
4542 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4543 BNX2X_STATE_DIAG):
4544 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4545 BNX2X_STATE_CLOSING_WAIT4_HALT):
4546 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4547 bnx2x_handle_mcast_eqe(bp);
4548 break;
4549
4550 case (EVENT_RING_OPCODE_FILTERS_RULES |
4551 BNX2X_STATE_OPEN):
4552 case (EVENT_RING_OPCODE_FILTERS_RULES |
4553 BNX2X_STATE_DIAG):
4554 case (EVENT_RING_OPCODE_FILTERS_RULES |
4555 BNX2X_STATE_CLOSING_WAIT4_HALT):
4556 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4557 bnx2x_handle_rx_mode_eqe(bp);
4558 break;
4559 default:
4560 /* unknown event log error and continue */
4561 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4562 elem->message.opcode, bp->state);
4563 }
4564 next_spqe:
4565 spqe_cnt++;
4566 } /* for */
4567
4568 smp_mb__before_atomic_inc();
4569 atomic_add(spqe_cnt, &bp->eq_spq_left);
4570
4571 bp->eq_cons = sw_cons;
4572 bp->eq_prod = sw_prod;
4573 /* Make sure that above mem writes were issued towards the memory */
4574 smp_wmb();
4575
4576 /* update producer */
4577 bnx2x_update_eq_prod(bp, bp->eq_prod);
4578 }
4579
4580 static void bnx2x_sp_task(struct work_struct *work)
4581 {
4582 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4583 u16 status;
4584
4585 status = bnx2x_update_dsb_idx(bp);
4586 /* if (status == 0) */
4587 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4588
4589 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4590
4591 /* HW attentions */
4592 if (status & BNX2X_DEF_SB_ATT_IDX) {
4593 bnx2x_attn_int(bp);
4594 status &= ~BNX2X_DEF_SB_ATT_IDX;
4595 }
4596
4597 /* SP events: STAT_QUERY and others */
4598 if (status & BNX2X_DEF_SB_IDX) {
4599 #ifdef BCM_CNIC
4600 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4601
4602 if ((!NO_FCOE(bp)) &&
4603 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4604 /*
4605 * Prevent local bottom-halves from running as
4606 * we are going to change the local NAPI list.
4607 */
4608 local_bh_disable();
4609 napi_schedule(&bnx2x_fcoe(bp, napi));
4610 local_bh_enable();
4611 }
4612 #endif
4613 /* Handle EQ completions */
4614 bnx2x_eq_int(bp);
4615
4616 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4617 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4618
4619 status &= ~BNX2X_DEF_SB_IDX;
4620 }
4621
4622 if (unlikely(status))
4623 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4624 status);
4625
4626 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4627 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4628 }
4629
4630 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4631 {
4632 struct net_device *dev = dev_instance;
4633 struct bnx2x *bp = netdev_priv(dev);
4634
4635 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4636 IGU_INT_DISABLE, 0);
4637
4638 #ifdef BNX2X_STOP_ON_ERROR
4639 if (unlikely(bp->panic))
4640 return IRQ_HANDLED;
4641 #endif
4642
4643 #ifdef BCM_CNIC
4644 {
4645 struct cnic_ops *c_ops;
4646
4647 rcu_read_lock();
4648 c_ops = rcu_dereference(bp->cnic_ops);
4649 if (c_ops)
4650 c_ops->cnic_handler(bp->cnic_data, NULL);
4651 rcu_read_unlock();
4652 }
4653 #endif
4654 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4655
4656 return IRQ_HANDLED;
4657 }
4658
4659 /* end of slow path */
4660
4661
4662 void bnx2x_drv_pulse(struct bnx2x *bp)
4663 {
4664 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4665 bp->fw_drv_pulse_wr_seq);
4666 }
4667
4668
4669 static void bnx2x_timer(unsigned long data)
4670 {
4671 u8 cos;
4672 struct bnx2x *bp = (struct bnx2x *) data;
4673
4674 if (!netif_running(bp->dev))
4675 return;
4676
4677 if (poll) {
4678 struct bnx2x_fastpath *fp = &bp->fp[0];
4679
4680 for_each_cos_in_tx_queue(fp, cos)
4681 bnx2x_tx_int(bp, &fp->txdata[cos]);
4682 bnx2x_rx_int(fp, 1000);
4683 }
4684
4685 if (!BP_NOMCP(bp)) {
4686 int mb_idx = BP_FW_MB_IDX(bp);
4687 u32 drv_pulse;
4688 u32 mcp_pulse;
4689
4690 ++bp->fw_drv_pulse_wr_seq;
4691 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4692 /* TBD - add SYSTEM_TIME */
4693 drv_pulse = bp->fw_drv_pulse_wr_seq;
4694 bnx2x_drv_pulse(bp);
4695
4696 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4697 MCP_PULSE_SEQ_MASK);
4698 /* The delta between driver pulse and mcp response
4699 * should be 1 (before mcp response) or 0 (after mcp response)
4700 */
4701 if ((drv_pulse != mcp_pulse) &&
4702 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4703 /* someone lost a heartbeat... */
4704 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4705 drv_pulse, mcp_pulse);
4706 }
4707 }
4708
4709 if (bp->state == BNX2X_STATE_OPEN)
4710 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4711
4712 mod_timer(&bp->timer, jiffies + bp->current_interval);
4713 }
4714
4715 /* end of Statistics */
4716
4717 /* nic init */
4718
4719 /*
4720 * nic init service functions
4721 */
4722
4723 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4724 {
4725 u32 i;
4726 if (!(len%4) && !(addr%4))
4727 for (i = 0; i < len; i += 4)
4728 REG_WR(bp, addr + i, fill);
4729 else
4730 for (i = 0; i < len; i++)
4731 REG_WR8(bp, addr + i, fill);
4732
4733 }
4734
4735 /* helper: writes FP SP data to FW - data_size in dwords */
4736 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4737 int fw_sb_id,
4738 u32 *sb_data_p,
4739 u32 data_size)
4740 {
4741 int index;
4742 for (index = 0; index < data_size; index++)
4743 REG_WR(bp, BAR_CSTRORM_INTMEM +
4744 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4745 sizeof(u32)*index,
4746 *(sb_data_p + index));
4747 }
4748
4749 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4750 {
4751 u32 *sb_data_p;
4752 u32 data_size = 0;
4753 struct hc_status_block_data_e2 sb_data_e2;
4754 struct hc_status_block_data_e1x sb_data_e1x;
4755
4756 /* disable the function first */
4757 if (!CHIP_IS_E1x(bp)) {
4758 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4759 sb_data_e2.common.state = SB_DISABLED;
4760 sb_data_e2.common.p_func.vf_valid = false;
4761 sb_data_p = (u32 *)&sb_data_e2;
4762 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4763 } else {
4764 memset(&sb_data_e1x, 0,
4765 sizeof(struct hc_status_block_data_e1x));
4766 sb_data_e1x.common.state = SB_DISABLED;
4767 sb_data_e1x.common.p_func.vf_valid = false;
4768 sb_data_p = (u32 *)&sb_data_e1x;
4769 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4770 }
4771 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4772
4773 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4774 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4775 CSTORM_STATUS_BLOCK_SIZE);
4776 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4777 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4778 CSTORM_SYNC_BLOCK_SIZE);
4779 }
4780
4781 /* helper: writes SP SB data to FW */
4782 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4783 struct hc_sp_status_block_data *sp_sb_data)
4784 {
4785 int func = BP_FUNC(bp);
4786 int i;
4787 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4788 REG_WR(bp, BAR_CSTRORM_INTMEM +
4789 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4790 i*sizeof(u32),
4791 *((u32 *)sp_sb_data + i));
4792 }
4793
4794 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4795 {
4796 int func = BP_FUNC(bp);
4797 struct hc_sp_status_block_data sp_sb_data;
4798 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4799
4800 sp_sb_data.state = SB_DISABLED;
4801 sp_sb_data.p_func.vf_valid = false;
4802
4803 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4804
4805 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4806 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4807 CSTORM_SP_STATUS_BLOCK_SIZE);
4808 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4809 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4810 CSTORM_SP_SYNC_BLOCK_SIZE);
4811
4812 }
4813
4814
4815 static inline
4816 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4817 int igu_sb_id, int igu_seg_id)
4818 {
4819 hc_sm->igu_sb_id = igu_sb_id;
4820 hc_sm->igu_seg_id = igu_seg_id;
4821 hc_sm->timer_value = 0xFF;
4822 hc_sm->time_to_expire = 0xFFFFFFFF;
4823 }
4824
4825
4826 /* allocates state machine ids. */
4827 static inline
4828 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4829 {
4830 /* zero out state machine indices */
4831 /* rx indices */
4832 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4833
4834 /* tx indices */
4835 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4836 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4837 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4838 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4839
4840 /* map indices */
4841 /* rx indices */
4842 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4843 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4844
4845 /* tx indices */
4846 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4847 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4848 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4849 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4850 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4851 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4852 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4853 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4854 }
4855
4856 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4857 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4858 {
4859 int igu_seg_id;
4860
4861 struct hc_status_block_data_e2 sb_data_e2;
4862 struct hc_status_block_data_e1x sb_data_e1x;
4863 struct hc_status_block_sm *hc_sm_p;
4864 int data_size;
4865 u32 *sb_data_p;
4866
4867 if (CHIP_INT_MODE_IS_BC(bp))
4868 igu_seg_id = HC_SEG_ACCESS_NORM;
4869 else
4870 igu_seg_id = IGU_SEG_ACCESS_NORM;
4871
4872 bnx2x_zero_fp_sb(bp, fw_sb_id);
4873
4874 if (!CHIP_IS_E1x(bp)) {
4875 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4876 sb_data_e2.common.state = SB_ENABLED;
4877 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4878 sb_data_e2.common.p_func.vf_id = vfid;
4879 sb_data_e2.common.p_func.vf_valid = vf_valid;
4880 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4881 sb_data_e2.common.same_igu_sb_1b = true;
4882 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4883 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4884 hc_sm_p = sb_data_e2.common.state_machine;
4885 sb_data_p = (u32 *)&sb_data_e2;
4886 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4887 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4888 } else {
4889 memset(&sb_data_e1x, 0,
4890 sizeof(struct hc_status_block_data_e1x));
4891 sb_data_e1x.common.state = SB_ENABLED;
4892 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4893 sb_data_e1x.common.p_func.vf_id = 0xff;
4894 sb_data_e1x.common.p_func.vf_valid = false;
4895 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4896 sb_data_e1x.common.same_igu_sb_1b = true;
4897 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4898 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4899 hc_sm_p = sb_data_e1x.common.state_machine;
4900 sb_data_p = (u32 *)&sb_data_e1x;
4901 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4902 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4903 }
4904
4905 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4906 igu_sb_id, igu_seg_id);
4907 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4908 igu_sb_id, igu_seg_id);
4909
4910 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4911
4912 /* write indecies to HW */
4913 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4914 }
4915
4916 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4917 u16 tx_usec, u16 rx_usec)
4918 {
4919 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4920 false, rx_usec);
4921 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4922 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4923 tx_usec);
4924 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4925 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4926 tx_usec);
4927 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4928 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4929 tx_usec);
4930 }
4931
4932 static void bnx2x_init_def_sb(struct bnx2x *bp)
4933 {
4934 struct host_sp_status_block *def_sb = bp->def_status_blk;
4935 dma_addr_t mapping = bp->def_status_blk_mapping;
4936 int igu_sp_sb_index;
4937 int igu_seg_id;
4938 int port = BP_PORT(bp);
4939 int func = BP_FUNC(bp);
4940 int reg_offset;
4941 u64 section;
4942 int index;
4943 struct hc_sp_status_block_data sp_sb_data;
4944 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4945
4946 if (CHIP_INT_MODE_IS_BC(bp)) {
4947 igu_sp_sb_index = DEF_SB_IGU_ID;
4948 igu_seg_id = HC_SEG_ACCESS_DEF;
4949 } else {
4950 igu_sp_sb_index = bp->igu_dsb_id;
4951 igu_seg_id = IGU_SEG_ACCESS_DEF;
4952 }
4953
4954 /* ATTN */
4955 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4956 atten_status_block);
4957 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4958
4959 bp->attn_state = 0;
4960
4961 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4962 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4963 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4964 int sindex;
4965 /* take care of sig[0]..sig[4] */
4966 for (sindex = 0; sindex < 4; sindex++)
4967 bp->attn_group[index].sig[sindex] =
4968 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4969
4970 if (!CHIP_IS_E1x(bp))
4971 /*
4972 * enable5 is separate from the rest of the registers,
4973 * and therefore the address skip is 4
4974 * and not 16 between the different groups
4975 */
4976 bp->attn_group[index].sig[4] = REG_RD(bp,
4977 reg_offset + 0x10 + 0x4*index);
4978 else
4979 bp->attn_group[index].sig[4] = 0;
4980 }
4981
4982 if (bp->common.int_block == INT_BLOCK_HC) {
4983 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4984 HC_REG_ATTN_MSG0_ADDR_L);
4985
4986 REG_WR(bp, reg_offset, U64_LO(section));
4987 REG_WR(bp, reg_offset + 4, U64_HI(section));
4988 } else if (!CHIP_IS_E1x(bp)) {
4989 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4990 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4991 }
4992
4993 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4994 sp_sb);
4995
4996 bnx2x_zero_sp_sb(bp);
4997
4998 sp_sb_data.state = SB_ENABLED;
4999 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5000 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5001 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5002 sp_sb_data.igu_seg_id = igu_seg_id;
5003 sp_sb_data.p_func.pf_id = func;
5004 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5005 sp_sb_data.p_func.vf_id = 0xff;
5006
5007 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5008
5009 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5010 }
5011
5012 void bnx2x_update_coalesce(struct bnx2x *bp)
5013 {
5014 int i;
5015
5016 for_each_eth_queue(bp, i)
5017 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5018 bp->tx_ticks, bp->rx_ticks);
5019 }
5020
5021 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5022 {
5023 spin_lock_init(&bp->spq_lock);
5024 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5025
5026 bp->spq_prod_idx = 0;
5027 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5028 bp->spq_prod_bd = bp->spq;
5029 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5030 }
5031
5032 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5033 {
5034 int i;
5035 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5036 union event_ring_elem *elem =
5037 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5038
5039 elem->next_page.addr.hi =
5040 cpu_to_le32(U64_HI(bp->eq_mapping +
5041 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5042 elem->next_page.addr.lo =
5043 cpu_to_le32(U64_LO(bp->eq_mapping +
5044 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5045 }
5046 bp->eq_cons = 0;
5047 bp->eq_prod = NUM_EQ_DESC;
5048 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5049 /* we want a warning message before it gets rought... */
5050 atomic_set(&bp->eq_spq_left,
5051 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5052 }
5053
5054
5055 /* called with netif_addr_lock_bh() */
5056 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5057 unsigned long rx_mode_flags,
5058 unsigned long rx_accept_flags,
5059 unsigned long tx_accept_flags,
5060 unsigned long ramrod_flags)
5061 {
5062 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5063 int rc;
5064
5065 memset(&ramrod_param, 0, sizeof(ramrod_param));
5066
5067 /* Prepare ramrod parameters */
5068 ramrod_param.cid = 0;
5069 ramrod_param.cl_id = cl_id;
5070 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5071 ramrod_param.func_id = BP_FUNC(bp);
5072
5073 ramrod_param.pstate = &bp->sp_state;
5074 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5075
5076 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5077 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5078
5079 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5080
5081 ramrod_param.ramrod_flags = ramrod_flags;
5082 ramrod_param.rx_mode_flags = rx_mode_flags;
5083
5084 ramrod_param.rx_accept_flags = rx_accept_flags;
5085 ramrod_param.tx_accept_flags = tx_accept_flags;
5086
5087 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5088 if (rc < 0) {
5089 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5090 return;
5091 }
5092 }
5093
5094 /* called with netif_addr_lock_bh() */
5095 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5096 {
5097 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5098 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5099
5100 #ifdef BCM_CNIC
5101 if (!NO_FCOE(bp))
5102
5103 /* Configure rx_mode of FCoE Queue */
5104 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5105 #endif
5106
5107 switch (bp->rx_mode) {
5108 case BNX2X_RX_MODE_NONE:
5109 /*
5110 * 'drop all' supersedes any accept flags that may have been
5111 * passed to the function.
5112 */
5113 break;
5114 case BNX2X_RX_MODE_NORMAL:
5115 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5117 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5118
5119 /* internal switching mode */
5120 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5121 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5122 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5123
5124 break;
5125 case BNX2X_RX_MODE_ALLMULTI:
5126 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5127 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5128 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5129
5130 /* internal switching mode */
5131 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5132 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5133 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5134
5135 break;
5136 case BNX2X_RX_MODE_PROMISC:
5137 /* According to deffinition of SI mode, iface in promisc mode
5138 * should receive matched and unmatched (in resolution of port)
5139 * unicast packets.
5140 */
5141 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5142 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5143 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5144 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5145
5146 /* internal switching mode */
5147 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5148 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5149
5150 if (IS_MF_SI(bp))
5151 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5152 else
5153 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5154
5155 break;
5156 default:
5157 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5158 return;
5159 }
5160
5161 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5162 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5163 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5164 }
5165
5166 __set_bit(RAMROD_RX, &ramrod_flags);
5167 __set_bit(RAMROD_TX, &ramrod_flags);
5168
5169 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5170 tx_accept_flags, ramrod_flags);
5171 }
5172
5173 static void bnx2x_init_internal_common(struct bnx2x *bp)
5174 {
5175 int i;
5176
5177 if (IS_MF_SI(bp))
5178 /*
5179 * In switch independent mode, the TSTORM needs to accept
5180 * packets that failed classification, since approximate match
5181 * mac addresses aren't written to NIG LLH
5182 */
5183 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5184 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5185 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5186 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5187 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5188
5189 /* Zero this manually as its initialization is
5190 currently missing in the initTool */
5191 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5192 REG_WR(bp, BAR_USTRORM_INTMEM +
5193 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5194 if (!CHIP_IS_E1x(bp)) {
5195 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5196 CHIP_INT_MODE_IS_BC(bp) ?
5197 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5198 }
5199 }
5200
5201 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5202 {
5203 switch (load_code) {
5204 case FW_MSG_CODE_DRV_LOAD_COMMON:
5205 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5206 bnx2x_init_internal_common(bp);
5207 /* no break */
5208
5209 case FW_MSG_CODE_DRV_LOAD_PORT:
5210 /* nothing to do */
5211 /* no break */
5212
5213 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5214 /* internal memory per function is
5215 initialized inside bnx2x_pf_init */
5216 break;
5217
5218 default:
5219 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5220 break;
5221 }
5222 }
5223
5224 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5225 {
5226 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5227 }
5228
5229 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5230 {
5231 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5232 }
5233
5234 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5235 {
5236 if (CHIP_IS_E1x(fp->bp))
5237 return BP_L_ID(fp->bp) + fp->index;
5238 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5239 return bnx2x_fp_igu_sb_id(fp);
5240 }
5241
5242 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5243 {
5244 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5245 u8 cos;
5246 unsigned long q_type = 0;
5247 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5248
5249 fp->cid = fp_idx;
5250 fp->cl_id = bnx2x_fp_cl_id(fp);
5251 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5252 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5253 /* qZone id equals to FW (per path) client id */
5254 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5255
5256 /* init shortcut */
5257 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5258 /* Setup SB indicies */
5259 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5260
5261 /* Configure Queue State object */
5262 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5263 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5264
5265 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5266
5267 /* init tx data */
5268 for_each_cos_in_tx_queue(fp, cos) {
5269 bnx2x_init_txdata(bp, &fp->txdata[cos],
5270 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5271 FP_COS_TO_TXQ(fp, cos),
5272 BNX2X_TX_SB_INDEX_BASE + cos);
5273 cids[cos] = fp->txdata[cos].cid;
5274 }
5275
5276 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5277 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5278 bnx2x_sp_mapping(bp, q_rdata), q_type);
5279
5280 /**
5281 * Configure classification DBs: Always enable Tx switching
5282 */
5283 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5284
5285 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5286 "cl_id %d fw_sb %d igu_sb %d\n",
5287 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5288 fp->igu_sb_id);
5289 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5290 fp->fw_sb_id, fp->igu_sb_id);
5291
5292 bnx2x_update_fpsb_idx(fp);
5293 }
5294
5295 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5296 {
5297 int i;
5298
5299 for_each_eth_queue(bp, i)
5300 bnx2x_init_eth_fp(bp, i);
5301 #ifdef BCM_CNIC
5302 if (!NO_FCOE(bp))
5303 bnx2x_init_fcoe_fp(bp);
5304
5305 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5306 BNX2X_VF_ID_INVALID, false,
5307 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5308
5309 #endif
5310
5311 /* Initialize MOD_ABS interrupts */
5312 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5313 bp->common.shmem_base, bp->common.shmem2_base,
5314 BP_PORT(bp));
5315 /* ensure status block indices were read */
5316 rmb();
5317
5318 bnx2x_init_def_sb(bp);
5319 bnx2x_update_dsb_idx(bp);
5320 bnx2x_init_rx_rings(bp);
5321 bnx2x_init_tx_rings(bp);
5322 bnx2x_init_sp_ring(bp);
5323 bnx2x_init_eq_ring(bp);
5324 bnx2x_init_internal(bp, load_code);
5325 bnx2x_pf_init(bp);
5326 bnx2x_stats_init(bp);
5327
5328 /* flush all before enabling interrupts */
5329 mb();
5330 mmiowb();
5331
5332 bnx2x_int_enable(bp);
5333
5334 /* Check for SPIO5 */
5335 bnx2x_attn_int_deasserted0(bp,
5336 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5337 AEU_INPUTS_ATTN_BITS_SPIO5);
5338 }
5339
5340 /* end of nic init */
5341
5342 /*
5343 * gzip service functions
5344 */
5345
5346 static int bnx2x_gunzip_init(struct bnx2x *bp)
5347 {
5348 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5349 &bp->gunzip_mapping, GFP_KERNEL);
5350 if (bp->gunzip_buf == NULL)
5351 goto gunzip_nomem1;
5352
5353 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5354 if (bp->strm == NULL)
5355 goto gunzip_nomem2;
5356
5357 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5358 if (bp->strm->workspace == NULL)
5359 goto gunzip_nomem3;
5360
5361 return 0;
5362
5363 gunzip_nomem3:
5364 kfree(bp->strm);
5365 bp->strm = NULL;
5366
5367 gunzip_nomem2:
5368 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5369 bp->gunzip_mapping);
5370 bp->gunzip_buf = NULL;
5371
5372 gunzip_nomem1:
5373 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5374 " un-compression\n");
5375 return -ENOMEM;
5376 }
5377
5378 static void bnx2x_gunzip_end(struct bnx2x *bp)
5379 {
5380 if (bp->strm) {
5381 vfree(bp->strm->workspace);
5382 kfree(bp->strm);
5383 bp->strm = NULL;
5384 }
5385
5386 if (bp->gunzip_buf) {
5387 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5388 bp->gunzip_mapping);
5389 bp->gunzip_buf = NULL;
5390 }
5391 }
5392
5393 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5394 {
5395 int n, rc;
5396
5397 /* check gzip header */
5398 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5399 BNX2X_ERR("Bad gzip header\n");
5400 return -EINVAL;
5401 }
5402
5403 n = 10;
5404
5405 #define FNAME 0x8
5406
5407 if (zbuf[3] & FNAME)
5408 while ((zbuf[n++] != 0) && (n < len));
5409
5410 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5411 bp->strm->avail_in = len - n;
5412 bp->strm->next_out = bp->gunzip_buf;
5413 bp->strm->avail_out = FW_BUF_SIZE;
5414
5415 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5416 if (rc != Z_OK)
5417 return rc;
5418
5419 rc = zlib_inflate(bp->strm, Z_FINISH);
5420 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5421 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5422 bp->strm->msg);
5423
5424 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5425 if (bp->gunzip_outlen & 0x3)
5426 netdev_err(bp->dev, "Firmware decompression error:"
5427 " gunzip_outlen (%d) not aligned\n",
5428 bp->gunzip_outlen);
5429 bp->gunzip_outlen >>= 2;
5430
5431 zlib_inflateEnd(bp->strm);
5432
5433 if (rc == Z_STREAM_END)
5434 return 0;
5435
5436 return rc;
5437 }
5438
5439 /* nic load/unload */
5440
5441 /*
5442 * General service functions
5443 */
5444
5445 /* send a NIG loopback debug packet */
5446 static void bnx2x_lb_pckt(struct bnx2x *bp)
5447 {
5448 u32 wb_write[3];
5449
5450 /* Ethernet source and destination addresses */
5451 wb_write[0] = 0x55555555;
5452 wb_write[1] = 0x55555555;
5453 wb_write[2] = 0x20; /* SOP */
5454 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5455
5456 /* NON-IP protocol */
5457 wb_write[0] = 0x09000000;
5458 wb_write[1] = 0x55555555;
5459 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5460 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5461 }
5462
5463 /* some of the internal memories
5464 * are not directly readable from the driver
5465 * to test them we send debug packets
5466 */
5467 static int bnx2x_int_mem_test(struct bnx2x *bp)
5468 {
5469 int factor;
5470 int count, i;
5471 u32 val = 0;
5472
5473 if (CHIP_REV_IS_FPGA(bp))
5474 factor = 120;
5475 else if (CHIP_REV_IS_EMUL(bp))
5476 factor = 200;
5477 else
5478 factor = 1;
5479
5480 /* Disable inputs of parser neighbor blocks */
5481 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5482 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5483 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5484 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5485
5486 /* Write 0 to parser credits for CFC search request */
5487 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5488
5489 /* send Ethernet packet */
5490 bnx2x_lb_pckt(bp);
5491
5492 /* TODO do i reset NIG statistic? */
5493 /* Wait until NIG register shows 1 packet of size 0x10 */
5494 count = 1000 * factor;
5495 while (count) {
5496
5497 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5498 val = *bnx2x_sp(bp, wb_data[0]);
5499 if (val == 0x10)
5500 break;
5501
5502 msleep(10);
5503 count--;
5504 }
5505 if (val != 0x10) {
5506 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5507 return -1;
5508 }
5509
5510 /* Wait until PRS register shows 1 packet */
5511 count = 1000 * factor;
5512 while (count) {
5513 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5514 if (val == 1)
5515 break;
5516
5517 msleep(10);
5518 count--;
5519 }
5520 if (val != 0x1) {
5521 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5522 return -2;
5523 }
5524
5525 /* Reset and init BRB, PRS */
5526 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5527 msleep(50);
5528 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5529 msleep(50);
5530 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5531 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5532
5533 DP(NETIF_MSG_HW, "part2\n");
5534
5535 /* Disable inputs of parser neighbor blocks */
5536 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5537 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5538 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5539 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5540
5541 /* Write 0 to parser credits for CFC search request */
5542 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5543
5544 /* send 10 Ethernet packets */
5545 for (i = 0; i < 10; i++)
5546 bnx2x_lb_pckt(bp);
5547
5548 /* Wait until NIG register shows 10 + 1
5549 packets of size 11*0x10 = 0xb0 */
5550 count = 1000 * factor;
5551 while (count) {
5552
5553 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5554 val = *bnx2x_sp(bp, wb_data[0]);
5555 if (val == 0xb0)
5556 break;
5557
5558 msleep(10);
5559 count--;
5560 }
5561 if (val != 0xb0) {
5562 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5563 return -3;
5564 }
5565
5566 /* Wait until PRS register shows 2 packets */
5567 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5568 if (val != 2)
5569 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5570
5571 /* Write 1 to parser credits for CFC search request */
5572 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5573
5574 /* Wait until PRS register shows 3 packets */
5575 msleep(10 * factor);
5576 /* Wait until NIG register shows 1 packet of size 0x10 */
5577 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5578 if (val != 3)
5579 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5580
5581 /* clear NIG EOP FIFO */
5582 for (i = 0; i < 11; i++)
5583 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5584 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5585 if (val != 1) {
5586 BNX2X_ERR("clear of NIG failed\n");
5587 return -4;
5588 }
5589
5590 /* Reset and init BRB, PRS, NIG */
5591 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5592 msleep(50);
5593 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5594 msleep(50);
5595 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5596 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5597 #ifndef BCM_CNIC
5598 /* set NIC mode */
5599 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5600 #endif
5601
5602 /* Enable inputs of parser neighbor blocks */
5603 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5604 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5605 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5606 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5607
5608 DP(NETIF_MSG_HW, "done\n");
5609
5610 return 0; /* OK */
5611 }
5612
5613 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5614 {
5615 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5616 if (!CHIP_IS_E1x(bp))
5617 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5618 else
5619 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5620 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5621 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5622 /*
5623 * mask read length error interrupts in brb for parser
5624 * (parsing unit and 'checksum and crc' unit)
5625 * these errors are legal (PU reads fixed length and CAC can cause
5626 * read length error on truncated packets)
5627 */
5628 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5629 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5630 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5631 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5632 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5633 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5634 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5635 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5636 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5637 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5638 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5639 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5640 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5641 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5642 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5643 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5644 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5645 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5646 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5647
5648 if (CHIP_REV_IS_FPGA(bp))
5649 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5650 else if (!CHIP_IS_E1x(bp))
5651 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5652 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5653 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5654 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5655 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5656 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5657 else
5658 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5659 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5660 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5661 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5662 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5663
5664 if (!CHIP_IS_E1x(bp))
5665 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5666 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5667
5668 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5669 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5670 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5671 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5672 }
5673
5674 static void bnx2x_reset_common(struct bnx2x *bp)
5675 {
5676 u32 val = 0x1400;
5677
5678 /* reset_common */
5679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5680 0xd3ffff7f);
5681
5682 if (CHIP_IS_E3(bp)) {
5683 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5684 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5685 }
5686
5687 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5688 }
5689
5690 static void bnx2x_setup_dmae(struct bnx2x *bp)
5691 {
5692 bp->dmae_ready = 0;
5693 spin_lock_init(&bp->dmae_lock);
5694 }
5695
5696 static void bnx2x_init_pxp(struct bnx2x *bp)
5697 {
5698 u16 devctl;
5699 int r_order, w_order;
5700
5701 pci_read_config_word(bp->pdev,
5702 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5703 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5704 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5705 if (bp->mrrs == -1)
5706 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5707 else {
5708 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5709 r_order = bp->mrrs;
5710 }
5711
5712 bnx2x_init_pxp_arb(bp, r_order, w_order);
5713 }
5714
5715 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5716 {
5717 int is_required;
5718 u32 val;
5719 int port;
5720
5721 if (BP_NOMCP(bp))
5722 return;
5723
5724 is_required = 0;
5725 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5726 SHARED_HW_CFG_FAN_FAILURE_MASK;
5727
5728 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5729 is_required = 1;
5730
5731 /*
5732 * The fan failure mechanism is usually related to the PHY type since
5733 * the power consumption of the board is affected by the PHY. Currently,
5734 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5735 */
5736 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5737 for (port = PORT_0; port < PORT_MAX; port++) {
5738 is_required |=
5739 bnx2x_fan_failure_det_req(
5740 bp,
5741 bp->common.shmem_base,
5742 bp->common.shmem2_base,
5743 port);
5744 }
5745
5746 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5747
5748 if (is_required == 0)
5749 return;
5750
5751 /* Fan failure is indicated by SPIO 5 */
5752 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5753 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5754
5755 /* set to active low mode */
5756 val = REG_RD(bp, MISC_REG_SPIO_INT);
5757 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5758 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5759 REG_WR(bp, MISC_REG_SPIO_INT, val);
5760
5761 /* enable interrupt to signal the IGU */
5762 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5763 val |= (1 << MISC_REGISTERS_SPIO_5);
5764 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5765 }
5766
5767 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5768 {
5769 u32 offset = 0;
5770
5771 if (CHIP_IS_E1(bp))
5772 return;
5773 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5774 return;
5775
5776 switch (BP_ABS_FUNC(bp)) {
5777 case 0:
5778 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5779 break;
5780 case 1:
5781 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5782 break;
5783 case 2:
5784 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5785 break;
5786 case 3:
5787 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5788 break;
5789 case 4:
5790 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5791 break;
5792 case 5:
5793 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5794 break;
5795 case 6:
5796 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5797 break;
5798 case 7:
5799 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5800 break;
5801 default:
5802 return;
5803 }
5804
5805 REG_WR(bp, offset, pretend_func_num);
5806 REG_RD(bp, offset);
5807 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5808 }
5809
5810 void bnx2x_pf_disable(struct bnx2x *bp)
5811 {
5812 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5813 val &= ~IGU_PF_CONF_FUNC_EN;
5814
5815 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5816 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5817 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5818 }
5819
5820 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5821 {
5822 u32 shmem_base[2], shmem2_base[2];
5823 shmem_base[0] = bp->common.shmem_base;
5824 shmem2_base[0] = bp->common.shmem2_base;
5825 if (!CHIP_IS_E1x(bp)) {
5826 shmem_base[1] =
5827 SHMEM2_RD(bp, other_shmem_base_addr);
5828 shmem2_base[1] =
5829 SHMEM2_RD(bp, other_shmem2_base_addr);
5830 }
5831 bnx2x_acquire_phy_lock(bp);
5832 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5833 bp->common.chip_id);
5834 bnx2x_release_phy_lock(bp);
5835 }
5836
5837 /**
5838 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5839 *
5840 * @bp: driver handle
5841 */
5842 static int bnx2x_init_hw_common(struct bnx2x *bp)
5843 {
5844 u32 val;
5845
5846 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5847
5848 /*
5849 * take the UNDI lock to protect undi_unload flow from accessing
5850 * registers while we're resetting the chip
5851 */
5852 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5853
5854 bnx2x_reset_common(bp);
5855 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5856
5857 val = 0xfffc;
5858 if (CHIP_IS_E3(bp)) {
5859 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5860 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5861 }
5862 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5863
5864 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5865
5866 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5867
5868 if (!CHIP_IS_E1x(bp)) {
5869 u8 abs_func_id;
5870
5871 /**
5872 * 4-port mode or 2-port mode we need to turn of master-enable
5873 * for everyone, after that, turn it back on for self.
5874 * so, we disregard multi-function or not, and always disable
5875 * for all functions on the given path, this means 0,2,4,6 for
5876 * path 0 and 1,3,5,7 for path 1
5877 */
5878 for (abs_func_id = BP_PATH(bp);
5879 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5880 if (abs_func_id == BP_ABS_FUNC(bp)) {
5881 REG_WR(bp,
5882 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5883 1);
5884 continue;
5885 }
5886
5887 bnx2x_pretend_func(bp, abs_func_id);
5888 /* clear pf enable */
5889 bnx2x_pf_disable(bp);
5890 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5891 }
5892 }
5893
5894 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5895 if (CHIP_IS_E1(bp)) {
5896 /* enable HW interrupt from PXP on USDM overflow
5897 bit 16 on INT_MASK_0 */
5898 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5899 }
5900
5901 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5902 bnx2x_init_pxp(bp);
5903
5904 #ifdef __BIG_ENDIAN
5905 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5906 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5907 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5908 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5909 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5910 /* make sure this value is 0 */
5911 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5912
5913 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5914 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5915 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5916 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5917 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5918 #endif
5919
5920 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5921
5922 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5923 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5924
5925 /* let the HW do it's magic ... */
5926 msleep(100);
5927 /* finish PXP init */
5928 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5929 if (val != 1) {
5930 BNX2X_ERR("PXP2 CFG failed\n");
5931 return -EBUSY;
5932 }
5933 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5934 if (val != 1) {
5935 BNX2X_ERR("PXP2 RD_INIT failed\n");
5936 return -EBUSY;
5937 }
5938
5939 /* Timers bug workaround E2 only. We need to set the entire ILT to
5940 * have entries with value "0" and valid bit on.
5941 * This needs to be done by the first PF that is loaded in a path
5942 * (i.e. common phase)
5943 */
5944 if (!CHIP_IS_E1x(bp)) {
5945 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5946 * (i.e. vnic3) to start even if it is marked as "scan-off".
5947 * This occurs when a different function (func2,3) is being marked
5948 * as "scan-off". Real-life scenario for example: if a driver is being
5949 * load-unloaded while func6,7 are down. This will cause the timer to access
5950 * the ilt, translate to a logical address and send a request to read/write.
5951 * Since the ilt for the function that is down is not valid, this will cause
5952 * a translation error which is unrecoverable.
5953 * The Workaround is intended to make sure that when this happens nothing fatal
5954 * will occur. The workaround:
5955 * 1. First PF driver which loads on a path will:
5956 * a. After taking the chip out of reset, by using pretend,
5957 * it will write "0" to the following registers of
5958 * the other vnics.
5959 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5960 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5961 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5962 * And for itself it will write '1' to
5963 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5964 * dmae-operations (writing to pram for example.)
5965 * note: can be done for only function 6,7 but cleaner this
5966 * way.
5967 * b. Write zero+valid to the entire ILT.
5968 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5969 * VNIC3 (of that port). The range allocated will be the
5970 * entire ILT. This is needed to prevent ILT range error.
5971 * 2. Any PF driver load flow:
5972 * a. ILT update with the physical addresses of the allocated
5973 * logical pages.
5974 * b. Wait 20msec. - note that this timeout is needed to make
5975 * sure there are no requests in one of the PXP internal
5976 * queues with "old" ILT addresses.
5977 * c. PF enable in the PGLC.
5978 * d. Clear the was_error of the PF in the PGLC. (could have
5979 * occured while driver was down)
5980 * e. PF enable in the CFC (WEAK + STRONG)
5981 * f. Timers scan enable
5982 * 3. PF driver unload flow:
5983 * a. Clear the Timers scan_en.
5984 * b. Polling for scan_on=0 for that PF.
5985 * c. Clear the PF enable bit in the PXP.
5986 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5987 * e. Write zero+valid to all ILT entries (The valid bit must
5988 * stay set)
5989 * f. If this is VNIC 3 of a port then also init
5990 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5991 * to the last enrty in the ILT.
5992 *
5993 * Notes:
5994 * Currently the PF error in the PGLC is non recoverable.
5995 * In the future the there will be a recovery routine for this error.
5996 * Currently attention is masked.
5997 * Having an MCP lock on the load/unload process does not guarantee that
5998 * there is no Timer disable during Func6/7 enable. This is because the
5999 * Timers scan is currently being cleared by the MCP on FLR.
6000 * Step 2.d can be done only for PF6/7 and the driver can also check if
6001 * there is error before clearing it. But the flow above is simpler and
6002 * more general.
6003 * All ILT entries are written by zero+valid and not just PF6/7
6004 * ILT entries since in the future the ILT entries allocation for
6005 * PF-s might be dynamic.
6006 */
6007 struct ilt_client_info ilt_cli;
6008 struct bnx2x_ilt ilt;
6009 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6010 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6011
6012 /* initialize dummy TM client */
6013 ilt_cli.start = 0;
6014 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6015 ilt_cli.client_num = ILT_CLIENT_TM;
6016
6017 /* Step 1: set zeroes to all ilt page entries with valid bit on
6018 * Step 2: set the timers first/last ilt entry to point
6019 * to the entire range to prevent ILT range error for 3rd/4th
6020 * vnic (this code assumes existance of the vnic)
6021 *
6022 * both steps performed by call to bnx2x_ilt_client_init_op()
6023 * with dummy TM client
6024 *
6025 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6026 * and his brother are split registers
6027 */
6028 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6029 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6030 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6031
6032 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6033 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6034 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6035 }
6036
6037
6038 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6039 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6040
6041 if (!CHIP_IS_E1x(bp)) {
6042 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6043 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6044 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6045
6046 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6047
6048 /* let the HW do it's magic ... */
6049 do {
6050 msleep(200);
6051 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6052 } while (factor-- && (val != 1));
6053
6054 if (val != 1) {
6055 BNX2X_ERR("ATC_INIT failed\n");
6056 return -EBUSY;
6057 }
6058 }
6059
6060 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6061
6062 /* clean the DMAE memory */
6063 bp->dmae_ready = 1;
6064 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6065
6066 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6067
6068 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6069
6070 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6071
6072 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6073
6074 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6075 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6076 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6077 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6078
6079 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6080
6081
6082 /* QM queues pointers table */
6083 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6084
6085 /* soft reset pulse */
6086 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6087 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6088
6089 #ifdef BCM_CNIC
6090 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6091 #endif
6092
6093 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6094 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6095 if (!CHIP_REV_IS_SLOW(bp))
6096 /* enable hw interrupt from doorbell Q */
6097 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6098
6099 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6100
6101 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6102 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6103
6104 if (!CHIP_IS_E1(bp))
6105 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6106
6107 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6108 /* Bit-map indicating which L2 hdrs may appear
6109 * after the basic Ethernet header
6110 */
6111 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6112 bp->path_has_ovlan ? 7 : 6);
6113
6114 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6115 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6116 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6117 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6118
6119 if (!CHIP_IS_E1x(bp)) {
6120 /* reset VFC memories */
6121 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6122 VFC_MEMORIES_RST_REG_CAM_RST |
6123 VFC_MEMORIES_RST_REG_RAM_RST);
6124 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6125 VFC_MEMORIES_RST_REG_CAM_RST |
6126 VFC_MEMORIES_RST_REG_RAM_RST);
6127
6128 msleep(20);
6129 }
6130
6131 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6132 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6133 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6134 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6135
6136 /* sync semi rtc */
6137 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6138 0x80000000);
6139 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6140 0x80000000);
6141
6142 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6143 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6144 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6145
6146 if (!CHIP_IS_E1x(bp))
6147 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6148 bp->path_has_ovlan ? 7 : 6);
6149
6150 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6151
6152 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6153
6154 #ifdef BCM_CNIC
6155 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6156 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6157 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6158 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6159 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6160 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6161 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6162 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6163 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6164 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6165 #endif
6166 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6167
6168 if (sizeof(union cdu_context) != 1024)
6169 /* we currently assume that a context is 1024 bytes */
6170 dev_alert(&bp->pdev->dev, "please adjust the size "
6171 "of cdu_context(%ld)\n",
6172 (long)sizeof(union cdu_context));
6173
6174 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6175 val = (4 << 24) + (0 << 12) + 1024;
6176 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6177
6178 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6179 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6180 /* enable context validation interrupt from CFC */
6181 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6182
6183 /* set the thresholds to prevent CFC/CDU race */
6184 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6185
6186 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6187
6188 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6189 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6190
6191 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6192 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6193
6194 /* Reset PCIE errors for debug */
6195 REG_WR(bp, 0x2814, 0xffffffff);
6196 REG_WR(bp, 0x3820, 0xffffffff);
6197
6198 if (!CHIP_IS_E1x(bp)) {
6199 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6200 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6201 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6202 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6203 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6204 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6205 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6206 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6207 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6208 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6209 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6210 }
6211
6212 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6213 if (!CHIP_IS_E1(bp)) {
6214 /* in E3 this done in per-port section */
6215 if (!CHIP_IS_E3(bp))
6216 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6217 }
6218 if (CHIP_IS_E1H(bp))
6219 /* not applicable for E2 (and above ...) */
6220 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6221
6222 if (CHIP_REV_IS_SLOW(bp))
6223 msleep(200);
6224
6225 /* finish CFC init */
6226 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6227 if (val != 1) {
6228 BNX2X_ERR("CFC LL_INIT failed\n");
6229 return -EBUSY;
6230 }
6231 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6232 if (val != 1) {
6233 BNX2X_ERR("CFC AC_INIT failed\n");
6234 return -EBUSY;
6235 }
6236 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6237 if (val != 1) {
6238 BNX2X_ERR("CFC CAM_INIT failed\n");
6239 return -EBUSY;
6240 }
6241 REG_WR(bp, CFC_REG_DEBUG0, 0);
6242
6243 if (CHIP_IS_E1(bp)) {
6244 /* read NIG statistic
6245 to see if this is our first up since powerup */
6246 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6247 val = *bnx2x_sp(bp, wb_data[0]);
6248
6249 /* do internal memory self test */
6250 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6251 BNX2X_ERR("internal mem self test failed\n");
6252 return -EBUSY;
6253 }
6254 }
6255
6256 bnx2x_setup_fan_failure_detection(bp);
6257
6258 /* clear PXP2 attentions */
6259 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6260
6261 bnx2x_enable_blocks_attention(bp);
6262 bnx2x_enable_blocks_parity(bp);
6263
6264 if (!BP_NOMCP(bp)) {
6265 if (CHIP_IS_E1x(bp))
6266 bnx2x__common_init_phy(bp);
6267 } else
6268 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6269
6270 return 0;
6271 }
6272
6273 /**
6274 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6275 *
6276 * @bp: driver handle
6277 */
6278 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6279 {
6280 int rc = bnx2x_init_hw_common(bp);
6281
6282 if (rc)
6283 return rc;
6284
6285 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6286 if (!BP_NOMCP(bp))
6287 bnx2x__common_init_phy(bp);
6288
6289 return 0;
6290 }
6291
6292 static int bnx2x_init_hw_port(struct bnx2x *bp)
6293 {
6294 int port = BP_PORT(bp);
6295 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6296 u32 low, high;
6297 u32 val;
6298
6299 bnx2x__link_reset(bp);
6300
6301 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6302
6303 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6304
6305 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6306 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6307 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6308
6309 /* Timers bug workaround: disables the pf_master bit in pglue at
6310 * common phase, we need to enable it here before any dmae access are
6311 * attempted. Therefore we manually added the enable-master to the
6312 * port phase (it also happens in the function phase)
6313 */
6314 if (!CHIP_IS_E1x(bp))
6315 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6316
6317 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6318 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6319 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6320 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6321
6322 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6323 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6324 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6325 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6326
6327 /* QM cid (connection) count */
6328 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6329
6330 #ifdef BCM_CNIC
6331 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6332 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6333 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6334 #endif
6335
6336 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6337
6338 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6339 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6340
6341 if (IS_MF(bp))
6342 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6343 else if (bp->dev->mtu > 4096) {
6344 if (bp->flags & ONE_PORT_FLAG)
6345 low = 160;
6346 else {
6347 val = bp->dev->mtu;
6348 /* (24*1024 + val*4)/256 */
6349 low = 96 + (val/64) +
6350 ((val % 64) ? 1 : 0);
6351 }
6352 } else
6353 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6354 high = low + 56; /* 14*1024/256 */
6355 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6356 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6357 }
6358
6359 if (CHIP_MODE_IS_4_PORT(bp))
6360 REG_WR(bp, (BP_PORT(bp) ?
6361 BRB1_REG_MAC_GUARANTIED_1 :
6362 BRB1_REG_MAC_GUARANTIED_0), 40);
6363
6364
6365 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6366 if (CHIP_IS_E3B0(bp))
6367 /* Ovlan exists only if we are in multi-function +
6368 * switch-dependent mode, in switch-independent there
6369 * is no ovlan headers
6370 */
6371 REG_WR(bp, BP_PORT(bp) ?
6372 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6373 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6374 (bp->path_has_ovlan ? 7 : 6));
6375
6376 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6377 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6378 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6379 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6380
6381 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6382 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6383 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6384 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6385
6386 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6387 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6388
6389 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6390
6391 if (CHIP_IS_E1x(bp)) {
6392 /* configure PBF to work without PAUSE mtu 9000 */
6393 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6394
6395 /* update threshold */
6396 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6397 /* update init credit */
6398 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6399
6400 /* probe changes */
6401 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6402 udelay(50);
6403 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6404 }
6405
6406 #ifdef BCM_CNIC
6407 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6408 #endif
6409 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6410 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6411
6412 if (CHIP_IS_E1(bp)) {
6413 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6414 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6415 }
6416 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6417
6418 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6419
6420 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6421 /* init aeu_mask_attn_func_0/1:
6422 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6423 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6424 * bits 4-7 are used for "per vn group attention" */
6425 val = IS_MF(bp) ? 0xF7 : 0x7;
6426 /* Enable DCBX attention for all but E1 */
6427 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6428 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6429
6430 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6431
6432 if (!CHIP_IS_E1x(bp)) {
6433 /* Bit-map indicating which L2 hdrs may appear after the
6434 * basic Ethernet header
6435 */
6436 REG_WR(bp, BP_PORT(bp) ?
6437 NIG_REG_P1_HDRS_AFTER_BASIC :
6438 NIG_REG_P0_HDRS_AFTER_BASIC,
6439 IS_MF_SD(bp) ? 7 : 6);
6440
6441 if (CHIP_IS_E3(bp))
6442 REG_WR(bp, BP_PORT(bp) ?
6443 NIG_REG_LLH1_MF_MODE :
6444 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6445 }
6446 if (!CHIP_IS_E3(bp))
6447 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6448
6449 if (!CHIP_IS_E1(bp)) {
6450 /* 0x2 disable mf_ov, 0x1 enable */
6451 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6452 (IS_MF_SD(bp) ? 0x1 : 0x2));
6453
6454 if (!CHIP_IS_E1x(bp)) {
6455 val = 0;
6456 switch (bp->mf_mode) {
6457 case MULTI_FUNCTION_SD:
6458 val = 1;
6459 break;
6460 case MULTI_FUNCTION_SI:
6461 val = 2;
6462 break;
6463 }
6464
6465 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6466 NIG_REG_LLH0_CLS_TYPE), val);
6467 }
6468 {
6469 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6470 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6471 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6472 }
6473 }
6474
6475
6476 /* If SPIO5 is set to generate interrupts, enable it for this port */
6477 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6478 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6479 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6480 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6481 val = REG_RD(bp, reg_addr);
6482 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6483 REG_WR(bp, reg_addr, val);
6484 }
6485
6486 return 0;
6487 }
6488
6489 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6490 {
6491 int reg;
6492
6493 if (CHIP_IS_E1(bp))
6494 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6495 else
6496 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6497
6498 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6499 }
6500
6501 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6502 {
6503 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6504 }
6505
6506 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6507 {
6508 u32 i, base = FUNC_ILT_BASE(func);
6509 for (i = base; i < base + ILT_PER_FUNC; i++)
6510 bnx2x_ilt_wr(bp, i, 0);
6511 }
6512
6513 static int bnx2x_init_hw_func(struct bnx2x *bp)
6514 {
6515 int port = BP_PORT(bp);
6516 int func = BP_FUNC(bp);
6517 int init_phase = PHASE_PF0 + func;
6518 struct bnx2x_ilt *ilt = BP_ILT(bp);
6519 u16 cdu_ilt_start;
6520 u32 addr, val;
6521 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6522 int i, main_mem_width;
6523
6524 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6525
6526 /* FLR cleanup - hmmm */
6527 if (!CHIP_IS_E1x(bp))
6528 bnx2x_pf_flr_clnup(bp);
6529
6530 /* set MSI reconfigure capability */
6531 if (bp->common.int_block == INT_BLOCK_HC) {
6532 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6533 val = REG_RD(bp, addr);
6534 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6535 REG_WR(bp, addr, val);
6536 }
6537
6538 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6539 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6540
6541 ilt = BP_ILT(bp);
6542 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6543
6544 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6545 ilt->lines[cdu_ilt_start + i].page =
6546 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6547 ilt->lines[cdu_ilt_start + i].page_mapping =
6548 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6549 /* cdu ilt pages are allocated manually so there's no need to
6550 set the size */
6551 }
6552 bnx2x_ilt_init_op(bp, INITOP_SET);
6553
6554 #ifdef BCM_CNIC
6555 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6556
6557 /* T1 hash bits value determines the T1 number of entries */
6558 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6559 #endif
6560
6561 #ifndef BCM_CNIC
6562 /* set NIC mode */
6563 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6564 #endif /* BCM_CNIC */
6565
6566 if (!CHIP_IS_E1x(bp)) {
6567 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6568
6569 /* Turn on a single ISR mode in IGU if driver is going to use
6570 * INT#x or MSI
6571 */
6572 if (!(bp->flags & USING_MSIX_FLAG))
6573 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6574 /*
6575 * Timers workaround bug: function init part.
6576 * Need to wait 20msec after initializing ILT,
6577 * needed to make sure there are no requests in
6578 * one of the PXP internal queues with "old" ILT addresses
6579 */
6580 msleep(20);
6581 /*
6582 * Master enable - Due to WB DMAE writes performed before this
6583 * register is re-initialized as part of the regular function
6584 * init
6585 */
6586 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6587 /* Enable the function in IGU */
6588 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6589 }
6590
6591 bp->dmae_ready = 1;
6592
6593 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6594
6595 if (!CHIP_IS_E1x(bp))
6596 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6597
6598 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6599 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6600 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6601 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6602 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6603 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6604 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6605 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6606 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6607 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6608 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6609 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6610 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6611
6612 if (!CHIP_IS_E1x(bp))
6613 REG_WR(bp, QM_REG_PF_EN, 1);
6614
6615 if (!CHIP_IS_E1x(bp)) {
6616 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6617 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6618 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6619 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6620 }
6621 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6622
6623 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6624 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6625 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6626 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6627 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6628 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6629 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6630 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6631 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6632 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6633 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6634 if (!CHIP_IS_E1x(bp))
6635 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6636
6637 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6638
6639 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6640
6641 if (!CHIP_IS_E1x(bp))
6642 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6643
6644 if (IS_MF(bp)) {
6645 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6646 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6647 }
6648
6649 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6650
6651 /* HC init per function */
6652 if (bp->common.int_block == INT_BLOCK_HC) {
6653 if (CHIP_IS_E1H(bp)) {
6654 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6655
6656 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6657 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6658 }
6659 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6660
6661 } else {
6662 int num_segs, sb_idx, prod_offset;
6663
6664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6665
6666 if (!CHIP_IS_E1x(bp)) {
6667 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6668 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6669 }
6670
6671 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6672
6673 if (!CHIP_IS_E1x(bp)) {
6674 int dsb_idx = 0;
6675 /**
6676 * Producer memory:
6677 * E2 mode: address 0-135 match to the mapping memory;
6678 * 136 - PF0 default prod; 137 - PF1 default prod;
6679 * 138 - PF2 default prod; 139 - PF3 default prod;
6680 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6681 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6682 * 144-147 reserved.
6683 *
6684 * E1.5 mode - In backward compatible mode;
6685 * for non default SB; each even line in the memory
6686 * holds the U producer and each odd line hold
6687 * the C producer. The first 128 producers are for
6688 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6689 * producers are for the DSB for each PF.
6690 * Each PF has five segments: (the order inside each
6691 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6692 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6693 * 144-147 attn prods;
6694 */
6695 /* non-default-status-blocks */
6696 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6697 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6698 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6699 prod_offset = (bp->igu_base_sb + sb_idx) *
6700 num_segs;
6701
6702 for (i = 0; i < num_segs; i++) {
6703 addr = IGU_REG_PROD_CONS_MEMORY +
6704 (prod_offset + i) * 4;
6705 REG_WR(bp, addr, 0);
6706 }
6707 /* send consumer update with value 0 */
6708 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6709 USTORM_ID, 0, IGU_INT_NOP, 1);
6710 bnx2x_igu_clear_sb(bp,
6711 bp->igu_base_sb + sb_idx);
6712 }
6713
6714 /* default-status-blocks */
6715 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6716 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6717
6718 if (CHIP_MODE_IS_4_PORT(bp))
6719 dsb_idx = BP_FUNC(bp);
6720 else
6721 dsb_idx = BP_VN(bp);
6722
6723 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6724 IGU_BC_BASE_DSB_PROD + dsb_idx :
6725 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6726
6727 /*
6728 * igu prods come in chunks of E1HVN_MAX (4) -
6729 * does not matters what is the current chip mode
6730 */
6731 for (i = 0; i < (num_segs * E1HVN_MAX);
6732 i += E1HVN_MAX) {
6733 addr = IGU_REG_PROD_CONS_MEMORY +
6734 (prod_offset + i)*4;
6735 REG_WR(bp, addr, 0);
6736 }
6737 /* send consumer update with 0 */
6738 if (CHIP_INT_MODE_IS_BC(bp)) {
6739 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6740 USTORM_ID, 0, IGU_INT_NOP, 1);
6741 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6742 CSTORM_ID, 0, IGU_INT_NOP, 1);
6743 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6744 XSTORM_ID, 0, IGU_INT_NOP, 1);
6745 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6746 TSTORM_ID, 0, IGU_INT_NOP, 1);
6747 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6748 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6749 } else {
6750 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6751 USTORM_ID, 0, IGU_INT_NOP, 1);
6752 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6753 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6754 }
6755 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6756
6757 /* !!! these should become driver const once
6758 rf-tool supports split-68 const */
6759 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6760 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6761 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6762 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6763 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6764 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6765 }
6766 }
6767
6768 /* Reset PCIE errors for debug */
6769 REG_WR(bp, 0x2114, 0xffffffff);
6770 REG_WR(bp, 0x2120, 0xffffffff);
6771
6772 if (CHIP_IS_E1x(bp)) {
6773 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6774 main_mem_base = HC_REG_MAIN_MEMORY +
6775 BP_PORT(bp) * (main_mem_size * 4);
6776 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6777 main_mem_width = 8;
6778
6779 val = REG_RD(bp, main_mem_prty_clr);
6780 if (val)
6781 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6782 "block during "
6783 "function init (0x%x)!\n", val);
6784
6785 /* Clear "false" parity errors in MSI-X table */
6786 for (i = main_mem_base;
6787 i < main_mem_base + main_mem_size * 4;
6788 i += main_mem_width) {
6789 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6790 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6791 i, main_mem_width / 4);
6792 }
6793 /* Clear HC parity attention */
6794 REG_RD(bp, main_mem_prty_clr);
6795 }
6796
6797 #ifdef BNX2X_STOP_ON_ERROR
6798 /* Enable STORMs SP logging */
6799 REG_WR8(bp, BAR_USTRORM_INTMEM +
6800 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6801 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6802 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6803 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6804 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6805 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6806 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6807 #endif
6808
6809 bnx2x_phy_probe(&bp->link_params);
6810
6811 return 0;
6812 }
6813
6814
6815 void bnx2x_free_mem(struct bnx2x *bp)
6816 {
6817 /* fastpath */
6818 bnx2x_free_fp_mem(bp);
6819 /* end of fastpath */
6820
6821 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6822 sizeof(struct host_sp_status_block));
6823
6824 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6825 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6826
6827 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6828 sizeof(struct bnx2x_slowpath));
6829
6830 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6831 bp->context.size);
6832
6833 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6834
6835 BNX2X_FREE(bp->ilt->lines);
6836
6837 #ifdef BCM_CNIC
6838 if (!CHIP_IS_E1x(bp))
6839 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6840 sizeof(struct host_hc_status_block_e2));
6841 else
6842 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6843 sizeof(struct host_hc_status_block_e1x));
6844
6845 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6846 #endif
6847
6848 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6849
6850 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6851 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6852 }
6853
6854 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6855 {
6856 int num_groups;
6857
6858 /* number of eth_queues */
6859 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6860
6861 /* Total number of FW statistics requests =
6862 * 1 for port stats + 1 for PF stats + num_eth_queues */
6863 bp->fw_stats_num = 2 + num_queue_stats;
6864
6865
6866 /* Request is built from stats_query_header and an array of
6867 * stats_query_cmd_group each of which contains
6868 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6869 * configured in the stats_query_header.
6870 */
6871 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6872 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6873
6874 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6875 num_groups * sizeof(struct stats_query_cmd_group);
6876
6877 /* Data for statistics requests + stats_conter
6878 *
6879 * stats_counter holds per-STORM counters that are incremented
6880 * when STORM has finished with the current request.
6881 */
6882 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6883 sizeof(struct per_pf_stats) +
6884 sizeof(struct per_queue_stats) * num_queue_stats +
6885 sizeof(struct stats_counter);
6886
6887 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6888 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6889
6890 /* Set shortcuts */
6891 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6892 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6893
6894 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6895 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6896
6897 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6898 bp->fw_stats_req_sz;
6899 return 0;
6900
6901 alloc_mem_err:
6902 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6903 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6904 return -ENOMEM;
6905 }
6906
6907
6908 int bnx2x_alloc_mem(struct bnx2x *bp)
6909 {
6910 #ifdef BCM_CNIC
6911 if (!CHIP_IS_E1x(bp))
6912 /* size = the status block + ramrod buffers */
6913 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6914 sizeof(struct host_hc_status_block_e2));
6915 else
6916 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6917 sizeof(struct host_hc_status_block_e1x));
6918
6919 /* allocate searcher T2 table */
6920 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6921 #endif
6922
6923
6924 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6925 sizeof(struct host_sp_status_block));
6926
6927 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6928 sizeof(struct bnx2x_slowpath));
6929
6930 /* Allocated memory for FW statistics */
6931 if (bnx2x_alloc_fw_stats_mem(bp))
6932 goto alloc_mem_err;
6933
6934 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6935
6936 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6937 bp->context.size);
6938
6939 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6940
6941 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6942 goto alloc_mem_err;
6943
6944 /* Slow path ring */
6945 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6946
6947 /* EQ */
6948 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6949 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6950
6951
6952 /* fastpath */
6953 /* need to be done at the end, since it's self adjusting to amount
6954 * of memory available for RSS queues
6955 */
6956 if (bnx2x_alloc_fp_mem(bp))
6957 goto alloc_mem_err;
6958 return 0;
6959
6960 alloc_mem_err:
6961 bnx2x_free_mem(bp);
6962 return -ENOMEM;
6963 }
6964
6965 /*
6966 * Init service functions
6967 */
6968
6969 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6970 struct bnx2x_vlan_mac_obj *obj, bool set,
6971 int mac_type, unsigned long *ramrod_flags)
6972 {
6973 int rc;
6974 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6975
6976 memset(&ramrod_param, 0, sizeof(ramrod_param));
6977
6978 /* Fill general parameters */
6979 ramrod_param.vlan_mac_obj = obj;
6980 ramrod_param.ramrod_flags = *ramrod_flags;
6981
6982 /* Fill a user request section if needed */
6983 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6984 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6985
6986 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6987
6988 /* Set the command: ADD or DEL */
6989 if (set)
6990 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6991 else
6992 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6993 }
6994
6995 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6996 if (rc < 0)
6997 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6998 return rc;
6999 }
7000
7001 int bnx2x_del_all_macs(struct bnx2x *bp,
7002 struct bnx2x_vlan_mac_obj *mac_obj,
7003 int mac_type, bool wait_for_comp)
7004 {
7005 int rc;
7006 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7007
7008 /* Wait for completion of requested */
7009 if (wait_for_comp)
7010 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7011
7012 /* Set the mac type of addresses we want to clear */
7013 __set_bit(mac_type, &vlan_mac_flags);
7014
7015 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7016 if (rc < 0)
7017 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7018
7019 return rc;
7020 }
7021
7022 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7023 {
7024 unsigned long ramrod_flags = 0;
7025
7026 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7027
7028 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7029 /* Eth MAC is set on RSS leading client (fp[0]) */
7030 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7031 BNX2X_ETH_MAC, &ramrod_flags);
7032 }
7033
7034 int bnx2x_setup_leading(struct bnx2x *bp)
7035 {
7036 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7037 }
7038
7039 /**
7040 * bnx2x_set_int_mode - configure interrupt mode
7041 *
7042 * @bp: driver handle
7043 *
7044 * In case of MSI-X it will also try to enable MSI-X.
7045 */
7046 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7047 {
7048 switch (int_mode) {
7049 case INT_MODE_MSI:
7050 bnx2x_enable_msi(bp);
7051 /* falling through... */
7052 case INT_MODE_INTx:
7053 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7054 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7055 break;
7056 default:
7057 /* Set number of queues according to bp->multi_mode value */
7058 bnx2x_set_num_queues(bp);
7059
7060 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7061 bp->num_queues);
7062
7063 /* if we can't use MSI-X we only need one fp,
7064 * so try to enable MSI-X with the requested number of fp's
7065 * and fallback to MSI or legacy INTx with one fp
7066 */
7067 if (bnx2x_enable_msix(bp)) {
7068 /* failed to enable MSI-X */
7069 if (bp->multi_mode)
7070 DP(NETIF_MSG_IFUP,
7071 "Multi requested but failed to "
7072 "enable MSI-X (%d), "
7073 "set number of queues to %d\n",
7074 bp->num_queues,
7075 1 + NON_ETH_CONTEXT_USE);
7076 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7077
7078 /* Try to enable MSI */
7079 if (!(bp->flags & DISABLE_MSI_FLAG))
7080 bnx2x_enable_msi(bp);
7081 }
7082 break;
7083 }
7084 }
7085
7086 /* must be called prioir to any HW initializations */
7087 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7088 {
7089 return L2_ILT_LINES(bp);
7090 }
7091
7092 void bnx2x_ilt_set_info(struct bnx2x *bp)
7093 {
7094 struct ilt_client_info *ilt_client;
7095 struct bnx2x_ilt *ilt = BP_ILT(bp);
7096 u16 line = 0;
7097
7098 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7099 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7100
7101 /* CDU */
7102 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7103 ilt_client->client_num = ILT_CLIENT_CDU;
7104 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7105 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7106 ilt_client->start = line;
7107 line += bnx2x_cid_ilt_lines(bp);
7108 #ifdef BCM_CNIC
7109 line += CNIC_ILT_LINES;
7110 #endif
7111 ilt_client->end = line - 1;
7112
7113 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7114 "flags 0x%x, hw psz %d\n",
7115 ilt_client->start,
7116 ilt_client->end,
7117 ilt_client->page_size,
7118 ilt_client->flags,
7119 ilog2(ilt_client->page_size >> 12));
7120
7121 /* QM */
7122 if (QM_INIT(bp->qm_cid_count)) {
7123 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7124 ilt_client->client_num = ILT_CLIENT_QM;
7125 ilt_client->page_size = QM_ILT_PAGE_SZ;
7126 ilt_client->flags = 0;
7127 ilt_client->start = line;
7128
7129 /* 4 bytes for each cid */
7130 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7131 QM_ILT_PAGE_SZ);
7132
7133 ilt_client->end = line - 1;
7134
7135 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7136 "flags 0x%x, hw psz %d\n",
7137 ilt_client->start,
7138 ilt_client->end,
7139 ilt_client->page_size,
7140 ilt_client->flags,
7141 ilog2(ilt_client->page_size >> 12));
7142
7143 }
7144 /* SRC */
7145 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7146 #ifdef BCM_CNIC
7147 ilt_client->client_num = ILT_CLIENT_SRC;
7148 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7149 ilt_client->flags = 0;
7150 ilt_client->start = line;
7151 line += SRC_ILT_LINES;
7152 ilt_client->end = line - 1;
7153
7154 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7155 "flags 0x%x, hw psz %d\n",
7156 ilt_client->start,
7157 ilt_client->end,
7158 ilt_client->page_size,
7159 ilt_client->flags,
7160 ilog2(ilt_client->page_size >> 12));
7161
7162 #else
7163 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7164 #endif
7165
7166 /* TM */
7167 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7168 #ifdef BCM_CNIC
7169 ilt_client->client_num = ILT_CLIENT_TM;
7170 ilt_client->page_size = TM_ILT_PAGE_SZ;
7171 ilt_client->flags = 0;
7172 ilt_client->start = line;
7173 line += TM_ILT_LINES;
7174 ilt_client->end = line - 1;
7175
7176 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7177 "flags 0x%x, hw psz %d\n",
7178 ilt_client->start,
7179 ilt_client->end,
7180 ilt_client->page_size,
7181 ilt_client->flags,
7182 ilog2(ilt_client->page_size >> 12));
7183
7184 #else
7185 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7186 #endif
7187 BUG_ON(line > ILT_MAX_LINES);
7188 }
7189
7190 /**
7191 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7192 *
7193 * @bp: driver handle
7194 * @fp: pointer to fastpath
7195 * @init_params: pointer to parameters structure
7196 *
7197 * parameters configured:
7198 * - HC configuration
7199 * - Queue's CDU context
7200 */
7201 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7202 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7203 {
7204
7205 u8 cos;
7206 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7207 if (!IS_FCOE_FP(fp)) {
7208 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7209 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7210
7211 /* If HC is supporterd, enable host coalescing in the transition
7212 * to INIT state.
7213 */
7214 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7215 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7216
7217 /* HC rate */
7218 init_params->rx.hc_rate = bp->rx_ticks ?
7219 (1000000 / bp->rx_ticks) : 0;
7220 init_params->tx.hc_rate = bp->tx_ticks ?
7221 (1000000 / bp->tx_ticks) : 0;
7222
7223 /* FW SB ID */
7224 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7225 fp->fw_sb_id;
7226
7227 /*
7228 * CQ index among the SB indices: FCoE clients uses the default
7229 * SB, therefore it's different.
7230 */
7231 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7232 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7233 }
7234
7235 /* set maximum number of COSs supported by this queue */
7236 init_params->max_cos = fp->max_cos;
7237
7238 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
7239 fp->index, init_params->max_cos);
7240
7241 /* set the context pointers queue object */
7242 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7243 init_params->cxts[cos] =
7244 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7245 }
7246
7247 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7248 struct bnx2x_queue_state_params *q_params,
7249 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7250 int tx_index, bool leading)
7251 {
7252 memset(tx_only_params, 0, sizeof(*tx_only_params));
7253
7254 /* Set the command */
7255 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7256
7257 /* Set tx-only QUEUE flags: don't zero statistics */
7258 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7259
7260 /* choose the index of the cid to send the slow path on */
7261 tx_only_params->cid_index = tx_index;
7262
7263 /* Set general TX_ONLY_SETUP parameters */
7264 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7265
7266 /* Set Tx TX_ONLY_SETUP parameters */
7267 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7268
7269 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7270 "cos %d, primary cid %d, cid %d, "
7271 "client id %d, sp-client id %d, flags %lx\n",
7272 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7273 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7274 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7275
7276 /* send the ramrod */
7277 return bnx2x_queue_state_change(bp, q_params);
7278 }
7279
7280
7281 /**
7282 * bnx2x_setup_queue - setup queue
7283 *
7284 * @bp: driver handle
7285 * @fp: pointer to fastpath
7286 * @leading: is leading
7287 *
7288 * This function performs 2 steps in a Queue state machine
7289 * actually: 1) RESET->INIT 2) INIT->SETUP
7290 */
7291
7292 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7293 bool leading)
7294 {
7295 struct bnx2x_queue_state_params q_params = {0};
7296 struct bnx2x_queue_setup_params *setup_params =
7297 &q_params.params.setup;
7298 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7299 &q_params.params.tx_only;
7300 int rc;
7301 u8 tx_index;
7302
7303 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
7304
7305 /* reset IGU state skip FCoE L2 queue */
7306 if (!IS_FCOE_FP(fp))
7307 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7308 IGU_INT_ENABLE, 0);
7309
7310 q_params.q_obj = &fp->q_obj;
7311 /* We want to wait for completion in this context */
7312 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7313
7314 /* Prepare the INIT parameters */
7315 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7316
7317 /* Set the command */
7318 q_params.cmd = BNX2X_Q_CMD_INIT;
7319
7320 /* Change the state to INIT */
7321 rc = bnx2x_queue_state_change(bp, &q_params);
7322 if (rc) {
7323 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7324 return rc;
7325 }
7326
7327 DP(BNX2X_MSG_SP, "init complete\n");
7328
7329
7330 /* Now move the Queue to the SETUP state... */
7331 memset(setup_params, 0, sizeof(*setup_params));
7332
7333 /* Set QUEUE flags */
7334 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7335
7336 /* Set general SETUP parameters */
7337 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7338 FIRST_TX_COS_INDEX);
7339
7340 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7341 &setup_params->rxq_params);
7342
7343 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7344 FIRST_TX_COS_INDEX);
7345
7346 /* Set the command */
7347 q_params.cmd = BNX2X_Q_CMD_SETUP;
7348
7349 /* Change the state to SETUP */
7350 rc = bnx2x_queue_state_change(bp, &q_params);
7351 if (rc) {
7352 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7353 return rc;
7354 }
7355
7356 /* loop through the relevant tx-only indices */
7357 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7358 tx_index < fp->max_cos;
7359 tx_index++) {
7360
7361 /* prepare and send tx-only ramrod*/
7362 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7363 tx_only_params, tx_index, leading);
7364 if (rc) {
7365 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7366 fp->index, tx_index);
7367 return rc;
7368 }
7369 }
7370
7371 return rc;
7372 }
7373
7374 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7375 {
7376 struct bnx2x_fastpath *fp = &bp->fp[index];
7377 struct bnx2x_fp_txdata *txdata;
7378 struct bnx2x_queue_state_params q_params = {0};
7379 int rc, tx_index;
7380
7381 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
7382
7383 q_params.q_obj = &fp->q_obj;
7384 /* We want to wait for completion in this context */
7385 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7386
7387
7388 /* close tx-only connections */
7389 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7390 tx_index < fp->max_cos;
7391 tx_index++){
7392
7393 /* ascertain this is a normal queue*/
7394 txdata = &fp->txdata[tx_index];
7395
7396 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
7397 txdata->txq_index);
7398
7399 /* send halt terminate on tx-only connection */
7400 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7401 memset(&q_params.params.terminate, 0,
7402 sizeof(q_params.params.terminate));
7403 q_params.params.terminate.cid_index = tx_index;
7404
7405 rc = bnx2x_queue_state_change(bp, &q_params);
7406 if (rc)
7407 return rc;
7408
7409 /* send halt terminate on tx-only connection */
7410 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7411 memset(&q_params.params.cfc_del, 0,
7412 sizeof(q_params.params.cfc_del));
7413 q_params.params.cfc_del.cid_index = tx_index;
7414 rc = bnx2x_queue_state_change(bp, &q_params);
7415 if (rc)
7416 return rc;
7417 }
7418 /* Stop the primary connection: */
7419 /* ...halt the connection */
7420 q_params.cmd = BNX2X_Q_CMD_HALT;
7421 rc = bnx2x_queue_state_change(bp, &q_params);
7422 if (rc)
7423 return rc;
7424
7425 /* ...terminate the connection */
7426 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7427 memset(&q_params.params.terminate, 0,
7428 sizeof(q_params.params.terminate));
7429 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7430 rc = bnx2x_queue_state_change(bp, &q_params);
7431 if (rc)
7432 return rc;
7433 /* ...delete cfc entry */
7434 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7435 memset(&q_params.params.cfc_del, 0,
7436 sizeof(q_params.params.cfc_del));
7437 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7438 return bnx2x_queue_state_change(bp, &q_params);
7439 }
7440
7441
7442 static void bnx2x_reset_func(struct bnx2x *bp)
7443 {
7444 int port = BP_PORT(bp);
7445 int func = BP_FUNC(bp);
7446 int i;
7447
7448 /* Disable the function in the FW */
7449 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7450 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7451 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7452 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7453
7454 /* FP SBs */
7455 for_each_eth_queue(bp, i) {
7456 struct bnx2x_fastpath *fp = &bp->fp[i];
7457 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7458 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7459 SB_DISABLED);
7460 }
7461
7462 #ifdef BCM_CNIC
7463 /* CNIC SB */
7464 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7465 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7466 SB_DISABLED);
7467 #endif
7468 /* SP SB */
7469 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7470 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7471 SB_DISABLED);
7472
7473 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7474 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7475 0);
7476
7477 /* Configure IGU */
7478 if (bp->common.int_block == INT_BLOCK_HC) {
7479 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7480 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7481 } else {
7482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7483 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7484 }
7485
7486 #ifdef BCM_CNIC
7487 /* Disable Timer scan */
7488 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7489 /*
7490 * Wait for at least 10ms and up to 2 second for the timers scan to
7491 * complete
7492 */
7493 for (i = 0; i < 200; i++) {
7494 msleep(10);
7495 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7496 break;
7497 }
7498 #endif
7499 /* Clear ILT */
7500 bnx2x_clear_func_ilt(bp, func);
7501
7502 /* Timers workaround bug for E2: if this is vnic-3,
7503 * we need to set the entire ilt range for this timers.
7504 */
7505 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7506 struct ilt_client_info ilt_cli;
7507 /* use dummy TM client */
7508 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7509 ilt_cli.start = 0;
7510 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7511 ilt_cli.client_num = ILT_CLIENT_TM;
7512
7513 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7514 }
7515
7516 /* this assumes that reset_port() called before reset_func()*/
7517 if (!CHIP_IS_E1x(bp))
7518 bnx2x_pf_disable(bp);
7519
7520 bp->dmae_ready = 0;
7521 }
7522
7523 static void bnx2x_reset_port(struct bnx2x *bp)
7524 {
7525 int port = BP_PORT(bp);
7526 u32 val;
7527
7528 /* Reset physical Link */
7529 bnx2x__link_reset(bp);
7530
7531 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7532
7533 /* Do not rcv packets to BRB */
7534 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7535 /* Do not direct rcv packets that are not for MCP to the BRB */
7536 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7537 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7538
7539 /* Configure AEU */
7540 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7541
7542 msleep(100);
7543 /* Check for BRB port occupancy */
7544 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7545 if (val)
7546 DP(NETIF_MSG_IFDOWN,
7547 "BRB1 is not empty %d blocks are occupied\n", val);
7548
7549 /* TODO: Close Doorbell port? */
7550 }
7551
7552 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7553 {
7554 struct bnx2x_func_state_params func_params = {0};
7555
7556 /* Prepare parameters for function state transitions */
7557 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7558
7559 func_params.f_obj = &bp->func_obj;
7560 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7561
7562 func_params.params.hw_init.load_phase = load_code;
7563
7564 return bnx2x_func_state_change(bp, &func_params);
7565 }
7566
7567 static inline int bnx2x_func_stop(struct bnx2x *bp)
7568 {
7569 struct bnx2x_func_state_params func_params = {0};
7570 int rc;
7571
7572 /* Prepare parameters for function state transitions */
7573 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7574 func_params.f_obj = &bp->func_obj;
7575 func_params.cmd = BNX2X_F_CMD_STOP;
7576
7577 /*
7578 * Try to stop the function the 'good way'. If fails (in case
7579 * of a parity error during bnx2x_chip_cleanup()) and we are
7580 * not in a debug mode, perform a state transaction in order to
7581 * enable further HW_RESET transaction.
7582 */
7583 rc = bnx2x_func_state_change(bp, &func_params);
7584 if (rc) {
7585 #ifdef BNX2X_STOP_ON_ERROR
7586 return rc;
7587 #else
7588 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7589 "transaction\n");
7590 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7591 return bnx2x_func_state_change(bp, &func_params);
7592 #endif
7593 }
7594
7595 return 0;
7596 }
7597
7598 /**
7599 * bnx2x_send_unload_req - request unload mode from the MCP.
7600 *
7601 * @bp: driver handle
7602 * @unload_mode: requested function's unload mode
7603 *
7604 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7605 */
7606 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7607 {
7608 u32 reset_code = 0;
7609 int port = BP_PORT(bp);
7610
7611 /* Select the UNLOAD request mode */
7612 if (unload_mode == UNLOAD_NORMAL)
7613 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7614
7615 else if (bp->flags & NO_WOL_FLAG)
7616 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7617
7618 else if (bp->wol) {
7619 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7620 u8 *mac_addr = bp->dev->dev_addr;
7621 u32 val;
7622 /* The mac address is written to entries 1-4 to
7623 preserve entry 0 which is used by the PMF */
7624 u8 entry = (BP_VN(bp) + 1)*8;
7625
7626 val = (mac_addr[0] << 8) | mac_addr[1];
7627 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7628
7629 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7630 (mac_addr[4] << 8) | mac_addr[5];
7631 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7632
7633 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7634
7635 } else
7636 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7637
7638 /* Send the request to the MCP */
7639 if (!BP_NOMCP(bp))
7640 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7641 else {
7642 int path = BP_PATH(bp);
7643
7644 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7645 "%d, %d, %d\n",
7646 path, load_count[path][0], load_count[path][1],
7647 load_count[path][2]);
7648 load_count[path][0]--;
7649 load_count[path][1 + port]--;
7650 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7651 "%d, %d, %d\n",
7652 path, load_count[path][0], load_count[path][1],
7653 load_count[path][2]);
7654 if (load_count[path][0] == 0)
7655 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7656 else if (load_count[path][1 + port] == 0)
7657 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7658 else
7659 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7660 }
7661
7662 return reset_code;
7663 }
7664
7665 /**
7666 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7667 *
7668 * @bp: driver handle
7669 */
7670 void bnx2x_send_unload_done(struct bnx2x *bp)
7671 {
7672 /* Report UNLOAD_DONE to MCP */
7673 if (!BP_NOMCP(bp))
7674 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7675 }
7676
7677 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7678 {
7679 int tout = 50;
7680 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7681
7682 if (!bp->port.pmf)
7683 return 0;
7684
7685 /*
7686 * (assumption: No Attention from MCP at this stage)
7687 * PMF probably in the middle of TXdisable/enable transaction
7688 * 1. Sync IRS for default SB
7689 * 2. Sync SP queue - this guarantes us that attention handling started
7690 * 3. Wait, that TXdisable/enable transaction completes
7691 *
7692 * 1+2 guranty that if DCBx attention was scheduled it already changed
7693 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7694 * received complettion for the transaction the state is TX_STOPPED.
7695 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7696 * transaction.
7697 */
7698
7699 /* make sure default SB ISR is done */
7700 if (msix)
7701 synchronize_irq(bp->msix_table[0].vector);
7702 else
7703 synchronize_irq(bp->pdev->irq);
7704
7705 flush_workqueue(bnx2x_wq);
7706
7707 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7708 BNX2X_F_STATE_STARTED && tout--)
7709 msleep(20);
7710
7711 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7712 BNX2X_F_STATE_STARTED) {
7713 #ifdef BNX2X_STOP_ON_ERROR
7714 return -EBUSY;
7715 #else
7716 /*
7717 * Failed to complete the transaction in a "good way"
7718 * Force both transactions with CLR bit
7719 */
7720 struct bnx2x_func_state_params func_params = {0};
7721
7722 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7723 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7724
7725 func_params.f_obj = &bp->func_obj;
7726 __set_bit(RAMROD_DRV_CLR_ONLY,
7727 &func_params.ramrod_flags);
7728
7729 /* STARTED-->TX_ST0PPED */
7730 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7731 bnx2x_func_state_change(bp, &func_params);
7732
7733 /* TX_ST0PPED-->STARTED */
7734 func_params.cmd = BNX2X_F_CMD_TX_START;
7735 return bnx2x_func_state_change(bp, &func_params);
7736 #endif
7737 }
7738
7739 return 0;
7740 }
7741
7742 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7743 {
7744 int port = BP_PORT(bp);
7745 int i, rc = 0;
7746 u8 cos;
7747 struct bnx2x_mcast_ramrod_params rparam = {0};
7748 u32 reset_code;
7749
7750 /* Wait until tx fastpath tasks complete */
7751 for_each_tx_queue(bp, i) {
7752 struct bnx2x_fastpath *fp = &bp->fp[i];
7753
7754 for_each_cos_in_tx_queue(fp, cos)
7755 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7756 #ifdef BNX2X_STOP_ON_ERROR
7757 if (rc)
7758 return;
7759 #endif
7760 }
7761
7762 /* Give HW time to discard old tx messages */
7763 usleep_range(1000, 1000);
7764
7765 /* Clean all ETH MACs */
7766 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7767 if (rc < 0)
7768 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7769
7770 /* Clean up UC list */
7771 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7772 true);
7773 if (rc < 0)
7774 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7775 "%d\n", rc);
7776
7777 /* Disable LLH */
7778 if (!CHIP_IS_E1(bp))
7779 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7780
7781 /* Set "drop all" (stop Rx).
7782 * We need to take a netif_addr_lock() here in order to prevent
7783 * a race between the completion code and this code.
7784 */
7785 netif_addr_lock_bh(bp->dev);
7786 /* Schedule the rx_mode command */
7787 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7788 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7789 else
7790 bnx2x_set_storm_rx_mode(bp);
7791
7792 /* Cleanup multicast configuration */
7793 rparam.mcast_obj = &bp->mcast_obj;
7794 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7795 if (rc < 0)
7796 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7797
7798 netif_addr_unlock_bh(bp->dev);
7799
7800
7801
7802 /*
7803 * Send the UNLOAD_REQUEST to the MCP. This will return if
7804 * this function should perform FUNC, PORT or COMMON HW
7805 * reset.
7806 */
7807 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7808
7809 /*
7810 * (assumption: No Attention from MCP at this stage)
7811 * PMF probably in the middle of TXdisable/enable transaction
7812 */
7813 rc = bnx2x_func_wait_started(bp);
7814 if (rc) {
7815 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7816 #ifdef BNX2X_STOP_ON_ERROR
7817 return;
7818 #endif
7819 }
7820
7821 /* Close multi and leading connections
7822 * Completions for ramrods are collected in a synchronous way
7823 */
7824 for_each_queue(bp, i)
7825 if (bnx2x_stop_queue(bp, i))
7826 #ifdef BNX2X_STOP_ON_ERROR
7827 return;
7828 #else
7829 goto unload_error;
7830 #endif
7831 /* If SP settings didn't get completed so far - something
7832 * very wrong has happen.
7833 */
7834 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7835 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7836
7837 #ifndef BNX2X_STOP_ON_ERROR
7838 unload_error:
7839 #endif
7840 rc = bnx2x_func_stop(bp);
7841 if (rc) {
7842 BNX2X_ERR("Function stop failed!\n");
7843 #ifdef BNX2X_STOP_ON_ERROR
7844 return;
7845 #endif
7846 }
7847
7848 /* Disable HW interrupts, NAPI */
7849 bnx2x_netif_stop(bp, 1);
7850
7851 /* Release IRQs */
7852 bnx2x_free_irq(bp);
7853
7854 /* Reset the chip */
7855 rc = bnx2x_reset_hw(bp, reset_code);
7856 if (rc)
7857 BNX2X_ERR("HW_RESET failed\n");
7858
7859
7860 /* Report UNLOAD_DONE to MCP */
7861 bnx2x_send_unload_done(bp);
7862 }
7863
7864 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7865 {
7866 u32 val;
7867
7868 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7869
7870 if (CHIP_IS_E1(bp)) {
7871 int port = BP_PORT(bp);
7872 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7873 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7874
7875 val = REG_RD(bp, addr);
7876 val &= ~(0x300);
7877 REG_WR(bp, addr, val);
7878 } else {
7879 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7880 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7881 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7882 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7883 }
7884 }
7885
7886 /* Close gates #2, #3 and #4: */
7887 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7888 {
7889 u32 val;
7890
7891 /* Gates #2 and #4a are closed/opened for "not E1" only */
7892 if (!CHIP_IS_E1(bp)) {
7893 /* #4 */
7894 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7895 /* #2 */
7896 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7897 }
7898
7899 /* #3 */
7900 if (CHIP_IS_E1x(bp)) {
7901 /* Prevent interrupts from HC on both ports */
7902 val = REG_RD(bp, HC_REG_CONFIG_1);
7903 REG_WR(bp, HC_REG_CONFIG_1,
7904 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7905 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7906
7907 val = REG_RD(bp, HC_REG_CONFIG_0);
7908 REG_WR(bp, HC_REG_CONFIG_0,
7909 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7910 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7911 } else {
7912 /* Prevent incomming interrupts in IGU */
7913 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7914
7915 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7916 (!close) ?
7917 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7918 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7919 }
7920
7921 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7922 close ? "closing" : "opening");
7923 mmiowb();
7924 }
7925
7926 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7927
7928 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7929 {
7930 /* Do some magic... */
7931 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7932 *magic_val = val & SHARED_MF_CLP_MAGIC;
7933 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7934 }
7935
7936 /**
7937 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7938 *
7939 * @bp: driver handle
7940 * @magic_val: old value of the `magic' bit.
7941 */
7942 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7943 {
7944 /* Restore the `magic' bit value... */
7945 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7946 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7947 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7948 }
7949
7950 /**
7951 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7952 *
7953 * @bp: driver handle
7954 * @magic_val: old value of 'magic' bit.
7955 *
7956 * Takes care of CLP configurations.
7957 */
7958 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7959 {
7960 u32 shmem;
7961 u32 validity_offset;
7962
7963 DP(NETIF_MSG_HW, "Starting\n");
7964
7965 /* Set `magic' bit in order to save MF config */
7966 if (!CHIP_IS_E1(bp))
7967 bnx2x_clp_reset_prep(bp, magic_val);
7968
7969 /* Get shmem offset */
7970 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7971 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7972
7973 /* Clear validity map flags */
7974 if (shmem > 0)
7975 REG_WR(bp, shmem + validity_offset, 0);
7976 }
7977
7978 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7979 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7980
7981 /**
7982 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7983 *
7984 * @bp: driver handle
7985 */
7986 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7987 {
7988 /* special handling for emulation and FPGA,
7989 wait 10 times longer */
7990 if (CHIP_REV_IS_SLOW(bp))
7991 msleep(MCP_ONE_TIMEOUT*10);
7992 else
7993 msleep(MCP_ONE_TIMEOUT);
7994 }
7995
7996 /*
7997 * initializes bp->common.shmem_base and waits for validity signature to appear
7998 */
7999 static int bnx2x_init_shmem(struct bnx2x *bp)
8000 {
8001 int cnt = 0;
8002 u32 val = 0;
8003
8004 do {
8005 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8006 if (bp->common.shmem_base) {
8007 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8008 if (val & SHR_MEM_VALIDITY_MB)
8009 return 0;
8010 }
8011
8012 bnx2x_mcp_wait_one(bp);
8013
8014 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8015
8016 BNX2X_ERR("BAD MCP validity signature\n");
8017
8018 return -ENODEV;
8019 }
8020
8021 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8022 {
8023 int rc = bnx2x_init_shmem(bp);
8024
8025 /* Restore the `magic' bit value */
8026 if (!CHIP_IS_E1(bp))
8027 bnx2x_clp_reset_done(bp, magic_val);
8028
8029 return rc;
8030 }
8031
8032 static void bnx2x_pxp_prep(struct bnx2x *bp)
8033 {
8034 if (!CHIP_IS_E1(bp)) {
8035 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8036 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8037 mmiowb();
8038 }
8039 }
8040
8041 /*
8042 * Reset the whole chip except for:
8043 * - PCIE core
8044 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8045 * one reset bit)
8046 * - IGU
8047 * - MISC (including AEU)
8048 * - GRC
8049 * - RBCN, RBCP
8050 */
8051 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8052 {
8053 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8054 u32 global_bits2, stay_reset2;
8055
8056 /*
8057 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8058 * (per chip) blocks.
8059 */
8060 global_bits2 =
8061 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8062 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8063
8064 /* Don't reset the following blocks */
8065 not_reset_mask1 =
8066 MISC_REGISTERS_RESET_REG_1_RST_HC |
8067 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8068 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8069
8070 not_reset_mask2 =
8071 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8072 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8073 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8074 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8075 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8076 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8077 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8078 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8079 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8080 MISC_REGISTERS_RESET_REG_2_PGLC;
8081
8082 /*
8083 * Keep the following blocks in reset:
8084 * - all xxMACs are handled by the bnx2x_link code.
8085 */
8086 stay_reset2 =
8087 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8088 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8089 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8090 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8091 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8092 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8093 MISC_REGISTERS_RESET_REG_2_XMAC |
8094 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8095
8096 /* Full reset masks according to the chip */
8097 reset_mask1 = 0xffffffff;
8098
8099 if (CHIP_IS_E1(bp))
8100 reset_mask2 = 0xffff;
8101 else if (CHIP_IS_E1H(bp))
8102 reset_mask2 = 0x1ffff;
8103 else if (CHIP_IS_E2(bp))
8104 reset_mask2 = 0xfffff;
8105 else /* CHIP_IS_E3 */
8106 reset_mask2 = 0x3ffffff;
8107
8108 /* Don't reset global blocks unless we need to */
8109 if (!global)
8110 reset_mask2 &= ~global_bits2;
8111
8112 /*
8113 * In case of attention in the QM, we need to reset PXP
8114 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8115 * because otherwise QM reset would release 'close the gates' shortly
8116 * before resetting the PXP, then the PSWRQ would send a write
8117 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8118 * read the payload data from PSWWR, but PSWWR would not
8119 * respond. The write queue in PGLUE would stuck, dmae commands
8120 * would not return. Therefore it's important to reset the second
8121 * reset register (containing the
8122 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8123 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8124 * bit).
8125 */
8126 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8127 reset_mask2 & (~not_reset_mask2));
8128
8129 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8130 reset_mask1 & (~not_reset_mask1));
8131
8132 barrier();
8133 mmiowb();
8134
8135 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8136 reset_mask2 & (~stay_reset2));
8137
8138 barrier();
8139 mmiowb();
8140
8141 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8142 mmiowb();
8143 }
8144
8145 /**
8146 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8147 * It should get cleared in no more than 1s.
8148 *
8149 * @bp: driver handle
8150 *
8151 * It should get cleared in no more than 1s. Returns 0 if
8152 * pending writes bit gets cleared.
8153 */
8154 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8155 {
8156 u32 cnt = 1000;
8157 u32 pend_bits = 0;
8158
8159 do {
8160 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8161
8162 if (pend_bits == 0)
8163 break;
8164
8165 usleep_range(1000, 1000);
8166 } while (cnt-- > 0);
8167
8168 if (cnt <= 0) {
8169 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8170 pend_bits);
8171 return -EBUSY;
8172 }
8173
8174 return 0;
8175 }
8176
8177 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8178 {
8179 int cnt = 1000;
8180 u32 val = 0;
8181 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8182
8183
8184 /* Empty the Tetris buffer, wait for 1s */
8185 do {
8186 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8187 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8188 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8189 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8190 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8191 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8192 ((port_is_idle_0 & 0x1) == 0x1) &&
8193 ((port_is_idle_1 & 0x1) == 0x1) &&
8194 (pgl_exp_rom2 == 0xffffffff))
8195 break;
8196 usleep_range(1000, 1000);
8197 } while (cnt-- > 0);
8198
8199 if (cnt <= 0) {
8200 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8201 " are still"
8202 " outstanding read requests after 1s!\n");
8203 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8204 " port_is_idle_0=0x%08x,"
8205 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8206 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8207 pgl_exp_rom2);
8208 return -EAGAIN;
8209 }
8210
8211 barrier();
8212
8213 /* Close gates #2, #3 and #4 */
8214 bnx2x_set_234_gates(bp, true);
8215
8216 /* Poll for IGU VQs for 57712 and newer chips */
8217 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8218 return -EAGAIN;
8219
8220
8221 /* TBD: Indicate that "process kill" is in progress to MCP */
8222
8223 /* Clear "unprepared" bit */
8224 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8225 barrier();
8226
8227 /* Make sure all is written to the chip before the reset */
8228 mmiowb();
8229
8230 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8231 * PSWHST, GRC and PSWRD Tetris buffer.
8232 */
8233 usleep_range(1000, 1000);
8234
8235 /* Prepare to chip reset: */
8236 /* MCP */
8237 if (global)
8238 bnx2x_reset_mcp_prep(bp, &val);
8239
8240 /* PXP */
8241 bnx2x_pxp_prep(bp);
8242 barrier();
8243
8244 /* reset the chip */
8245 bnx2x_process_kill_chip_reset(bp, global);
8246 barrier();
8247
8248 /* Recover after reset: */
8249 /* MCP */
8250 if (global && bnx2x_reset_mcp_comp(bp, val))
8251 return -EAGAIN;
8252
8253 /* TBD: Add resetting the NO_MCP mode DB here */
8254
8255 /* PXP */
8256 bnx2x_pxp_prep(bp);
8257
8258 /* Open the gates #2, #3 and #4 */
8259 bnx2x_set_234_gates(bp, false);
8260
8261 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8262 * reset state, re-enable attentions. */
8263
8264 return 0;
8265 }
8266
8267 int bnx2x_leader_reset(struct bnx2x *bp)
8268 {
8269 int rc = 0;
8270 bool global = bnx2x_reset_is_global(bp);
8271
8272 /* Try to recover after the failure */
8273 if (bnx2x_process_kill(bp, global)) {
8274 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8275 "Aii!\n", BP_PATH(bp));
8276 rc = -EAGAIN;
8277 goto exit_leader_reset;
8278 }
8279
8280 /*
8281 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8282 * state.
8283 */
8284 bnx2x_set_reset_done(bp);
8285 if (global)
8286 bnx2x_clear_reset_global(bp);
8287
8288 exit_leader_reset:
8289 bp->is_leader = 0;
8290 bnx2x_release_leader_lock(bp);
8291 smp_mb();
8292 return rc;
8293 }
8294
8295 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8296 {
8297 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8298
8299 /* Disconnect this device */
8300 netif_device_detach(bp->dev);
8301
8302 /*
8303 * Block ifup for all function on this engine until "process kill"
8304 * or power cycle.
8305 */
8306 bnx2x_set_reset_in_progress(bp);
8307
8308 /* Shut down the power */
8309 bnx2x_set_power_state(bp, PCI_D3hot);
8310
8311 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8312
8313 smp_mb();
8314 }
8315
8316 /*
8317 * Assumption: runs under rtnl lock. This together with the fact
8318 * that it's called only from bnx2x_sp_rtnl() ensure that it
8319 * will never be called when netif_running(bp->dev) is false.
8320 */
8321 static void bnx2x_parity_recover(struct bnx2x *bp)
8322 {
8323 bool global = false;
8324
8325 DP(NETIF_MSG_HW, "Handling parity\n");
8326 while (1) {
8327 switch (bp->recovery_state) {
8328 case BNX2X_RECOVERY_INIT:
8329 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8330 bnx2x_chk_parity_attn(bp, &global, false);
8331
8332 /* Try to get a LEADER_LOCK HW lock */
8333 if (bnx2x_trylock_leader_lock(bp)) {
8334 bnx2x_set_reset_in_progress(bp);
8335 /*
8336 * Check if there is a global attention and if
8337 * there was a global attention, set the global
8338 * reset bit.
8339 */
8340
8341 if (global)
8342 bnx2x_set_reset_global(bp);
8343
8344 bp->is_leader = 1;
8345 }
8346
8347 /* Stop the driver */
8348 /* If interface has been removed - break */
8349 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8350 return;
8351
8352 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8353
8354 /*
8355 * Reset MCP command sequence number and MCP mail box
8356 * sequence as we are going to reset the MCP.
8357 */
8358 if (global) {
8359 bp->fw_seq = 0;
8360 bp->fw_drv_pulse_wr_seq = 0;
8361 }
8362
8363 /* Ensure "is_leader", MCP command sequence and
8364 * "recovery_state" update values are seen on other
8365 * CPUs.
8366 */
8367 smp_mb();
8368 break;
8369
8370 case BNX2X_RECOVERY_WAIT:
8371 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8372 if (bp->is_leader) {
8373 int other_engine = BP_PATH(bp) ? 0 : 1;
8374 u32 other_load_counter =
8375 bnx2x_get_load_cnt(bp, other_engine);
8376 u32 load_counter =
8377 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8378 global = bnx2x_reset_is_global(bp);
8379
8380 /*
8381 * In case of a parity in a global block, let
8382 * the first leader that performs a
8383 * leader_reset() reset the global blocks in
8384 * order to clear global attentions. Otherwise
8385 * the the gates will remain closed for that
8386 * engine.
8387 */
8388 if (load_counter ||
8389 (global && other_load_counter)) {
8390 /* Wait until all other functions get
8391 * down.
8392 */
8393 schedule_delayed_work(&bp->sp_rtnl_task,
8394 HZ/10);
8395 return;
8396 } else {
8397 /* If all other functions got down -
8398 * try to bring the chip back to
8399 * normal. In any case it's an exit
8400 * point for a leader.
8401 */
8402 if (bnx2x_leader_reset(bp)) {
8403 bnx2x_recovery_failed(bp);
8404 return;
8405 }
8406
8407 /* If we are here, means that the
8408 * leader has succeeded and doesn't
8409 * want to be a leader any more. Try
8410 * to continue as a none-leader.
8411 */
8412 break;
8413 }
8414 } else { /* non-leader */
8415 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8416 /* Try to get a LEADER_LOCK HW lock as
8417 * long as a former leader may have
8418 * been unloaded by the user or
8419 * released a leadership by another
8420 * reason.
8421 */
8422 if (bnx2x_trylock_leader_lock(bp)) {
8423 /* I'm a leader now! Restart a
8424 * switch case.
8425 */
8426 bp->is_leader = 1;
8427 break;
8428 }
8429
8430 schedule_delayed_work(&bp->sp_rtnl_task,
8431 HZ/10);
8432 return;
8433
8434 } else {
8435 /*
8436 * If there was a global attention, wait
8437 * for it to be cleared.
8438 */
8439 if (bnx2x_reset_is_global(bp)) {
8440 schedule_delayed_work(
8441 &bp->sp_rtnl_task,
8442 HZ/10);
8443 return;
8444 }
8445
8446 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8447 bnx2x_recovery_failed(bp);
8448 else {
8449 bp->recovery_state =
8450 BNX2X_RECOVERY_DONE;
8451 smp_mb();
8452 }
8453
8454 return;
8455 }
8456 }
8457 default:
8458 return;
8459 }
8460 }
8461 }
8462
8463 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8464 * scheduled on a general queue in order to prevent a dead lock.
8465 */
8466 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8467 {
8468 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8469
8470 rtnl_lock();
8471
8472 if (!netif_running(bp->dev))
8473 goto sp_rtnl_exit;
8474
8475 /* if stop on error is defined no recovery flows should be executed */
8476 #ifdef BNX2X_STOP_ON_ERROR
8477 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8478 "so reset not done to allow debug dump,\n"
8479 "you will need to reboot when done\n");
8480 goto sp_rtnl_not_reset;
8481 #endif
8482
8483 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8484 /*
8485 * Clear all pending SP commands as we are going to reset the
8486 * function anyway.
8487 */
8488 bp->sp_rtnl_state = 0;
8489 smp_mb();
8490
8491 bnx2x_parity_recover(bp);
8492
8493 goto sp_rtnl_exit;
8494 }
8495
8496 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8497 /*
8498 * Clear all pending SP commands as we are going to reset the
8499 * function anyway.
8500 */
8501 bp->sp_rtnl_state = 0;
8502 smp_mb();
8503
8504 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8505 bnx2x_nic_load(bp, LOAD_NORMAL);
8506
8507 goto sp_rtnl_exit;
8508 }
8509 #ifdef BNX2X_STOP_ON_ERROR
8510 sp_rtnl_not_reset:
8511 #endif
8512 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8513 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8514
8515 sp_rtnl_exit:
8516 rtnl_unlock();
8517 }
8518
8519 /* end of nic load/unload */
8520
8521 static void bnx2x_period_task(struct work_struct *work)
8522 {
8523 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8524
8525 if (!netif_running(bp->dev))
8526 goto period_task_exit;
8527
8528 if (CHIP_REV_IS_SLOW(bp)) {
8529 BNX2X_ERR("period task called on emulation, ignoring\n");
8530 goto period_task_exit;
8531 }
8532
8533 bnx2x_acquire_phy_lock(bp);
8534 /*
8535 * The barrier is needed to ensure the ordering between the writing to
8536 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8537 * the reading here.
8538 */
8539 smp_mb();
8540 if (bp->port.pmf) {
8541 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8542
8543 /* Re-queue task in 1 sec */
8544 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8545 }
8546
8547 bnx2x_release_phy_lock(bp);
8548 period_task_exit:
8549 return;
8550 }
8551
8552 /*
8553 * Init service functions
8554 */
8555
8556 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8557 {
8558 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8559 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8560 return base + (BP_ABS_FUNC(bp)) * stride;
8561 }
8562
8563 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8564 {
8565 u32 reg = bnx2x_get_pretend_reg(bp);
8566
8567 /* Flush all outstanding writes */
8568 mmiowb();
8569
8570 /* Pretend to be function 0 */
8571 REG_WR(bp, reg, 0);
8572 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8573
8574 /* From now we are in the "like-E1" mode */
8575 bnx2x_int_disable(bp);
8576
8577 /* Flush all outstanding writes */
8578 mmiowb();
8579
8580 /* Restore the original function */
8581 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8582 REG_RD(bp, reg);
8583 }
8584
8585 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8586 {
8587 if (CHIP_IS_E1(bp))
8588 bnx2x_int_disable(bp);
8589 else
8590 bnx2x_undi_int_disable_e1h(bp);
8591 }
8592
8593 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8594 {
8595 u32 val;
8596
8597 /* Check if there is any driver already loaded */
8598 val = REG_RD(bp, MISC_REG_UNPREPARED);
8599 if (val == 0x1) {
8600
8601 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8602 /*
8603 * Check if it is the UNDI driver
8604 * UNDI driver initializes CID offset for normal bell to 0x7
8605 */
8606 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8607 if (val == 0x7) {
8608 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8609 /* save our pf_num */
8610 int orig_pf_num = bp->pf_num;
8611 int port;
8612 u32 swap_en, swap_val, value;
8613
8614 /* clear the UNDI indication */
8615 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8616
8617 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8618
8619 /* try unload UNDI on port 0 */
8620 bp->pf_num = 0;
8621 bp->fw_seq =
8622 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8623 DRV_MSG_SEQ_NUMBER_MASK);
8624 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8625
8626 /* if UNDI is loaded on the other port */
8627 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8628
8629 /* send "DONE" for previous unload */
8630 bnx2x_fw_command(bp,
8631 DRV_MSG_CODE_UNLOAD_DONE, 0);
8632
8633 /* unload UNDI on port 1 */
8634 bp->pf_num = 1;
8635 bp->fw_seq =
8636 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8637 DRV_MSG_SEQ_NUMBER_MASK);
8638 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8639
8640 bnx2x_fw_command(bp, reset_code, 0);
8641 }
8642
8643 bnx2x_undi_int_disable(bp);
8644 port = BP_PORT(bp);
8645
8646 /* close input traffic and wait for it */
8647 /* Do not rcv packets to BRB */
8648 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8649 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8650 /* Do not direct rcv packets that are not for MCP to
8651 * the BRB */
8652 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8653 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8654 /* clear AEU */
8655 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8656 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8657 msleep(10);
8658
8659 /* save NIG port swap info */
8660 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8661 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8662 /* reset device */
8663 REG_WR(bp,
8664 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8665 0xd3ffffff);
8666
8667 value = 0x1400;
8668 if (CHIP_IS_E3(bp)) {
8669 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8670 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8671 }
8672
8673 REG_WR(bp,
8674 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8675 value);
8676
8677 /* take the NIG out of reset and restore swap values */
8678 REG_WR(bp,
8679 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8680 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8681 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8682 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8683
8684 /* send unload done to the MCP */
8685 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8686
8687 /* restore our func and fw_seq */
8688 bp->pf_num = orig_pf_num;
8689 bp->fw_seq =
8690 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8691 DRV_MSG_SEQ_NUMBER_MASK);
8692 }
8693
8694 /* now it's safe to release the lock */
8695 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8696 }
8697 }
8698
8699 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8700 {
8701 u32 val, val2, val3, val4, id;
8702 u16 pmc;
8703
8704 /* Get the chip revision id and number. */
8705 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8706 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8707 id = ((val & 0xffff) << 16);
8708 val = REG_RD(bp, MISC_REG_CHIP_REV);
8709 id |= ((val & 0xf) << 12);
8710 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8711 id |= ((val & 0xff) << 4);
8712 val = REG_RD(bp, MISC_REG_BOND_ID);
8713 id |= (val & 0xf);
8714 bp->common.chip_id = id;
8715
8716 /* Set doorbell size */
8717 bp->db_size = (1 << BNX2X_DB_SHIFT);
8718
8719 if (!CHIP_IS_E1x(bp)) {
8720 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8721 if ((val & 1) == 0)
8722 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8723 else
8724 val = (val >> 1) & 1;
8725 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8726 "2_PORT_MODE");
8727 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8728 CHIP_2_PORT_MODE;
8729
8730 if (CHIP_MODE_IS_4_PORT(bp))
8731 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8732 else
8733 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8734 } else {
8735 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8736 bp->pfid = bp->pf_num; /* 0..7 */
8737 }
8738
8739 bp->link_params.chip_id = bp->common.chip_id;
8740 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8741
8742 val = (REG_RD(bp, 0x2874) & 0x55);
8743 if ((bp->common.chip_id & 0x1) ||
8744 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8745 bp->flags |= ONE_PORT_FLAG;
8746 BNX2X_DEV_INFO("single port device\n");
8747 }
8748
8749 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8750 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8751 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8752 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8753 bp->common.flash_size, bp->common.flash_size);
8754
8755 bnx2x_init_shmem(bp);
8756
8757
8758
8759 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8760 MISC_REG_GENERIC_CR_1 :
8761 MISC_REG_GENERIC_CR_0));
8762
8763 bp->link_params.shmem_base = bp->common.shmem_base;
8764 bp->link_params.shmem2_base = bp->common.shmem2_base;
8765 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8766 bp->common.shmem_base, bp->common.shmem2_base);
8767
8768 if (!bp->common.shmem_base) {
8769 BNX2X_DEV_INFO("MCP not active\n");
8770 bp->flags |= NO_MCP_FLAG;
8771 return;
8772 }
8773
8774 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8775 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8776
8777 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8778 SHARED_HW_CFG_LED_MODE_MASK) >>
8779 SHARED_HW_CFG_LED_MODE_SHIFT);
8780
8781 bp->link_params.feature_config_flags = 0;
8782 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8783 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8784 bp->link_params.feature_config_flags |=
8785 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8786 else
8787 bp->link_params.feature_config_flags &=
8788 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8789
8790 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8791 bp->common.bc_ver = val;
8792 BNX2X_DEV_INFO("bc_ver %X\n", val);
8793 if (val < BNX2X_BC_VER) {
8794 /* for now only warn
8795 * later we might need to enforce this */
8796 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8797 "please upgrade BC\n", BNX2X_BC_VER, val);
8798 }
8799 bp->link_params.feature_config_flags |=
8800 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8801 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8802
8803 bp->link_params.feature_config_flags |=
8804 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8805 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8806
8807 bp->link_params.feature_config_flags |=
8808 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8809 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8810
8811 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8812 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8813
8814 BNX2X_DEV_INFO("%sWoL capable\n",
8815 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8816
8817 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8818 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8819 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8820 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8821
8822 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8823 val, val2, val3, val4);
8824 }
8825
8826 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8827 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8828
8829 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8830 {
8831 int pfid = BP_FUNC(bp);
8832 int igu_sb_id;
8833 u32 val;
8834 u8 fid, igu_sb_cnt = 0;
8835
8836 bp->igu_base_sb = 0xff;
8837 if (CHIP_INT_MODE_IS_BC(bp)) {
8838 int vn = BP_VN(bp);
8839 igu_sb_cnt = bp->igu_sb_cnt;
8840 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8841 FP_SB_MAX_E1x;
8842
8843 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8844 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8845
8846 return;
8847 }
8848
8849 /* IGU in normal mode - read CAM */
8850 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8851 igu_sb_id++) {
8852 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8853 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8854 continue;
8855 fid = IGU_FID(val);
8856 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8857 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8858 continue;
8859 if (IGU_VEC(val) == 0)
8860 /* default status block */
8861 bp->igu_dsb_id = igu_sb_id;
8862 else {
8863 if (bp->igu_base_sb == 0xff)
8864 bp->igu_base_sb = igu_sb_id;
8865 igu_sb_cnt++;
8866 }
8867 }
8868 }
8869
8870 #ifdef CONFIG_PCI_MSI
8871 /*
8872 * It's expected that number of CAM entries for this functions is equal
8873 * to the number evaluated based on the MSI-X table size. We want a
8874 * harsh warning if these values are different!
8875 */
8876 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8877 #endif
8878
8879 if (igu_sb_cnt == 0)
8880 BNX2X_ERR("CAM configuration error\n");
8881 }
8882
8883 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8884 u32 switch_cfg)
8885 {
8886 int cfg_size = 0, idx, port = BP_PORT(bp);
8887
8888 /* Aggregation of supported attributes of all external phys */
8889 bp->port.supported[0] = 0;
8890 bp->port.supported[1] = 0;
8891 switch (bp->link_params.num_phys) {
8892 case 1:
8893 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8894 cfg_size = 1;
8895 break;
8896 case 2:
8897 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8898 cfg_size = 1;
8899 break;
8900 case 3:
8901 if (bp->link_params.multi_phy_config &
8902 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8903 bp->port.supported[1] =
8904 bp->link_params.phy[EXT_PHY1].supported;
8905 bp->port.supported[0] =
8906 bp->link_params.phy[EXT_PHY2].supported;
8907 } else {
8908 bp->port.supported[0] =
8909 bp->link_params.phy[EXT_PHY1].supported;
8910 bp->port.supported[1] =
8911 bp->link_params.phy[EXT_PHY2].supported;
8912 }
8913 cfg_size = 2;
8914 break;
8915 }
8916
8917 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8918 BNX2X_ERR("NVRAM config error. BAD phy config."
8919 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8920 SHMEM_RD(bp,
8921 dev_info.port_hw_config[port].external_phy_config),
8922 SHMEM_RD(bp,
8923 dev_info.port_hw_config[port].external_phy_config2));
8924 return;
8925 }
8926
8927 if (CHIP_IS_E3(bp))
8928 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8929 else {
8930 switch (switch_cfg) {
8931 case SWITCH_CFG_1G:
8932 bp->port.phy_addr = REG_RD(
8933 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8934 break;
8935 case SWITCH_CFG_10G:
8936 bp->port.phy_addr = REG_RD(
8937 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8938 break;
8939 default:
8940 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8941 bp->port.link_config[0]);
8942 return;
8943 }
8944 }
8945 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8946 /* mask what we support according to speed_cap_mask per configuration */
8947 for (idx = 0; idx < cfg_size; idx++) {
8948 if (!(bp->link_params.speed_cap_mask[idx] &
8949 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8950 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8951
8952 if (!(bp->link_params.speed_cap_mask[idx] &
8953 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8954 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8955
8956 if (!(bp->link_params.speed_cap_mask[idx] &
8957 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8958 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8959
8960 if (!(bp->link_params.speed_cap_mask[idx] &
8961 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8962 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8963
8964 if (!(bp->link_params.speed_cap_mask[idx] &
8965 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8966 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8967 SUPPORTED_1000baseT_Full);
8968
8969 if (!(bp->link_params.speed_cap_mask[idx] &
8970 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8971 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8972
8973 if (!(bp->link_params.speed_cap_mask[idx] &
8974 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8975 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8976
8977 }
8978
8979 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8980 bp->port.supported[1]);
8981 }
8982
8983 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8984 {
8985 u32 link_config, idx, cfg_size = 0;
8986 bp->port.advertising[0] = 0;
8987 bp->port.advertising[1] = 0;
8988 switch (bp->link_params.num_phys) {
8989 case 1:
8990 case 2:
8991 cfg_size = 1;
8992 break;
8993 case 3:
8994 cfg_size = 2;
8995 break;
8996 }
8997 for (idx = 0; idx < cfg_size; idx++) {
8998 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8999 link_config = bp->port.link_config[idx];
9000 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9001 case PORT_FEATURE_LINK_SPEED_AUTO:
9002 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9003 bp->link_params.req_line_speed[idx] =
9004 SPEED_AUTO_NEG;
9005 bp->port.advertising[idx] |=
9006 bp->port.supported[idx];
9007 } else {
9008 /* force 10G, no AN */
9009 bp->link_params.req_line_speed[idx] =
9010 SPEED_10000;
9011 bp->port.advertising[idx] |=
9012 (ADVERTISED_10000baseT_Full |
9013 ADVERTISED_FIBRE);
9014 continue;
9015 }
9016 break;
9017
9018 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9019 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9020 bp->link_params.req_line_speed[idx] =
9021 SPEED_10;
9022 bp->port.advertising[idx] |=
9023 (ADVERTISED_10baseT_Full |
9024 ADVERTISED_TP);
9025 } else {
9026 BNX2X_ERR("NVRAM config error. "
9027 "Invalid link_config 0x%x"
9028 " speed_cap_mask 0x%x\n",
9029 link_config,
9030 bp->link_params.speed_cap_mask[idx]);
9031 return;
9032 }
9033 break;
9034
9035 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9036 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9037 bp->link_params.req_line_speed[idx] =
9038 SPEED_10;
9039 bp->link_params.req_duplex[idx] =
9040 DUPLEX_HALF;
9041 bp->port.advertising[idx] |=
9042 (ADVERTISED_10baseT_Half |
9043 ADVERTISED_TP);
9044 } else {
9045 BNX2X_ERR("NVRAM config error. "
9046 "Invalid link_config 0x%x"
9047 " speed_cap_mask 0x%x\n",
9048 link_config,
9049 bp->link_params.speed_cap_mask[idx]);
9050 return;
9051 }
9052 break;
9053
9054 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9055 if (bp->port.supported[idx] &
9056 SUPPORTED_100baseT_Full) {
9057 bp->link_params.req_line_speed[idx] =
9058 SPEED_100;
9059 bp->port.advertising[idx] |=
9060 (ADVERTISED_100baseT_Full |
9061 ADVERTISED_TP);
9062 } else {
9063 BNX2X_ERR("NVRAM config error. "
9064 "Invalid link_config 0x%x"
9065 " speed_cap_mask 0x%x\n",
9066 link_config,
9067 bp->link_params.speed_cap_mask[idx]);
9068 return;
9069 }
9070 break;
9071
9072 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9073 if (bp->port.supported[idx] &
9074 SUPPORTED_100baseT_Half) {
9075 bp->link_params.req_line_speed[idx] =
9076 SPEED_100;
9077 bp->link_params.req_duplex[idx] =
9078 DUPLEX_HALF;
9079 bp->port.advertising[idx] |=
9080 (ADVERTISED_100baseT_Half |
9081 ADVERTISED_TP);
9082 } else {
9083 BNX2X_ERR("NVRAM config error. "
9084 "Invalid link_config 0x%x"
9085 " speed_cap_mask 0x%x\n",
9086 link_config,
9087 bp->link_params.speed_cap_mask[idx]);
9088 return;
9089 }
9090 break;
9091
9092 case PORT_FEATURE_LINK_SPEED_1G:
9093 if (bp->port.supported[idx] &
9094 SUPPORTED_1000baseT_Full) {
9095 bp->link_params.req_line_speed[idx] =
9096 SPEED_1000;
9097 bp->port.advertising[idx] |=
9098 (ADVERTISED_1000baseT_Full |
9099 ADVERTISED_TP);
9100 } else {
9101 BNX2X_ERR("NVRAM config error. "
9102 "Invalid link_config 0x%x"
9103 " speed_cap_mask 0x%x\n",
9104 link_config,
9105 bp->link_params.speed_cap_mask[idx]);
9106 return;
9107 }
9108 break;
9109
9110 case PORT_FEATURE_LINK_SPEED_2_5G:
9111 if (bp->port.supported[idx] &
9112 SUPPORTED_2500baseX_Full) {
9113 bp->link_params.req_line_speed[idx] =
9114 SPEED_2500;
9115 bp->port.advertising[idx] |=
9116 (ADVERTISED_2500baseX_Full |
9117 ADVERTISED_TP);
9118 } else {
9119 BNX2X_ERR("NVRAM config error. "
9120 "Invalid link_config 0x%x"
9121 " speed_cap_mask 0x%x\n",
9122 link_config,
9123 bp->link_params.speed_cap_mask[idx]);
9124 return;
9125 }
9126 break;
9127
9128 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9129 if (bp->port.supported[idx] &
9130 SUPPORTED_10000baseT_Full) {
9131 bp->link_params.req_line_speed[idx] =
9132 SPEED_10000;
9133 bp->port.advertising[idx] |=
9134 (ADVERTISED_10000baseT_Full |
9135 ADVERTISED_FIBRE);
9136 } else {
9137 BNX2X_ERR("NVRAM config error. "
9138 "Invalid link_config 0x%x"
9139 " speed_cap_mask 0x%x\n",
9140 link_config,
9141 bp->link_params.speed_cap_mask[idx]);
9142 return;
9143 }
9144 break;
9145 case PORT_FEATURE_LINK_SPEED_20G:
9146 bp->link_params.req_line_speed[idx] = SPEED_20000;
9147
9148 break;
9149 default:
9150 BNX2X_ERR("NVRAM config error. "
9151 "BAD link speed link_config 0x%x\n",
9152 link_config);
9153 bp->link_params.req_line_speed[idx] =
9154 SPEED_AUTO_NEG;
9155 bp->port.advertising[idx] =
9156 bp->port.supported[idx];
9157 break;
9158 }
9159
9160 bp->link_params.req_flow_ctrl[idx] = (link_config &
9161 PORT_FEATURE_FLOW_CONTROL_MASK);
9162 if ((bp->link_params.req_flow_ctrl[idx] ==
9163 BNX2X_FLOW_CTRL_AUTO) &&
9164 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9165 bp->link_params.req_flow_ctrl[idx] =
9166 BNX2X_FLOW_CTRL_NONE;
9167 }
9168
9169 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9170 " 0x%x advertising 0x%x\n",
9171 bp->link_params.req_line_speed[idx],
9172 bp->link_params.req_duplex[idx],
9173 bp->link_params.req_flow_ctrl[idx],
9174 bp->port.advertising[idx]);
9175 }
9176 }
9177
9178 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9179 {
9180 mac_hi = cpu_to_be16(mac_hi);
9181 mac_lo = cpu_to_be32(mac_lo);
9182 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9183 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9184 }
9185
9186 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9187 {
9188 int port = BP_PORT(bp);
9189 u32 config;
9190 u32 ext_phy_type, ext_phy_config;
9191
9192 bp->link_params.bp = bp;
9193 bp->link_params.port = port;
9194
9195 bp->link_params.lane_config =
9196 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9197
9198 bp->link_params.speed_cap_mask[0] =
9199 SHMEM_RD(bp,
9200 dev_info.port_hw_config[port].speed_capability_mask);
9201 bp->link_params.speed_cap_mask[1] =
9202 SHMEM_RD(bp,
9203 dev_info.port_hw_config[port].speed_capability_mask2);
9204 bp->port.link_config[0] =
9205 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9206
9207 bp->port.link_config[1] =
9208 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9209
9210 bp->link_params.multi_phy_config =
9211 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9212 /* If the device is capable of WoL, set the default state according
9213 * to the HW
9214 */
9215 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9216 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9217 (config & PORT_FEATURE_WOL_ENABLED));
9218
9219 BNX2X_DEV_INFO("lane_config 0x%08x "
9220 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9221 bp->link_params.lane_config,
9222 bp->link_params.speed_cap_mask[0],
9223 bp->port.link_config[0]);
9224
9225 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9226 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9227 bnx2x_phy_probe(&bp->link_params);
9228 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9229
9230 bnx2x_link_settings_requested(bp);
9231
9232 /*
9233 * If connected directly, work with the internal PHY, otherwise, work
9234 * with the external PHY
9235 */
9236 ext_phy_config =
9237 SHMEM_RD(bp,
9238 dev_info.port_hw_config[port].external_phy_config);
9239 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9240 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9241 bp->mdio.prtad = bp->port.phy_addr;
9242
9243 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9244 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9245 bp->mdio.prtad =
9246 XGXS_EXT_PHY_ADDR(ext_phy_config);
9247
9248 /*
9249 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9250 * In MF mode, it is set to cover self test cases
9251 */
9252 if (IS_MF(bp))
9253 bp->port.need_hw_lock = 1;
9254 else
9255 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9256 bp->common.shmem_base,
9257 bp->common.shmem2_base);
9258 }
9259
9260 #ifdef BCM_CNIC
9261 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9262 {
9263 int port = BP_PORT(bp);
9264 int func = BP_ABS_FUNC(bp);
9265
9266 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9267 drv_lic_key[port].max_iscsi_conn);
9268 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9269 drv_lic_key[port].max_fcoe_conn);
9270
9271 /* Get the number of maximum allowed iSCSI and FCoE connections */
9272 bp->cnic_eth_dev.max_iscsi_conn =
9273 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9274 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9275
9276 bp->cnic_eth_dev.max_fcoe_conn =
9277 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9278 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9279
9280 /* Read the WWN: */
9281 if (!IS_MF(bp)) {
9282 /* Port info */
9283 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9284 SHMEM_RD(bp,
9285 dev_info.port_hw_config[port].
9286 fcoe_wwn_port_name_upper);
9287 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9288 SHMEM_RD(bp,
9289 dev_info.port_hw_config[port].
9290 fcoe_wwn_port_name_lower);
9291
9292 /* Node info */
9293 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9294 SHMEM_RD(bp,
9295 dev_info.port_hw_config[port].
9296 fcoe_wwn_node_name_upper);
9297 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9298 SHMEM_RD(bp,
9299 dev_info.port_hw_config[port].
9300 fcoe_wwn_node_name_lower);
9301 } else if (!IS_MF_SD(bp)) {
9302 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9303
9304 /*
9305 * Read the WWN info only if the FCoE feature is enabled for
9306 * this function.
9307 */
9308 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9309 /* Port info */
9310 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9311 MF_CFG_RD(bp, func_ext_config[func].
9312 fcoe_wwn_port_name_upper);
9313 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9314 MF_CFG_RD(bp, func_ext_config[func].
9315 fcoe_wwn_port_name_lower);
9316
9317 /* Node info */
9318 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9319 MF_CFG_RD(bp, func_ext_config[func].
9320 fcoe_wwn_node_name_upper);
9321 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9322 MF_CFG_RD(bp, func_ext_config[func].
9323 fcoe_wwn_node_name_lower);
9324 }
9325 }
9326
9327 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9328 bp->cnic_eth_dev.max_iscsi_conn,
9329 bp->cnic_eth_dev.max_fcoe_conn);
9330
9331 /*
9332 * If maximum allowed number of connections is zero -
9333 * disable the feature.
9334 */
9335 if (!bp->cnic_eth_dev.max_iscsi_conn)
9336 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9337
9338 if (!bp->cnic_eth_dev.max_fcoe_conn)
9339 bp->flags |= NO_FCOE_FLAG;
9340 }
9341 #endif
9342
9343 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9344 {
9345 u32 val, val2;
9346 int func = BP_ABS_FUNC(bp);
9347 int port = BP_PORT(bp);
9348 #ifdef BCM_CNIC
9349 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9350 u8 *fip_mac = bp->fip_mac;
9351 #endif
9352
9353 /* Zero primary MAC configuration */
9354 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9355
9356 if (BP_NOMCP(bp)) {
9357 BNX2X_ERROR("warning: random MAC workaround active\n");
9358 random_ether_addr(bp->dev->dev_addr);
9359 } else if (IS_MF(bp)) {
9360 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9361 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9362 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9363 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9364 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9365
9366 #ifdef BCM_CNIC
9367 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9368 * FCoE MAC then the appropriate feature should be disabled.
9369 */
9370 if (IS_MF_SI(bp)) {
9371 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9372 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9373 val2 = MF_CFG_RD(bp, func_ext_config[func].
9374 iscsi_mac_addr_upper);
9375 val = MF_CFG_RD(bp, func_ext_config[func].
9376 iscsi_mac_addr_lower);
9377 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9378 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9379 iscsi_mac);
9380 } else
9381 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9382
9383 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9384 val2 = MF_CFG_RD(bp, func_ext_config[func].
9385 fcoe_mac_addr_upper);
9386 val = MF_CFG_RD(bp, func_ext_config[func].
9387 fcoe_mac_addr_lower);
9388 bnx2x_set_mac_buf(fip_mac, val, val2);
9389 BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n",
9390 fip_mac);
9391
9392 } else
9393 bp->flags |= NO_FCOE_FLAG;
9394 }
9395 #endif
9396 } else {
9397 /* in SF read MACs from port configuration */
9398 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9399 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9400 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9401
9402 #ifdef BCM_CNIC
9403 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9404 iscsi_mac_upper);
9405 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9406 iscsi_mac_lower);
9407 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9408
9409 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9410 fcoe_fip_mac_upper);
9411 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9412 fcoe_fip_mac_lower);
9413 bnx2x_set_mac_buf(fip_mac, val, val2);
9414 #endif
9415 }
9416
9417 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9418 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9419
9420 #ifdef BCM_CNIC
9421 /* Set the FCoE MAC in MF_SD mode */
9422 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9423 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9424
9425 /* Disable iSCSI if MAC configuration is
9426 * invalid.
9427 */
9428 if (!is_valid_ether_addr(iscsi_mac)) {
9429 bp->flags |= NO_ISCSI_FLAG;
9430 memset(iscsi_mac, 0, ETH_ALEN);
9431 }
9432
9433 /* Disable FCoE if MAC configuration is
9434 * invalid.
9435 */
9436 if (!is_valid_ether_addr(fip_mac)) {
9437 bp->flags |= NO_FCOE_FLAG;
9438 memset(bp->fip_mac, 0, ETH_ALEN);
9439 }
9440 #endif
9441
9442 if (!is_valid_ether_addr(bp->dev->dev_addr))
9443 dev_err(&bp->pdev->dev,
9444 "bad Ethernet MAC address configuration: "
9445 "%pM, change it manually before bringing up "
9446 "the appropriate network interface\n",
9447 bp->dev->dev_addr);
9448 }
9449
9450 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9451 {
9452 int /*abs*/func = BP_ABS_FUNC(bp);
9453 int vn;
9454 u32 val = 0;
9455 int rc = 0;
9456
9457 bnx2x_get_common_hwinfo(bp);
9458
9459 /*
9460 * initialize IGU parameters
9461 */
9462 if (CHIP_IS_E1x(bp)) {
9463 bp->common.int_block = INT_BLOCK_HC;
9464
9465 bp->igu_dsb_id = DEF_SB_IGU_ID;
9466 bp->igu_base_sb = 0;
9467 } else {
9468 bp->common.int_block = INT_BLOCK_IGU;
9469
9470 /* do not allow device reset during IGU info preocessing */
9471 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9472
9473 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9474
9475 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9476 int tout = 5000;
9477
9478 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9479
9480 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9482 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9483
9484 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9485 tout--;
9486 usleep_range(1000, 1000);
9487 }
9488
9489 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9490 dev_err(&bp->pdev->dev,
9491 "FORCING Normal Mode failed!!!\n");
9492 return -EPERM;
9493 }
9494 }
9495
9496 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9497 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9498 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9499 } else
9500 BNX2X_DEV_INFO("IGU Normal Mode\n");
9501
9502 bnx2x_get_igu_cam_info(bp);
9503
9504 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9505 }
9506
9507 /*
9508 * set base FW non-default (fast path) status block id, this value is
9509 * used to initialize the fw_sb_id saved on the fp/queue structure to
9510 * determine the id used by the FW.
9511 */
9512 if (CHIP_IS_E1x(bp))
9513 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9514 else /*
9515 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9516 * the same queue are indicated on the same IGU SB). So we prefer
9517 * FW and IGU SBs to be the same value.
9518 */
9519 bp->base_fw_ndsb = bp->igu_base_sb;
9520
9521 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9522 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9523 bp->igu_sb_cnt, bp->base_fw_ndsb);
9524
9525 /*
9526 * Initialize MF configuration
9527 */
9528
9529 bp->mf_ov = 0;
9530 bp->mf_mode = 0;
9531 vn = BP_VN(bp);
9532
9533 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9534 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9535 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9536 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9537
9538 if (SHMEM2_HAS(bp, mf_cfg_addr))
9539 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9540 else
9541 bp->common.mf_cfg_base = bp->common.shmem_base +
9542 offsetof(struct shmem_region, func_mb) +
9543 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9544 /*
9545 * get mf configuration:
9546 * 1. existence of MF configuration
9547 * 2. MAC address must be legal (check only upper bytes)
9548 * for Switch-Independent mode;
9549 * OVLAN must be legal for Switch-Dependent mode
9550 * 3. SF_MODE configures specific MF mode
9551 */
9552 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9553 /* get mf configuration */
9554 val = SHMEM_RD(bp,
9555 dev_info.shared_feature_config.config);
9556 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9557
9558 switch (val) {
9559 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9560 val = MF_CFG_RD(bp, func_mf_config[func].
9561 mac_upper);
9562 /* check for legal mac (upper bytes)*/
9563 if (val != 0xffff) {
9564 bp->mf_mode = MULTI_FUNCTION_SI;
9565 bp->mf_config[vn] = MF_CFG_RD(bp,
9566 func_mf_config[func].config);
9567 } else
9568 BNX2X_DEV_INFO("illegal MAC address "
9569 "for SI\n");
9570 break;
9571 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9572 /* get OV configuration */
9573 val = MF_CFG_RD(bp,
9574 func_mf_config[FUNC_0].e1hov_tag);
9575 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9576
9577 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9578 bp->mf_mode = MULTI_FUNCTION_SD;
9579 bp->mf_config[vn] = MF_CFG_RD(bp,
9580 func_mf_config[func].config);
9581 } else
9582 BNX2X_DEV_INFO("illegal OV for SD\n");
9583 break;
9584 default:
9585 /* Unknown configuration: reset mf_config */
9586 bp->mf_config[vn] = 0;
9587 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9588 }
9589 }
9590
9591 BNX2X_DEV_INFO("%s function mode\n",
9592 IS_MF(bp) ? "multi" : "single");
9593
9594 switch (bp->mf_mode) {
9595 case MULTI_FUNCTION_SD:
9596 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9597 FUNC_MF_CFG_E1HOV_TAG_MASK;
9598 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9599 bp->mf_ov = val;
9600 bp->path_has_ovlan = true;
9601
9602 BNX2X_DEV_INFO("MF OV for func %d is %d "
9603 "(0x%04x)\n", func, bp->mf_ov,
9604 bp->mf_ov);
9605 } else {
9606 dev_err(&bp->pdev->dev,
9607 "No valid MF OV for func %d, "
9608 "aborting\n", func);
9609 return -EPERM;
9610 }
9611 break;
9612 case MULTI_FUNCTION_SI:
9613 BNX2X_DEV_INFO("func %d is in MF "
9614 "switch-independent mode\n", func);
9615 break;
9616 default:
9617 if (vn) {
9618 dev_err(&bp->pdev->dev,
9619 "VN %d is in a single function mode, "
9620 "aborting\n", vn);
9621 return -EPERM;
9622 }
9623 break;
9624 }
9625
9626 /* check if other port on the path needs ovlan:
9627 * Since MF configuration is shared between ports
9628 * Possible mixed modes are only
9629 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9630 */
9631 if (CHIP_MODE_IS_4_PORT(bp) &&
9632 !bp->path_has_ovlan &&
9633 !IS_MF(bp) &&
9634 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9635 u8 other_port = !BP_PORT(bp);
9636 u8 other_func = BP_PATH(bp) + 2*other_port;
9637 val = MF_CFG_RD(bp,
9638 func_mf_config[other_func].e1hov_tag);
9639 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9640 bp->path_has_ovlan = true;
9641 }
9642 }
9643
9644 /* adjust igu_sb_cnt to MF for E1x */
9645 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9646 bp->igu_sb_cnt /= E1HVN_MAX;
9647
9648 /* port info */
9649 bnx2x_get_port_hwinfo(bp);
9650
9651 /* Get MAC addresses */
9652 bnx2x_get_mac_hwinfo(bp);
9653
9654 #ifdef BCM_CNIC
9655 bnx2x_get_cnic_info(bp);
9656 #endif
9657
9658 /* Get current FW pulse sequence */
9659 if (!BP_NOMCP(bp)) {
9660 int mb_idx = BP_FW_MB_IDX(bp);
9661
9662 bp->fw_drv_pulse_wr_seq =
9663 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9664 DRV_PULSE_SEQ_MASK);
9665 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9666 }
9667
9668 return rc;
9669 }
9670
9671 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9672 {
9673 int cnt, i, block_end, rodi;
9674 char vpd_data[BNX2X_VPD_LEN+1];
9675 char str_id_reg[VENDOR_ID_LEN+1];
9676 char str_id_cap[VENDOR_ID_LEN+1];
9677 u8 len;
9678
9679 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9680 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9681
9682 if (cnt < BNX2X_VPD_LEN)
9683 goto out_not_found;
9684
9685 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9686 PCI_VPD_LRDT_RO_DATA);
9687 if (i < 0)
9688 goto out_not_found;
9689
9690
9691 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9692 pci_vpd_lrdt_size(&vpd_data[i]);
9693
9694 i += PCI_VPD_LRDT_TAG_SIZE;
9695
9696 if (block_end > BNX2X_VPD_LEN)
9697 goto out_not_found;
9698
9699 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9700 PCI_VPD_RO_KEYWORD_MFR_ID);
9701 if (rodi < 0)
9702 goto out_not_found;
9703
9704 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9705
9706 if (len != VENDOR_ID_LEN)
9707 goto out_not_found;
9708
9709 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9710
9711 /* vendor specific info */
9712 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9713 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9714 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9715 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9716
9717 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9718 PCI_VPD_RO_KEYWORD_VENDOR0);
9719 if (rodi >= 0) {
9720 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9721
9722 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9723
9724 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9725 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9726 bp->fw_ver[len] = ' ';
9727 }
9728 }
9729 return;
9730 }
9731 out_not_found:
9732 return;
9733 }
9734
9735 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9736 {
9737 u32 flags = 0;
9738
9739 if (CHIP_REV_IS_FPGA(bp))
9740 SET_FLAGS(flags, MODE_FPGA);
9741 else if (CHIP_REV_IS_EMUL(bp))
9742 SET_FLAGS(flags, MODE_EMUL);
9743 else
9744 SET_FLAGS(flags, MODE_ASIC);
9745
9746 if (CHIP_MODE_IS_4_PORT(bp))
9747 SET_FLAGS(flags, MODE_PORT4);
9748 else
9749 SET_FLAGS(flags, MODE_PORT2);
9750
9751 if (CHIP_IS_E2(bp))
9752 SET_FLAGS(flags, MODE_E2);
9753 else if (CHIP_IS_E3(bp)) {
9754 SET_FLAGS(flags, MODE_E3);
9755 if (CHIP_REV(bp) == CHIP_REV_Ax)
9756 SET_FLAGS(flags, MODE_E3_A0);
9757 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9758 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9759 }
9760
9761 if (IS_MF(bp)) {
9762 SET_FLAGS(flags, MODE_MF);
9763 switch (bp->mf_mode) {
9764 case MULTI_FUNCTION_SD:
9765 SET_FLAGS(flags, MODE_MF_SD);
9766 break;
9767 case MULTI_FUNCTION_SI:
9768 SET_FLAGS(flags, MODE_MF_SI);
9769 break;
9770 }
9771 } else
9772 SET_FLAGS(flags, MODE_SF);
9773
9774 #if defined(__LITTLE_ENDIAN)
9775 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9776 #else /*(__BIG_ENDIAN)*/
9777 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9778 #endif
9779 INIT_MODE_FLAGS(bp) = flags;
9780 }
9781
9782 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9783 {
9784 int func;
9785 int timer_interval;
9786 int rc;
9787
9788 mutex_init(&bp->port.phy_mutex);
9789 mutex_init(&bp->fw_mb_mutex);
9790 spin_lock_init(&bp->stats_lock);
9791 #ifdef BCM_CNIC
9792 mutex_init(&bp->cnic_mutex);
9793 #endif
9794
9795 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9796 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9797 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9798 rc = bnx2x_get_hwinfo(bp);
9799 if (rc)
9800 return rc;
9801
9802 bnx2x_set_modes_bitmap(bp);
9803
9804 rc = bnx2x_alloc_mem_bp(bp);
9805 if (rc)
9806 return rc;
9807
9808 bnx2x_read_fwinfo(bp);
9809
9810 func = BP_FUNC(bp);
9811
9812 /* need to reset chip if undi was active */
9813 if (!BP_NOMCP(bp))
9814 bnx2x_undi_unload(bp);
9815
9816 /* init fw_seq after undi_unload! */
9817 if (!BP_NOMCP(bp)) {
9818 bp->fw_seq =
9819 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9820 DRV_MSG_SEQ_NUMBER_MASK);
9821 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9822 }
9823
9824 if (CHIP_REV_IS_FPGA(bp))
9825 dev_err(&bp->pdev->dev, "FPGA detected\n");
9826
9827 if (BP_NOMCP(bp) && (func == 0))
9828 dev_err(&bp->pdev->dev, "MCP disabled, "
9829 "must load devices in order!\n");
9830
9831 bp->multi_mode = multi_mode;
9832
9833 /* Set TPA flags */
9834 if (disable_tpa) {
9835 bp->flags &= ~TPA_ENABLE_FLAG;
9836 bp->dev->features &= ~NETIF_F_LRO;
9837 } else {
9838 bp->flags |= TPA_ENABLE_FLAG;
9839 bp->dev->features |= NETIF_F_LRO;
9840 }
9841 bp->disable_tpa = disable_tpa;
9842
9843 if (CHIP_IS_E1(bp))
9844 bp->dropless_fc = 0;
9845 else
9846 bp->dropless_fc = dropless_fc;
9847
9848 bp->mrrs = mrrs;
9849
9850 bp->tx_ring_size = MAX_TX_AVAIL;
9851
9852 /* make sure that the numbers are in the right granularity */
9853 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9854 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9855
9856 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9857 bp->current_interval = (poll ? poll : timer_interval);
9858
9859 init_timer(&bp->timer);
9860 bp->timer.expires = jiffies + bp->current_interval;
9861 bp->timer.data = (unsigned long) bp;
9862 bp->timer.function = bnx2x_timer;
9863
9864 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9865 bnx2x_dcbx_init_params(bp);
9866
9867 #ifdef BCM_CNIC
9868 if (CHIP_IS_E1x(bp))
9869 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9870 else
9871 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9872 #endif
9873
9874 /* multiple tx priority */
9875 if (CHIP_IS_E1x(bp))
9876 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9877 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9878 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9879 if (CHIP_IS_E3B0(bp))
9880 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9881
9882 return rc;
9883 }
9884
9885
9886 /****************************************************************************
9887 * General service functions
9888 ****************************************************************************/
9889
9890 /*
9891 * net_device service functions
9892 */
9893
9894 /* called with rtnl_lock */
9895 static int bnx2x_open(struct net_device *dev)
9896 {
9897 struct bnx2x *bp = netdev_priv(dev);
9898 bool global = false;
9899 int other_engine = BP_PATH(bp) ? 0 : 1;
9900 u32 other_load_counter, load_counter;
9901
9902 netif_carrier_off(dev);
9903
9904 bnx2x_set_power_state(bp, PCI_D0);
9905
9906 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9907 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9908
9909 /*
9910 * If parity had happen during the unload, then attentions
9911 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9912 * want the first function loaded on the current engine to
9913 * complete the recovery.
9914 */
9915 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9916 bnx2x_chk_parity_attn(bp, &global, true))
9917 do {
9918 /*
9919 * If there are attentions and they are in a global
9920 * blocks, set the GLOBAL_RESET bit regardless whether
9921 * it will be this function that will complete the
9922 * recovery or not.
9923 */
9924 if (global)
9925 bnx2x_set_reset_global(bp);
9926
9927 /*
9928 * Only the first function on the current engine should
9929 * try to recover in open. In case of attentions in
9930 * global blocks only the first in the chip should try
9931 * to recover.
9932 */
9933 if ((!load_counter &&
9934 (!global || !other_load_counter)) &&
9935 bnx2x_trylock_leader_lock(bp) &&
9936 !bnx2x_leader_reset(bp)) {
9937 netdev_info(bp->dev, "Recovered in open\n");
9938 break;
9939 }
9940
9941 /* recovery has failed... */
9942 bnx2x_set_power_state(bp, PCI_D3hot);
9943 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9944
9945 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9946 " completed yet. Try again later. If u still see this"
9947 " message after a few retries then power cycle is"
9948 " required.\n");
9949
9950 return -EAGAIN;
9951 } while (0);
9952
9953 bp->recovery_state = BNX2X_RECOVERY_DONE;
9954 return bnx2x_nic_load(bp, LOAD_OPEN);
9955 }
9956
9957 /* called with rtnl_lock */
9958 static int bnx2x_close(struct net_device *dev)
9959 {
9960 struct bnx2x *bp = netdev_priv(dev);
9961
9962 /* Unload the driver, release IRQs */
9963 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9964
9965 /* Power off */
9966 bnx2x_set_power_state(bp, PCI_D3hot);
9967
9968 return 0;
9969 }
9970
9971 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9972 struct bnx2x_mcast_ramrod_params *p)
9973 {
9974 int mc_count = netdev_mc_count(bp->dev);
9975 struct bnx2x_mcast_list_elem *mc_mac =
9976 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9977 struct netdev_hw_addr *ha;
9978
9979 if (!mc_mac)
9980 return -ENOMEM;
9981
9982 INIT_LIST_HEAD(&p->mcast_list);
9983
9984 netdev_for_each_mc_addr(ha, bp->dev) {
9985 mc_mac->mac = bnx2x_mc_addr(ha);
9986 list_add_tail(&mc_mac->link, &p->mcast_list);
9987 mc_mac++;
9988 }
9989
9990 p->mcast_list_len = mc_count;
9991
9992 return 0;
9993 }
9994
9995 static inline void bnx2x_free_mcast_macs_list(
9996 struct bnx2x_mcast_ramrod_params *p)
9997 {
9998 struct bnx2x_mcast_list_elem *mc_mac =
9999 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10000 link);
10001
10002 WARN_ON(!mc_mac);
10003 kfree(mc_mac);
10004 }
10005
10006 /**
10007 * bnx2x_set_uc_list - configure a new unicast MACs list.
10008 *
10009 * @bp: driver handle
10010 *
10011 * We will use zero (0) as a MAC type for these MACs.
10012 */
10013 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10014 {
10015 int rc;
10016 struct net_device *dev = bp->dev;
10017 struct netdev_hw_addr *ha;
10018 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10019 unsigned long ramrod_flags = 0;
10020
10021 /* First schedule a cleanup up of old configuration */
10022 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10023 if (rc < 0) {
10024 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10025 return rc;
10026 }
10027
10028 netdev_for_each_uc_addr(ha, dev) {
10029 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10030 BNX2X_UC_LIST_MAC, &ramrod_flags);
10031 if (rc < 0) {
10032 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10033 rc);
10034 return rc;
10035 }
10036 }
10037
10038 /* Execute the pending commands */
10039 __set_bit(RAMROD_CONT, &ramrod_flags);
10040 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10041 BNX2X_UC_LIST_MAC, &ramrod_flags);
10042 }
10043
10044 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10045 {
10046 struct net_device *dev = bp->dev;
10047 struct bnx2x_mcast_ramrod_params rparam = {0};
10048 int rc = 0;
10049
10050 rparam.mcast_obj = &bp->mcast_obj;
10051
10052 /* first, clear all configured multicast MACs */
10053 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10054 if (rc < 0) {
10055 BNX2X_ERR("Failed to clear multicast "
10056 "configuration: %d\n", rc);
10057 return rc;
10058 }
10059
10060 /* then, configure a new MACs list */
10061 if (netdev_mc_count(dev)) {
10062 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10063 if (rc) {
10064 BNX2X_ERR("Failed to create multicast MACs "
10065 "list: %d\n", rc);
10066 return rc;
10067 }
10068
10069 /* Now add the new MACs */
10070 rc = bnx2x_config_mcast(bp, &rparam,
10071 BNX2X_MCAST_CMD_ADD);
10072 if (rc < 0)
10073 BNX2X_ERR("Failed to set a new multicast "
10074 "configuration: %d\n", rc);
10075
10076 bnx2x_free_mcast_macs_list(&rparam);
10077 }
10078
10079 return rc;
10080 }
10081
10082
10083 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10084 void bnx2x_set_rx_mode(struct net_device *dev)
10085 {
10086 struct bnx2x *bp = netdev_priv(dev);
10087 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10088
10089 if (bp->state != BNX2X_STATE_OPEN) {
10090 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10091 return;
10092 }
10093
10094 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10095
10096 if (dev->flags & IFF_PROMISC)
10097 rx_mode = BNX2X_RX_MODE_PROMISC;
10098 else if ((dev->flags & IFF_ALLMULTI) ||
10099 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10100 CHIP_IS_E1(bp)))
10101 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10102 else {
10103 /* some multicasts */
10104 if (bnx2x_set_mc_list(bp) < 0)
10105 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10106
10107 if (bnx2x_set_uc_list(bp) < 0)
10108 rx_mode = BNX2X_RX_MODE_PROMISC;
10109 }
10110
10111 bp->rx_mode = rx_mode;
10112
10113 /* Schedule the rx_mode command */
10114 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10115 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10116 return;
10117 }
10118
10119 bnx2x_set_storm_rx_mode(bp);
10120 }
10121
10122 /* called with rtnl_lock */
10123 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10124 int devad, u16 addr)
10125 {
10126 struct bnx2x *bp = netdev_priv(netdev);
10127 u16 value;
10128 int rc;
10129
10130 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10131 prtad, devad, addr);
10132
10133 /* The HW expects different devad if CL22 is used */
10134 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10135
10136 bnx2x_acquire_phy_lock(bp);
10137 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10138 bnx2x_release_phy_lock(bp);
10139 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10140
10141 if (!rc)
10142 rc = value;
10143 return rc;
10144 }
10145
10146 /* called with rtnl_lock */
10147 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10148 u16 addr, u16 value)
10149 {
10150 struct bnx2x *bp = netdev_priv(netdev);
10151 int rc;
10152
10153 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10154 " value 0x%x\n", prtad, devad, addr, value);
10155
10156 /* The HW expects different devad if CL22 is used */
10157 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10158
10159 bnx2x_acquire_phy_lock(bp);
10160 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10161 bnx2x_release_phy_lock(bp);
10162 return rc;
10163 }
10164
10165 /* called with rtnl_lock */
10166 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10167 {
10168 struct bnx2x *bp = netdev_priv(dev);
10169 struct mii_ioctl_data *mdio = if_mii(ifr);
10170
10171 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10172 mdio->phy_id, mdio->reg_num, mdio->val_in);
10173
10174 if (!netif_running(dev))
10175 return -EAGAIN;
10176
10177 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10178 }
10179
10180 #ifdef CONFIG_NET_POLL_CONTROLLER
10181 static void poll_bnx2x(struct net_device *dev)
10182 {
10183 struct bnx2x *bp = netdev_priv(dev);
10184
10185 disable_irq(bp->pdev->irq);
10186 bnx2x_interrupt(bp->pdev->irq, dev);
10187 enable_irq(bp->pdev->irq);
10188 }
10189 #endif
10190
10191 static const struct net_device_ops bnx2x_netdev_ops = {
10192 .ndo_open = bnx2x_open,
10193 .ndo_stop = bnx2x_close,
10194 .ndo_start_xmit = bnx2x_start_xmit,
10195 .ndo_select_queue = bnx2x_select_queue,
10196 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10197 .ndo_set_mac_address = bnx2x_change_mac_addr,
10198 .ndo_validate_addr = eth_validate_addr,
10199 .ndo_do_ioctl = bnx2x_ioctl,
10200 .ndo_change_mtu = bnx2x_change_mtu,
10201 .ndo_fix_features = bnx2x_fix_features,
10202 .ndo_set_features = bnx2x_set_features,
10203 .ndo_tx_timeout = bnx2x_tx_timeout,
10204 #ifdef CONFIG_NET_POLL_CONTROLLER
10205 .ndo_poll_controller = poll_bnx2x,
10206 #endif
10207 .ndo_setup_tc = bnx2x_setup_tc,
10208
10209 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10210 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10211 #endif
10212 };
10213
10214 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10215 {
10216 struct device *dev = &bp->pdev->dev;
10217
10218 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10219 bp->flags |= USING_DAC_FLAG;
10220 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10221 dev_err(dev, "dma_set_coherent_mask failed, "
10222 "aborting\n");
10223 return -EIO;
10224 }
10225 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10226 dev_err(dev, "System does not support DMA, aborting\n");
10227 return -EIO;
10228 }
10229
10230 return 0;
10231 }
10232
10233 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10234 struct net_device *dev,
10235 unsigned long board_type)
10236 {
10237 struct bnx2x *bp;
10238 int rc;
10239
10240 SET_NETDEV_DEV(dev, &pdev->dev);
10241 bp = netdev_priv(dev);
10242
10243 bp->dev = dev;
10244 bp->pdev = pdev;
10245 bp->flags = 0;
10246 bp->pf_num = PCI_FUNC(pdev->devfn);
10247
10248 rc = pci_enable_device(pdev);
10249 if (rc) {
10250 dev_err(&bp->pdev->dev,
10251 "Cannot enable PCI device, aborting\n");
10252 goto err_out;
10253 }
10254
10255 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10256 dev_err(&bp->pdev->dev,
10257 "Cannot find PCI device base address, aborting\n");
10258 rc = -ENODEV;
10259 goto err_out_disable;
10260 }
10261
10262 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10263 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10264 " base address, aborting\n");
10265 rc = -ENODEV;
10266 goto err_out_disable;
10267 }
10268
10269 if (atomic_read(&pdev->enable_cnt) == 1) {
10270 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10271 if (rc) {
10272 dev_err(&bp->pdev->dev,
10273 "Cannot obtain PCI resources, aborting\n");
10274 goto err_out_disable;
10275 }
10276
10277 pci_set_master(pdev);
10278 pci_save_state(pdev);
10279 }
10280
10281 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10282 if (bp->pm_cap == 0) {
10283 dev_err(&bp->pdev->dev,
10284 "Cannot find power management capability, aborting\n");
10285 rc = -EIO;
10286 goto err_out_release;
10287 }
10288
10289 if (!pci_is_pcie(pdev)) {
10290 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10291 rc = -EIO;
10292 goto err_out_release;
10293 }
10294
10295 rc = bnx2x_set_coherency_mask(bp);
10296 if (rc)
10297 goto err_out_release;
10298
10299 dev->mem_start = pci_resource_start(pdev, 0);
10300 dev->base_addr = dev->mem_start;
10301 dev->mem_end = pci_resource_end(pdev, 0);
10302
10303 dev->irq = pdev->irq;
10304
10305 bp->regview = pci_ioremap_bar(pdev, 0);
10306 if (!bp->regview) {
10307 dev_err(&bp->pdev->dev,
10308 "Cannot map register space, aborting\n");
10309 rc = -ENOMEM;
10310 goto err_out_release;
10311 }
10312
10313 bnx2x_set_power_state(bp, PCI_D0);
10314
10315 /* clean indirect addresses */
10316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10317 PCICFG_VENDOR_ID_OFFSET);
10318 /*
10319 * Clean the following indirect addresses for all functions since it
10320 * is not used by the driver.
10321 */
10322 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10323 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10324 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10325 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10326
10327 if (CHIP_IS_E1x(bp)) {
10328 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10329 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10330 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10331 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10332 }
10333
10334 /*
10335 * Enable internal target-read (in case we are probed after PF FLR).
10336 * Must be done prior to any BAR read access. Only for 57712 and up
10337 */
10338 if (board_type != BCM57710 &&
10339 board_type != BCM57711 &&
10340 board_type != BCM57711E)
10341 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10342
10343 /* Reset the load counter */
10344 bnx2x_clear_load_cnt(bp);
10345
10346 dev->watchdog_timeo = TX_TIMEOUT;
10347
10348 dev->netdev_ops = &bnx2x_netdev_ops;
10349 bnx2x_set_ethtool_ops(dev);
10350
10351 dev->priv_flags |= IFF_UNICAST_FLT;
10352
10353 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10354 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10355 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
10356
10357 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10358 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10359
10360 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10361 if (bp->flags & USING_DAC_FLAG)
10362 dev->features |= NETIF_F_HIGHDMA;
10363
10364 /* Add Loopback capability to the device */
10365 dev->hw_features |= NETIF_F_LOOPBACK;
10366
10367 #ifdef BCM_DCBNL
10368 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10369 #endif
10370
10371 /* get_port_hwinfo() will set prtad and mmds properly */
10372 bp->mdio.prtad = MDIO_PRTAD_NONE;
10373 bp->mdio.mmds = 0;
10374 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10375 bp->mdio.dev = dev;
10376 bp->mdio.mdio_read = bnx2x_mdio_read;
10377 bp->mdio.mdio_write = bnx2x_mdio_write;
10378
10379 return 0;
10380
10381 err_out_release:
10382 if (atomic_read(&pdev->enable_cnt) == 1)
10383 pci_release_regions(pdev);
10384
10385 err_out_disable:
10386 pci_disable_device(pdev);
10387 pci_set_drvdata(pdev, NULL);
10388
10389 err_out:
10390 return rc;
10391 }
10392
10393 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10394 int *width, int *speed)
10395 {
10396 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10397
10398 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10399
10400 /* return value of 1=2.5GHz 2=5GHz */
10401 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10402 }
10403
10404 static int bnx2x_check_firmware(struct bnx2x *bp)
10405 {
10406 const struct firmware *firmware = bp->firmware;
10407 struct bnx2x_fw_file_hdr *fw_hdr;
10408 struct bnx2x_fw_file_section *sections;
10409 u32 offset, len, num_ops;
10410 u16 *ops_offsets;
10411 int i;
10412 const u8 *fw_ver;
10413
10414 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10415 return -EINVAL;
10416
10417 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10418 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10419
10420 /* Make sure none of the offsets and sizes make us read beyond
10421 * the end of the firmware data */
10422 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10423 offset = be32_to_cpu(sections[i].offset);
10424 len = be32_to_cpu(sections[i].len);
10425 if (offset + len > firmware->size) {
10426 dev_err(&bp->pdev->dev,
10427 "Section %d length is out of bounds\n", i);
10428 return -EINVAL;
10429 }
10430 }
10431
10432 /* Likewise for the init_ops offsets */
10433 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10434 ops_offsets = (u16 *)(firmware->data + offset);
10435 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10436
10437 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10438 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10439 dev_err(&bp->pdev->dev,
10440 "Section offset %d is out of bounds\n", i);
10441 return -EINVAL;
10442 }
10443 }
10444
10445 /* Check FW version */
10446 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10447 fw_ver = firmware->data + offset;
10448 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10449 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10450 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10451 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10452 dev_err(&bp->pdev->dev,
10453 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10454 fw_ver[0], fw_ver[1], fw_ver[2],
10455 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10456 BCM_5710_FW_MINOR_VERSION,
10457 BCM_5710_FW_REVISION_VERSION,
10458 BCM_5710_FW_ENGINEERING_VERSION);
10459 return -EINVAL;
10460 }
10461
10462 return 0;
10463 }
10464
10465 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10466 {
10467 const __be32 *source = (const __be32 *)_source;
10468 u32 *target = (u32 *)_target;
10469 u32 i;
10470
10471 for (i = 0; i < n/4; i++)
10472 target[i] = be32_to_cpu(source[i]);
10473 }
10474
10475 /*
10476 Ops array is stored in the following format:
10477 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10478 */
10479 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10480 {
10481 const __be32 *source = (const __be32 *)_source;
10482 struct raw_op *target = (struct raw_op *)_target;
10483 u32 i, j, tmp;
10484
10485 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10486 tmp = be32_to_cpu(source[j]);
10487 target[i].op = (tmp >> 24) & 0xff;
10488 target[i].offset = tmp & 0xffffff;
10489 target[i].raw_data = be32_to_cpu(source[j + 1]);
10490 }
10491 }
10492
10493 /**
10494 * IRO array is stored in the following format:
10495 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10496 */
10497 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10498 {
10499 const __be32 *source = (const __be32 *)_source;
10500 struct iro *target = (struct iro *)_target;
10501 u32 i, j, tmp;
10502
10503 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10504 target[i].base = be32_to_cpu(source[j]);
10505 j++;
10506 tmp = be32_to_cpu(source[j]);
10507 target[i].m1 = (tmp >> 16) & 0xffff;
10508 target[i].m2 = tmp & 0xffff;
10509 j++;
10510 tmp = be32_to_cpu(source[j]);
10511 target[i].m3 = (tmp >> 16) & 0xffff;
10512 target[i].size = tmp & 0xffff;
10513 j++;
10514 }
10515 }
10516
10517 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10518 {
10519 const __be16 *source = (const __be16 *)_source;
10520 u16 *target = (u16 *)_target;
10521 u32 i;
10522
10523 for (i = 0; i < n/2; i++)
10524 target[i] = be16_to_cpu(source[i]);
10525 }
10526
10527 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10528 do { \
10529 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10530 bp->arr = kmalloc(len, GFP_KERNEL); \
10531 if (!bp->arr) { \
10532 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10533 goto lbl; \
10534 } \
10535 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10536 (u8 *)bp->arr, len); \
10537 } while (0)
10538
10539 int bnx2x_init_firmware(struct bnx2x *bp)
10540 {
10541 const char *fw_file_name;
10542 struct bnx2x_fw_file_hdr *fw_hdr;
10543 int rc;
10544
10545 if (CHIP_IS_E1(bp))
10546 fw_file_name = FW_FILE_NAME_E1;
10547 else if (CHIP_IS_E1H(bp))
10548 fw_file_name = FW_FILE_NAME_E1H;
10549 else if (!CHIP_IS_E1x(bp))
10550 fw_file_name = FW_FILE_NAME_E2;
10551 else {
10552 BNX2X_ERR("Unsupported chip revision\n");
10553 return -EINVAL;
10554 }
10555
10556 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10557
10558 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10559 if (rc) {
10560 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10561 goto request_firmware_exit;
10562 }
10563
10564 rc = bnx2x_check_firmware(bp);
10565 if (rc) {
10566 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10567 goto request_firmware_exit;
10568 }
10569
10570 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10571
10572 /* Initialize the pointers to the init arrays */
10573 /* Blob */
10574 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10575
10576 /* Opcodes */
10577 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10578
10579 /* Offsets */
10580 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10581 be16_to_cpu_n);
10582
10583 /* STORMs firmware */
10584 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10585 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10586 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10587 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10588 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10589 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10590 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10591 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10592 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10593 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10594 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10595 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10596 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10597 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10598 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10599 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10600 /* IRO */
10601 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10602
10603 return 0;
10604
10605 iro_alloc_err:
10606 kfree(bp->init_ops_offsets);
10607 init_offsets_alloc_err:
10608 kfree(bp->init_ops);
10609 init_ops_alloc_err:
10610 kfree(bp->init_data);
10611 request_firmware_exit:
10612 release_firmware(bp->firmware);
10613
10614 return rc;
10615 }
10616
10617 static void bnx2x_release_firmware(struct bnx2x *bp)
10618 {
10619 kfree(bp->init_ops_offsets);
10620 kfree(bp->init_ops);
10621 kfree(bp->init_data);
10622 release_firmware(bp->firmware);
10623 }
10624
10625
10626 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10627 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10628 .init_hw_cmn = bnx2x_init_hw_common,
10629 .init_hw_port = bnx2x_init_hw_port,
10630 .init_hw_func = bnx2x_init_hw_func,
10631
10632 .reset_hw_cmn = bnx2x_reset_common,
10633 .reset_hw_port = bnx2x_reset_port,
10634 .reset_hw_func = bnx2x_reset_func,
10635
10636 .gunzip_init = bnx2x_gunzip_init,
10637 .gunzip_end = bnx2x_gunzip_end,
10638
10639 .init_fw = bnx2x_init_firmware,
10640 .release_fw = bnx2x_release_firmware,
10641 };
10642
10643 void bnx2x__init_func_obj(struct bnx2x *bp)
10644 {
10645 /* Prepare DMAE related driver resources */
10646 bnx2x_setup_dmae(bp);
10647
10648 bnx2x_init_func_obj(bp, &bp->func_obj,
10649 bnx2x_sp(bp, func_rdata),
10650 bnx2x_sp_mapping(bp, func_rdata),
10651 &bnx2x_func_sp_drv);
10652 }
10653
10654 /* must be called after sriov-enable */
10655 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10656 {
10657 int cid_count = BNX2X_L2_CID_COUNT(bp);
10658
10659 #ifdef BCM_CNIC
10660 cid_count += CNIC_CID_MAX;
10661 #endif
10662 return roundup(cid_count, QM_CID_ROUND);
10663 }
10664
10665 /**
10666 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10667 *
10668 * @dev: pci device
10669 *
10670 */
10671 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10672 {
10673 int pos;
10674 u16 control;
10675
10676 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10677
10678 /*
10679 * If MSI-X is not supported - return number of SBs needed to support
10680 * one fast path queue: one FP queue + SB for CNIC
10681 */
10682 if (!pos)
10683 return 1 + CNIC_PRESENT;
10684
10685 /*
10686 * The value in the PCI configuration space is the index of the last
10687 * entry, namely one less than the actual size of the table, which is
10688 * exactly what we want to return from this function: number of all SBs
10689 * without the default SB.
10690 */
10691 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10692 return control & PCI_MSIX_FLAGS_QSIZE;
10693 }
10694
10695 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10696 const struct pci_device_id *ent)
10697 {
10698 struct net_device *dev = NULL;
10699 struct bnx2x *bp;
10700 int pcie_width, pcie_speed;
10701 int rc, max_non_def_sbs;
10702 int rx_count, tx_count, rss_count;
10703 /*
10704 * An estimated maximum supported CoS number according to the chip
10705 * version.
10706 * We will try to roughly estimate the maximum number of CoSes this chip
10707 * may support in order to minimize the memory allocated for Tx
10708 * netdev_queue's. This number will be accurately calculated during the
10709 * initialization of bp->max_cos based on the chip versions AND chip
10710 * revision in the bnx2x_init_bp().
10711 */
10712 u8 max_cos_est = 0;
10713
10714 switch (ent->driver_data) {
10715 case BCM57710:
10716 case BCM57711:
10717 case BCM57711E:
10718 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10719 break;
10720
10721 case BCM57712:
10722 case BCM57712_MF:
10723 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10724 break;
10725
10726 case BCM57800:
10727 case BCM57800_MF:
10728 case BCM57810:
10729 case BCM57810_MF:
10730 case BCM57840:
10731 case BCM57840_MF:
10732 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10733 break;
10734
10735 default:
10736 pr_err("Unknown board_type (%ld), aborting\n",
10737 ent->driver_data);
10738 return -ENODEV;
10739 }
10740
10741 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10742
10743 /* !!! FIXME !!!
10744 * Do not allow the maximum SB count to grow above 16
10745 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10746 * We will use the FP_SB_MAX_E1x macro for this matter.
10747 */
10748 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10749
10750 WARN_ON(!max_non_def_sbs);
10751
10752 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10753 rss_count = max_non_def_sbs - CNIC_PRESENT;
10754
10755 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10756 rx_count = rss_count + FCOE_PRESENT;
10757
10758 /*
10759 * Maximum number of netdev Tx queues:
10760 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10761 */
10762 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10763
10764 /* dev zeroed in init_etherdev */
10765 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10766 if (!dev) {
10767 dev_err(&pdev->dev, "Cannot allocate net device\n");
10768 return -ENOMEM;
10769 }
10770
10771 bp = netdev_priv(dev);
10772
10773 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10774 tx_count, rx_count);
10775
10776 bp->igu_sb_cnt = max_non_def_sbs;
10777 bp->msg_enable = debug;
10778 pci_set_drvdata(pdev, dev);
10779
10780 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10781 if (rc < 0) {
10782 free_netdev(dev);
10783 return rc;
10784 }
10785
10786 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
10787
10788 rc = bnx2x_init_bp(bp);
10789 if (rc)
10790 goto init_one_exit;
10791
10792 /*
10793 * Map doorbels here as we need the real value of bp->max_cos which
10794 * is initialized in bnx2x_init_bp().
10795 */
10796 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10797 min_t(u64, BNX2X_DB_SIZE(bp),
10798 pci_resource_len(pdev, 2)));
10799 if (!bp->doorbells) {
10800 dev_err(&bp->pdev->dev,
10801 "Cannot map doorbell space, aborting\n");
10802 rc = -ENOMEM;
10803 goto init_one_exit;
10804 }
10805
10806 /* calc qm_cid_count */
10807 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10808
10809 #ifdef BCM_CNIC
10810 /* disable FCOE L2 queue for E1x and E3*/
10811 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10812 bp->flags |= NO_FCOE_FLAG;
10813
10814 #endif
10815
10816 /* Configure interrupt mode: try to enable MSI-X/MSI if
10817 * needed, set bp->num_queues appropriately.
10818 */
10819 bnx2x_set_int_mode(bp);
10820
10821 /* Add all NAPI objects */
10822 bnx2x_add_all_napi(bp);
10823
10824 rc = register_netdev(dev);
10825 if (rc) {
10826 dev_err(&pdev->dev, "Cannot register net device\n");
10827 goto init_one_exit;
10828 }
10829
10830 #ifdef BCM_CNIC
10831 if (!NO_FCOE(bp)) {
10832 /* Add storage MAC address */
10833 rtnl_lock();
10834 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10835 rtnl_unlock();
10836 }
10837 #endif
10838
10839 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10840
10841 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10842 board_info[ent->driver_data].name,
10843 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10844 pcie_width,
10845 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10846 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10847 "5GHz (Gen2)" : "2.5GHz",
10848 dev->base_addr, bp->pdev->irq, dev->dev_addr);
10849
10850 return 0;
10851
10852 init_one_exit:
10853 if (bp->regview)
10854 iounmap(bp->regview);
10855
10856 if (bp->doorbells)
10857 iounmap(bp->doorbells);
10858
10859 free_netdev(dev);
10860
10861 if (atomic_read(&pdev->enable_cnt) == 1)
10862 pci_release_regions(pdev);
10863
10864 pci_disable_device(pdev);
10865 pci_set_drvdata(pdev, NULL);
10866
10867 return rc;
10868 }
10869
10870 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10871 {
10872 struct net_device *dev = pci_get_drvdata(pdev);
10873 struct bnx2x *bp;
10874
10875 if (!dev) {
10876 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10877 return;
10878 }
10879 bp = netdev_priv(dev);
10880
10881 #ifdef BCM_CNIC
10882 /* Delete storage MAC address */
10883 if (!NO_FCOE(bp)) {
10884 rtnl_lock();
10885 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10886 rtnl_unlock();
10887 }
10888 #endif
10889
10890 #ifdef BCM_DCBNL
10891 /* Delete app tlvs from dcbnl */
10892 bnx2x_dcbnl_update_applist(bp, true);
10893 #endif
10894
10895 unregister_netdev(dev);
10896
10897 /* Delete all NAPI objects */
10898 bnx2x_del_all_napi(bp);
10899
10900 /* Power on: we can't let PCI layer write to us while we are in D3 */
10901 bnx2x_set_power_state(bp, PCI_D0);
10902
10903 /* Disable MSI/MSI-X */
10904 bnx2x_disable_msi(bp);
10905
10906 /* Power off */
10907 bnx2x_set_power_state(bp, PCI_D3hot);
10908
10909 /* Make sure RESET task is not scheduled before continuing */
10910 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10911
10912 if (bp->regview)
10913 iounmap(bp->regview);
10914
10915 if (bp->doorbells)
10916 iounmap(bp->doorbells);
10917
10918 bnx2x_free_mem_bp(bp);
10919
10920 free_netdev(dev);
10921
10922 if (atomic_read(&pdev->enable_cnt) == 1)
10923 pci_release_regions(pdev);
10924
10925 pci_disable_device(pdev);
10926 pci_set_drvdata(pdev, NULL);
10927 }
10928
10929 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10930 {
10931 int i;
10932
10933 bp->state = BNX2X_STATE_ERROR;
10934
10935 bp->rx_mode = BNX2X_RX_MODE_NONE;
10936
10937 #ifdef BCM_CNIC
10938 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10939 #endif
10940 /* Stop Tx */
10941 bnx2x_tx_disable(bp);
10942
10943 bnx2x_netif_stop(bp, 0);
10944
10945 del_timer_sync(&bp->timer);
10946
10947 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10948
10949 /* Release IRQs */
10950 bnx2x_free_irq(bp);
10951
10952 /* Free SKBs, SGEs, TPA pool and driver internals */
10953 bnx2x_free_skbs(bp);
10954
10955 for_each_rx_queue(bp, i)
10956 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10957
10958 bnx2x_free_mem(bp);
10959
10960 bp->state = BNX2X_STATE_CLOSED;
10961
10962 netif_carrier_off(bp->dev);
10963
10964 return 0;
10965 }
10966
10967 static void bnx2x_eeh_recover(struct bnx2x *bp)
10968 {
10969 u32 val;
10970
10971 mutex_init(&bp->port.phy_mutex);
10972
10973 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10974 bp->link_params.shmem_base = bp->common.shmem_base;
10975 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10976
10977 if (!bp->common.shmem_base ||
10978 (bp->common.shmem_base < 0xA0000) ||
10979 (bp->common.shmem_base >= 0xC0000)) {
10980 BNX2X_DEV_INFO("MCP not active\n");
10981 bp->flags |= NO_MCP_FLAG;
10982 return;
10983 }
10984
10985 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10986 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10987 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10988 BNX2X_ERR("BAD MCP validity signature\n");
10989
10990 if (!BP_NOMCP(bp)) {
10991 bp->fw_seq =
10992 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10993 DRV_MSG_SEQ_NUMBER_MASK);
10994 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10995 }
10996 }
10997
10998 /**
10999 * bnx2x_io_error_detected - called when PCI error is detected
11000 * @pdev: Pointer to PCI device
11001 * @state: The current pci connection state
11002 *
11003 * This function is called after a PCI bus error affecting
11004 * this device has been detected.
11005 */
11006 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11007 pci_channel_state_t state)
11008 {
11009 struct net_device *dev = pci_get_drvdata(pdev);
11010 struct bnx2x *bp = netdev_priv(dev);
11011
11012 rtnl_lock();
11013
11014 netif_device_detach(dev);
11015
11016 if (state == pci_channel_io_perm_failure) {
11017 rtnl_unlock();
11018 return PCI_ERS_RESULT_DISCONNECT;
11019 }
11020
11021 if (netif_running(dev))
11022 bnx2x_eeh_nic_unload(bp);
11023
11024 pci_disable_device(pdev);
11025
11026 rtnl_unlock();
11027
11028 /* Request a slot reset */
11029 return PCI_ERS_RESULT_NEED_RESET;
11030 }
11031
11032 /**
11033 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11034 * @pdev: Pointer to PCI device
11035 *
11036 * Restart the card from scratch, as if from a cold-boot.
11037 */
11038 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11039 {
11040 struct net_device *dev = pci_get_drvdata(pdev);
11041 struct bnx2x *bp = netdev_priv(dev);
11042
11043 rtnl_lock();
11044
11045 if (pci_enable_device(pdev)) {
11046 dev_err(&pdev->dev,
11047 "Cannot re-enable PCI device after reset\n");
11048 rtnl_unlock();
11049 return PCI_ERS_RESULT_DISCONNECT;
11050 }
11051
11052 pci_set_master(pdev);
11053 pci_restore_state(pdev);
11054
11055 if (netif_running(dev))
11056 bnx2x_set_power_state(bp, PCI_D0);
11057
11058 rtnl_unlock();
11059
11060 return PCI_ERS_RESULT_RECOVERED;
11061 }
11062
11063 /**
11064 * bnx2x_io_resume - called when traffic can start flowing again
11065 * @pdev: Pointer to PCI device
11066 *
11067 * This callback is called when the error recovery driver tells us that
11068 * its OK to resume normal operation.
11069 */
11070 static void bnx2x_io_resume(struct pci_dev *pdev)
11071 {
11072 struct net_device *dev = pci_get_drvdata(pdev);
11073 struct bnx2x *bp = netdev_priv(dev);
11074
11075 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11076 netdev_err(bp->dev, "Handling parity error recovery. "
11077 "Try again later\n");
11078 return;
11079 }
11080
11081 rtnl_lock();
11082
11083 bnx2x_eeh_recover(bp);
11084
11085 if (netif_running(dev))
11086 bnx2x_nic_load(bp, LOAD_NORMAL);
11087
11088 netif_device_attach(dev);
11089
11090 rtnl_unlock();
11091 }
11092
11093 static struct pci_error_handlers bnx2x_err_handler = {
11094 .error_detected = bnx2x_io_error_detected,
11095 .slot_reset = bnx2x_io_slot_reset,
11096 .resume = bnx2x_io_resume,
11097 };
11098
11099 static struct pci_driver bnx2x_pci_driver = {
11100 .name = DRV_MODULE_NAME,
11101 .id_table = bnx2x_pci_tbl,
11102 .probe = bnx2x_init_one,
11103 .remove = __devexit_p(bnx2x_remove_one),
11104 .suspend = bnx2x_suspend,
11105 .resume = bnx2x_resume,
11106 .err_handler = &bnx2x_err_handler,
11107 };
11108
11109 static int __init bnx2x_init(void)
11110 {
11111 int ret;
11112
11113 pr_info("%s", version);
11114
11115 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11116 if (bnx2x_wq == NULL) {
11117 pr_err("Cannot create workqueue\n");
11118 return -ENOMEM;
11119 }
11120
11121 ret = pci_register_driver(&bnx2x_pci_driver);
11122 if (ret) {
11123 pr_err("Cannot register driver\n");
11124 destroy_workqueue(bnx2x_wq);
11125 }
11126 return ret;
11127 }
11128
11129 static void __exit bnx2x_cleanup(void)
11130 {
11131 pci_unregister_driver(&bnx2x_pci_driver);
11132
11133 destroy_workqueue(bnx2x_wq);
11134 }
11135
11136 void bnx2x_notify_link_changed(struct bnx2x *bp)
11137 {
11138 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11139 }
11140
11141 module_init(bnx2x_init);
11142 module_exit(bnx2x_cleanup);
11143
11144 #ifdef BCM_CNIC
11145 /**
11146 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11147 *
11148 * @bp: driver handle
11149 * @set: set or clear the CAM entry
11150 *
11151 * This function will wait until the ramdord completion returns.
11152 * Return 0 if success, -ENODEV if ramrod doesn't return.
11153 */
11154 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11155 {
11156 unsigned long ramrod_flags = 0;
11157
11158 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11159 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11160 &bp->iscsi_l2_mac_obj, true,
11161 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11162 }
11163
11164 /* count denotes the number of new completions we have seen */
11165 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11166 {
11167 struct eth_spe *spe;
11168
11169 #ifdef BNX2X_STOP_ON_ERROR
11170 if (unlikely(bp->panic))
11171 return;
11172 #endif
11173
11174 spin_lock_bh(&bp->spq_lock);
11175 BUG_ON(bp->cnic_spq_pending < count);
11176 bp->cnic_spq_pending -= count;
11177
11178
11179 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11180 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11181 & SPE_HDR_CONN_TYPE) >>
11182 SPE_HDR_CONN_TYPE_SHIFT;
11183 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11184 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11185
11186 /* Set validation for iSCSI L2 client before sending SETUP
11187 * ramrod
11188 */
11189 if (type == ETH_CONNECTION_TYPE) {
11190 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11191 bnx2x_set_ctx_validation(bp, &bp->context.
11192 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11193 BNX2X_ISCSI_ETH_CID);
11194 }
11195
11196 /*
11197 * There may be not more than 8 L2, not more than 8 L5 SPEs
11198 * and in the air. We also check that number of outstanding
11199 * COMMON ramrods is not more than the EQ and SPQ can
11200 * accommodate.
11201 */
11202 if (type == ETH_CONNECTION_TYPE) {
11203 if (!atomic_read(&bp->cq_spq_left))
11204 break;
11205 else
11206 atomic_dec(&bp->cq_spq_left);
11207 } else if (type == NONE_CONNECTION_TYPE) {
11208 if (!atomic_read(&bp->eq_spq_left))
11209 break;
11210 else
11211 atomic_dec(&bp->eq_spq_left);
11212 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11213 (type == FCOE_CONNECTION_TYPE)) {
11214 if (bp->cnic_spq_pending >=
11215 bp->cnic_eth_dev.max_kwqe_pending)
11216 break;
11217 else
11218 bp->cnic_spq_pending++;
11219 } else {
11220 BNX2X_ERR("Unknown SPE type: %d\n", type);
11221 bnx2x_panic();
11222 break;
11223 }
11224
11225 spe = bnx2x_sp_get_next(bp);
11226 *spe = *bp->cnic_kwq_cons;
11227
11228 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11229 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11230
11231 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11232 bp->cnic_kwq_cons = bp->cnic_kwq;
11233 else
11234 bp->cnic_kwq_cons++;
11235 }
11236 bnx2x_sp_prod_update(bp);
11237 spin_unlock_bh(&bp->spq_lock);
11238 }
11239
11240 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11241 struct kwqe_16 *kwqes[], u32 count)
11242 {
11243 struct bnx2x *bp = netdev_priv(dev);
11244 int i;
11245
11246 #ifdef BNX2X_STOP_ON_ERROR
11247 if (unlikely(bp->panic))
11248 return -EIO;
11249 #endif
11250
11251 spin_lock_bh(&bp->spq_lock);
11252
11253 for (i = 0; i < count; i++) {
11254 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11255
11256 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11257 break;
11258
11259 *bp->cnic_kwq_prod = *spe;
11260
11261 bp->cnic_kwq_pending++;
11262
11263 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11264 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11265 spe->data.update_data_addr.hi,
11266 spe->data.update_data_addr.lo,
11267 bp->cnic_kwq_pending);
11268
11269 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11270 bp->cnic_kwq_prod = bp->cnic_kwq;
11271 else
11272 bp->cnic_kwq_prod++;
11273 }
11274
11275 spin_unlock_bh(&bp->spq_lock);
11276
11277 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11278 bnx2x_cnic_sp_post(bp, 0);
11279
11280 return i;
11281 }
11282
11283 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11284 {
11285 struct cnic_ops *c_ops;
11286 int rc = 0;
11287
11288 mutex_lock(&bp->cnic_mutex);
11289 c_ops = rcu_dereference_protected(bp->cnic_ops,
11290 lockdep_is_held(&bp->cnic_mutex));
11291 if (c_ops)
11292 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11293 mutex_unlock(&bp->cnic_mutex);
11294
11295 return rc;
11296 }
11297
11298 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11299 {
11300 struct cnic_ops *c_ops;
11301 int rc = 0;
11302
11303 rcu_read_lock();
11304 c_ops = rcu_dereference(bp->cnic_ops);
11305 if (c_ops)
11306 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11307 rcu_read_unlock();
11308
11309 return rc;
11310 }
11311
11312 /*
11313 * for commands that have no data
11314 */
11315 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11316 {
11317 struct cnic_ctl_info ctl = {0};
11318
11319 ctl.cmd = cmd;
11320
11321 return bnx2x_cnic_ctl_send(bp, &ctl);
11322 }
11323
11324 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11325 {
11326 struct cnic_ctl_info ctl = {0};
11327
11328 /* first we tell CNIC and only then we count this as a completion */
11329 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11330 ctl.data.comp.cid = cid;
11331 ctl.data.comp.error = err;
11332
11333 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11334 bnx2x_cnic_sp_post(bp, 0);
11335 }
11336
11337
11338 /* Called with netif_addr_lock_bh() taken.
11339 * Sets an rx_mode config for an iSCSI ETH client.
11340 * Doesn't block.
11341 * Completion should be checked outside.
11342 */
11343 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11344 {
11345 unsigned long accept_flags = 0, ramrod_flags = 0;
11346 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11347 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11348
11349 if (start) {
11350 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11351 * because it's the only way for UIO Queue to accept
11352 * multicasts (in non-promiscuous mode only one Queue per
11353 * function will receive multicast packets (leading in our
11354 * case).
11355 */
11356 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11357 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11358 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11359 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11360
11361 /* Clear STOP_PENDING bit if START is requested */
11362 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11363
11364 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11365 } else
11366 /* Clear START_PENDING bit if STOP is requested */
11367 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11368
11369 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11370 set_bit(sched_state, &bp->sp_state);
11371 else {
11372 __set_bit(RAMROD_RX, &ramrod_flags);
11373 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11374 ramrod_flags);
11375 }
11376 }
11377
11378
11379 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11380 {
11381 struct bnx2x *bp = netdev_priv(dev);
11382 int rc = 0;
11383
11384 switch (ctl->cmd) {
11385 case DRV_CTL_CTXTBL_WR_CMD: {
11386 u32 index = ctl->data.io.offset;
11387 dma_addr_t addr = ctl->data.io.dma_addr;
11388
11389 bnx2x_ilt_wr(bp, index, addr);
11390 break;
11391 }
11392
11393 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11394 int count = ctl->data.credit.credit_count;
11395
11396 bnx2x_cnic_sp_post(bp, count);
11397 break;
11398 }
11399
11400 /* rtnl_lock is held. */
11401 case DRV_CTL_START_L2_CMD: {
11402 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11403 unsigned long sp_bits = 0;
11404
11405 /* Configure the iSCSI classification object */
11406 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11407 cp->iscsi_l2_client_id,
11408 cp->iscsi_l2_cid, BP_FUNC(bp),
11409 bnx2x_sp(bp, mac_rdata),
11410 bnx2x_sp_mapping(bp, mac_rdata),
11411 BNX2X_FILTER_MAC_PENDING,
11412 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11413 &bp->macs_pool);
11414
11415 /* Set iSCSI MAC address */
11416 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11417 if (rc)
11418 break;
11419
11420 mmiowb();
11421 barrier();
11422
11423 /* Start accepting on iSCSI L2 ring */
11424
11425 netif_addr_lock_bh(dev);
11426 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11427 netif_addr_unlock_bh(dev);
11428
11429 /* bits to wait on */
11430 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11431 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11432
11433 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11434 BNX2X_ERR("rx_mode completion timed out!\n");
11435
11436 break;
11437 }
11438
11439 /* rtnl_lock is held. */
11440 case DRV_CTL_STOP_L2_CMD: {
11441 unsigned long sp_bits = 0;
11442
11443 /* Stop accepting on iSCSI L2 ring */
11444 netif_addr_lock_bh(dev);
11445 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11446 netif_addr_unlock_bh(dev);
11447
11448 /* bits to wait on */
11449 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11450 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11451
11452 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11453 BNX2X_ERR("rx_mode completion timed out!\n");
11454
11455 mmiowb();
11456 barrier();
11457
11458 /* Unset iSCSI L2 MAC */
11459 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11460 BNX2X_ISCSI_ETH_MAC, true);
11461 break;
11462 }
11463 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11464 int count = ctl->data.credit.credit_count;
11465
11466 smp_mb__before_atomic_inc();
11467 atomic_add(count, &bp->cq_spq_left);
11468 smp_mb__after_atomic_inc();
11469 break;
11470 }
11471
11472 default:
11473 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11474 rc = -EINVAL;
11475 }
11476
11477 return rc;
11478 }
11479
11480 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11481 {
11482 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11483
11484 if (bp->flags & USING_MSIX_FLAG) {
11485 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11486 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11487 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11488 } else {
11489 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11490 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11491 }
11492 if (!CHIP_IS_E1x(bp))
11493 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11494 else
11495 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11496
11497 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11498 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11499 cp->irq_arr[1].status_blk = bp->def_status_blk;
11500 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11501 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11502
11503 cp->num_irq = 2;
11504 }
11505
11506 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11507 void *data)
11508 {
11509 struct bnx2x *bp = netdev_priv(dev);
11510 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11511
11512 if (ops == NULL)
11513 return -EINVAL;
11514
11515 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11516 if (!bp->cnic_kwq)
11517 return -ENOMEM;
11518
11519 bp->cnic_kwq_cons = bp->cnic_kwq;
11520 bp->cnic_kwq_prod = bp->cnic_kwq;
11521 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11522
11523 bp->cnic_spq_pending = 0;
11524 bp->cnic_kwq_pending = 0;
11525
11526 bp->cnic_data = data;
11527
11528 cp->num_irq = 0;
11529 cp->drv_state |= CNIC_DRV_STATE_REGD;
11530 cp->iro_arr = bp->iro_arr;
11531
11532 bnx2x_setup_cnic_irq_info(bp);
11533
11534 rcu_assign_pointer(bp->cnic_ops, ops);
11535
11536 return 0;
11537 }
11538
11539 static int bnx2x_unregister_cnic(struct net_device *dev)
11540 {
11541 struct bnx2x *bp = netdev_priv(dev);
11542 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11543
11544 mutex_lock(&bp->cnic_mutex);
11545 cp->drv_state = 0;
11546 rcu_assign_pointer(bp->cnic_ops, NULL);
11547 mutex_unlock(&bp->cnic_mutex);
11548 synchronize_rcu();
11549 kfree(bp->cnic_kwq);
11550 bp->cnic_kwq = NULL;
11551
11552 return 0;
11553 }
11554
11555 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11556 {
11557 struct bnx2x *bp = netdev_priv(dev);
11558 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11559
11560 /* If both iSCSI and FCoE are disabled - return NULL in
11561 * order to indicate CNIC that it should not try to work
11562 * with this device.
11563 */
11564 if (NO_ISCSI(bp) && NO_FCOE(bp))
11565 return NULL;
11566
11567 cp->drv_owner = THIS_MODULE;
11568 cp->chip_id = CHIP_ID(bp);
11569 cp->pdev = bp->pdev;
11570 cp->io_base = bp->regview;
11571 cp->io_base2 = bp->doorbells;
11572 cp->max_kwqe_pending = 8;
11573 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11574 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11575 bnx2x_cid_ilt_lines(bp);
11576 cp->ctx_tbl_len = CNIC_ILT_LINES;
11577 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11578 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11579 cp->drv_ctl = bnx2x_drv_ctl;
11580 cp->drv_register_cnic = bnx2x_register_cnic;
11581 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11582 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11583 cp->iscsi_l2_client_id =
11584 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11585 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11586
11587 if (NO_ISCSI_OOO(bp))
11588 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11589
11590 if (NO_ISCSI(bp))
11591 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11592
11593 if (NO_FCOE(bp))
11594 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11595
11596 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11597 "starting cid %d\n",
11598 cp->ctx_blk_size,
11599 cp->ctx_tbl_offset,
11600 cp->ctx_tbl_len,
11601 cp->starting_cid);
11602 return cp;
11603 }
11604 EXPORT_SYMBOL(bnx2x_cnic_probe);
11605
11606 #endif /* BCM_CNIC */
11607
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree