| blob | 88082ac6f2cdb6dce7ea8b8e8c37fdaa85f730bf |
1 /*
2 * MPC8544 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 / {
13 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 PowerPC,8544@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>;
31 bus-frequency = <0>;
32 clock-frequency = <0>;
33 };
34 };
36 memory {
37 device_type = "memory";
38 reg = <00000000 00000000>; // Filled by U-Boot
39 };
41 soc8544@e0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 device_type = "soc";
47 ranges = <00001000 e0001000 000ff000
48 80000000 80000000 20000000
49 a0000000 a0000000 10000000
50 b0000000 b0000000 00100000
51 c0000000 c0000000 20000000
52 b0100000 b0100000 00100000
53 e1000000 e1000000 00010000
54 e1010000 e1010000 00010000
55 e1020000 e1020000 00010000>;
56 reg = <e0000000 00001000>; // CCSRBAR 1M
57 bus-frequency = <0>; // Filled out by uboot.
59 memory-controller@2000 {
60 compatible = "fsl,8544-memory-controller";
61 reg = <2000 1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <12 2>;
64 };
66 l2-cache-controller@20000 {
67 compatible = "fsl,8544-l2-cache-controller";
68 reg = <20000 1000>;
69 cache-line-size = <20>; // 32 bytes
70 cache-size = <40000>; // L2, 256K
71 interrupt-parent = <&mpic>;
72 interrupts = <10 2>;
73 };
75 i2c@3000 {
76 device_type = "i2c";
77 compatible = "fsl-i2c";
78 reg = <3000 100>;
79 interrupts = <2b 2>;
80 interrupt-parent = <&mpic>;
81 dfsrr;
82 };
84 mdio@24520 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 device_type = "mdio";
88 compatible = "gianfar";
89 reg = <24520 20>;
90 phy0: ethernet-phy@0 {
91 interrupt-parent = <&mpic>;
92 interrupts = <a 1>;
93 reg = <0>;
94 device_type = "ethernet-phy";
95 };
96 phy1: ethernet-phy@1 {
97 interrupt-parent = <&mpic>;
98 interrupts = <a 1>;
99 reg = <1>;
100 device_type = "ethernet-phy";
101 };
102 };
104 ethernet@24000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 device_type = "network";
108 model = "TSEC";
109 compatible = "gianfar";
110 reg = <24000 1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>;
113 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>;
115 phy-connection-type = "rgmii-id";
116 };
118 ethernet@26000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 device_type = "network";
122 model = "TSEC";
123 compatible = "gianfar";
124 reg = <26000 1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <1f 2 20 2 21 2>;
127 interrupt-parent = <&mpic>;
128 phy-handle = <&phy1>;
129 phy-connection-type = "rgmii-id";
130 };
132 serial@4500 {
133 device_type = "serial";
134 compatible = "ns16550";
135 reg = <4500 100>;
136 clock-frequency = <0>;
137 interrupts = <2a 2>;
138 interrupt-parent = <&mpic>;
139 };
141 serial@4600 {
142 device_type = "serial";
143 compatible = "ns16550";
144 reg = <4600 100>;
145 clock-frequency = <0>;
146 interrupts = <2a 2>;
147 interrupt-parent = <&mpic>;
148 };
150 pci@8000 {
151 compatible = "fsl,mpc8540-pci";
152 device_type = "pci";
153 interrupt-map-mask = <f800 0 0 7>;
154 interrupt-map = <
156 /* IDSEL 0x11 J17 Slot 1 */
157 8800 0 0 1 &mpic 2 1
158 8800 0 0 2 &mpic 3 1
159 8800 0 0 3 &mpic 4 1
160 8800 0 0 4 &mpic 1 1
162 /* IDSEL 0x12 J16 Slot 2 */
164 9000 0 0 1 &mpic 3 1
165 9000 0 0 2 &mpic 4 1
166 9000 0 0 3 &mpic 2 1
167 9000 0 0 4 &mpic 1 1>;
169 interrupt-parent = <&mpic>;
170 interrupts = <18 2>;
171 bus-range = <0 ff>;
172 ranges = <02000000 0 c0000000 c0000000 0 20000000
173 01000000 0 00000000 e1000000 0 00010000>;
174 clock-frequency = <3f940aa>;
175 #interrupt-cells = <1>;
176 #size-cells = <2>;
177 #address-cells = <3>;
178 reg = <8000 1000>;
179 };
181 pcie@9000 {
182 compatible = "fsl,mpc8548-pcie";
183 device_type = "pci";
184 #interrupt-cells = <1>;
185 #size-cells = <2>;
186 #address-cells = <3>;
187 reg = <9000 1000>;
188 bus-range = <0 ff>;
189 ranges = <02000000 0 80000000 80000000 0 20000000
190 01000000 0 00000000 e1010000 0 00010000>;
191 clock-frequency = <1fca055>;
192 interrupt-parent = <&mpic>;
193 interrupts = <1a 2>;
194 interrupt-map-mask = <f800 0 0 7>;
195 interrupt-map = <
196 /* IDSEL 0x0 */
197 0000 0 0 1 &mpic 4 1
198 0000 0 0 2 &mpic 5 1
199 0000 0 0 3 &mpic 6 1
200 0000 0 0 4 &mpic 7 1
201 >;
202 };
204 pcie@a000 {
205 compatible = "fsl,mpc8548-pcie";
206 device_type = "pci";
207 #interrupt-cells = <1>;
208 #size-cells = <2>;
209 #address-cells = <3>;
210 reg = <a000 1000>;
211 bus-range = <0 ff>;
212 ranges = <02000000 0 a0000000 a0000000 0 10000000
213 01000000 0 00000000 e1020000 0 00010000>;
214 clock-frequency = <1fca055>;
215 interrupt-parent = <&mpic>;
216 interrupts = <19 2>;
217 interrupt-map-mask = <f800 0 0 7>;
218 interrupt-map = <
219 /* IDSEL 0x0 */
220 0000 0 0 1 &mpic 0 1
221 0000 0 0 2 &mpic 1 1
222 0000 0 0 3 &mpic 2 1
223 0000 0 0 4 &mpic 3 1
224 >;
225 };
227 pcie@b000 {
228 compatible = "fsl,mpc8548-pcie";
229 device_type = "pci";
230 #interrupt-cells = <1>;
231 #size-cells = <2>;
232 #address-cells = <3>;
233 reg = <b000 1000>;
234 bus-range = <0 ff>;
235 ranges = <02000000 0 b0000000 b0000000 0 00100000
236 01000000 0 00000000 b0100000 0 00100000>;
237 clock-frequency = <1fca055>;
238 interrupt-parent = <&mpic>;
239 interrupts = <1b 2>;
240 interrupt-map-mask = <fb00 0 0 0>;
241 interrupt-map = <
242 // IDSEL 0x1c USB
243 e000 0 0 0 &i8259 c 2
244 e100 0 0 0 &i8259 9 2
245 e200 0 0 0 &i8259 a 2
246 e300 0 0 0 &i8259 b 2
248 // IDSEL 0x1d Audio
249 e800 0 0 0 &i8259 6 2
251 // IDSEL 0x1e Legacy
252 f000 0 0 0 &i8259 7 2
253 f100 0 0 0 &i8259 7 2
255 // IDSEL 0x1f IDE/SATA
256 f800 0 0 0 &i8259 e 2
257 f900 0 0 0 &i8259 5 2
258 >;
259 uli1575@0 {
260 reg = <0 0 0 0 0>;
261 #size-cells = <2>;
262 #address-cells = <3>;
263 ranges = <02000000 0 b0000000
264 02000000 0 b0000000
265 0 00100000
266 01000000 0 00000000
267 01000000 0 00000000
268 0 00100000>;
270 pci_bridge@0 {
271 reg = <0 0 0 0 0>;
272 #size-cells = <2>;
273 #address-cells = <3>;
274 ranges = <02000000 0 b0000000
275 02000000 0 b0000000
276 0 00100000
277 01000000 0 00000000
278 01000000 0 00000000
279 0 00100000>;
281 isa@1e {
282 device_type = "isa";
283 #interrupt-cells = <2>;
284 #size-cells = <1>;
285 #address-cells = <2>;
286 reg = <f000 0 0 0 0>;
287 ranges = <1 0
288 01000000 0 0
289 00001000>;
290 interrupt-parent = <&i8259>;
292 i8259: interrupt-controller@20 {
293 reg = <1 20 2
294 1 a0 2
295 1 4d0 2>;
296 interrupt-controller;
297 device_type = "interrupt-controller";
298 #address-cells = <0>;
299 #interrupt-cells = <2>;
300 compatible = "chrp,iic";
301 interrupts = <9 2>;
302 interrupt-parent = <&mpic>;
303 };
305 i8042@60 {
306 #size-cells = <0>;
307 #address-cells = <1>;
308 reg = <1 60 1 1 64 1>;
309 interrupts = <1 3 c 3>;
310 interrupt-parent = <&i8259>;
312 keyboard@0 {
313 reg = <0>;
314 compatible = "pnpPNP,303";
315 };
317 mouse@1 {
318 reg = <1>;
319 compatible = "pnpPNP,f03";
320 };
321 };
323 rtc@70 {
324 compatible = "pnpPNP,b00";
325 reg = <1 70 2>;
326 };
328 gpio@400 {
329 reg = <1 400 80>;
330 };
331 };
332 };
333 };
335 };
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,mpc8548-guts";
339 reg = <e0000 1000>;
340 fsl,has-rstcr;
341 };
343 mpic: pic@40000 {
344 clock-frequency = <0>;
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
348 reg = <40000 40000>;
349 compatible = "chrp,open-pic";
350 device_type = "open-pic";
351 big-endian;
352 };
353 };
354 };