2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pci-aspm.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit
= 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
94 RTL_GIGA_MAC_NONE
= 0x00,
95 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
96 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask
; /* Clears the bits supported by this chip */
131 } rtl_chip_info
[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device
*);
169 static void rtl_hw_start_8168(struct net_device
*);
170 static void rtl_hw_start_8101(struct net_device
*);
172 static struct pci_device_id rtl8169_pci_tbl
[] = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
181 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
182 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
184 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
188 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
195 static int rx_copybreak
= 16383;
202 MAC0
= 0, /* Ethernet hardware address. */
204 MAR0
= 8, /* Multicast filter. */
205 CounterAddrLow
= 0x10,
206 CounterAddrHigh
= 0x14,
207 TxDescStartAddrLow
= 0x20,
208 TxDescStartAddrHigh
= 0x24,
209 TxHDescStartAddrLow
= 0x28,
210 TxHDescStartAddrHigh
= 0x2c,
233 RxDescAddrLow
= 0xe4,
234 RxDescAddrHigh
= 0xe8,
237 FuncEventMask
= 0xf4,
238 FuncPresetState
= 0xf8,
239 FuncForceEvent
= 0xfc,
242 enum rtl8110_registers
{
248 enum rtl8168_8101_registers
{
251 #define CSIAR_FLAG 0x80000000
252 #define CSIAR_WRITE_CMD 0x80000000
253 #define CSIAR_BYTE_ENABLE 0x0f
254 #define CSIAR_BYTE_ENABLE_SHIFT 12
255 #define CSIAR_ADDR_MASK 0x0fff
258 #define EPHYAR_FLAG 0x80000000
259 #define EPHYAR_WRITE_CMD 0x80000000
260 #define EPHYAR_REG_MASK 0x1f
261 #define EPHYAR_REG_SHIFT 16
262 #define EPHYAR_DATA_MASK 0xffff
264 #define FIX_NAK_1 (1 << 4)
265 #define FIX_NAK_2 (1 << 3)
267 #define EFUSEAR_FLAG 0x80000000
268 #define EFUSEAR_WRITE_CMD 0x80000000
269 #define EFUSEAR_READ_CMD 0x00000000
270 #define EFUSEAR_REG_MASK 0x03ff
271 #define EFUSEAR_REG_SHIFT 8
272 #define EFUSEAR_DATA_MASK 0xff
275 enum rtl_register_content
{
276 /* InterruptStatusBits */
280 TxDescUnavail
= 0x0080,
302 /* TXPoll register p.5 */
303 HPQ
= 0x80, /* Poll cmd on the high prio queue */
304 NPQ
= 0x40, /* Poll cmd on the low prio queue */
305 FSWInt
= 0x01, /* Forced software interrupt */
309 Cfg9346_Unlock
= 0xc0,
314 AcceptBroadcast
= 0x08,
315 AcceptMulticast
= 0x04,
317 AcceptAllPhys
= 0x01,
324 TxInterFrameGapShift
= 24,
325 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
327 /* Config1 register p.24 */
330 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
331 Speed_down
= (1 << 4),
335 PMEnable
= (1 << 0), /* Power Management Enable */
337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz
= 0x01,
339 PCI_Clock_33MHz
= 0x00,
341 /* Config3 register p.25 */
342 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
344 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
346 /* Config5 register p.27 */
347 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
349 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake
= (1 << 1), /* LanWake enable/disable */
351 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
354 TBIReset
= 0x80000000,
355 TBILoopback
= 0x40000000,
356 TBINwEnable
= 0x20000000,
357 TBINwRestart
= 0x10000000,
358 TBILinkOk
= 0x02000000,
359 TBINwComplete
= 0x01000000,
362 EnableBist
= (1 << 15), // 8168 8101
363 Mac_dbgo_oe
= (1 << 14), // 8168 8101
364 Normal_mode
= (1 << 13), // unused
365 Force_half_dup
= (1 << 12), // 8168 8101
366 Force_rxflow_en
= (1 << 11), // 8168 8101
367 Force_txflow_en
= (1 << 10), // 8168 8101
368 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
369 ASF
= (1 << 8), // 8168 8101
370 PktCntrDisable
= (1 << 7), // 8168 8101
371 Mac_dbgo_sel
= 0x001c, // 8168
376 INTT_0
= 0x0000, // 8168
377 INTT_1
= 0x0001, // 8168
378 INTT_2
= 0x0002, // 8168
379 INTT_3
= 0x0003, // 8168
381 /* rtl8169_PHYstatus */
392 TBILinkOK
= 0x02000000,
394 /* DumpCounterCommand */
398 enum desc_status_bit
{
399 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd
= (1 << 30), /* End of descriptor ring */
401 FirstFrag
= (1 << 29), /* First segment of a packet */
402 LastFrag
= (1 << 28), /* Final segment of a packet */
405 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift
= 16, /* MSS value position */
407 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS
= (1 << 18), /* Calculate IP checksum */
409 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag
= (1 << 17), /* Add VLAN tag */
414 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
415 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
417 #define RxProtoUDP (PID1)
418 #define RxProtoTCP (PID0)
419 #define RxProtoIP (PID1 | PID0)
420 #define RxProtoMask RxProtoIP
422 IPFail
= (1 << 16), /* IP checksum failed */
423 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
424 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag
= (1 << 16), /* VLAN tag available */
428 #define RsvdMask 0x3fffc000
445 u8 __pad
[sizeof(void *) - sizeof(u32
)];
449 RTL_FEATURE_WOL
= (1 << 0),
450 RTL_FEATURE_MSI
= (1 << 1),
451 RTL_FEATURE_GMII
= (1 << 2),
454 struct rtl8169_counters
{
461 __le32 tx_one_collision
;
462 __le32 tx_multi_collision
;
470 struct rtl8169_private
{
471 void __iomem
*mmio_addr
; /* memory map physical address */
472 struct pci_dev
*pci_dev
; /* Index of PCI device */
473 struct net_device
*dev
;
474 struct napi_struct napi
;
475 spinlock_t lock
; /* spin lock flag */
479 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
483 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
484 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr
;
486 dma_addr_t RxPhyAddr
;
487 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
488 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
491 struct timer_list timer
;
496 int phy_1000_ctrl_reg
;
497 #ifdef CONFIG_R8169_VLAN
498 struct vlan_group
*vlgrp
;
500 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
501 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
502 void (*phy_reset_enable
)(void __iomem
*);
503 void (*hw_start
)(struct net_device
*);
504 unsigned int (*phy_reset_pending
)(void __iomem
*);
505 unsigned int (*link_ok
)(void __iomem
*);
506 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
508 struct delayed_work task
;
511 struct mii_if_info mii
;
512 struct rtl8169_counters counters
;
515 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
516 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
517 module_param(rx_copybreak
, int, 0);
518 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
519 module_param(use_dac
, int, 0);
520 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
521 module_param_named(debug
, debug
.msg_enable
, int, 0);
522 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
523 MODULE_LICENSE("GPL");
524 MODULE_VERSION(RTL8169_VERSION
);
526 static int rtl8169_open(struct net_device
*dev
);
527 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
528 struct net_device
*dev
);
529 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
530 static int rtl8169_init_ring(struct net_device
*dev
);
531 static void rtl_hw_start(struct net_device
*dev
);
532 static int rtl8169_close(struct net_device
*dev
);
533 static void rtl_set_rx_mode(struct net_device
*dev
);
534 static void rtl8169_tx_timeout(struct net_device
*dev
);
535 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
536 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
537 void __iomem
*, u32 budget
);
538 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
539 static void rtl8169_down(struct net_device
*dev
);
540 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
541 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
543 static const unsigned int rtl8169_rx_config
=
544 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
546 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
550 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
552 for (i
= 20; i
> 0; i
--) {
554 * Check if the RTL8169 has completed writing to the specified
557 if (!(RTL_R32(PHYAR
) & 0x80000000))
562 * According to hardware specs a 20us delay is required after write
563 * complete indication, but before sending next command.
568 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
572 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
574 for (i
= 20; i
> 0; i
--) {
576 * Check if the RTL8169 has completed retrieving data from
577 * the specified MII register.
579 if (RTL_R32(PHYAR
) & 0x80000000) {
580 value
= RTL_R32(PHYAR
) & 0xffff;
586 * According to hardware specs a 20us delay is required after read
587 * complete indication, but before sending next command.
594 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
596 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
599 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
603 val
= mdio_read(ioaddr
, reg_addr
);
604 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
607 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
610 struct rtl8169_private
*tp
= netdev_priv(dev
);
611 void __iomem
*ioaddr
= tp
->mmio_addr
;
613 mdio_write(ioaddr
, location
, val
);
616 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
618 struct rtl8169_private
*tp
= netdev_priv(dev
);
619 void __iomem
*ioaddr
= tp
->mmio_addr
;
621 return mdio_read(ioaddr
, location
);
624 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
628 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
629 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
631 for (i
= 0; i
< 100; i
++) {
632 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
638 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
643 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
645 for (i
= 0; i
< 100; i
++) {
646 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
647 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
656 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
660 RTL_W32(CSIDR
, value
);
661 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
662 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
664 for (i
= 0; i
< 100; i
++) {
665 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
671 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
676 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
677 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
679 for (i
= 0; i
< 100; i
++) {
680 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
681 value
= RTL_R32(CSIDR
);
690 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
695 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
697 for (i
= 0; i
< 300; i
++) {
698 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
699 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
708 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
710 RTL_W16(IntrMask
, 0x0000);
712 RTL_W16(IntrStatus
, 0xffff);
715 static void rtl8169_asic_down(void __iomem
*ioaddr
)
717 RTL_W8(ChipCmd
, 0x00);
718 rtl8169_irq_mask_and_ack(ioaddr
);
722 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
724 return RTL_R32(TBICSR
) & TBIReset
;
727 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
729 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
732 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
734 return RTL_R32(TBICSR
) & TBILinkOk
;
737 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
739 return RTL_R8(PHYstatus
) & LinkStatus
;
742 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
744 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
747 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
751 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
752 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
755 static void rtl8169_check_link_status(struct net_device
*dev
,
756 struct rtl8169_private
*tp
,
757 void __iomem
*ioaddr
)
761 spin_lock_irqsave(&tp
->lock
, flags
);
762 if (tp
->link_ok(ioaddr
)) {
763 netif_carrier_on(dev
);
764 if (netif_msg_ifup(tp
))
765 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
767 if (netif_msg_ifdown(tp
))
768 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
769 netif_carrier_off(dev
);
771 spin_unlock_irqrestore(&tp
->lock
, flags
);
774 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
776 struct rtl8169_private
*tp
= netdev_priv(dev
);
777 void __iomem
*ioaddr
= tp
->mmio_addr
;
782 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
783 wol
->supported
= WAKE_ANY
;
785 spin_lock_irq(&tp
->lock
);
787 options
= RTL_R8(Config1
);
788 if (!(options
& PMEnable
))
791 options
= RTL_R8(Config3
);
792 if (options
& LinkUp
)
793 wol
->wolopts
|= WAKE_PHY
;
794 if (options
& MagicPacket
)
795 wol
->wolopts
|= WAKE_MAGIC
;
797 options
= RTL_R8(Config5
);
799 wol
->wolopts
|= WAKE_UCAST
;
801 wol
->wolopts
|= WAKE_BCAST
;
803 wol
->wolopts
|= WAKE_MCAST
;
806 spin_unlock_irq(&tp
->lock
);
809 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
811 struct rtl8169_private
*tp
= netdev_priv(dev
);
812 void __iomem
*ioaddr
= tp
->mmio_addr
;
819 { WAKE_ANY
, Config1
, PMEnable
},
820 { WAKE_PHY
, Config3
, LinkUp
},
821 { WAKE_MAGIC
, Config3
, MagicPacket
},
822 { WAKE_UCAST
, Config5
, UWF
},
823 { WAKE_BCAST
, Config5
, BWF
},
824 { WAKE_MCAST
, Config5
, MWF
},
825 { WAKE_ANY
, Config5
, LanWake
}
828 spin_lock_irq(&tp
->lock
);
830 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
832 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
833 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
834 if (wol
->wolopts
& cfg
[i
].opt
)
835 options
|= cfg
[i
].mask
;
836 RTL_W8(cfg
[i
].reg
, options
);
839 RTL_W8(Cfg9346
, Cfg9346_Lock
);
842 tp
->features
|= RTL_FEATURE_WOL
;
844 tp
->features
&= ~RTL_FEATURE_WOL
;
845 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
847 spin_unlock_irq(&tp
->lock
);
852 static void rtl8169_get_drvinfo(struct net_device
*dev
,
853 struct ethtool_drvinfo
*info
)
855 struct rtl8169_private
*tp
= netdev_priv(dev
);
857 strcpy(info
->driver
, MODULENAME
);
858 strcpy(info
->version
, RTL8169_VERSION
);
859 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
862 static int rtl8169_get_regs_len(struct net_device
*dev
)
864 return R8169_REGS_SIZE
;
867 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
868 u8 autoneg
, u16 speed
, u8 duplex
)
870 struct rtl8169_private
*tp
= netdev_priv(dev
);
871 void __iomem
*ioaddr
= tp
->mmio_addr
;
875 reg
= RTL_R32(TBICSR
);
876 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
877 (duplex
== DUPLEX_FULL
)) {
878 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
879 } else if (autoneg
== AUTONEG_ENABLE
)
880 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
882 if (netif_msg_link(tp
)) {
883 printk(KERN_WARNING
"%s: "
884 "incorrect speed setting refused in TBI mode\n",
893 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
894 u8 autoneg
, u16 speed
, u8 duplex
)
896 struct rtl8169_private
*tp
= netdev_priv(dev
);
897 void __iomem
*ioaddr
= tp
->mmio_addr
;
900 if (autoneg
== AUTONEG_ENABLE
) {
903 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
904 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
905 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
906 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
908 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
909 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
911 /* The 8100e/8101e/8102e do Fast Ethernet only. */
912 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
913 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
914 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
915 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
916 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
917 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
918 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
919 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
920 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
921 } else if (netif_msg_link(tp
)) {
922 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
926 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
928 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
929 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
930 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
933 * Vendor specific (0x1f) and reserved (0x0e) MII
936 mdio_write(ioaddr
, 0x1f, 0x0000);
937 mdio_write(ioaddr
, 0x0e, 0x0000);
940 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
941 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
945 if (speed
== SPEED_10
)
947 else if (speed
== SPEED_100
)
948 bmcr
= BMCR_SPEED100
;
952 if (duplex
== DUPLEX_FULL
)
953 bmcr
|= BMCR_FULLDPLX
;
955 mdio_write(ioaddr
, 0x1f, 0x0000);
958 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
960 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
962 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
963 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
964 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
965 mdio_write(ioaddr
, 0x17, 0x2138);
966 mdio_write(ioaddr
, 0x0e, 0x0260);
968 mdio_write(ioaddr
, 0x17, 0x2108);
969 mdio_write(ioaddr
, 0x0e, 0x0000);
976 static int rtl8169_set_speed(struct net_device
*dev
,
977 u8 autoneg
, u16 speed
, u8 duplex
)
979 struct rtl8169_private
*tp
= netdev_priv(dev
);
982 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
984 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
985 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
990 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
992 struct rtl8169_private
*tp
= netdev_priv(dev
);
996 spin_lock_irqsave(&tp
->lock
, flags
);
997 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
998 spin_unlock_irqrestore(&tp
->lock
, flags
);
1003 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1005 struct rtl8169_private
*tp
= netdev_priv(dev
);
1007 return tp
->cp_cmd
& RxChkSum
;
1010 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1012 struct rtl8169_private
*tp
= netdev_priv(dev
);
1013 void __iomem
*ioaddr
= tp
->mmio_addr
;
1014 unsigned long flags
;
1016 spin_lock_irqsave(&tp
->lock
, flags
);
1019 tp
->cp_cmd
|= RxChkSum
;
1021 tp
->cp_cmd
&= ~RxChkSum
;
1023 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1026 spin_unlock_irqrestore(&tp
->lock
, flags
);
1031 #ifdef CONFIG_R8169_VLAN
1033 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1034 struct sk_buff
*skb
)
1036 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
1037 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1040 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1041 struct vlan_group
*grp
)
1043 struct rtl8169_private
*tp
= netdev_priv(dev
);
1044 void __iomem
*ioaddr
= tp
->mmio_addr
;
1045 unsigned long flags
;
1047 spin_lock_irqsave(&tp
->lock
, flags
);
1050 * Do not disable RxVlan on 8110SCd.
1052 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1053 tp
->cp_cmd
|= RxVlan
;
1055 tp
->cp_cmd
&= ~RxVlan
;
1056 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1058 spin_unlock_irqrestore(&tp
->lock
, flags
);
1061 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1062 struct sk_buff
*skb
)
1064 u32 opts2
= le32_to_cpu(desc
->opts2
);
1065 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1068 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1069 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1077 #else /* !CONFIG_R8169_VLAN */
1079 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1080 struct sk_buff
*skb
)
1085 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1086 struct sk_buff
*skb
)
1093 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1095 struct rtl8169_private
*tp
= netdev_priv(dev
);
1096 void __iomem
*ioaddr
= tp
->mmio_addr
;
1100 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1101 cmd
->port
= PORT_FIBRE
;
1102 cmd
->transceiver
= XCVR_INTERNAL
;
1104 status
= RTL_R32(TBICSR
);
1105 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1106 cmd
->autoneg
= !!(status
& TBINwEnable
);
1108 cmd
->speed
= SPEED_1000
;
1109 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1114 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1116 struct rtl8169_private
*tp
= netdev_priv(dev
);
1118 return mii_ethtool_gset(&tp
->mii
, cmd
);
1121 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1123 struct rtl8169_private
*tp
= netdev_priv(dev
);
1124 unsigned long flags
;
1127 spin_lock_irqsave(&tp
->lock
, flags
);
1129 rc
= tp
->get_settings(dev
, cmd
);
1131 spin_unlock_irqrestore(&tp
->lock
, flags
);
1135 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1138 struct rtl8169_private
*tp
= netdev_priv(dev
);
1139 unsigned long flags
;
1141 if (regs
->len
> R8169_REGS_SIZE
)
1142 regs
->len
= R8169_REGS_SIZE
;
1144 spin_lock_irqsave(&tp
->lock
, flags
);
1145 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1146 spin_unlock_irqrestore(&tp
->lock
, flags
);
1149 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1151 struct rtl8169_private
*tp
= netdev_priv(dev
);
1153 return tp
->msg_enable
;
1156 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1158 struct rtl8169_private
*tp
= netdev_priv(dev
);
1160 tp
->msg_enable
= value
;
1163 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1170 "tx_single_collisions",
1171 "tx_multi_collisions",
1179 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1183 return ARRAY_SIZE(rtl8169_gstrings
);
1189 static void rtl8169_update_counters(struct net_device
*dev
)
1191 struct rtl8169_private
*tp
= netdev_priv(dev
);
1192 void __iomem
*ioaddr
= tp
->mmio_addr
;
1193 struct rtl8169_counters
*counters
;
1199 * Some chips are unable to dump tally counters when the receiver
1202 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1205 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1209 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1210 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1211 RTL_W32(CounterAddrLow
, cmd
);
1212 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1215 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1216 /* copy updated counters */
1217 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1223 RTL_W32(CounterAddrLow
, 0);
1224 RTL_W32(CounterAddrHigh
, 0);
1226 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1229 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1230 struct ethtool_stats
*stats
, u64
*data
)
1232 struct rtl8169_private
*tp
= netdev_priv(dev
);
1236 rtl8169_update_counters(dev
);
1238 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1239 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1240 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1241 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1242 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1243 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1244 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1245 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1246 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1247 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1248 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1249 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1250 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1253 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1257 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1262 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1263 .get_drvinfo
= rtl8169_get_drvinfo
,
1264 .get_regs_len
= rtl8169_get_regs_len
,
1265 .get_link
= ethtool_op_get_link
,
1266 .get_settings
= rtl8169_get_settings
,
1267 .set_settings
= rtl8169_set_settings
,
1268 .get_msglevel
= rtl8169_get_msglevel
,
1269 .set_msglevel
= rtl8169_set_msglevel
,
1270 .get_rx_csum
= rtl8169_get_rx_csum
,
1271 .set_rx_csum
= rtl8169_set_rx_csum
,
1272 .set_tx_csum
= ethtool_op_set_tx_csum
,
1273 .set_sg
= ethtool_op_set_sg
,
1274 .set_tso
= ethtool_op_set_tso
,
1275 .get_regs
= rtl8169_get_regs
,
1276 .get_wol
= rtl8169_get_wol
,
1277 .set_wol
= rtl8169_set_wol
,
1278 .get_strings
= rtl8169_get_strings
,
1279 .get_sset_count
= rtl8169_get_sset_count
,
1280 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1283 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1284 void __iomem
*ioaddr
)
1287 * The driver currently handles the 8168Bf and the 8168Be identically
1288 * but they can be identified more specifically through the test below
1291 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1293 * Same thing for the 8101Eb and the 8101Ec:
1295 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1303 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1304 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1305 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1306 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1309 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1310 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1311 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1312 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1313 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1314 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1315 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1316 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1317 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1320 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1321 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1322 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1323 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1326 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1327 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1328 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1329 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1330 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1331 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1332 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1333 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1334 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1335 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1336 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1337 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1338 /* FIXME: where did these entries come from ? -- FR */
1339 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1340 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1343 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1344 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1345 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1346 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1347 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1348 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1351 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1355 reg
= RTL_R32(TxConfig
);
1356 while ((reg
& p
->mask
) != p
->val
)
1358 tp
->mac_version
= p
->mac_version
;
1361 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1363 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1371 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1374 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1379 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1381 struct phy_reg phy_reg_init
[] = {
1443 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1446 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1448 struct phy_reg phy_reg_init
[] = {
1454 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1457 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1458 void __iomem
*ioaddr
)
1460 struct pci_dev
*pdev
= tp
->pci_dev
;
1461 u16 vendor_id
, device_id
;
1463 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1464 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1466 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1469 mdio_write(ioaddr
, 0x1f, 0x0001);
1470 mdio_write(ioaddr
, 0x10, 0xf01b);
1471 mdio_write(ioaddr
, 0x1f, 0x0000);
1474 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1475 void __iomem
*ioaddr
)
1477 struct phy_reg phy_reg_init
[] = {
1517 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1519 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1522 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1524 struct phy_reg phy_reg_init
[] = {
1572 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1575 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1577 struct phy_reg phy_reg_init
[] = {
1582 mdio_write(ioaddr
, 0x1f, 0x0001);
1583 mdio_patch(ioaddr
, 0x16, 1 << 0);
1585 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1588 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1590 struct phy_reg phy_reg_init
[] = {
1596 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1599 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1601 struct phy_reg phy_reg_init
[] = {
1609 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1612 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1614 struct phy_reg phy_reg_init
[] = {
1620 mdio_write(ioaddr
, 0x1f, 0x0000);
1621 mdio_patch(ioaddr
, 0x14, 1 << 5);
1622 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1624 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1627 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1629 struct phy_reg phy_reg_init
[] = {
1649 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1651 mdio_patch(ioaddr
, 0x14, 1 << 5);
1652 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1653 mdio_write(ioaddr
, 0x1f, 0x0000);
1656 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1658 struct phy_reg phy_reg_init
[] = {
1676 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1678 mdio_patch(ioaddr
, 0x16, 1 << 0);
1679 mdio_patch(ioaddr
, 0x14, 1 << 5);
1680 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1681 mdio_write(ioaddr
, 0x1f, 0x0000);
1684 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1686 struct phy_reg phy_reg_init
[] = {
1698 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1700 mdio_patch(ioaddr
, 0x16, 1 << 0);
1701 mdio_patch(ioaddr
, 0x14, 1 << 5);
1702 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1703 mdio_write(ioaddr
, 0x1f, 0x0000);
1706 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1708 rtl8168c_3_hw_phy_config(ioaddr
);
1711 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1713 static struct phy_reg phy_reg_init_0
[] = {
1732 static struct phy_reg phy_reg_init_1
[] = {
1739 static struct phy_reg phy_reg_init_2
[] = {
2095 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2097 mdio_write(ioaddr
, 0x1f, 0x0002);
2098 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2099 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2101 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2103 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2104 struct phy_reg phy_reg_init
[] = {
2114 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2116 val
= mdio_read(ioaddr
, 0x0d);
2118 if ((val
& 0x00ff) != 0x006c) {
2120 0x0065, 0x0066, 0x0067, 0x0068,
2121 0x0069, 0x006a, 0x006b, 0x006c
2125 mdio_write(ioaddr
, 0x1f, 0x0002);
2128 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2129 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2132 struct phy_reg phy_reg_init
[] = {
2140 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2143 mdio_write(ioaddr
, 0x1f, 0x0002);
2144 mdio_patch(ioaddr
, 0x0d, 0x0300);
2145 mdio_patch(ioaddr
, 0x0f, 0x0010);
2147 mdio_write(ioaddr
, 0x1f, 0x0002);
2148 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2149 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2151 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2154 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2156 static struct phy_reg phy_reg_init_0
[] = {
2181 static struct phy_reg phy_reg_init_1
[] = {
2494 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2496 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2497 struct phy_reg phy_reg_init
[] = {
2508 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2510 val
= mdio_read(ioaddr
, 0x0d);
2511 if ((val
& 0x00ff) != 0x006c) {
2513 0x0065, 0x0066, 0x0067, 0x0068,
2514 0x0069, 0x006a, 0x006b, 0x006c
2518 mdio_write(ioaddr
, 0x1f, 0x0002);
2521 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2522 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2525 struct phy_reg phy_reg_init
[] = {
2533 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2536 mdio_write(ioaddr
, 0x1f, 0x0002);
2537 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2538 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2540 mdio_write(ioaddr
, 0x1f, 0x0001);
2541 mdio_write(ioaddr
, 0x17, 0x0cc0);
2543 mdio_write(ioaddr
, 0x1f, 0x0002);
2544 mdio_patch(ioaddr
, 0x0f, 0x0017);
2546 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2549 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2551 struct phy_reg phy_reg_init
[] = {
2607 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2610 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2612 struct phy_reg phy_reg_init
[] = {
2619 mdio_write(ioaddr
, 0x1f, 0x0000);
2620 mdio_patch(ioaddr
, 0x11, 1 << 12);
2621 mdio_patch(ioaddr
, 0x19, 1 << 13);
2622 mdio_patch(ioaddr
, 0x10, 1 << 15);
2624 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2627 static void rtl_hw_phy_config(struct net_device
*dev
)
2629 struct rtl8169_private
*tp
= netdev_priv(dev
);
2630 void __iomem
*ioaddr
= tp
->mmio_addr
;
2632 rtl8169_print_mac_version(tp
);
2634 switch (tp
->mac_version
) {
2635 case RTL_GIGA_MAC_VER_01
:
2637 case RTL_GIGA_MAC_VER_02
:
2638 case RTL_GIGA_MAC_VER_03
:
2639 rtl8169s_hw_phy_config(ioaddr
);
2641 case RTL_GIGA_MAC_VER_04
:
2642 rtl8169sb_hw_phy_config(ioaddr
);
2644 case RTL_GIGA_MAC_VER_05
:
2645 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2647 case RTL_GIGA_MAC_VER_06
:
2648 rtl8169sce_hw_phy_config(ioaddr
);
2650 case RTL_GIGA_MAC_VER_07
:
2651 case RTL_GIGA_MAC_VER_08
:
2652 case RTL_GIGA_MAC_VER_09
:
2653 rtl8102e_hw_phy_config(ioaddr
);
2655 case RTL_GIGA_MAC_VER_11
:
2656 rtl8168bb_hw_phy_config(ioaddr
);
2658 case RTL_GIGA_MAC_VER_12
:
2659 rtl8168bef_hw_phy_config(ioaddr
);
2661 case RTL_GIGA_MAC_VER_17
:
2662 rtl8168bef_hw_phy_config(ioaddr
);
2664 case RTL_GIGA_MAC_VER_18
:
2665 rtl8168cp_1_hw_phy_config(ioaddr
);
2667 case RTL_GIGA_MAC_VER_19
:
2668 rtl8168c_1_hw_phy_config(ioaddr
);
2670 case RTL_GIGA_MAC_VER_20
:
2671 rtl8168c_2_hw_phy_config(ioaddr
);
2673 case RTL_GIGA_MAC_VER_21
:
2674 rtl8168c_3_hw_phy_config(ioaddr
);
2676 case RTL_GIGA_MAC_VER_22
:
2677 rtl8168c_4_hw_phy_config(ioaddr
);
2679 case RTL_GIGA_MAC_VER_23
:
2680 case RTL_GIGA_MAC_VER_24
:
2681 rtl8168cp_2_hw_phy_config(ioaddr
);
2683 case RTL_GIGA_MAC_VER_25
:
2684 rtl8168d_1_hw_phy_config(ioaddr
);
2686 case RTL_GIGA_MAC_VER_26
:
2687 rtl8168d_2_hw_phy_config(ioaddr
);
2689 case RTL_GIGA_MAC_VER_27
:
2690 rtl8168d_3_hw_phy_config(ioaddr
);
2698 static void rtl8169_phy_timer(unsigned long __opaque
)
2700 struct net_device
*dev
= (struct net_device
*)__opaque
;
2701 struct rtl8169_private
*tp
= netdev_priv(dev
);
2702 struct timer_list
*timer
= &tp
->timer
;
2703 void __iomem
*ioaddr
= tp
->mmio_addr
;
2704 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2706 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2708 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2711 spin_lock_irq(&tp
->lock
);
2713 if (tp
->phy_reset_pending(ioaddr
)) {
2715 * A busy loop could burn quite a few cycles on nowadays CPU.
2716 * Let's delay the execution of the timer for a few ticks.
2722 if (tp
->link_ok(ioaddr
))
2725 if (netif_msg_link(tp
))
2726 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
2728 tp
->phy_reset_enable(ioaddr
);
2731 mod_timer(timer
, jiffies
+ timeout
);
2733 spin_unlock_irq(&tp
->lock
);
2736 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2738 struct rtl8169_private
*tp
= netdev_priv(dev
);
2739 struct timer_list
*timer
= &tp
->timer
;
2741 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2744 del_timer_sync(timer
);
2747 static inline void rtl8169_request_timer(struct net_device
*dev
)
2749 struct rtl8169_private
*tp
= netdev_priv(dev
);
2750 struct timer_list
*timer
= &tp
->timer
;
2752 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2755 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2758 #ifdef CONFIG_NET_POLL_CONTROLLER
2760 * Polling 'interrupt' - used by things like netconsole to send skbs
2761 * without having to re-enable interrupts. It's not called while
2762 * the interrupt routine is executing.
2764 static void rtl8169_netpoll(struct net_device
*dev
)
2766 struct rtl8169_private
*tp
= netdev_priv(dev
);
2767 struct pci_dev
*pdev
= tp
->pci_dev
;
2769 disable_irq(pdev
->irq
);
2770 rtl8169_interrupt(pdev
->irq
, dev
);
2771 enable_irq(pdev
->irq
);
2775 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2776 void __iomem
*ioaddr
)
2779 pci_release_regions(pdev
);
2780 pci_disable_device(pdev
);
2784 static void rtl8169_phy_reset(struct net_device
*dev
,
2785 struct rtl8169_private
*tp
)
2787 void __iomem
*ioaddr
= tp
->mmio_addr
;
2790 tp
->phy_reset_enable(ioaddr
);
2791 for (i
= 0; i
< 100; i
++) {
2792 if (!tp
->phy_reset_pending(ioaddr
))
2796 if (netif_msg_link(tp
))
2797 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
2800 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2802 void __iomem
*ioaddr
= tp
->mmio_addr
;
2804 rtl_hw_phy_config(dev
);
2806 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2807 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2811 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2813 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2814 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2816 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2817 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2819 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2820 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2823 rtl8169_phy_reset(dev
, tp
);
2826 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2827 * only 8101. Don't panic.
2829 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2831 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
2832 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
2835 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2837 void __iomem
*ioaddr
= tp
->mmio_addr
;
2841 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2842 high
= addr
[4] | (addr
[5] << 8);
2844 spin_lock_irq(&tp
->lock
);
2846 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2848 RTL_W32(MAC4
, high
);
2854 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2856 spin_unlock_irq(&tp
->lock
);
2859 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2861 struct rtl8169_private
*tp
= netdev_priv(dev
);
2862 struct sockaddr
*addr
= p
;
2864 if (!is_valid_ether_addr(addr
->sa_data
))
2865 return -EADDRNOTAVAIL
;
2867 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2869 rtl_rar_set(tp
, dev
->dev_addr
);
2874 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2876 struct rtl8169_private
*tp
= netdev_priv(dev
);
2877 struct mii_ioctl_data
*data
= if_mii(ifr
);
2879 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2882 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2886 data
->phy_id
= 32; /* Internal PHY */
2890 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2894 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2900 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2905 static const struct rtl_cfg_info
{
2906 void (*hw_start
)(struct net_device
*);
2907 unsigned int region
;
2913 } rtl_cfg_infos
[] = {
2915 .hw_start
= rtl_hw_start_8169
,
2918 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2919 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2920 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2921 .features
= RTL_FEATURE_GMII
,
2922 .default_ver
= RTL_GIGA_MAC_VER_01
,
2925 .hw_start
= rtl_hw_start_8168
,
2928 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2929 TxErr
| TxOK
| RxOK
| RxErr
,
2930 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2931 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2932 .default_ver
= RTL_GIGA_MAC_VER_11
,
2935 .hw_start
= rtl_hw_start_8101
,
2938 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2939 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2940 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2941 .features
= RTL_FEATURE_MSI
,
2942 .default_ver
= RTL_GIGA_MAC_VER_13
,
2946 /* Cfg9346_Unlock assumed. */
2947 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2948 const struct rtl_cfg_info
*cfg
)
2953 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2954 if (cfg
->features
& RTL_FEATURE_MSI
) {
2955 if (pci_enable_msi(pdev
)) {
2956 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2959 msi
= RTL_FEATURE_MSI
;
2962 RTL_W8(Config2
, cfg2
);
2966 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2968 if (tp
->features
& RTL_FEATURE_MSI
) {
2969 pci_disable_msi(pdev
);
2970 tp
->features
&= ~RTL_FEATURE_MSI
;
2974 static const struct net_device_ops rtl8169_netdev_ops
= {
2975 .ndo_open
= rtl8169_open
,
2976 .ndo_stop
= rtl8169_close
,
2977 .ndo_get_stats
= rtl8169_get_stats
,
2978 .ndo_start_xmit
= rtl8169_start_xmit
,
2979 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2980 .ndo_validate_addr
= eth_validate_addr
,
2981 .ndo_change_mtu
= rtl8169_change_mtu
,
2982 .ndo_set_mac_address
= rtl_set_mac_address
,
2983 .ndo_do_ioctl
= rtl8169_ioctl
,
2984 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2985 #ifdef CONFIG_R8169_VLAN
2986 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2988 #ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller
= rtl8169_netpoll
,
2994 static int __devinit
2995 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2997 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2998 const unsigned int region
= cfg
->region
;
2999 struct rtl8169_private
*tp
;
3000 struct mii_if_info
*mii
;
3001 struct net_device
*dev
;
3002 void __iomem
*ioaddr
;
3006 if (netif_msg_drv(&debug
)) {
3007 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3008 MODULENAME
, RTL8169_VERSION
);
3011 dev
= alloc_etherdev(sizeof (*tp
));
3013 if (netif_msg_drv(&debug
))
3014 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3019 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3020 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3021 tp
= netdev_priv(dev
);
3024 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3028 mii
->mdio_read
= rtl_mdio_read
;
3029 mii
->mdio_write
= rtl_mdio_write
;
3030 mii
->phy_id_mask
= 0x1f;
3031 mii
->reg_num_mask
= 0x1f;
3032 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3034 /* disable ASPM completely as that cause random device stop working
3035 * problems as well as full system hangs for some PCIe devices users */
3036 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3037 PCIE_LINK_STATE_CLKPM
);
3039 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3040 rc
= pci_enable_device(pdev
);
3042 if (netif_msg_probe(tp
))
3043 dev_err(&pdev
->dev
, "enable failure\n");
3044 goto err_out_free_dev_1
;
3047 rc
= pci_set_mwi(pdev
);
3049 goto err_out_disable_2
;
3051 /* make sure PCI base addr 1 is MMIO */
3052 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3053 if (netif_msg_probe(tp
)) {
3055 "region #%d not an MMIO resource, aborting\n",
3062 /* check for weird/broken PCI region reporting */
3063 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3064 if (netif_msg_probe(tp
)) {
3066 "Invalid PCI region size(s), aborting\n");
3072 rc
= pci_request_regions(pdev
, MODULENAME
);
3074 if (netif_msg_probe(tp
))
3075 dev_err(&pdev
->dev
, "could not request regions.\n");
3079 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3081 if ((sizeof(dma_addr_t
) > 4) &&
3082 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3083 tp
->cp_cmd
|= PCIDAC
;
3084 dev
->features
|= NETIF_F_HIGHDMA
;
3086 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3088 if (netif_msg_probe(tp
)) {
3090 "DMA configuration failed.\n");
3092 goto err_out_free_res_4
;
3096 /* ioremap MMIO region */
3097 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3099 if (netif_msg_probe(tp
))
3100 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
3102 goto err_out_free_res_4
;
3105 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3106 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
3107 dev_info(&pdev
->dev
, "no PCI Express capability\n");
3109 RTL_W16(IntrMask
, 0x0000);
3111 /* Soft reset the chip. */
3112 RTL_W8(ChipCmd
, CmdReset
);
3114 /* Check that the chip has finished the reset. */
3115 for (i
= 0; i
< 100; i
++) {
3116 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3118 msleep_interruptible(1);
3121 RTL_W16(IntrStatus
, 0xffff);
3123 pci_set_master(pdev
);
3125 /* Identify chip attached to board */
3126 rtl8169_get_mac_version(tp
, ioaddr
);
3128 /* Use appropriate default if unknown */
3129 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3130 if (netif_msg_probe(tp
)) {
3131 dev_notice(&pdev
->dev
,
3132 "unknown MAC, using family default\n");
3134 tp
->mac_version
= cfg
->default_ver
;
3137 rtl8169_print_mac_version(tp
);
3139 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3140 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3143 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3145 "driver bug, MAC version not found in rtl_chip_info\n");
3150 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3151 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3152 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3153 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3154 tp
->features
|= RTL_FEATURE_WOL
;
3155 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3156 tp
->features
|= RTL_FEATURE_WOL
;
3157 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3158 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3160 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3161 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3162 tp
->set_speed
= rtl8169_set_speed_tbi
;
3163 tp
->get_settings
= rtl8169_gset_tbi
;
3164 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3165 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3166 tp
->link_ok
= rtl8169_tbi_link_ok
;
3167 tp
->do_ioctl
= rtl_tbi_ioctl
;
3169 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3171 tp
->set_speed
= rtl8169_set_speed_xmii
;
3172 tp
->get_settings
= rtl8169_gset_xmii
;
3173 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3174 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3175 tp
->link_ok
= rtl8169_xmii_link_ok
;
3176 tp
->do_ioctl
= rtl_xmii_ioctl
;
3179 spin_lock_init(&tp
->lock
);
3181 tp
->mmio_addr
= ioaddr
;
3183 /* Get MAC address */
3184 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3185 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3186 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3188 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3189 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3190 dev
->irq
= pdev
->irq
;
3191 dev
->base_addr
= (unsigned long) ioaddr
;
3193 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3195 #ifdef CONFIG_R8169_VLAN
3196 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3199 tp
->intr_mask
= 0xffff;
3200 tp
->align
= cfg
->align
;
3201 tp
->hw_start
= cfg
->hw_start
;
3202 tp
->intr_event
= cfg
->intr_event
;
3203 tp
->napi_event
= cfg
->napi_event
;
3205 init_timer(&tp
->timer
);
3206 tp
->timer
.data
= (unsigned long) dev
;
3207 tp
->timer
.function
= rtl8169_phy_timer
;
3209 rc
= register_netdev(dev
);
3213 pci_set_drvdata(pdev
, dev
);
3215 if (netif_msg_probe(tp
)) {
3216 u32 xid
= RTL_R32(TxConfig
) & 0x9cf0f8ff;
3218 printk(KERN_INFO
"%s: %s at 0x%lx, "
3219 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3220 "XID %08x IRQ %d\n",
3222 rtl_chip_info
[tp
->chipset
].name
,
3224 dev
->dev_addr
[0], dev
->dev_addr
[1],
3225 dev
->dev_addr
[2], dev
->dev_addr
[3],
3226 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
3229 rtl8169_init_phy(dev
, tp
);
3232 * Pretend we are using VLANs; This bypasses a nasty bug where
3233 * Interrupts stop flowing on high load on 8110SCd controllers.
3235 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3236 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3238 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3244 rtl_disable_msi(pdev
, tp
);
3247 pci_release_regions(pdev
);
3249 pci_clear_mwi(pdev
);
3251 pci_disable_device(pdev
);
3257 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3259 struct net_device
*dev
= pci_get_drvdata(pdev
);
3260 struct rtl8169_private
*tp
= netdev_priv(dev
);
3262 flush_scheduled_work();
3264 unregister_netdev(dev
);
3266 /* restore original MAC address */
3267 rtl_rar_set(tp
, dev
->perm_addr
);
3269 rtl_disable_msi(pdev
, tp
);
3270 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3271 pci_set_drvdata(pdev
, NULL
);
3274 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
3277 unsigned int max_frame
= mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3279 if (max_frame
!= 16383)
3280 printk(KERN_WARNING PFX
"WARNING! Changing of MTU on this "
3281 "NIC may lead to frame reception errors!\n");
3283 tp
->rx_buf_sz
= (max_frame
> RX_BUF_SIZE
) ? max_frame
: RX_BUF_SIZE
;
3286 static int rtl8169_open(struct net_device
*dev
)
3288 struct rtl8169_private
*tp
= netdev_priv(dev
);
3289 struct pci_dev
*pdev
= tp
->pci_dev
;
3290 int retval
= -ENOMEM
;
3294 * Note that we use a magic value here, its wierd I know
3295 * its done because, some subset of rtl8169 hardware suffers from
3296 * a problem in which frames received that are longer than
3297 * the size set in RxMaxSize register return garbage sizes
3298 * when received. To avoid this we need to turn off filtering,
3299 * which is done by setting a value of 16383 in the RxMaxSize register
3300 * and allocating 16k frames to handle the largest possible rx value
3301 * thats what the magic math below does.
3303 rtl8169_set_rxbufsize(tp
, 16383 - VLAN_ETH_HLEN
- ETH_FCS_LEN
);
3306 * Rx and Tx desscriptors needs 256 bytes alignment.
3307 * pci_alloc_consistent provides more.
3309 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
3311 if (!tp
->TxDescArray
)
3314 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
3316 if (!tp
->RxDescArray
)
3319 retval
= rtl8169_init_ring(dev
);
3323 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3327 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3328 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3331 goto err_release_ring_2
;
3333 napi_enable(&tp
->napi
);
3337 rtl8169_request_timer(dev
);
3339 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3344 rtl8169_rx_clear(tp
);
3346 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3349 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3354 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3356 /* Disable interrupts */
3357 rtl8169_irq_mask_and_ack(ioaddr
);
3359 /* Reset the chipset */
3360 RTL_W8(ChipCmd
, CmdReset
);
3366 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3368 void __iomem
*ioaddr
= tp
->mmio_addr
;
3369 u32 cfg
= rtl8169_rx_config
;
3371 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3372 RTL_W32(RxConfig
, cfg
);
3374 /* Set DMA burst size and Interframe Gap Time */
3375 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3376 (InterFrameGap
<< TxInterFrameGapShift
));
3379 static void rtl_hw_start(struct net_device
*dev
)
3381 struct rtl8169_private
*tp
= netdev_priv(dev
);
3382 void __iomem
*ioaddr
= tp
->mmio_addr
;
3385 /* Soft reset the chip. */
3386 RTL_W8(ChipCmd
, CmdReset
);
3388 /* Check that the chip has finished the reset. */
3389 for (i
= 0; i
< 100; i
++) {
3390 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3392 msleep_interruptible(1);
3397 netif_start_queue(dev
);
3401 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3402 void __iomem
*ioaddr
)
3405 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3406 * register to be written before TxDescAddrLow to work.
3407 * Switching from MMIO to I/O access fixes the issue as well.
3409 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3410 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3411 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3412 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3415 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3419 cmd
= RTL_R16(CPlusCmd
);
3420 RTL_W16(CPlusCmd
, cmd
);
3424 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3426 /* Low hurts. Let's disable the filtering. */
3427 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3430 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3437 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3438 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3439 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3440 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3445 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3446 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3447 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3448 RTL_W32(0x7c, p
->val
);
3454 static void rtl_hw_start_8169(struct net_device
*dev
)
3456 struct rtl8169_private
*tp
= netdev_priv(dev
);
3457 void __iomem
*ioaddr
= tp
->mmio_addr
;
3458 struct pci_dev
*pdev
= tp
->pci_dev
;
3460 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3461 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3462 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3465 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3466 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3467 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3468 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3469 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3470 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3472 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3474 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3476 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3477 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3478 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3479 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3480 rtl_set_rx_tx_config_registers(tp
);
3482 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3484 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3485 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3486 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3487 "Bit-3 and bit-14 MUST be 1\n");
3488 tp
->cp_cmd
|= (1 << 14);
3491 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3493 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3496 * Undocumented corner. Supposedly:
3497 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3499 RTL_W16(IntrMitigate
, 0x0000);
3501 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3503 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3504 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3505 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3506 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3507 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3508 rtl_set_rx_tx_config_registers(tp
);
3511 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3513 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3516 RTL_W32(RxMissed
, 0);
3518 rtl_set_rx_mode(dev
);
3520 /* no early-rx interrupts */
3521 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3523 /* Enable all known interrupts by setting the interrupt mask. */
3524 RTL_W16(IntrMask
, tp
->intr_event
);
3527 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3529 struct net_device
*dev
= pci_get_drvdata(pdev
);
3530 struct rtl8169_private
*tp
= netdev_priv(dev
);
3531 int cap
= tp
->pcie_cap
;
3536 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3537 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3538 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3542 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3546 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3547 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3551 unsigned int offset
;
3556 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
3561 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3562 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3567 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3569 struct net_device
*dev
= pci_get_drvdata(pdev
);
3570 struct rtl8169_private
*tp
= netdev_priv(dev
);
3571 int cap
= tp
->pcie_cap
;
3576 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3577 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3578 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3582 #define R8168_CPCMD_QUIRK_MASK (\
3593 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3595 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3597 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3599 rtl_tx_performance_tweak(pdev
,
3600 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3603 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3605 rtl_hw_start_8168bb(ioaddr
, pdev
);
3607 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3609 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3612 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3614 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3616 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3618 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3620 rtl_disable_clock_request(pdev
);
3622 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3625 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3627 static struct ephy_info e_info_8168cp
[] = {
3628 { 0x01, 0, 0x0001 },
3629 { 0x02, 0x0800, 0x1000 },
3630 { 0x03, 0, 0x0042 },
3631 { 0x06, 0x0080, 0x0000 },
3635 rtl_csi_access_enable(ioaddr
);
3637 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3639 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3642 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3644 rtl_csi_access_enable(ioaddr
);
3646 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3648 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3650 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3653 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3655 rtl_csi_access_enable(ioaddr
);
3657 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3660 RTL_W8(DBG_REG
, 0x20);
3662 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3664 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3666 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3669 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3671 static struct ephy_info e_info_8168c_1
[] = {
3672 { 0x02, 0x0800, 0x1000 },
3673 { 0x03, 0, 0x0002 },
3674 { 0x06, 0x0080, 0x0000 }
3677 rtl_csi_access_enable(ioaddr
);
3679 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3681 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3683 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3686 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3688 static struct ephy_info e_info_8168c_2
[] = {
3689 { 0x01, 0, 0x0001 },
3690 { 0x03, 0x0400, 0x0220 }
3693 rtl_csi_access_enable(ioaddr
);
3695 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3697 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3700 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3702 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3705 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3707 rtl_csi_access_enable(ioaddr
);
3709 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3712 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3714 rtl_csi_access_enable(ioaddr
);
3716 rtl_disable_clock_request(pdev
);
3718 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3720 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3722 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3725 static void rtl_hw_start_8168(struct net_device
*dev
)
3727 struct rtl8169_private
*tp
= netdev_priv(dev
);
3728 void __iomem
*ioaddr
= tp
->mmio_addr
;
3729 struct pci_dev
*pdev
= tp
->pci_dev
;
3731 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3733 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3735 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3737 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3739 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3741 RTL_W16(IntrMitigate
, 0x5151);
3743 /* Work around for RxFIFO overflow. */
3744 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
3745 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
3746 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3747 tp
->intr_event
&= ~RxOverflow
;
3750 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3752 rtl_set_rx_mode(dev
);
3754 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3755 (InterFrameGap
<< TxInterFrameGapShift
));
3759 switch (tp
->mac_version
) {
3760 case RTL_GIGA_MAC_VER_11
:
3761 rtl_hw_start_8168bb(ioaddr
, pdev
);
3764 case RTL_GIGA_MAC_VER_12
:
3765 case RTL_GIGA_MAC_VER_17
:
3766 rtl_hw_start_8168bef(ioaddr
, pdev
);
3769 case RTL_GIGA_MAC_VER_18
:
3770 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3773 case RTL_GIGA_MAC_VER_19
:
3774 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3777 case RTL_GIGA_MAC_VER_20
:
3778 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3781 case RTL_GIGA_MAC_VER_21
:
3782 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3785 case RTL_GIGA_MAC_VER_22
:
3786 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3789 case RTL_GIGA_MAC_VER_23
:
3790 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3793 case RTL_GIGA_MAC_VER_24
:
3794 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3797 case RTL_GIGA_MAC_VER_25
:
3798 case RTL_GIGA_MAC_VER_26
:
3799 case RTL_GIGA_MAC_VER_27
:
3800 rtl_hw_start_8168d(ioaddr
, pdev
);
3804 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3805 dev
->name
, tp
->mac_version
);
3809 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3811 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3813 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3815 RTL_W16(IntrMask
, tp
->intr_event
);
3818 #define R810X_CPCMD_QUIRK_MASK (\
3830 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3832 static struct ephy_info e_info_8102e_1
[] = {
3833 { 0x01, 0, 0x6e65 },
3834 { 0x02, 0, 0x091f },
3835 { 0x03, 0, 0xc2f9 },
3836 { 0x06, 0, 0xafb5 },
3837 { 0x07, 0, 0x0e00 },
3838 { 0x19, 0, 0xec80 },
3839 { 0x01, 0, 0x2e65 },
3844 rtl_csi_access_enable(ioaddr
);
3846 RTL_W8(DBG_REG
, FIX_NAK_1
);
3848 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3851 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3852 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3854 cfg1
= RTL_R8(Config1
);
3855 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3856 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3858 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3860 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3863 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3865 rtl_csi_access_enable(ioaddr
);
3867 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3869 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3870 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3872 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3875 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3877 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3879 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3882 static void rtl_hw_start_8101(struct net_device
*dev
)
3884 struct rtl8169_private
*tp
= netdev_priv(dev
);
3885 void __iomem
*ioaddr
= tp
->mmio_addr
;
3886 struct pci_dev
*pdev
= tp
->pci_dev
;
3888 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3889 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3890 int cap
= tp
->pcie_cap
;
3893 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3894 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3898 switch (tp
->mac_version
) {
3899 case RTL_GIGA_MAC_VER_07
:
3900 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3903 case RTL_GIGA_MAC_VER_08
:
3904 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3907 case RTL_GIGA_MAC_VER_09
:
3908 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3912 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3914 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3916 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3918 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3920 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3922 RTL_W16(IntrMitigate
, 0x0000);
3924 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3926 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3927 rtl_set_rx_tx_config_registers(tp
);
3929 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3933 rtl_set_rx_mode(dev
);
3935 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3937 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3939 RTL_W16(IntrMask
, tp
->intr_event
);
3942 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3944 struct rtl8169_private
*tp
= netdev_priv(dev
);
3947 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3952 if (!netif_running(dev
))
3957 rtl8169_set_rxbufsize(tp
, dev
->mtu
);
3959 ret
= rtl8169_init_ring(dev
);
3963 napi_enable(&tp
->napi
);
3967 rtl8169_request_timer(dev
);
3973 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3975 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3976 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3979 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
3980 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
3982 struct pci_dev
*pdev
= tp
->pci_dev
;
3984 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
3985 PCI_DMA_FROMDEVICE
);
3986 dev_kfree_skb(*sk_buff
);
3988 rtl8169_make_unusable_by_asic(desc
);
3991 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3993 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3995 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3998 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4001 desc
->addr
= cpu_to_le64(mapping
);
4003 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4006 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
4007 struct net_device
*dev
,
4008 struct RxDesc
*desc
, int rx_buf_sz
,
4009 unsigned int align
, gfp_t gfp
)
4011 struct sk_buff
*skb
;
4015 pad
= align
? align
: NET_IP_ALIGN
;
4017 skb
= __netdev_alloc_skb(dev
, rx_buf_sz
+ pad
, gfp
);
4021 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
4023 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
4024 PCI_DMA_FROMDEVICE
);
4026 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4031 rtl8169_make_unusable_by_asic(desc
);
4035 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4039 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4040 if (tp
->Rx_skbuff
[i
]) {
4041 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
4042 tp
->RxDescArray
+ i
);
4047 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
4048 u32 start
, u32 end
, gfp_t gfp
)
4052 for (cur
= start
; end
- cur
!= 0; cur
++) {
4053 struct sk_buff
*skb
;
4054 unsigned int i
= cur
% NUM_RX_DESC
;
4056 WARN_ON((s32
)(end
- cur
) < 0);
4058 if (tp
->Rx_skbuff
[i
])
4061 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
4062 tp
->RxDescArray
+ i
,
4063 tp
->rx_buf_sz
, tp
->align
, gfp
);
4067 tp
->Rx_skbuff
[i
] = skb
;
4072 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4074 desc
->opts1
|= cpu_to_le32(RingEnd
);
4077 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4079 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4082 static int rtl8169_init_ring(struct net_device
*dev
)
4084 struct rtl8169_private
*tp
= netdev_priv(dev
);
4086 rtl8169_init_ring_indexes(tp
);
4088 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4089 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
4091 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
, GFP_KERNEL
) != NUM_RX_DESC
)
4094 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4099 rtl8169_rx_clear(tp
);
4103 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
4104 struct TxDesc
*desc
)
4106 unsigned int len
= tx_skb
->len
;
4108 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
4115 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4119 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
4120 unsigned int entry
= i
% NUM_TX_DESC
;
4121 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4122 unsigned int len
= tx_skb
->len
;
4125 struct sk_buff
*skb
= tx_skb
->skb
;
4127 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
4128 tp
->TxDescArray
+ entry
);
4133 tp
->dev
->stats
.tx_dropped
++;
4136 tp
->cur_tx
= tp
->dirty_tx
= 0;
4139 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4141 struct rtl8169_private
*tp
= netdev_priv(dev
);
4143 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4144 schedule_delayed_work(&tp
->task
, 4);
4147 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4149 struct rtl8169_private
*tp
= netdev_priv(dev
);
4150 void __iomem
*ioaddr
= tp
->mmio_addr
;
4152 synchronize_irq(dev
->irq
);
4154 /* Wait for any pending NAPI task to complete */
4155 napi_disable(&tp
->napi
);
4157 rtl8169_irq_mask_and_ack(ioaddr
);
4159 tp
->intr_mask
= 0xffff;
4160 RTL_W16(IntrMask
, tp
->intr_event
);
4161 napi_enable(&tp
->napi
);
4164 static void rtl8169_reinit_task(struct work_struct
*work
)
4166 struct rtl8169_private
*tp
=
4167 container_of(work
, struct rtl8169_private
, task
.work
);
4168 struct net_device
*dev
= tp
->dev
;
4173 if (!netif_running(dev
))
4176 rtl8169_wait_for_quiescence(dev
);
4179 ret
= rtl8169_open(dev
);
4180 if (unlikely(ret
< 0)) {
4181 if (net_ratelimit() && netif_msg_drv(tp
)) {
4182 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
4183 " Rescheduling.\n", dev
->name
, ret
);
4185 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4192 static void rtl8169_reset_task(struct work_struct
*work
)
4194 struct rtl8169_private
*tp
=
4195 container_of(work
, struct rtl8169_private
, task
.work
);
4196 struct net_device
*dev
= tp
->dev
;
4200 if (!netif_running(dev
))
4203 rtl8169_wait_for_quiescence(dev
);
4205 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4206 rtl8169_tx_clear(tp
);
4208 if (tp
->dirty_rx
== tp
->cur_rx
) {
4209 rtl8169_init_ring_indexes(tp
);
4211 netif_wake_queue(dev
);
4212 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4214 if (net_ratelimit() && netif_msg_intr(tp
)) {
4215 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
4218 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4225 static void rtl8169_tx_timeout(struct net_device
*dev
)
4227 struct rtl8169_private
*tp
= netdev_priv(dev
);
4229 rtl8169_hw_reset(tp
->mmio_addr
);
4231 /* Let's wait a bit while any (async) irq lands on */
4232 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4235 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4238 struct skb_shared_info
*info
= skb_shinfo(skb
);
4239 unsigned int cur_frag
, entry
;
4240 struct TxDesc
* uninitialized_var(txd
);
4243 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4244 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4249 entry
= (entry
+ 1) % NUM_TX_DESC
;
4251 txd
= tp
->TxDescArray
+ entry
;
4253 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4254 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
4256 /* anti gcc 2.95.3 bugware (sic) */
4257 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4259 txd
->opts1
= cpu_to_le32(status
);
4260 txd
->addr
= cpu_to_le64(mapping
);
4262 tp
->tx_skb
[entry
].len
= len
;
4266 tp
->tx_skb
[entry
].skb
= skb
;
4267 txd
->opts1
|= cpu_to_le32(LastFrag
);
4273 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4275 if (dev
->features
& NETIF_F_TSO
) {
4276 u32 mss
= skb_shinfo(skb
)->gso_size
;
4279 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4281 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4282 const struct iphdr
*ip
= ip_hdr(skb
);
4284 if (ip
->protocol
== IPPROTO_TCP
)
4285 return IPCS
| TCPCS
;
4286 else if (ip
->protocol
== IPPROTO_UDP
)
4287 return IPCS
| UDPCS
;
4288 WARN_ON(1); /* we need a WARN() */
4293 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4294 struct net_device
*dev
)
4296 struct rtl8169_private
*tp
= netdev_priv(dev
);
4297 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
4298 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4299 void __iomem
*ioaddr
= tp
->mmio_addr
;
4304 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4305 if (netif_msg_drv(tp
)) {
4307 "%s: BUG! Tx Ring full when queue awake!\n",
4313 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4316 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4318 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4320 len
= skb_headlen(skb
);
4324 opts1
|= FirstFrag
| LastFrag
;
4325 tp
->tx_skb
[entry
].skb
= skb
;
4328 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
4330 tp
->tx_skb
[entry
].len
= len
;
4331 txd
->addr
= cpu_to_le64(mapping
);
4332 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4336 /* anti gcc 2.95.3 bugware (sic) */
4337 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4338 txd
->opts1
= cpu_to_le32(status
);
4340 tp
->cur_tx
+= frags
+ 1;
4344 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4346 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4347 netif_stop_queue(dev
);
4349 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4350 netif_wake_queue(dev
);
4353 return NETDEV_TX_OK
;
4356 netif_stop_queue(dev
);
4357 dev
->stats
.tx_dropped
++;
4358 return NETDEV_TX_BUSY
;
4361 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4363 struct rtl8169_private
*tp
= netdev_priv(dev
);
4364 struct pci_dev
*pdev
= tp
->pci_dev
;
4365 void __iomem
*ioaddr
= tp
->mmio_addr
;
4366 u16 pci_status
, pci_cmd
;
4368 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4369 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4371 if (netif_msg_intr(tp
)) {
4373 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4374 dev
->name
, pci_cmd
, pci_status
);
4378 * The recovery sequence below admits a very elaborated explanation:
4379 * - it seems to work;
4380 * - I did not see what else could be done;
4381 * - it makes iop3xx happy.
4383 * Feel free to adjust to your needs.
4385 if (pdev
->broken_parity_status
)
4386 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4388 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4390 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4392 pci_write_config_word(pdev
, PCI_STATUS
,
4393 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4394 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4395 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4397 /* The infamous DAC f*ckup only happens at boot time */
4398 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4399 if (netif_msg_intr(tp
))
4400 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
4401 tp
->cp_cmd
&= ~PCIDAC
;
4402 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4403 dev
->features
&= ~NETIF_F_HIGHDMA
;
4406 rtl8169_hw_reset(ioaddr
);
4408 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4411 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4412 struct rtl8169_private
*tp
,
4413 void __iomem
*ioaddr
)
4415 unsigned int dirty_tx
, tx_left
;
4417 dirty_tx
= tp
->dirty_tx
;
4419 tx_left
= tp
->cur_tx
- dirty_tx
;
4421 while (tx_left
> 0) {
4422 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4423 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4424 u32 len
= tx_skb
->len
;
4428 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4429 if (status
& DescOwn
)
4432 dev
->stats
.tx_bytes
+= len
;
4433 dev
->stats
.tx_packets
++;
4435 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
4437 if (status
& LastFrag
) {
4438 dev_kfree_skb(tx_skb
->skb
);
4445 if (tp
->dirty_tx
!= dirty_tx
) {
4446 tp
->dirty_tx
= dirty_tx
;
4448 if (netif_queue_stopped(dev
) &&
4449 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4450 netif_wake_queue(dev
);
4453 * 8168 hack: TxPoll requests are lost when the Tx packets are
4454 * too close. Let's kick an extra TxPoll request when a burst
4455 * of start_xmit activity is detected (if it is not detected,
4456 * it is slow enough). -- FR
4459 if (tp
->cur_tx
!= dirty_tx
)
4460 RTL_W8(TxPoll
, NPQ
);
4464 static inline int rtl8169_fragmented_frame(u32 status
)
4466 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4469 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
4471 u32 opts1
= le32_to_cpu(desc
->opts1
);
4472 u32 status
= opts1
& RxProtoMask
;
4474 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4475 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
4476 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
4477 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4479 skb
->ip_summed
= CHECKSUM_NONE
;
4482 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
4483 struct rtl8169_private
*tp
, int pkt_size
,
4486 struct sk_buff
*skb
;
4489 if (pkt_size
>= rx_copybreak
)
4492 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
4496 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
4497 PCI_DMA_FROMDEVICE
);
4498 skb_reserve(skb
, NET_IP_ALIGN
);
4499 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
4506 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4507 struct rtl8169_private
*tp
,
4508 void __iomem
*ioaddr
, u32 budget
)
4510 unsigned int cur_rx
, rx_left
;
4511 unsigned int delta
, count
;
4513 cur_rx
= tp
->cur_rx
;
4514 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4515 rx_left
= min(rx_left
, budget
);
4517 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4518 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4519 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4523 status
= le32_to_cpu(desc
->opts1
);
4525 if (status
& DescOwn
)
4527 if (unlikely(status
& RxRES
)) {
4528 if (netif_msg_rx_err(tp
)) {
4530 "%s: Rx ERROR. status = %08x\n",
4533 dev
->stats
.rx_errors
++;
4534 if (status
& (RxRWT
| RxRUNT
))
4535 dev
->stats
.rx_length_errors
++;
4537 dev
->stats
.rx_crc_errors
++;
4538 if (status
& RxFOVF
) {
4539 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4540 dev
->stats
.rx_fifo_errors
++;
4542 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4544 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
4545 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4546 int pkt_size
= (status
& 0x00001FFF) - 4;
4547 struct pci_dev
*pdev
= tp
->pci_dev
;
4550 * The driver does not support incoming fragmented
4551 * frames. They are seen as a symptom of over-mtu
4554 if (unlikely(rtl8169_fragmented_frame(status
))) {
4555 dev
->stats
.rx_dropped
++;
4556 dev
->stats
.rx_length_errors
++;
4557 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4561 rtl8169_rx_csum(skb
, desc
);
4563 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
4564 pci_dma_sync_single_for_device(pdev
, addr
,
4565 pkt_size
, PCI_DMA_FROMDEVICE
);
4566 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4568 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
4569 PCI_DMA_FROMDEVICE
);
4570 tp
->Rx_skbuff
[entry
] = NULL
;
4573 skb_put(skb
, pkt_size
);
4574 skb
->protocol
= eth_type_trans(skb
, dev
);
4576 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
4577 netif_receive_skb(skb
);
4579 dev
->stats
.rx_bytes
+= pkt_size
;
4580 dev
->stats
.rx_packets
++;
4583 /* Work around for AMD plateform. */
4584 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4585 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4591 count
= cur_rx
- tp
->cur_rx
;
4592 tp
->cur_rx
= cur_rx
;
4594 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
, GFP_ATOMIC
);
4595 if (!delta
&& count
&& netif_msg_intr(tp
))
4596 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
4597 tp
->dirty_rx
+= delta
;
4600 * FIXME: until there is periodic timer to try and refill the ring,
4601 * a temporary shortage may definitely kill the Rx process.
4602 * - disable the asic to try and avoid an overflow and kick it again
4604 * - how do others driver handle this condition (Uh oh...).
4606 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
4607 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
4612 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4614 struct net_device
*dev
= dev_instance
;
4615 struct rtl8169_private
*tp
= netdev_priv(dev
);
4616 void __iomem
*ioaddr
= tp
->mmio_addr
;
4620 /* loop handling interrupts until we have no new ones or
4621 * we hit a invalid/hotplug case.
4623 status
= RTL_R16(IntrStatus
);
4624 while (status
&& status
!= 0xffff) {
4627 /* Handle all of the error cases first. These will reset
4628 * the chip, so just exit the loop.
4630 if (unlikely(!netif_running(dev
))) {
4631 rtl8169_asic_down(ioaddr
);
4635 /* Work around for rx fifo overflow */
4636 if (unlikely(status
& RxFIFOOver
) &&
4637 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4638 tp
->mac_version
== RTL_GIGA_MAC_VER_22
)) {
4639 netif_stop_queue(dev
);
4640 rtl8169_tx_timeout(dev
);
4644 if (unlikely(status
& SYSErr
)) {
4645 rtl8169_pcierr_interrupt(dev
);
4649 if (status
& LinkChg
)
4650 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4652 /* We need to see the lastest version of tp->intr_mask to
4653 * avoid ignoring an MSI interrupt and having to wait for
4654 * another event which may never come.
4657 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4658 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4659 tp
->intr_mask
= ~tp
->napi_event
;
4661 if (likely(napi_schedule_prep(&tp
->napi
)))
4662 __napi_schedule(&tp
->napi
);
4663 else if (netif_msg_intr(tp
)) {
4664 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
4669 /* We only get a new MSI interrupt when all active irq
4670 * sources on the chip have been acknowledged. So, ack
4671 * everything we've seen and check if new sources have become
4672 * active to avoid blocking all interrupts from the chip.
4675 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4676 status
= RTL_R16(IntrStatus
);
4679 return IRQ_RETVAL(handled
);
4682 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4684 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4685 struct net_device
*dev
= tp
->dev
;
4686 void __iomem
*ioaddr
= tp
->mmio_addr
;
4689 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4690 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4692 if (work_done
< budget
) {
4693 napi_complete(napi
);
4695 /* We need for force the visibility of tp->intr_mask
4696 * for other CPUs, as we can loose an MSI interrupt
4697 * and potentially wait for a retransmit timeout if we don't.
4698 * The posted write to IntrMask is safe, as it will
4699 * eventually make it to the chip and we won't loose anything
4702 tp
->intr_mask
= 0xffff;
4704 RTL_W16(IntrMask
, tp
->intr_event
);
4710 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4712 struct rtl8169_private
*tp
= netdev_priv(dev
);
4714 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4717 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4718 RTL_W32(RxMissed
, 0);
4721 static void rtl8169_down(struct net_device
*dev
)
4723 struct rtl8169_private
*tp
= netdev_priv(dev
);
4724 void __iomem
*ioaddr
= tp
->mmio_addr
;
4725 unsigned int intrmask
;
4727 rtl8169_delete_timer(dev
);
4729 netif_stop_queue(dev
);
4731 napi_disable(&tp
->napi
);
4734 spin_lock_irq(&tp
->lock
);
4736 rtl8169_asic_down(ioaddr
);
4738 rtl8169_rx_missed(dev
, ioaddr
);
4740 spin_unlock_irq(&tp
->lock
);
4742 synchronize_irq(dev
->irq
);
4744 /* Give a racing hard_start_xmit a few cycles to complete. */
4745 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4748 * And now for the 50k$ question: are IRQ disabled or not ?
4750 * Two paths lead here:
4752 * -> netif_running() is available to sync the current code and the
4753 * IRQ handler. See rtl8169_interrupt for details.
4754 * 2) dev->change_mtu
4755 * -> rtl8169_poll can not be issued again and re-enable the
4756 * interruptions. Let's simply issue the IRQ down sequence again.
4758 * No loop if hotpluged or major error (0xffff).
4760 intrmask
= RTL_R16(IntrMask
);
4761 if (intrmask
&& (intrmask
!= 0xffff))
4764 rtl8169_tx_clear(tp
);
4766 rtl8169_rx_clear(tp
);
4769 static int rtl8169_close(struct net_device
*dev
)
4771 struct rtl8169_private
*tp
= netdev_priv(dev
);
4772 struct pci_dev
*pdev
= tp
->pci_dev
;
4774 /* update counters before going down */
4775 rtl8169_update_counters(dev
);
4779 free_irq(dev
->irq
, dev
);
4781 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4783 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4785 tp
->TxDescArray
= NULL
;
4786 tp
->RxDescArray
= NULL
;
4791 static void rtl_set_rx_mode(struct net_device
*dev
)
4793 struct rtl8169_private
*tp
= netdev_priv(dev
);
4794 void __iomem
*ioaddr
= tp
->mmio_addr
;
4795 unsigned long flags
;
4796 u32 mc_filter
[2]; /* Multicast hash filter */
4800 if (dev
->flags
& IFF_PROMISC
) {
4801 /* Unconditionally log net taps. */
4802 if (netif_msg_link(tp
)) {
4803 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
4807 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4809 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4810 } else if ((dev
->mc_count
> multicast_filter_limit
)
4811 || (dev
->flags
& IFF_ALLMULTI
)) {
4812 /* Too many to filter perfectly -- accept all multicasts. */
4813 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4814 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4816 struct dev_mc_list
*mclist
;
4819 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4820 mc_filter
[1] = mc_filter
[0] = 0;
4821 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
4822 i
++, mclist
= mclist
->next
) {
4823 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
4824 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4825 rx_mode
|= AcceptMulticast
;
4829 spin_lock_irqsave(&tp
->lock
, flags
);
4831 tmp
= rtl8169_rx_config
| rx_mode
|
4832 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4834 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4835 u32 data
= mc_filter
[0];
4837 mc_filter
[0] = swab32(mc_filter
[1]);
4838 mc_filter
[1] = swab32(data
);
4841 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4842 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4844 RTL_W32(RxConfig
, tmp
);
4846 spin_unlock_irqrestore(&tp
->lock
, flags
);
4850 * rtl8169_get_stats - Get rtl8169 read/write statistics
4851 * @dev: The Ethernet Device to get statistics for
4853 * Get TX/RX statistics for rtl8169
4855 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4857 struct rtl8169_private
*tp
= netdev_priv(dev
);
4858 void __iomem
*ioaddr
= tp
->mmio_addr
;
4859 unsigned long flags
;
4861 if (netif_running(dev
)) {
4862 spin_lock_irqsave(&tp
->lock
, flags
);
4863 rtl8169_rx_missed(dev
, ioaddr
);
4864 spin_unlock_irqrestore(&tp
->lock
, flags
);
4870 static void rtl8169_net_suspend(struct net_device
*dev
)
4872 if (!netif_running(dev
))
4875 netif_device_detach(dev
);
4876 netif_stop_queue(dev
);
4881 static int rtl8169_suspend(struct device
*device
)
4883 struct pci_dev
*pdev
= to_pci_dev(device
);
4884 struct net_device
*dev
= pci_get_drvdata(pdev
);
4886 rtl8169_net_suspend(dev
);
4891 static int rtl8169_resume(struct device
*device
)
4893 struct pci_dev
*pdev
= to_pci_dev(device
);
4894 struct net_device
*dev
= pci_get_drvdata(pdev
);
4896 if (!netif_running(dev
))
4899 netif_device_attach(dev
);
4901 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4906 static struct dev_pm_ops rtl8169_pm_ops
= {
4907 .suspend
= rtl8169_suspend
,
4908 .resume
= rtl8169_resume
,
4909 .freeze
= rtl8169_suspend
,
4910 .thaw
= rtl8169_resume
,
4911 .poweroff
= rtl8169_suspend
,
4912 .restore
= rtl8169_resume
,
4915 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4917 #else /* !CONFIG_PM */
4919 #define RTL8169_PM_OPS NULL
4921 #endif /* !CONFIG_PM */
4923 static void rtl_shutdown(struct pci_dev
*pdev
)
4925 struct net_device
*dev
= pci_get_drvdata(pdev
);
4926 struct rtl8169_private
*tp
= netdev_priv(dev
);
4927 void __iomem
*ioaddr
= tp
->mmio_addr
;
4929 rtl8169_net_suspend(dev
);
4931 /* restore original MAC address */
4932 rtl_rar_set(tp
, dev
->perm_addr
);
4934 spin_lock_irq(&tp
->lock
);
4936 rtl8169_asic_down(ioaddr
);
4938 spin_unlock_irq(&tp
->lock
);
4940 if (system_state
== SYSTEM_POWER_OFF
) {
4941 /* WoL fails with some 8168 when the receiver is disabled. */
4942 if (tp
->features
& RTL_FEATURE_WOL
) {
4943 pci_clear_master(pdev
);
4945 RTL_W8(ChipCmd
, CmdRxEnb
);
4950 pci_wake_from_d3(pdev
, true);
4951 pci_set_power_state(pdev
, PCI_D3hot
);
4955 static struct pci_driver rtl8169_pci_driver
= {
4957 .id_table
= rtl8169_pci_tbl
,
4958 .probe
= rtl8169_init_one
,
4959 .remove
= __devexit_p(rtl8169_remove_one
),
4960 .shutdown
= rtl_shutdown
,
4961 .driver
.pm
= RTL8169_PM_OPS
,
4964 static int __init
rtl8169_init_module(void)
4966 return pci_register_driver(&rtl8169_pci_driver
);
4969 static void __exit
rtl8169_cleanup_module(void)
4971 pci_unregister_driver(&rtl8169_pci_driver
);
4974 module_init(rtl8169_init_module
);
4975 module_exit(rtl8169_cleanup_module
);