arch/arm/mach-davinci/clock.c

   1 /*
   2  * Clock and PLL control for DaVinci devices
   3  *
   4  * Copyright (C) 2006-2007 Texas Instruments.
   5  * Copyright (C) 2008-2009 Deep Root Systems, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/mutex.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24
  25 #include <mach/psc.h>
  26 #include <mach/cputype.h>
  27 #include "clock.h"
  28
  29 static LIST_HEAD(clocks);
  30 static DEFINE_MUTEX(clocks_mutex);
  31 static DEFINE_SPINLOCK(clockfw_lock);
  32
  33 static unsigned psc_domain(struct clk *clk)
  34 {
  35         return (clk->flags & PSC_DSP)
  36                 ? DAVINCI_GPSC_DSPDOMAIN
  37                 : DAVINCI_GPSC_ARMDOMAIN;
  38 }
  39
  40 static void __clk_enable(struct clk *clk)
  41 {
  42         if (clk->parent)
  43                 __clk_enable(clk->parent);
  44         if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
  45                 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
  46                                 clk->lpsc, 1);
  47 }
  48
  49 static void __clk_disable(struct clk *clk)
  50 {
  51         if (WARN_ON(clk->usecount == 0))
  52                 return;
  53         if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
  54                 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
  55                                 clk->lpsc, 0);
  56         if (clk->parent)
  57                 __clk_disable(clk->parent);
  58 }
  59
  60 int clk_enable(struct clk *clk)
  61 {
  62         unsigned long flags;
  63
  64         if (clk == NULL || IS_ERR(clk))
  65                 return -EINVAL;
  66
  67         spin_lock_irqsave(&clockfw_lock, flags);
  68         __clk_enable(clk);
  69         spin_unlock_irqrestore(&clockfw_lock, flags);
  70
  71         return 0;
  72 }
  73 EXPORT_SYMBOL(clk_enable);
  74
  75 void clk_disable(struct clk *clk)
  76 {
  77         unsigned long flags;
  78
  79         if (clk == NULL || IS_ERR(clk))
  80                 return;
  81
  82         spin_lock_irqsave(&clockfw_lock, flags);
  83         __clk_disable(clk);
  84         spin_unlock_irqrestore(&clockfw_lock, flags);
  85 }
  86 EXPORT_SYMBOL(clk_disable);
  87
  88 unsigned long clk_get_rate(struct clk *clk)
  89 {
  90         if (clk == NULL || IS_ERR(clk))
  91                 return -EINVAL;
  92
  93         return clk->rate;
  94 }
  95 EXPORT_SYMBOL(clk_get_rate);
  96
  97 long clk_round_rate(struct clk *clk, unsigned long rate)
  98 {
  99         if (clk == NULL || IS_ERR(clk))
 100                 return -EINVAL;
 101
 102         return clk->rate;
 103 }
 104 EXPORT_SYMBOL(clk_round_rate);
 105
 106 int clk_set_rate(struct clk *clk, unsigned long rate)
 107 {
 108         if (clk == NULL || IS_ERR(clk))
 109                 return -EINVAL;
 110
 111         /* changing the clk rate is not supported */
 112         return -EINVAL;
 113 }
 114 EXPORT_SYMBOL(clk_set_rate);
 115
 116 int clk_register(struct clk *clk)
 117 {
 118         if (clk == NULL || IS_ERR(clk))
 119                 return -EINVAL;
 120
 121         if (WARN(clk->parent && !clk->parent->rate,
 122                         "CLK: %s parent %s has no rate!\n",
 123                         clk->name, clk->parent->name))
 124                 return -EINVAL;
 125
 126         INIT_LIST_HEAD(&clk->children);
 127
 128         mutex_lock(&clocks_mutex);
 129         list_add_tail(&clk->node, &clocks);
 130         if (clk->parent)
 131                 list_add_tail(&clk->childnode, &clk->parent->children);
 132         mutex_unlock(&clocks_mutex);
 133
 134         /* If rate is already set, use it */
 135         if (clk->rate)
 136                 return 0;
 137
 138         /* Otherwise, default to parent rate */
 139         if (clk->parent)
 140                 clk->rate = clk->parent->rate;
 141
 142         return 0;
 143 }
 144 EXPORT_SYMBOL(clk_register);
 145
 146 void clk_unregister(struct clk *clk)
 147 {
 148         if (clk == NULL || IS_ERR(clk))
 149                 return;
 150
 151         mutex_lock(&clocks_mutex);
 152         list_del(&clk->node);
 153         list_del(&clk->childnode);
 154         mutex_unlock(&clocks_mutex);
 155 }
 156 EXPORT_SYMBOL(clk_unregister);
 157
 158 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
 159 /*
 160  * Disable any unused clocks left on by the bootloader
 161  */
 162 static int __init clk_disable_unused(void)
 163 {
 164         struct clk *ck;
 165
 166         spin_lock_irq(&clockfw_lock);
 167         list_for_each_entry(ck, &clocks, node) {
 168                 if (ck->usecount > 0)
 169                         continue;
 170                 if (!(ck->flags & CLK_PSC))
 171                         continue;
 172
 173                 /* ignore if in Disabled or SwRstDisable states */
 174                 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
 175                         continue;
 176
 177                 pr_info("Clocks: disable unused %s\n", ck->name);
 178                 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
 179         }
 180         spin_unlock_irq(&clockfw_lock);
 181
 182         return 0;
 183 }
 184 late_initcall(clk_disable_unused);
 185 #endif
 186
 187 static void clk_sysclk_recalc(struct clk *clk)
 188 {
 189         u32 v, plldiv;
 190         struct pll_data *pll;
 191
 192         /* If this is the PLL base clock, no more calculations needed */
 193         if (clk->pll_data)
 194                 return;
 195
 196         if (WARN_ON(!clk->parent))
 197                 return;
 198
 199         clk->rate = clk->parent->rate;
 200
 201         /* Otherwise, the parent must be a PLL */
 202         if (WARN_ON(!clk->parent->pll_data))
 203                 return;
 204
 205         pll = clk->parent->pll_data;
 206
 207         /* If pre-PLL, source clock is before the multiplier and divider(s) */
 208         if (clk->flags & PRE_PLL)
 209                 clk->rate = pll->input_rate;
 210
 211         if (!clk->div_reg)
 212                 return;
 213
 214         v = __raw_readl(pll->base + clk->div_reg);
 215         if (v & PLLDIV_EN) {
 216                 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
 217                 if (plldiv)
 218                         clk->rate /= plldiv;
 219         }
 220 }
 221
 222 static void __init clk_pll_init(struct clk *clk)
 223 {
 224         u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
 225         u8 bypass;
 226         struct pll_data *pll = clk->pll_data;
 227
 228         pll->base = IO_ADDRESS(pll->phys_base);
 229         ctrl = __raw_readl(pll->base + PLLCTL);
 230         clk->rate = pll->input_rate = clk->parent->rate;
 231
 232         if (ctrl & PLLCTL_PLLEN) {
 233                 bypass = 0;
 234                 mult = __raw_readl(pll->base + PLLM);
 235                 if (cpu_is_davinci_dm365())
 236                         mult = 2 * (mult & PLLM_PLLM_MASK);
 237                 else
 238                         mult = (mult & PLLM_PLLM_MASK) + 1;
 239         } else
 240                 bypass = 1;
 241
 242         if (pll->flags & PLL_HAS_PREDIV) {
 243                 prediv = __raw_readl(pll->base + PREDIV);
 244                 if (prediv & PLLDIV_EN)
 245                         prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
 246                 else
 247                         prediv = 1;
 248         }
 249
 250         /* pre-divider is fixed, but (some?) chips won't report that */
 251         if (cpu_is_davinci_dm355() && pll->num == 1)
 252                 prediv = 8;
 253
 254         if (pll->flags & PLL_HAS_POSTDIV) {
 255                 postdiv = __raw_readl(pll->base + POSTDIV);
 256                 if (postdiv & PLLDIV_EN)
 257                         postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
 258                 else
 259                         postdiv = 1;
 260         }
 261
 262         if (!bypass) {
 263                 clk->rate /= prediv;
 264                 clk->rate *= mult;
 265                 clk->rate /= postdiv;
 266         }
 267
 268         pr_debug("PLL%d: input = %lu MHz [ ",
 269                  pll->num, clk->parent->rate / 1000000);
 270         if (bypass)
 271                 pr_debug("bypass ");
 272         if (prediv > 1)
 273                 pr_debug("/ %d ", prediv);
 274         if (mult > 1)
 275                 pr_debug("* %d ", mult);
 276         if (postdiv > 1)
 277                 pr_debug("/ %d ", postdiv);
 278         pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
 279 }
 280
 281 int __init davinci_clk_init(struct davinci_clk *clocks)
 282   {
 283         struct davinci_clk *c;
 284         struct clk *clk;
 285
 286         for (c = clocks; c->lk.clk; c++) {
 287                 clk = c->lk.clk;
 288
 289                 if (clk->pll_data)
 290                         clk_pll_init(clk);
 291
 292                 /* Calculate rates for PLL-derived clocks */
 293                 else if (clk->flags & CLK_PLL)
 294                         clk_sysclk_recalc(clk);
 295
 296                 if (clk->lpsc)
 297                         clk->flags |= CLK_PSC;
 298
 299                 clkdev_add(&c->lk);
 300                 clk_register(clk);
 301
 302                 /* Turn on clocks that Linux doesn't otherwise manage */
 303                 if (clk->flags & ALWAYS_ENABLED)
 304                         clk_enable(clk);
 305         }
 306
 307         return 0;
 308 }
 309
 310 #ifdef CONFIG_PROC_FS
 311 #include <linux/proc_fs.h>
 312 #include <linux/seq_file.h>
 313
 314 static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
 315 {
 316         return *pos < 1 ? (void *)1 : NULL;
 317 }
 318
 319 static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
 320 {
 321         ++*pos;
 322         return NULL;
 323 }
 324
 325 static void davinci_ck_stop(struct seq_file *m, void *v)
 326 {
 327 }
 328
 329 #define CLKNAME_MAX     10              /* longest clock name */
 330 #define NEST_DELTA      2
 331 #define NEST_MAX        4
 332
 333 static void
 334 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 335 {
 336         char            *state;
 337         char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
 338         struct clk      *clk;
 339         unsigned        i;
 340
 341         if (parent->flags & CLK_PLL)
 342                 state = "pll";
 343         else if (parent->flags & CLK_PSC)
 344                 state = "psc";
 345         else
 346                 state = "";
 347
 348         /* <nest spaces> name <pad to end> */
 349         memset(buf, ' ', sizeof(buf) - 1);
 350         buf[sizeof(buf) - 1] = 0;
 351         i = strlen(parent->name);
 352         memcpy(buf + nest, parent->name,
 353                         min(i, (unsigned)(sizeof(buf) - 1 - nest)));
 354
 355         seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
 356                    buf, parent->usecount, state, clk_get_rate(parent));
 357         /* REVISIT show device associations too */
 358
 359         /* cost is now small, but not linear... */
 360         list_for_each_entry(clk, &parent->children, childnode) {
 361                 dump_clock(s, nest + NEST_DELTA, clk);
 362         }
 363 }
 364
 365 static int davinci_ck_show(struct seq_file *m, void *v)
 366 {
 367         /* Show clock tree; we know the main oscillator is first.
 368          * We trust nonzero usecounts equate to PSC enables...
 369          */
 370         mutex_lock(&clocks_mutex);
 371         if (!list_empty(&clocks))
 372                 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
 373         mutex_unlock(&clocks_mutex);
 374
 375         return 0;
 376 }
 377
 378 static const struct seq_operations davinci_ck_op = {
 379         .start  = davinci_ck_start,
 380         .next   = davinci_ck_next,
 381         .stop   = davinci_ck_stop,
 382         .show   = davinci_ck_show
 383 };
 384
 385 static int davinci_ck_open(struct inode *inode, struct file *file)
 386 {
 387         return seq_open(file, &davinci_ck_op);
 388 }
 389
 390 static const struct file_operations proc_davinci_ck_operations = {
 391         .open           = davinci_ck_open,
 392         .read           = seq_read,
 393         .llseek         = seq_lseek,
 394         .release        = seq_release,
 395 };
 396
 397 static int __init davinci_ck_proc_init(void)
 398 {
 399         proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
 400         return 0;
 401
 402 }
 403 __initcall(davinci_ck_proc_init);
 404 #endif /* CONFIG_DEBUG_PROC_FS */