arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/i2c.h>
  20 #include <linux/io.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c/at24.h>
  23 #include <linux/leds.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/mtd/nand.h>
  27 #include <asm/setup.h>
  28 #include <asm/mach-types.h>
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <mach/mux.h>
  32 #include <mach/hardware.h>
  33 #include <mach/dm365.h>
  34 #include <mach/psc.h>
  35 #include <mach/common.h>
  36 #include <mach/i2c.h>
  37 #include <mach/serial.h>
  38 #include <mach/mmc.h>
  39 #include <mach/nand.h>
  40
  41
  42 static inline int have_imager(void)
  43 {
  44         /* REVISIT when it's supported, trigger via Kconfig */
  45         return 0;
  46 }
  47
  48 static inline int have_tvp7002(void)
  49 {
  50         /* REVISIT when it's supported, trigger via Kconfig */
  51         return 0;
  52 }
  53
  54
  55 #define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
  56 #define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
  57 #define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
  58
  59 #define DM365_EVM_PHY_MASK              (0x2)
  60 #define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
  61
  62 /*
  63  * A MAX-II CPLD is used for various board control functions.
  64  */
  65 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  66
  67 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  68 #define CPLD_TEST       CPLD_OFFSET(0,1)
  69 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  70 #define CPLD_MUX        CPLD_OFFSET(0,3)
  71 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  72 #define CPLD_POWER      CPLD_OFFSET(1,1)
  73 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  74 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  75
  76 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  77 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  78
  79 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  80 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  81 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  82 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  83 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  84 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  85 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  86 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  87 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  88
  89 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  90
  91 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  92 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  93 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  94 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  95 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  96 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
  97
  98 static void __iomem *cpld;
  99
 100
 101 /* NOTE:  this is geared for the standard config, with a socketed
 102  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 103  * swap chips with a different block size, partitioning will
 104  * need to be changed. This NAND chip MT29F16G08FAA is the default
 105  * NAND shipped with the Spectrum Digital DM365 EVM
 106  */
 107 #define NAND_BLOCK_SIZE         SZ_128K
 108
 109 static struct mtd_partition davinci_nand_partitions[] = {
 110         {
 111                 /* UBL (a few copies) plus U-Boot */
 112                 .name           = "bootloader",
 113                 .offset         = 0,
 114                 .size           = 28 * NAND_BLOCK_SIZE,
 115                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 116         }, {
 117                 /* U-Boot environment */
 118                 .name           = "params",
 119                 .offset         = MTDPART_OFS_APPEND,
 120                 .size           = 2 * NAND_BLOCK_SIZE,
 121                 .mask_flags     = 0,
 122         }, {
 123                 .name           = "kernel",
 124                 .offset         = MTDPART_OFS_APPEND,
 125                 .size           = SZ_4M,
 126                 .mask_flags     = 0,
 127         }, {
 128                 .name           = "filesystem1",
 129                 .offset         = MTDPART_OFS_APPEND,
 130                 .size           = SZ_512M,
 131                 .mask_flags     = 0,
 132         }, {
 133                 .name           = "filesystem2",
 134                 .offset         = MTDPART_OFS_APPEND,
 135                 .size           = MTDPART_SIZ_FULL,
 136                 .mask_flags     = 0,
 137         }
 138         /* two blocks with bad block table (and mirror) at the end */
 139 };
 140
 141 static struct davinci_nand_pdata davinci_nand_data = {
 142         .mask_chipsel           = BIT(14),
 143         .parts                  = davinci_nand_partitions,
 144         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 145         .ecc_mode               = NAND_ECC_HW,
 146         .options                = NAND_USE_FLASH_BBT,
 147 };
 148
 149 static struct resource davinci_nand_resources[] = {
 150         {
 151                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 152                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 153                 .flags          = IORESOURCE_MEM,
 154         }, {
 155                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 156                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 157                 .flags          = IORESOURCE_MEM,
 158         },
 159 };
 160
 161 static struct platform_device davinci_nand_device = {
 162         .name                   = "davinci_nand",
 163         .id                     = 0,
 164         .num_resources          = ARRAY_SIZE(davinci_nand_resources),
 165         .resource               = davinci_nand_resources,
 166         .dev                    = {
 167                 .platform_data  = &davinci_nand_data,
 168         },
 169 };
 170
 171 static struct at24_platform_data eeprom_info = {
 172         .byte_len       = (256*1024) / 8,
 173         .page_size      = 64,
 174         .flags          = AT24_FLAG_ADDR16,
 175         .setup          = davinci_get_mac_addr,
 176         .context        = (void *)0x7f00,
 177 };
 178
 179 static struct snd_platform_data dm365_evm_snd_data;
 180
 181 static struct i2c_board_info i2c_info[] = {
 182         {
 183                 I2C_BOARD_INFO("24c256", 0x50),
 184                 .platform_data  = &eeprom_info,
 185         },
 186         {
 187                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 188         },
 189 };
 190
 191 static struct davinci_i2c_platform_data i2c_pdata = {
 192         .bus_freq       = 400   /* kHz */,
 193         .bus_delay      = 0     /* usec */,
 194 };
 195
 196 static int cpld_mmc_get_cd(int module)
 197 {
 198         if (!cpld)
 199                 return -ENXIO;
 200
 201         /* low == card present */
 202         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 203 }
 204
 205 static int cpld_mmc_get_ro(int module)
 206 {
 207         if (!cpld)
 208                 return -ENXIO;
 209
 210         /* high == card's write protect switch active */
 211         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 212 }
 213
 214 static struct davinci_mmc_config dm365evm_mmc_config = {
 215         .get_cd         = cpld_mmc_get_cd,
 216         .get_ro         = cpld_mmc_get_ro,
 217         .wires          = 4,
 218         .max_freq       = 50000000,
 219         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 220         .version        = MMC_CTLR_VERSION_2,
 221 };
 222
 223 static void dm365evm_emac_configure(void)
 224 {
 225         /*
 226          * EMAC pins are multiplexed with GPIO and UART
 227          * Further details are available at the DM365 ARM
 228          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 229          */
 230         davinci_cfg_reg(DM365_EMAC_TX_EN);
 231         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 232         davinci_cfg_reg(DM365_EMAC_COL);
 233         davinci_cfg_reg(DM365_EMAC_TXD3);
 234         davinci_cfg_reg(DM365_EMAC_TXD2);
 235         davinci_cfg_reg(DM365_EMAC_TXD1);
 236         davinci_cfg_reg(DM365_EMAC_TXD0);
 237         davinci_cfg_reg(DM365_EMAC_RXD3);
 238         davinci_cfg_reg(DM365_EMAC_RXD2);
 239         davinci_cfg_reg(DM365_EMAC_RXD1);
 240         davinci_cfg_reg(DM365_EMAC_RXD0);
 241         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 242         davinci_cfg_reg(DM365_EMAC_RX_DV);
 243         davinci_cfg_reg(DM365_EMAC_RX_ER);
 244         davinci_cfg_reg(DM365_EMAC_CRS);
 245         davinci_cfg_reg(DM365_EMAC_MDIO);
 246         davinci_cfg_reg(DM365_EMAC_MDCLK);
 247
 248         /*
 249          * EMAC interrupts are multiplexed with GPIO interrupts
 250          * Details are available at the DM365 ARM
 251          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 252          */
 253         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 254         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 255         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 256         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 257 }
 258
 259 static void dm365evm_mmc_configure(void)
 260 {
 261         /*
 262          * MMC/SD pins are multiplexed with GPIO and EMIF
 263          * Further details are available at the DM365 ARM
 264          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 265          */
 266         davinci_cfg_reg(DM365_SD1_CLK);
 267         davinci_cfg_reg(DM365_SD1_CMD);
 268         davinci_cfg_reg(DM365_SD1_DATA3);
 269         davinci_cfg_reg(DM365_SD1_DATA2);
 270         davinci_cfg_reg(DM365_SD1_DATA1);
 271         davinci_cfg_reg(DM365_SD1_DATA0);
 272 }
 273
 274 static void __init evm_init_i2c(void)
 275 {
 276         davinci_init_i2c(&i2c_pdata);
 277         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 278 }
 279
 280 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
 281         &davinci_nand_device,
 282 };
 283
 284 static inline int have_leds(void)
 285 {
 286 #ifdef CONFIG_LEDS_CLASS
 287         return 1;
 288 #else
 289         return 0;
 290 #endif
 291 }
 292
 293 struct cpld_led {
 294         struct led_classdev     cdev;
 295         u8                      mask;
 296 };
 297
 298 static const struct {
 299         const char *name;
 300         const char *trigger;
 301 } cpld_leds[] = {
 302         { "dm365evm::ds2", },
 303         { "dm365evm::ds3", },
 304         { "dm365evm::ds4", },
 305         { "dm365evm::ds5", },
 306         { "dm365evm::ds6", "nand-disk", },
 307         { "dm365evm::ds7", "mmc1", },
 308         { "dm365evm::ds8", "mmc0", },
 309         { "dm365evm::ds9", "heartbeat", },
 310 };
 311
 312 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 313 {
 314         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 315         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 316
 317         if (b != LED_OFF)
 318                 reg &= ~led->mask;
 319         else
 320                 reg |= led->mask;
 321         __raw_writeb(reg, cpld + CPLD_LEDS);
 322 }
 323
 324 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 325 {
 326         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 327         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 328
 329         return (reg & led->mask) ? LED_OFF : LED_FULL;
 330 }
 331
 332 static int __init cpld_leds_init(void)
 333 {
 334         int     i;
 335
 336         if (!have_leds() ||  !cpld)
 337                 return 0;
 338
 339         /* setup LEDs */
 340         __raw_writeb(0xff, cpld + CPLD_LEDS);
 341         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 342                 struct cpld_led *led;
 343
 344                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 345                 if (!led)
 346                         break;
 347
 348                 led->cdev.name = cpld_leds[i].name;
 349                 led->cdev.brightness_set = cpld_led_set;
 350                 led->cdev.brightness_get = cpld_led_get;
 351                 led->cdev.default_trigger = cpld_leds[i].trigger;
 352                 led->mask = BIT(i);
 353
 354                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 355                         kfree(led);
 356                         break;
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362 /* run after subsys_initcall() for LEDs */
 363 fs_initcall(cpld_leds_init);
 364
 365
 366 static void __init evm_init_cpld(void)
 367 {
 368         u8 mux, resets;
 369         const char *label;
 370         struct clk *aemif_clk;
 371
 372         /* Make sure we can configure the CPLD through CS1.  Then
 373          * leave it on for later access to MMC and LED registers.
 374          */
 375         aemif_clk = clk_get(NULL, "aemif");
 376         if (IS_ERR(aemif_clk))
 377                 return;
 378         clk_enable(aemif_clk);
 379
 380         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 381                         "cpld") == NULL)
 382                 goto fail;
 383         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 384         if (!cpld) {
 385                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 386                                 SECTION_SIZE);
 387 fail:
 388                 pr_err("ERROR: can't map CPLD\n");
 389                 clk_disable(aemif_clk);
 390                 return;
 391         }
 392
 393         /* External muxing for some signals */
 394         mux = 0;
 395
 396         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 397          * NOTE:  SW4 bus width setting must match!
 398          */
 399         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 400                 /* external keypad mux */
 401                 mux |= BIT(7);
 402
 403                 platform_add_devices(dm365_evm_nand_devices,
 404                                 ARRAY_SIZE(dm365_evm_nand_devices));
 405         } else {
 406                 /* no OneNAND support yet */
 407         }
 408
 409         /* Leave external chips in reset when unused. */
 410         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 411
 412         /* Static video input config with SN74CBT16214 1-of-3 mux:
 413          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 414          *  - port b2 == imager (mux lowbits == 2 or 7)
 415          *  - port b3 == tvp5146 (mux lowbits == 5)
 416          *
 417          * Runtime switching could work too, with limitations.
 418          */
 419         if (have_imager()) {
 420                 label = "HD imager";
 421                 mux |= 1;
 422
 423                 /* externally mux MMC1/ENET/AIC33 to imager */
 424                 mux |= BIT(6) | BIT(5) | BIT(3);
 425         } else {
 426                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 427
 428                 /* we can use MMC1 ... */
 429                 dm365evm_mmc_configure();
 430                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 431
 432                 /* ... and ENET ... */
 433                 dm365evm_emac_configure();
 434                 soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
 435                 soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
 436                 resets &= ~BIT(3);
 437
 438                 /* ... and AIC33 */
 439                 resets &= ~BIT(1);
 440
 441                 if (have_tvp7002()) {
 442                         mux |= 2;
 443                         resets &= ~BIT(2);
 444                         label = "tvp7002 HD";
 445                 } else {
 446                         /* default to tvp5146 */
 447                         mux |= 5;
 448                         resets &= ~BIT(0);
 449                         label = "tvp5146 SD";
 450                 }
 451         }
 452         __raw_writeb(mux, cpld + CPLD_MUX);
 453         __raw_writeb(resets, cpld + CPLD_RESETS);
 454         pr_info("EVM: %s video input\n", label);
 455
 456         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 457 }
 458
 459 static struct davinci_uart_config uart_config __initdata = {
 460         .enabled_uarts = (1 << 0),
 461 };
 462
 463 static void __init dm365_evm_map_io(void)
 464 {
 465         dm365_init();
 466 }
 467
 468 static __init void dm365_evm_init(void)
 469 {
 470         evm_init_i2c();
 471         davinci_serial_init(&uart_config);
 472
 473         dm365evm_emac_configure();
 474         dm365evm_mmc_configure();
 475
 476         davinci_setup_mmc(0, &dm365evm_mmc_config);
 477
 478         /* maybe setup mmc1/etc ... _after_ mmc0 */
 479         evm_init_cpld();
 480
 481         dm365_init_asp(&dm365_evm_snd_data);
 482 }
 483
 484 static __init void dm365_evm_irq_init(void)
 485 {
 486         davinci_irq_init();
 487 }
 488
 489 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 490         .phys_io        = IO_PHYS,
 491         .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 492         .boot_params    = (0x80000100),
 493         .map_io         = dm365_evm_map_io,
 494         .init_irq       = dm365_evm_irq_init,
 495         .timer          = &davinci_timer,
 496         .init_machine   = dm365_evm_init,
 497 MACHINE_END
 498