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gma500: don't dynamically allocate the psb_gtt struct
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / gma500 / psb_drv.c
blobf6264803375dfba91e4b0413eb4bdb9272f23762
1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "framebuffer.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "intel_bios.h"
30 #include "mid_bios.h"
31 #include "mdfld_dsi_dbi.h"
32 #include <drm/drm_pciids.h>
33 #include "power.h"
34 #include <linux/cpu.h>
35 #include <linux/notifier.h>
36 #include <linux/spinlock.h>
37 #include <linux/pm_runtime.h>
38 #include <acpi/video.h>
39
40 static int drm_psb_trap_pagefaults;
41
42 int drm_psb_no_fb;
43
44 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
45
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
49 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
50
51
52 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
53 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
54 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
55 #if defined(CONFIG_DRM_PSB_MRST)
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
64 #endif
65 #if defined(CONFIG_DRM_PSB_MFLD)
66 { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
67 { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
68 { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
69 { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
70 { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
71 { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
72 { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
73 { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
74 #endif
75 #if defined(CONFIG_DRM_PSB_CDV)
76 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
77 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
78 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
79 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
80 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
81 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
82 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
83 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
84 #endif
85 { 0, 0, 0}
86 };
87 MODULE_DEVICE_TABLE(pci, pciidlist);
88
89 /*
90 * Standard IOCTLs.
91 */
92
93 #define DRM_IOCTL_PSB_SIZES \
94 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
95 struct drm_psb_sizes_arg)
96 #define DRM_IOCTL_PSB_FUSE_REG \
97 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
98 #define DRM_IOCTL_PSB_DC_STATE \
99 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
100 struct drm_psb_dc_state_arg)
101 #define DRM_IOCTL_PSB_ADB \
102 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
103 #define DRM_IOCTL_PSB_MODE_OPERATION \
104 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
105 struct drm_psb_mode_operation_arg)
106 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
107 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
108 struct drm_psb_stolen_memory_arg)
109 #define DRM_IOCTL_PSB_REGISTER_RW \
110 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
111 struct drm_psb_register_rw_arg)
112 #define DRM_IOCTL_PSB_DPST \
113 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
114 uint32_t)
115 #define DRM_IOCTL_PSB_GAMMA \
116 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
117 struct drm_psb_dpst_lut_arg)
118 #define DRM_IOCTL_PSB_DPST_BL \
119 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
120 uint32_t)
121 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
122 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
123 struct drm_psb_get_pipe_from_crtc_id_arg)
124
125 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
126 struct drm_file *file_priv);
127 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
128 struct drm_file *file_priv);
129 static int psb_adb_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file_priv);
131 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
132 struct drm_file *file_priv);
133 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
134 struct drm_file *file_priv);
135 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
136 struct drm_file *file_priv);
137 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
138 struct drm_file *file_priv);
139 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file_priv);
141 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
142 struct drm_file *file_priv);
143
144 #define PSB_IOCTL_DEF(ioctl, func, flags) \
145 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
146
147 static struct drm_ioctl_desc psb_ioctls[] = {
148 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
149 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
150 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
152 DRM_AUTH),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
154 DRM_AUTH),
155 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
156 DRM_AUTH),
157 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
159 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
160 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
161 psb_intel_get_pipe_from_crtc_id, 0),
162
163 };
164
165 static void psb_lastclose(struct drm_device *dev)
166 {
167 return;
168 }
169
170 static void psb_do_takedown(struct drm_device *dev)
171 {
172 /* FIXME: do we need to clean up the gtt here ? */
173 }
174
175 static int psb_do_init(struct drm_device *dev)
176 {
177 struct drm_psb_private *dev_priv =
178 (struct drm_psb_private *) dev->dev_private;
179 struct psb_gtt *pg = &dev_priv->gtt;
180
181 uint32_t stolen_gtt;
182
183 int ret = -ENOMEM;
184
185 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
186 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
187 ret = -EINVAL;
188 goto out_err;
189 }
190
191
192 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
193 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
194 stolen_gtt =
195 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
196
197 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
198 (stolen_gtt << PAGE_SHIFT) * 1024;
199
200 if (1 || drm_debug) {
201 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
202 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
203 DRM_INFO("SGX core id = 0x%08x\n", core_id);
204 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
205 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
206 _PSB_CC_REVISION_MAJOR_SHIFT,
207 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
208 _PSB_CC_REVISION_MINOR_SHIFT);
209 DRM_INFO
210 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
211 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
212 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
213 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
214 _PSB_CC_REVISION_DESIGNER_SHIFT);
215 }
216
217
218 spin_lock_init(&dev_priv->irqmask_lock);
219
220 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
221 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
222 PSB_RSGX32(PSB_CR_BIF_BANK1);
223 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
224 PSB_CR_BIF_CTRL);
225 psb_spank(dev_priv);
226
227 /* mmu_gatt ?? */
228 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
229 return 0;
230 out_err:
231 psb_do_takedown(dev);
232 return ret;
233 }
234
235 static int psb_driver_unload(struct drm_device *dev)
236 {
237 struct drm_psb_private *dev_priv = dev->dev_private;
238
239 /* Kill vblank etc here */
240
241 gma_backlight_exit(dev);
242
243 if (drm_psb_no_fb == 0)
244 psb_modeset_cleanup(dev);
245
246 if (dev_priv) {
247 psb_lid_timer_takedown(dev_priv);
248 gma_intel_opregion_exit(dev);
249
250 psb_do_takedown(dev);
251
252
253 if (dev_priv->pf_pd) {
254 psb_mmu_free_pagedir(dev_priv->pf_pd);
255 dev_priv->pf_pd = NULL;
256 }
257 if (dev_priv->mmu) {
258 struct psb_gtt *pg = &dev_priv->gtt;
259
260 down_read(&pg->sem);
261 psb_mmu_remove_pfn_sequence(
262 psb_mmu_get_default_pd
263 (dev_priv->mmu),
264 pg->mmu_gatt_start,
265 dev_priv->vram_stolen_size >> PAGE_SHIFT);
266 up_read(&pg->sem);
267 psb_mmu_driver_takedown(dev_priv->mmu);
268 dev_priv->mmu = NULL;
269 }
270 psb_gtt_takedown(dev);
271 if (dev_priv->scratch_page) {
272 __free_page(dev_priv->scratch_page);
273 dev_priv->scratch_page = NULL;
274 }
275 if (dev_priv->vdc_reg) {
276 iounmap(dev_priv->vdc_reg);
277 dev_priv->vdc_reg = NULL;
278 }
279 if (dev_priv->sgx_reg) {
280 iounmap(dev_priv->sgx_reg);
281 dev_priv->sgx_reg = NULL;
282 }
283
284 kfree(dev_priv);
285 dev->dev_private = NULL;
286
287 /*destroy VBT data*/
288 psb_intel_destroy_bios(dev);
289 }
290
291 gma_power_uninit(dev);
292
293 return 0;
294 }
295
296
297 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
298 {
299 struct drm_psb_private *dev_priv;
300 unsigned long resource_start;
301 struct psb_gtt *pg;
302 unsigned long irqflags;
303 int ret = -ENOMEM;
304 uint32_t tt_pages;
305 struct drm_connector *connector;
306 struct psb_intel_output *psb_intel_output;
307
308 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
309 if (dev_priv == NULL)
310 return -ENOMEM;
311
312 dev_priv->ops = (struct psb_ops *)chipset;
313 dev_priv->dev = dev;
314 dev->dev_private = (void *) dev_priv;
315
316 dev_priv->num_pipe = dev_priv->ops->pipes;
317
318 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
319
320 dev_priv->vdc_reg =
321 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
322 if (!dev_priv->vdc_reg)
323 goto out_err;
324
325 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
326 PSB_SGX_SIZE);
327 if (!dev_priv->sgx_reg)
328 goto out_err;
329
330 ret = dev_priv->ops->chip_setup(dev);
331 if (ret)
332 goto out_err;
333
334 /* Init OSPM support */
335 gma_power_init(dev);
336
337 ret = -ENOMEM;
338
339 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
340 if (!dev_priv->scratch_page)
341 goto out_err;
342
343 set_pages_uc(dev_priv->scratch_page, 1);
344
345 ret = psb_gtt_init(dev, 0);
346 if (ret)
347 goto out_err;
348
349 dev_priv->mmu = psb_mmu_driver_init((void *)0,
350 drm_psb_trap_pagefaults, 0,
351 dev_priv);
352 if (!dev_priv->mmu)
353 goto out_err;
354
355 pg = &dev_priv->gtt;
356
357 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
358 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
359
360
361 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
362 if (!dev_priv->pf_pd)
363 goto out_err;
364
365 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
366 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
367
368 ret = psb_do_init(dev);
369 if (ret)
370 return ret;
371
372 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
373 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
374
375 /* igd_opregion_init(&dev_priv->opregion_dev); */
376 acpi_video_register();
377 if (dev_priv->lid_state)
378 psb_lid_timer_init(dev_priv);
379
380 ret = drm_vblank_init(dev, dev_priv->num_pipe);
381 if (ret)
382 goto out_err;
383
384 /*
385 * Install interrupt handlers prior to powering off SGX or else we will
386 * crash.
387 */
388 dev_priv->vdc_irq_mask = 0;
389 dev_priv->pipestat[0] = 0;
390 dev_priv->pipestat[1] = 0;
391 dev_priv->pipestat[2] = 0;
392 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
393 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
394 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
395 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
396 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
397 if (drm_core_check_feature(dev, DRIVER_MODESET))
398 drm_irq_install(dev);
399
400 dev->vblank_disable_allowed = 1;
401
402 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
403
404 dev->driver->get_vblank_counter = psb_get_vblank_counter;
405
406 #if defined(CONFIG_DRM_PSB_MFLD)
407 /* FIXME: this is not the right place for this stuff ! */
408 if (IS_MFLD(dev)) {
409 #ifdef CONFIG_MDFLD_DSI_DPU
410 /*init dpu info*/
411 mdfld_dbi_dpu_init(dev);
412 #else
413 mdfld_dbi_dsr_init(dev);
414 #endif /*CONFIG_MDFLD_DSI_DPU*/
415 /* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/
416 }
417 #endif
418 if (drm_psb_no_fb == 0) {
419 psb_modeset_init(dev);
420 psb_fbdev_init(dev);
421 drm_kms_helper_poll_init(dev);
422 }
423
424 /* Only add backlight support if we have LVDS output */
425 list_for_each_entry(connector, &dev->mode_config.connector_list,
426 head) {
427 psb_intel_output = to_psb_intel_output(connector);
428
429 switch (psb_intel_output->type) {
430 case INTEL_OUTPUT_LVDS:
431 ret = gma_backlight_init(dev);
432 break;
433 }
434 }
435
436 if (ret)
437 return ret;
438 #if 0
439 /*enable runtime pm at last*/
440 pm_runtime_enable(&dev->pdev->dev);
441 pm_runtime_set_active(&dev->pdev->dev);
442 #endif
443 /*Intel drm driver load is done, continue doing pvr load*/
444 return 0;
445 out_err:
446 psb_driver_unload(dev);
447 return ret;
448 }
449
450 int psb_driver_device_is_agp(struct drm_device *dev)
451 {
452 return 0;
453 }
454
455
456 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
457 struct drm_file *file_priv)
458 {
459 struct drm_psb_private *dev_priv = psb_priv(dev);
460 struct drm_psb_sizes_arg *arg =
461 (struct drm_psb_sizes_arg *) data;
462
463 *arg = dev_priv->sizes;
464 return 0;
465 }
466
467 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
468 struct drm_file *file_priv)
469 {
470 uint32_t flags;
471 uint32_t obj_id;
472 struct drm_mode_object *obj;
473 struct drm_connector *connector;
474 struct drm_crtc *crtc;
475 struct drm_psb_dc_state_arg *arg =
476 (struct drm_psb_dc_state_arg *)data;
477
478
479 /* Double check MRST case */
480 if (IS_MRST(dev) || IS_MFLD(dev))
481 return -EOPNOTSUPP;
482
483 flags = arg->flags;
484 obj_id = arg->obj_id;
485
486 if (flags & PSB_DC_CRTC_MASK) {
487 obj = drm_mode_object_find(dev, obj_id,
488 DRM_MODE_OBJECT_CRTC);
489 if (!obj) {
490 dev_dbg(dev->dev, "Invalid CRTC object.\n");
491 return -EINVAL;
492 }
493
494 crtc = obj_to_crtc(obj);
495
496 mutex_lock(&dev->mode_config.mutex);
497 if (drm_helper_crtc_in_use(crtc)) {
498 if (flags & PSB_DC_CRTC_SAVE)
499 crtc->funcs->save(crtc);
500 else
501 crtc->funcs->restore(crtc);
502 }
503 mutex_unlock(&dev->mode_config.mutex);
504
505 return 0;
506 } else if (flags & PSB_DC_OUTPUT_MASK) {
507 obj = drm_mode_object_find(dev, obj_id,
508 DRM_MODE_OBJECT_CONNECTOR);
509 if (!obj) {
510 dev_dbg(dev->dev, "Invalid connector id.\n");
511 return -EINVAL;
512 }
513
514 connector = obj_to_connector(obj);
515 if (flags & PSB_DC_OUTPUT_SAVE)
516 connector->funcs->save(connector);
517 else
518 connector->funcs->restore(connector);
519
520 return 0;
521 }
522 return -EINVAL;
523 }
524
525 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv)
527 {
528 struct drm_psb_private *dev_priv = psb_priv(dev);
529 uint32_t *arg = data;
530 struct backlight_device *bd = dev_priv->backlight_device;
531 dev_priv->blc_adj2 = *arg;
532
533 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
534 if (bd) {
535 bd->props.brightness = bd->ops->get_brightness(bd);
536 backlight_update_status(bd);
537 }
538 #endif
539 return 0;
540 }
541
542 static int psb_adb_ioctl(struct drm_device *dev, void *data,
543 struct drm_file *file_priv)
544 {
545 struct drm_psb_private *dev_priv = psb_priv(dev);
546 uint32_t *arg = data;
547 struct backlight_device *bd = dev_priv->backlight_device;
548 dev_priv->blc_adj1 = *arg;
549
550 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
551 if (bd) {
552 bd->props.brightness = bd->ops->get_brightness(bd);
553 backlight_update_status(bd);
554 }
555 #endif
556 return 0;
557 }
558
559 /* return the current mode to the dpst module */
560 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
561 struct drm_file *file_priv)
562 {
563 struct drm_psb_private *dev_priv = psb_priv(dev);
564 uint32_t *arg = data;
565 uint32_t x;
566 uint32_t y;
567 uint32_t reg;
568
569 if (!gma_power_begin(dev, 0))
570 return -EIO;
571
572 reg = PSB_RVDC32(PIPEASRC);
573
574 gma_power_end(dev);
575
576 /* horizontal is the left 16 bits */
577 x = reg >> 16;
578 /* vertical is the right 16 bits */
579 y = reg & 0x0000ffff;
580
581 /* the values are the image size minus one */
582 x++;
583 y++;
584
585 *arg = (x << 16) | y;
586
587 return 0;
588 }
589 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *file_priv)
591 {
592 struct drm_psb_dpst_lut_arg *lut_arg = data;
593 struct drm_mode_object *obj;
594 struct drm_crtc *crtc;
595 struct drm_connector *connector;
596 struct psb_intel_crtc *psb_intel_crtc;
597 int i = 0;
598 int32_t obj_id;
599
600 obj_id = lut_arg->output_id;
601 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
602 if (!obj) {
603 dev_dbg(dev->dev, "Invalid Connector object.\n");
604 return -EINVAL;
605 }
606
607 connector = obj_to_connector(obj);
608 crtc = connector->encoder->crtc;
609 psb_intel_crtc = to_psb_intel_crtc(crtc);
610
611 for (i = 0; i < 256; i++)
612 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
613
614 psb_intel_crtc_load_lut(crtc);
615
616 return 0;
617 }
618
619 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
620 struct drm_file *file_priv)
621 {
622 uint32_t obj_id;
623 uint16_t op;
624 struct drm_mode_modeinfo *umode;
625 struct drm_display_mode *mode = NULL;
626 struct drm_psb_mode_operation_arg *arg;
627 struct drm_mode_object *obj;
628 struct drm_connector *connector;
629 struct drm_framebuffer *drm_fb;
630 struct psb_framebuffer *psb_fb;
631 struct drm_connector_helper_funcs *connector_funcs;
632 int ret = 0;
633 int resp = MODE_OK;
634 struct drm_psb_private *dev_priv = psb_priv(dev);
635
636 arg = (struct drm_psb_mode_operation_arg *)data;
637 obj_id = arg->obj_id;
638 op = arg->operation;
639
640 switch (op) {
641 case PSB_MODE_OPERATION_SET_DC_BASE:
642 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
643 if (!obj) {
644 dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
645 return -EINVAL;
646 }
647
648 drm_fb = obj_to_fb(obj);
649 psb_fb = to_psb_fb(drm_fb);
650
651 if (gma_power_begin(dev, 0)) {
652 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
653 REG_READ(DSPASURF);
654 gma_power_end(dev);
655 } else {
656 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
657 }
658
659 return 0;
660 case PSB_MODE_OPERATION_MODE_VALID:
661 umode = &arg->mode;
662
663 mutex_lock(&dev->mode_config.mutex);
664
665 obj = drm_mode_object_find(dev, obj_id,
666 DRM_MODE_OBJECT_CONNECTOR);
667 if (!obj) {
668 ret = -EINVAL;
669 goto mode_op_out;
670 }
671
672 connector = obj_to_connector(obj);
673
674 mode = drm_mode_create(dev);
675 if (!mode) {
676 ret = -ENOMEM;
677 goto mode_op_out;
678 }
679
680 /* drm_crtc_convert_umode(mode, umode); */
681 {
682 mode->clock = umode->clock;
683 mode->hdisplay = umode->hdisplay;
684 mode->hsync_start = umode->hsync_start;
685 mode->hsync_end = umode->hsync_end;
686 mode->htotal = umode->htotal;
687 mode->hskew = umode->hskew;
688 mode->vdisplay = umode->vdisplay;
689 mode->vsync_start = umode->vsync_start;
690 mode->vsync_end = umode->vsync_end;
691 mode->vtotal = umode->vtotal;
692 mode->vscan = umode->vscan;
693 mode->vrefresh = umode->vrefresh;
694 mode->flags = umode->flags;
695 mode->type = umode->type;
696 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
697 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
698 }
699
700 connector_funcs = (struct drm_connector_helper_funcs *)
701 connector->helper_private;
702
703 if (connector_funcs->mode_valid) {
704 resp = connector_funcs->mode_valid(connector, mode);
705 arg->data = (void *)resp;
706 }
707
708 /*do some clean up work*/
709 if (mode)
710 drm_mode_destroy(dev, mode);
711 mode_op_out:
712 mutex_unlock(&dev->mode_config.mutex);
713 return ret;
714
715 default:
716 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
717 return -EOPNOTSUPP;
718 }
719
720 return 0;
721 }
722
723 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
725 {
726 struct drm_psb_private *dev_priv = psb_priv(dev);
727 struct drm_psb_stolen_memory_arg *arg = data;
728
729 arg->base = dev_priv->stolen_base;
730 arg->size = dev_priv->vram_stolen_size;
731
732 return 0;
733 }
734
735 /* FIXME: needs Medfield changes */
736 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *file_priv)
738 {
739 struct drm_psb_private *dev_priv = psb_priv(dev);
740 struct drm_psb_register_rw_arg *arg = data;
741 bool usage = arg->b_force_hw_on ? true : false;
742
743 if (arg->display_write_mask != 0) {
744 if (gma_power_begin(dev, usage)) {
745 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
746 PSB_WVDC32(arg->display.pfit_controls,
747 PFIT_CONTROL);
748 if (arg->display_write_mask &
749 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
750 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
751 PFIT_AUTO_RATIOS);
752 if (arg->display_write_mask &
753 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
754 PSB_WVDC32(
755 arg->display.pfit_programmed_scale_ratios,
756 PFIT_PGM_RATIOS);
757 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
758 PSB_WVDC32(arg->display.pipeasrc,
759 PIPEASRC);
760 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
761 PSB_WVDC32(arg->display.pipebsrc,
762 PIPEBSRC);
763 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
764 PSB_WVDC32(arg->display.vtotal_a,
765 VTOTAL_A);
766 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
767 PSB_WVDC32(arg->display.vtotal_b,
768 VTOTAL_B);
769 gma_power_end(dev);
770 } else {
771 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
772 dev_priv->savePFIT_CONTROL =
773 arg->display.pfit_controls;
774 if (arg->display_write_mask &
775 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
776 dev_priv->savePFIT_AUTO_RATIOS =
777 arg->display.pfit_autoscale_ratios;
778 if (arg->display_write_mask &
779 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
780 dev_priv->savePFIT_PGM_RATIOS =
781 arg->display.pfit_programmed_scale_ratios;
782 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
783 dev_priv->savePIPEASRC = arg->display.pipeasrc;
784 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
785 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
786 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
787 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
788 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
789 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
790 }
791 }
792
793 if (arg->display_read_mask != 0) {
794 if (gma_power_begin(dev, usage)) {
795 if (arg->display_read_mask &
796 REGRWBITS_PFIT_CONTROLS)
797 arg->display.pfit_controls =
798 PSB_RVDC32(PFIT_CONTROL);
799 if (arg->display_read_mask &
800 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
801 arg->display.pfit_autoscale_ratios =
802 PSB_RVDC32(PFIT_AUTO_RATIOS);
803 if (arg->display_read_mask &
804 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
805 arg->display.pfit_programmed_scale_ratios =
806 PSB_RVDC32(PFIT_PGM_RATIOS);
807 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
808 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
809 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
810 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
811 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
812 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
813 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
814 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
815 gma_power_end(dev);
816 } else {
817 if (arg->display_read_mask &
818 REGRWBITS_PFIT_CONTROLS)
819 arg->display.pfit_controls =
820 dev_priv->savePFIT_CONTROL;
821 if (arg->display_read_mask &
822 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
823 arg->display.pfit_autoscale_ratios =
824 dev_priv->savePFIT_AUTO_RATIOS;
825 if (arg->display_read_mask &
826 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
827 arg->display.pfit_programmed_scale_ratios =
828 dev_priv->savePFIT_PGM_RATIOS;
829 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
830 arg->display.pipeasrc = dev_priv->savePIPEASRC;
831 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
832 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
833 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
834 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
835 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
836 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
837 }
838 }
839
840 if (arg->overlay_write_mask != 0) {
841 if (gma_power_begin(dev, usage)) {
842 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
843 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
844 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
845 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
846 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
847 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
848 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
849 }
850 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
851 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
852 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
853 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
854 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
855 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
856 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
857 }
858
859 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
860 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
861
862 if (arg->overlay.b_wait_vblank) {
863 /* Wait for 20ms.*/
864 unsigned long vblank_timeout = jiffies
865 + HZ/50;
866 uint32_t temp;
867 while (time_before_eq(jiffies,
868 vblank_timeout)) {
869 temp = PSB_RVDC32(OV_DOVASTA);
870 if ((temp & (0x1 << 31)) != 0)
871 break;
872 cpu_relax();
873 }
874 }
875 }
876 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
877 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
878 if (arg->overlay.b_wait_vblank) {
879 /* Wait for 20ms.*/
880 unsigned long vblank_timeout =
881 jiffies + HZ/50;
882 uint32_t temp;
883 while (time_before_eq(jiffies,
884 vblank_timeout)) {
885 temp = PSB_RVDC32(OVC_DOVCSTA);
886 if ((temp & (0x1 << 31)) != 0)
887 break;
888 cpu_relax();
889 }
890 }
891 }
892 gma_power_end(dev);
893 } else {
894 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
895 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
896 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
897 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
898 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
899 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
900 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
901 }
902 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
903 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
904 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
905 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
906 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
907 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
908 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
909 }
910 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
911 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
912 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
913 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
914 }
915 }
916
917 if (arg->overlay_read_mask != 0) {
918 if (gma_power_begin(dev, usage)) {
919 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
920 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
921 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
922 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
923 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
924 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
925 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
926 }
927 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
928 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
929 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
930 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
931 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
932 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
933 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
934 }
935 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
936 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
937 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
938 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
939 gma_power_end(dev);
940 } else {
941 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
942 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
943 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
944 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
945 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
946 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
947 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
948 }
949 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
950 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
951 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
952 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
953 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
954 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
955 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
956 }
957 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
958 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
959 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
960 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
961 }
962 }
963
964 if (arg->sprite_enable_mask != 0) {
965 if (gma_power_begin(dev, usage)) {
966 PSB_WVDC32(0x1F3E, DSPARB);
967 PSB_WVDC32(arg->sprite.dspa_control
968 | PSB_RVDC32(DSPACNTR), DSPACNTR);
969 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
970 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
971 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
972 PSB_RVDC32(DSPASURF);
973 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
974 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
975 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
976 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
977 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
978 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
979 PSB_RVDC32(DSPCSURF);
980 gma_power_end(dev);
981 }
982 }
983
984 if (arg->sprite_disable_mask != 0) {
985 if (gma_power_begin(dev, usage)) {
986 PSB_WVDC32(0x3F3E, DSPARB);
987 PSB_WVDC32(0x0, DSPCCNTR);
988 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
989 PSB_RVDC32(DSPCSURF);
990 gma_power_end(dev);
991 }
992 }
993
994 if (arg->subpicture_enable_mask != 0) {
995 if (gma_power_begin(dev, usage)) {
996 uint32_t temp;
997 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
998 temp = PSB_RVDC32(DSPACNTR);
999 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1000 temp &= ~DISPPLANE_BOTTOM;
1001 temp |= DISPPLANE_32BPP;
1002 PSB_WVDC32(temp, DSPACNTR);
1003
1004 temp = PSB_RVDC32(DSPABASE);
1005 PSB_WVDC32(temp, DSPABASE);
1006 PSB_RVDC32(DSPABASE);
1007 temp = PSB_RVDC32(DSPASURF);
1008 PSB_WVDC32(temp, DSPASURF);
1009 PSB_RVDC32(DSPASURF);
1010 }
1011 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1012 temp = PSB_RVDC32(DSPBCNTR);
1013 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1014 temp &= ~DISPPLANE_BOTTOM;
1015 temp |= DISPPLANE_32BPP;
1016 PSB_WVDC32(temp, DSPBCNTR);
1017
1018 temp = PSB_RVDC32(DSPBBASE);
1019 PSB_WVDC32(temp, DSPBBASE);
1020 PSB_RVDC32(DSPBBASE);
1021 temp = PSB_RVDC32(DSPBSURF);
1022 PSB_WVDC32(temp, DSPBSURF);
1023 PSB_RVDC32(DSPBSURF);
1024 }
1025 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1026 temp = PSB_RVDC32(DSPCCNTR);
1027 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1028 temp &= ~DISPPLANE_BOTTOM;
1029 temp |= DISPPLANE_32BPP;
1030 PSB_WVDC32(temp, DSPCCNTR);
1031
1032 temp = PSB_RVDC32(DSPCBASE);
1033 PSB_WVDC32(temp, DSPCBASE);
1034 PSB_RVDC32(DSPCBASE);
1035 temp = PSB_RVDC32(DSPCSURF);
1036 PSB_WVDC32(temp, DSPCSURF);
1037 PSB_RVDC32(DSPCSURF);
1038 }
1039 gma_power_end(dev);
1040 }
1041 }
1042
1043 if (arg->subpicture_disable_mask != 0) {
1044 if (gma_power_begin(dev, usage)) {
1045 uint32_t temp;
1046 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1047 temp = PSB_RVDC32(DSPACNTR);
1048 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1049 temp |= DISPPLANE_32BPP_NO_ALPHA;
1050 PSB_WVDC32(temp, DSPACNTR);
1051
1052 temp = PSB_RVDC32(DSPABASE);
1053 PSB_WVDC32(temp, DSPABASE);
1054 PSB_RVDC32(DSPABASE);
1055 temp = PSB_RVDC32(DSPASURF);
1056 PSB_WVDC32(temp, DSPASURF);
1057 PSB_RVDC32(DSPASURF);
1058 }
1059 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1060 temp = PSB_RVDC32(DSPBCNTR);
1061 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1062 temp |= DISPPLANE_32BPP_NO_ALPHA;
1063 PSB_WVDC32(temp, DSPBCNTR);
1064
1065 temp = PSB_RVDC32(DSPBBASE);
1066 PSB_WVDC32(temp, DSPBBASE);
1067 PSB_RVDC32(DSPBBASE);
1068 temp = PSB_RVDC32(DSPBSURF);
1069 PSB_WVDC32(temp, DSPBSURF);
1070 PSB_RVDC32(DSPBSURF);
1071 }
1072 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1073 temp = PSB_RVDC32(DSPCCNTR);
1074 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1075 temp |= DISPPLANE_32BPP_NO_ALPHA;
1076 PSB_WVDC32(temp, DSPCCNTR);
1077
1078 temp = PSB_RVDC32(DSPCBASE);
1079 PSB_WVDC32(temp, DSPCBASE);
1080 PSB_RVDC32(DSPCBASE);
1081 temp = PSB_RVDC32(DSPCSURF);
1082 PSB_WVDC32(temp, DSPCSURF);
1083 PSB_RVDC32(DSPCSURF);
1084 }
1085 gma_power_end(dev);
1086 }
1087 }
1088
1089 return 0;
1090 }
1091
1092 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1093 {
1094 return 0;
1095 }
1096
1097 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1098 {
1099 }
1100
1101 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1102 unsigned long arg)
1103 {
1104 struct drm_file *file_priv = filp->private_data;
1105 struct drm_device *dev = file_priv->minor->dev;
1106 struct drm_psb_private *dev_priv = dev->dev_private;
1107 static unsigned int runtime_allowed;
1108
1109 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1110 runtime_allowed++;
1111 pm_runtime_allow(&dev->pdev->dev);
1112 dev_priv->rpm_enabled = 1;
1113 }
1114 return drm_ioctl(filp, cmd, arg);
1115 /* FIXME: do we need to wrap the other side of this */
1116 }
1117
1118
1119 /* When a client dies:
1120 * - Check for and clean up flipped page state
1121 */
1122 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1123 {
1124 }
1125
1126 static void psb_remove(struct pci_dev *pdev)
1127 {
1128 struct drm_device *dev = pci_get_drvdata(pdev);
1129 drm_put_dev(dev);
1130 }
1131
1132 static const struct dev_pm_ops psb_pm_ops = {
1133 .runtime_suspend = psb_runtime_suspend,
1134 .runtime_resume = psb_runtime_resume,
1135 .runtime_idle = psb_runtime_idle,
1136 };
1137
1138 static struct vm_operations_struct psb_gem_vm_ops = {
1139 .fault = psb_gem_fault,
1140 .open = drm_gem_vm_open,
1141 .close = drm_gem_vm_close,
1142 };
1143
1144 static struct drm_driver driver = {
1145 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1146 DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1147 .load = psb_driver_load,
1148 .unload = psb_driver_unload,
1149
1150 .ioctls = psb_ioctls,
1151 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1152 .device_is_agp = psb_driver_device_is_agp,
1153 .irq_preinstall = psb_irq_preinstall,
1154 .irq_postinstall = psb_irq_postinstall,
1155 .irq_uninstall = psb_irq_uninstall,
1156 .irq_handler = psb_irq_handler,
1157 .enable_vblank = psb_enable_vblank,
1158 .disable_vblank = psb_disable_vblank,
1159 .get_vblank_counter = psb_get_vblank_counter,
1160 .lastclose = psb_lastclose,
1161 .open = psb_driver_open,
1162 .preclose = psb_driver_preclose,
1163 .postclose = psb_driver_close,
1164 .reclaim_buffers = drm_core_reclaim_buffers,
1165
1166 .gem_init_object = psb_gem_init_object,
1167 .gem_free_object = psb_gem_free_object,
1168 .gem_vm_ops = &psb_gem_vm_ops,
1169 .dumb_create = psb_gem_dumb_create,
1170 .dumb_map_offset = psb_gem_dumb_map_gtt,
1171 .dumb_destroy = psb_gem_dumb_destroy,
1172
1173 .fops = {
1174 .owner = THIS_MODULE,
1175 .open = drm_open,
1176 .release = drm_release,
1177 .unlocked_ioctl = psb_unlocked_ioctl,
1178 .mmap = drm_gem_mmap,
1179 .poll = drm_poll,
1180 .fasync = drm_fasync,
1181 .read = drm_read,
1182 },
1183 .name = DRIVER_NAME,
1184 .desc = DRIVER_DESC,
1185 .date = PSB_DRM_DRIVER_DATE,
1186 .major = PSB_DRM_DRIVER_MAJOR,
1187 .minor = PSB_DRM_DRIVER_MINOR,
1188 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1189 };
1190
1191 static struct pci_driver psb_pci_driver = {
1192 .name = DRIVER_NAME,
1193 .id_table = pciidlist,
1194 .resume = gma_power_resume,
1195 .suspend = gma_power_suspend,
1196 .probe = psb_probe,
1197 .remove = psb_remove,
1198 #ifdef CONFIG_PM
1199 .driver.pm = &psb_pm_ops,
1200 #endif
1201 };
1202
1203 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1204 {
1205 /* MLD Added this from Inaky's patch */
1206 if (pci_enable_msi(pdev))
1207 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1208 return drm_get_pci_dev(pdev, ent, &driver);
1209 }
1210
1211 static int __init psb_init(void)
1212 {
1213 return drm_pci_init(&driver, &psb_pci_driver);
1214 }
1215
1216 static void __exit psb_exit(void)
1217 {
1218 drm_pci_exit(&driver, &psb_pci_driver);
1219 }
1220
1221 late_initcall(psb_init);
1222 module_exit(psb_exit);
1223
1224 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1225 MODULE_DESCRIPTION(DRIVER_DESC);
1226 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree