2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
29 #include <asm/mpc52xx.h>
30 #include <sysdev/fsl_soc.h>
32 #define DRV_NAME "mpc-i2c"
34 #define MPC_I2C_CLOCK_LEGACY 0
35 #define MPC_I2C_CLOCK_PRESERVE (~0U)
37 #define MPC_I2C_FDR 0x04
38 #define MPC_I2C_CR 0x08
39 #define MPC_I2C_SR 0x0c
40 #define MPC_I2C_DR 0x10
41 #define MPC_I2C_DFSRR 0x14
62 wait_queue_head_t queue
;
63 struct i2c_adapter adap
;
67 struct mpc_i2c_divider
{
69 u16 fdr
; /* including dfsrr */
73 void (*setup
)(struct device_node
*node
, struct mpc_i2c
*i2c
,
74 u32 clock
, u32 prescaler
);
78 static inline void writeccr(struct mpc_i2c
*i2c
, u32 x
)
80 writeb(x
, i2c
->base
+ MPC_I2C_CR
);
83 static irqreturn_t
mpc_i2c_isr(int irq
, void *dev_id
)
85 struct mpc_i2c
*i2c
= dev_id
;
86 if (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
) {
87 /* Read again to allow register to stabilise */
88 i2c
->interrupt
= readb(i2c
->base
+ MPC_I2C_SR
);
89 writeb(0, i2c
->base
+ MPC_I2C_SR
);
95 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
96 * the bus, because it wants to send ACK.
97 * Following sequence of enabling/disabling and sending start/stop generates
98 * the pulse, so it's all OK.
100 static void mpc_i2c_fixup(struct mpc_i2c
*i2c
)
104 writeccr(i2c
, CCR_MEN
);
106 writeccr(i2c
, CCR_MSTA
| CCR_MTX
);
108 writeccr(i2c
, CCR_MSTA
| CCR_MTX
| CCR_MEN
);
110 writeccr(i2c
, CCR_MEN
);
114 static int i2c_wait(struct mpc_i2c
*i2c
, unsigned timeout
, int writing
)
116 unsigned long orig_jiffies
= jiffies
;
120 if (i2c
->irq
== NO_IRQ
) {
121 while (!(readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
)) {
123 if (time_after(jiffies
, orig_jiffies
+ timeout
)) {
124 dev_dbg(i2c
->dev
, "timeout\n");
130 x
= readb(i2c
->base
+ MPC_I2C_SR
);
131 writeb(0, i2c
->base
+ MPC_I2C_SR
);
134 result
= wait_event_timeout(i2c
->queue
,
135 (i2c
->interrupt
& CSR_MIF
), timeout
);
137 if (unlikely(!(i2c
->interrupt
& CSR_MIF
))) {
138 dev_dbg(i2c
->dev
, "wait timeout\n");
150 if (!(x
& CSR_MCF
)) {
151 dev_dbg(i2c
->dev
, "unfinished\n");
156 dev_dbg(i2c
->dev
, "MAL\n");
160 if (writing
&& (x
& CSR_RXAK
)) {
161 dev_dbg(i2c
->dev
, "No RXAK\n");
163 writeccr(i2c
, CCR_MEN
);
169 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
170 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx
[] __devinitconst
= {
171 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
172 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
173 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
174 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
175 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
176 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
177 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
178 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
179 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
180 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
181 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
182 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
183 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
184 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
185 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
186 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
187 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
188 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
191 static int __devinit
mpc_i2c_get_fdr_52xx(struct device_node
*node
, u32 clock
,
194 const struct mpc_i2c_divider
*div
= NULL
;
195 unsigned int pvr
= mfspr(SPRN_PVR
);
199 if (clock
== MPC_I2C_CLOCK_LEGACY
)
202 /* Determine divider value */
203 divider
= mpc5xxx_get_bus_frequency(node
) / clock
;
206 * We want to choose an FDR/DFSR that generates an I2C bus speed that
207 * is equal to or lower than the requested speed.
209 for (i
= 0; i
< ARRAY_SIZE(mpc_i2c_dividers_52xx
); i
++) {
210 div
= &mpc_i2c_dividers_52xx
[i
];
211 /* Old MPC5200 rev A CPUs do not support the high bits */
212 if (div
->fdr
& 0xc0 && pvr
== 0x80822011)
214 if (div
->divider
>= divider
)
218 return div
? (int)div
->fdr
: -EINVAL
;
221 static void __devinit
mpc_i2c_setup_52xx(struct device_node
*node
,
223 u32 clock
, u32 prescaler
)
227 if (clock
== MPC_I2C_CLOCK_PRESERVE
) {
228 dev_dbg(i2c
->dev
, "using fdr %d\n",
229 readb(i2c
->base
+ MPC_I2C_FDR
));
233 ret
= mpc_i2c_get_fdr_52xx(node
, clock
, prescaler
);
234 fdr
= (ret
>= 0) ? ret
: 0x3f; /* backward compatibility */
236 writeb(fdr
& 0xff, i2c
->base
+ MPC_I2C_FDR
);
239 dev_info(i2c
->dev
, "clock %d Hz (fdr=%d)\n", clock
, fdr
);
241 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
242 static void __devinit
mpc_i2c_setup_52xx(struct device_node
*node
,
244 u32 clock
, u32 prescaler
)
247 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
249 #ifdef CONFIG_PPC_MPC512x
250 static void __devinit
mpc_i2c_setup_512x(struct device_node
*node
,
252 u32 clock
, u32 prescaler
)
254 struct device_node
*node_ctrl
;
259 /* Enable I2C interrupts for mpc5121 */
260 node_ctrl
= of_find_compatible_node(NULL
, NULL
,
261 "fsl,mpc5121-i2c-ctrl");
263 ctrl
= of_iomap(node_ctrl
, 0);
265 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
266 pval
= of_get_property(node
, "reg", NULL
);
267 idx
= (*pval
& 0xff) / 0x20;
268 setbits32(ctrl
, 1 << (24 + idx
* 2));
271 of_node_put(node_ctrl
);
274 /* The clock setup for the 52xx works also fine for the 512x */
275 mpc_i2c_setup_52xx(node
, i2c
, clock
, prescaler
);
277 #else /* CONFIG_PPC_MPC512x */
278 static void __devinit
mpc_i2c_setup_512x(struct device_node
*node
,
280 u32 clock
, u32 prescaler
)
283 #endif /* CONFIG_PPC_MPC512x */
285 #ifdef CONFIG_FSL_SOC
286 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx
[] __devinitconst
= {
287 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
288 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
289 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
290 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
291 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
292 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
293 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
294 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
295 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
296 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
297 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
298 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
299 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
300 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
301 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
302 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
303 {49152, 0x011e}, {61440, 0x011f}
306 static u32 __devinit
mpc_i2c_get_sec_cfg_8xxx(void)
308 struct device_node
*node
= NULL
;
312 node
= of_find_node_by_name(NULL
, "global-utilities");
314 const u32
*prop
= of_get_property(node
, "reg", NULL
);
317 * Map and check POR Device Status Register 2
318 * (PORDEVSR2) at 0xE0014
320 reg
= ioremap(get_immrbase() + *prop
+ 0x14, 0x4);
323 "Error: couldn't map PORDEVSR2\n");
325 val
= in_be32(reg
) & 0x00000080; /* sec-cfg */
335 static int __devinit
mpc_i2c_get_fdr_8xxx(struct device_node
*node
, u32 clock
,
338 const struct mpc_i2c_divider
*div
= NULL
;
342 if (clock
== MPC_I2C_CLOCK_LEGACY
)
345 /* Determine proper divider value */
346 if (of_device_is_compatible(node
, "fsl,mpc8544-i2c"))
347 prescaler
= mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
351 divider
= fsl_get_sys_freq() / clock
/ prescaler
;
353 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
354 fsl_get_sys_freq(), clock
, divider
);
357 * We want to choose an FDR/DFSR that generates an I2C bus speed that
358 * is equal to or lower than the requested speed.
360 for (i
= 0; i
< ARRAY_SIZE(mpc_i2c_dividers_8xxx
); i
++) {
361 div
= &mpc_i2c_dividers_8xxx
[i
];
362 if (div
->divider
>= divider
)
366 return div
? (int)div
->fdr
: -EINVAL
;
369 static void __devinit
mpc_i2c_setup_8xxx(struct device_node
*node
,
371 u32 clock
, u32 prescaler
)
375 if (clock
== MPC_I2C_CLOCK_PRESERVE
) {
376 dev_dbg(i2c
->dev
, "using dfsrr %d, fdr %d\n",
377 readb(i2c
->base
+ MPC_I2C_DFSRR
),
378 readb(i2c
->base
+ MPC_I2C_FDR
));
382 ret
= mpc_i2c_get_fdr_8xxx(node
, clock
, prescaler
);
383 fdr
= (ret
>= 0) ? ret
: 0x1031; /* backward compatibility */
385 writeb(fdr
& 0xff, i2c
->base
+ MPC_I2C_FDR
);
386 writeb((fdr
>> 8) & 0xff, i2c
->base
+ MPC_I2C_DFSRR
);
389 dev_info(i2c
->dev
, "clock %d Hz (dfsrr=%d fdr=%d)\n",
390 clock
, fdr
>> 8, fdr
& 0xff);
393 #else /* !CONFIG_FSL_SOC */
394 static void __devinit
mpc_i2c_setup_8xxx(struct device_node
*node
,
396 u32 clock
, u32 prescaler
)
399 #endif /* CONFIG_FSL_SOC */
401 static void mpc_i2c_start(struct mpc_i2c
*i2c
)
403 /* Clear arbitration */
404 writeb(0, i2c
->base
+ MPC_I2C_SR
);
406 writeccr(i2c
, CCR_MEN
);
409 static void mpc_i2c_stop(struct mpc_i2c
*i2c
)
411 writeccr(i2c
, CCR_MEN
);
414 static int mpc_write(struct mpc_i2c
*i2c
, int target
,
415 const u8
*data
, int length
, int restart
)
418 unsigned timeout
= i2c
->adap
.timeout
;
419 u32 flags
= restart
? CCR_RSTA
: 0;
421 /* Start as master */
422 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
423 /* Write target byte */
424 writeb((target
<< 1), i2c
->base
+ MPC_I2C_DR
);
426 result
= i2c_wait(i2c
, timeout
, 1);
430 for (i
= 0; i
< length
; i
++) {
431 /* Write data byte */
432 writeb(data
[i
], i2c
->base
+ MPC_I2C_DR
);
434 result
= i2c_wait(i2c
, timeout
, 1);
442 static int mpc_read(struct mpc_i2c
*i2c
, int target
,
443 u8
*data
, int length
, int restart
)
445 unsigned timeout
= i2c
->adap
.timeout
;
447 u32 flags
= restart
? CCR_RSTA
: 0;
449 /* Switch to read - restart */
450 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
451 /* Write target address byte - this time with the read flag set */
452 writeb((target
<< 1) | 1, i2c
->base
+ MPC_I2C_DR
);
454 result
= i2c_wait(i2c
, timeout
, 1);
460 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
462 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
);
464 readb(i2c
->base
+ MPC_I2C_DR
);
467 for (i
= 0; i
< length
; i
++) {
468 result
= i2c_wait(i2c
, timeout
, 0);
472 /* Generate txack on next to last byte */
474 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
475 /* Do not generate stop on last byte */
477 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
);
478 data
[i
] = readb(i2c
->base
+ MPC_I2C_DR
);
484 static int mpc_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
486 struct i2c_msg
*pmsg
;
489 unsigned long orig_jiffies
= jiffies
;
490 struct mpc_i2c
*i2c
= i2c_get_adapdata(adap
);
494 /* Allow bus up to 1s to become not busy */
495 while (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MBB
) {
496 if (signal_pending(current
)) {
497 dev_dbg(i2c
->dev
, "Interrupted\n");
501 if (time_after(jiffies
, orig_jiffies
+ HZ
)) {
502 dev_dbg(i2c
->dev
, "timeout\n");
503 if (readb(i2c
->base
+ MPC_I2C_SR
) ==
504 (CSR_MCF
| CSR_MBB
| CSR_RXAK
))
511 for (i
= 0; ret
>= 0 && i
< num
; i
++) {
514 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
515 pmsg
->flags
& I2C_M_RD
? "read" : "write",
516 pmsg
->len
, pmsg
->addr
, i
+ 1, num
);
517 if (pmsg
->flags
& I2C_M_RD
)
519 mpc_read(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
522 mpc_write(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
525 return (ret
< 0) ? ret
: num
;
528 static u32
mpc_functionality(struct i2c_adapter
*adap
)
530 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
533 static const struct i2c_algorithm mpc_algo
= {
534 .master_xfer
= mpc_xfer
,
535 .functionality
= mpc_functionality
,
538 static struct i2c_adapter mpc_ops
= {
539 .owner
= THIS_MODULE
,
540 .name
= "MPC adapter",
545 static int __devinit
fsl_i2c_probe(struct of_device
*op
,
546 const struct of_device_id
*match
)
550 u32 clock
= MPC_I2C_CLOCK_LEGACY
;
554 i2c
= kzalloc(sizeof(*i2c
), GFP_KERNEL
);
558 i2c
->dev
= &op
->dev
; /* for debug and error output */
560 init_waitqueue_head(&i2c
->queue
);
562 i2c
->base
= of_iomap(op
->node
, 0);
564 dev_err(i2c
->dev
, "failed to map controller\n");
569 i2c
->irq
= irq_of_parse_and_map(op
->node
, 0);
570 if (i2c
->irq
!= NO_IRQ
) { /* i2c->irq = NO_IRQ implies polling */
571 result
= request_irq(i2c
->irq
, mpc_i2c_isr
,
572 IRQF_SHARED
, "i2c-mpc", i2c
);
574 dev_err(i2c
->dev
, "failed to attach interrupt\n");
579 if (of_get_property(op
->node
, "fsl,preserve-clocking", NULL
)) {
580 clock
= MPC_I2C_CLOCK_PRESERVE
;
582 prop
= of_get_property(op
->node
, "clock-frequency", &plen
);
583 if (prop
&& plen
== sizeof(u32
))
588 struct mpc_i2c_data
*data
= match
->data
;
589 data
->setup(op
->node
, i2c
, clock
, data
->prescaler
);
591 /* Backwards compatibility */
592 if (of_get_property(op
->node
, "dfsrr", NULL
))
593 mpc_i2c_setup_8xxx(op
->node
, i2c
, clock
, 0);
596 dev_set_drvdata(&op
->dev
, i2c
);
599 i2c_set_adapdata(&i2c
->adap
, i2c
);
600 i2c
->adap
.dev
.parent
= &op
->dev
;
602 result
= i2c_add_adapter(&i2c
->adap
);
604 dev_err(i2c
->dev
, "failed to add adapter\n");
607 of_register_i2c_devices(&i2c
->adap
, op
->node
);
612 dev_set_drvdata(&op
->dev
, NULL
);
613 free_irq(i2c
->irq
, i2c
);
615 irq_dispose_mapping(i2c
->irq
);
622 static int __devexit
fsl_i2c_remove(struct of_device
*op
)
624 struct mpc_i2c
*i2c
= dev_get_drvdata(&op
->dev
);
626 i2c_del_adapter(&i2c
->adap
);
627 dev_set_drvdata(&op
->dev
, NULL
);
629 if (i2c
->irq
!= NO_IRQ
)
630 free_irq(i2c
->irq
, i2c
);
632 irq_dispose_mapping(i2c
->irq
);
638 static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata
= {
639 .setup
= mpc_i2c_setup_512x
,
642 static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata
= {
643 .setup
= mpc_i2c_setup_52xx
,
646 static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata
= {
647 .setup
= mpc_i2c_setup_8xxx
,
650 static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata
= {
651 .setup
= mpc_i2c_setup_8xxx
,
655 static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata
= {
656 .setup
= mpc_i2c_setup_8xxx
,
660 static const struct of_device_id mpc_i2c_of_match
[] = {
661 {.compatible
= "mpc5200-i2c", .data
= &mpc_i2c_data_52xx
, },
662 {.compatible
= "fsl,mpc5200b-i2c", .data
= &mpc_i2c_data_52xx
, },
663 {.compatible
= "fsl,mpc5200-i2c", .data
= &mpc_i2c_data_52xx
, },
664 {.compatible
= "fsl,mpc5121-i2c", .data
= &mpc_i2c_data_512x
, },
665 {.compatible
= "fsl,mpc8313-i2c", .data
= &mpc_i2c_data_8313
, },
666 {.compatible
= "fsl,mpc8543-i2c", .data
= &mpc_i2c_data_8543
, },
667 {.compatible
= "fsl,mpc8544-i2c", .data
= &mpc_i2c_data_8544
, },
668 /* Backward compatibility */
669 {.compatible
= "fsl-i2c", },
672 MODULE_DEVICE_TABLE(of
, mpc_i2c_of_match
);
674 /* Structure for a device driver */
675 static struct of_platform_driver mpc_i2c_driver
= {
676 .match_table
= mpc_i2c_of_match
,
677 .probe
= fsl_i2c_probe
,
678 .remove
= __devexit_p(fsl_i2c_remove
),
680 .owner
= THIS_MODULE
,
685 static int __init
fsl_i2c_init(void)
689 rv
= of_register_platform_driver(&mpc_i2c_driver
);
691 printk(KERN_ERR DRV_NAME
692 " of_register_platform_driver failed (%i)\n", rv
);
696 static void __exit
fsl_i2c_exit(void)
698 of_unregister_platform_driver(&mpc_i2c_driver
);
701 module_init(fsl_i2c_init
);
702 module_exit(fsl_i2c_exit
);
704 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
705 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
706 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
707 MODULE_LICENSE("GPL");