2 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/list.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
15 #include "mv88e6xxx.h"
20 #define ID_6085 0x04a0
21 #define ID_6095 0x0950
22 #define ID_6131 0x1060
24 static char *mv88e6131_probe(struct mii_bus
*bus
, int sw_addr
)
28 ret
= __mv88e6xxx_reg_read(bus
, sw_addr
, REG_PORT(0), 0x03);
32 return "Marvell 88E6085";
34 return "Marvell 88E6095/88E6095F";
36 return "Marvell 88E6131";
42 static int mv88e6131_switch_reset(struct dsa_switch
*ds
)
48 * Set all ports to the disabled state.
50 for (i
= 0; i
< 11; i
++) {
51 ret
= REG_READ(REG_PORT(i
), 0x04);
52 REG_WRITE(REG_PORT(i
), 0x04, ret
& 0xfffc);
56 * Wait for transmit queues to drain.
63 REG_WRITE(REG_GLOBAL
, 0x04, 0xc400);
66 * Wait up to one second for reset to complete.
68 for (i
= 0; i
< 1000; i
++) {
69 ret
= REG_READ(REG_GLOBAL
, 0x00);
70 if ((ret
& 0xc800) == 0xc800)
81 static int mv88e6131_setup_global(struct dsa_switch
*ds
)
87 * Enable the PHY polling unit, don't discard packets with
88 * excessive collisions, use a weighted fair queueing scheme
89 * to arbitrate between packet queues, set the maximum frame
90 * size to 1632, and mask all interrupt sources.
92 REG_WRITE(REG_GLOBAL
, 0x04, 0x4400);
95 * Set the default address aging time to 5 minutes, and
96 * enable address learn messages to be sent to all message
99 REG_WRITE(REG_GLOBAL
, 0x0a, 0x0148);
102 * Configure the priority mapping registers.
104 ret
= mv88e6xxx_config_prio(ds
);
109 * Set the VLAN ethertype to 0x8100.
111 REG_WRITE(REG_GLOBAL
, 0x19, 0x8100);
114 * Disable ARP mirroring, and configure the upstream port as
115 * the port to which ingress and egress monitor frames are to
118 REG_WRITE(REG_GLOBAL
, 0x1a, (dsa_upstream_port(ds
) * 0x1100) | 0x00f0);
121 * Disable cascade port functionality, and set the switch's
124 REG_WRITE(REG_GLOBAL
, 0x1c, 0xe000 | (ds
->index
& 0x1f));
127 * Send all frames with destination addresses matching
128 * 01:80:c2:00:00:0x to the CPU port.
130 REG_WRITE(REG_GLOBAL2
, 0x03, 0xffff);
133 * Ignore removed tag data on doubly tagged packets, disable
134 * flow control messages, force flow control priority to the
135 * highest, and send all special multicast frames to the CPU
136 * port at the highest priority.
138 REG_WRITE(REG_GLOBAL2
, 0x05, 0x00ff);
141 * Program the DSA routing table.
143 for (i
= 0; i
< 32; i
++) {
147 if (i
!= ds
->index
&& i
< ds
->dst
->pd
->nr_chips
)
148 nexthop
= ds
->pd
->rtable
[i
] & 0x1f;
150 REG_WRITE(REG_GLOBAL2
, 0x06, 0x8000 | (i
<< 8) | nexthop
);
154 * Clear all trunk masks.
156 for (i
= 0; i
< 8; i
++)
157 REG_WRITE(REG_GLOBAL2
, 0x07, 0x8000 | (i
<< 12) | 0x7ff);
160 * Clear all trunk mappings.
162 for (i
= 0; i
< 16; i
++)
163 REG_WRITE(REG_GLOBAL2
, 0x08, 0x8000 | (i
<< 11));
166 * Force the priority of IGMP/MLD snoop frames and ARP frames
167 * to the highest setting.
169 REG_WRITE(REG_GLOBAL2
, 0x0f, 0x00ff);
174 static int mv88e6131_setup_port(struct dsa_switch
*ds
, int p
)
176 struct mv88e6xxx_priv_state
*ps
= (void *)(ds
+ 1);
177 int addr
= REG_PORT(p
);
181 * MAC Forcing register: don't force link, speed, duplex
182 * or flow control state to any particular values on physical
183 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
184 * (100 Mb/s on 6085) full duplex.
186 if (dsa_is_cpu_port(ds
, p
) || ds
->dsa_port_mask
& (1 << p
))
187 if (ps
->id
== ID_6085
)
188 REG_WRITE(addr
, 0x01, 0x003d); /* 100 Mb/s */
190 REG_WRITE(addr
, 0x01, 0x003e); /* 1000 Mb/s */
192 REG_WRITE(addr
, 0x01, 0x0003);
195 * Port Control: disable Core Tag, disable Drop-on-Lock,
196 * transmit frames unmodified, disable Header mode,
197 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
198 * tunneling, determine priority by looking at 802.1p and
199 * IP priority fields (IP prio has precedence), and set STP
200 * state to Forwarding.
202 * If this is the upstream port for this switch, enable
203 * forwarding of unknown unicasts, and enable DSA tagging
206 * If this is the link to another switch, use DSA tagging
207 * mode, but do not enable forwarding of unknown unicasts.
210 if (p
== dsa_upstream_port(ds
))
212 if (ds
->dsa_port_mask
& (1 << p
))
214 REG_WRITE(addr
, 0x04, val
);
217 * Port Control 1: disable trunking. Also, if this is the
218 * CPU port, enable learn messages to be sent to this port.
220 REG_WRITE(addr
, 0x05, dsa_is_cpu_port(ds
, p
) ? 0x8000 : 0x0000);
223 * Port based VLAN map: give each port its own address
224 * database, allow the CPU port to talk to each of the 'real'
225 * ports, and allow each of the 'real' ports to only talk to
228 val
= (p
& 0xf) << 12;
229 if (dsa_is_cpu_port(ds
, p
))
230 val
|= ds
->phys_port_mask
;
232 val
|= 1 << dsa_upstream_port(ds
);
233 REG_WRITE(addr
, 0x06, val
);
236 * Default VLAN ID and priority: don't set a default VLAN
237 * ID, and set the default packet priority to zero.
239 REG_WRITE(addr
, 0x07, 0x0000);
242 * Port Control 2: don't force a good FCS, don't use
243 * VLAN-based, source address-based or destination
244 * address-based priority overrides, don't let the switch
245 * add or strip 802.1q tags, don't discard tagged or
246 * untagged frames on this port, do a destination address
247 * lookup on received packets as usual, don't send a copy
248 * of all transmitted/received frames on this port to the
249 * CPU, and configure the upstream port number.
251 * If this is the upstream port for this switch, enable
252 * forwarding of unknown multicast addresses.
254 val
= 0x0080 | dsa_upstream_port(ds
);
255 if (p
== dsa_upstream_port(ds
))
257 REG_WRITE(addr
, 0x08, val
);
260 * Rate Control: disable ingress rate limiting.
262 REG_WRITE(addr
, 0x09, 0x0000);
265 * Rate Control 2: disable egress rate limiting.
267 REG_WRITE(addr
, 0x0a, 0x0000);
270 * Port Association Vector: when learning source addresses
271 * of packets, add the address to the address database using
272 * a port bitmap that has only the bit for this port set and
273 * the other bits clear.
275 REG_WRITE(addr
, 0x0b, 1 << p
);
278 * Tag Remap: use an identity 802.1p prio -> switch prio
281 REG_WRITE(addr
, 0x18, 0x3210);
284 * Tag Remap 2: use an identity 802.1p prio -> switch prio
287 REG_WRITE(addr
, 0x19, 0x7654);
292 static int mv88e6131_setup(struct dsa_switch
*ds
)
294 struct mv88e6xxx_priv_state
*ps
= (void *)(ds
+ 1);
298 mutex_init(&ps
->smi_mutex
);
299 mv88e6xxx_ppu_state_init(ds
);
300 mutex_init(&ps
->stats_mutex
);
302 ps
->id
= REG_READ(REG_PORT(0), 0x03) & 0xfff0;
304 ret
= mv88e6131_switch_reset(ds
);
308 /* @@@ initialise vtu and atu */
310 ret
= mv88e6131_setup_global(ds
);
314 for (i
= 0; i
< 11; i
++) {
315 ret
= mv88e6131_setup_port(ds
, i
);
323 static int mv88e6131_port_to_phy_addr(int port
)
325 if (port
>= 0 && port
<= 11)
331 mv88e6131_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
333 int addr
= mv88e6131_port_to_phy_addr(port
);
334 return mv88e6xxx_phy_read_ppu(ds
, addr
, regnum
);
338 mv88e6131_phy_write(struct dsa_switch
*ds
,
339 int port
, int regnum
, u16 val
)
341 int addr
= mv88e6131_port_to_phy_addr(port
);
342 return mv88e6xxx_phy_write_ppu(ds
, addr
, regnum
, val
);
345 static struct mv88e6xxx_hw_stat mv88e6131_hw_stats
[] = {
346 { "in_good_octets", 8, 0x00, },
347 { "in_bad_octets", 4, 0x02, },
348 { "in_unicast", 4, 0x04, },
349 { "in_broadcasts", 4, 0x06, },
350 { "in_multicasts", 4, 0x07, },
351 { "in_pause", 4, 0x16, },
352 { "in_undersize", 4, 0x18, },
353 { "in_fragments", 4, 0x19, },
354 { "in_oversize", 4, 0x1a, },
355 { "in_jabber", 4, 0x1b, },
356 { "in_rx_error", 4, 0x1c, },
357 { "in_fcs_error", 4, 0x1d, },
358 { "out_octets", 8, 0x0e, },
359 { "out_unicast", 4, 0x10, },
360 { "out_broadcasts", 4, 0x13, },
361 { "out_multicasts", 4, 0x12, },
362 { "out_pause", 4, 0x15, },
363 { "excessive", 4, 0x11, },
364 { "collisions", 4, 0x1e, },
365 { "deferred", 4, 0x05, },
366 { "single", 4, 0x14, },
367 { "multiple", 4, 0x17, },
368 { "out_fcs_error", 4, 0x03, },
369 { "late", 4, 0x1f, },
370 { "hist_64bytes", 4, 0x08, },
371 { "hist_65_127bytes", 4, 0x09, },
372 { "hist_128_255bytes", 4, 0x0a, },
373 { "hist_256_511bytes", 4, 0x0b, },
374 { "hist_512_1023bytes", 4, 0x0c, },
375 { "hist_1024_max_bytes", 4, 0x0d, },
379 mv88e6131_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
381 mv88e6xxx_get_strings(ds
, ARRAY_SIZE(mv88e6131_hw_stats
),
382 mv88e6131_hw_stats
, port
, data
);
386 mv88e6131_get_ethtool_stats(struct dsa_switch
*ds
,
387 int port
, uint64_t *data
)
389 mv88e6xxx_get_ethtool_stats(ds
, ARRAY_SIZE(mv88e6131_hw_stats
),
390 mv88e6131_hw_stats
, port
, data
);
393 static int mv88e6131_get_sset_count(struct dsa_switch
*ds
)
395 return ARRAY_SIZE(mv88e6131_hw_stats
);
398 static struct dsa_switch_driver mv88e6131_switch_driver
= {
399 .tag_protocol
= cpu_to_be16(ETH_P_DSA
),
400 .priv_size
= sizeof(struct mv88e6xxx_priv_state
),
401 .probe
= mv88e6131_probe
,
402 .setup
= mv88e6131_setup
,
403 .set_addr
= mv88e6xxx_set_addr_direct
,
404 .phy_read
= mv88e6131_phy_read
,
405 .phy_write
= mv88e6131_phy_write
,
406 .poll_link
= mv88e6xxx_poll_link
,
407 .get_strings
= mv88e6131_get_strings
,
408 .get_ethtool_stats
= mv88e6131_get_ethtool_stats
,
409 .get_sset_count
= mv88e6131_get_sset_count
,
412 static int __init
mv88e6131_init(void)
414 register_switch_driver(&mv88e6131_switch_driver
);
417 module_init(mv88e6131_init
);
419 static void __exit
mv88e6131_cleanup(void)
421 unregister_switch_driver(&mv88e6131_switch_driver
);
423 module_exit(mv88e6131_cleanup
);