2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
34 #include <asm/alternative.h>
38 #define wrmsrl(msr, val) \
40 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
41 (unsigned long)(val)); \
42 native_write_msr((msr), (u32)((u64)(val)), \
43 (u32)((u64)(val) >> 32)); \
49 * register -------------------------------
50 * | HT | no HT | HT | no HT |
51 *-----------------------------------------
52 * offcore | core | core | cpu | core |
53 * lbr_sel | core | core | cpu | core |
54 * ld_lat | cpu | core | cpu | core |
55 *-----------------------------------------
57 * Given that there is a small number of shared regs,
58 * we can pre-allocate their slot in the per-cpu
59 * per-core reg tables.
62 EXTRA_REG_NONE
= -1, /* not used */
64 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
65 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
67 EXTRA_REG_MAX
/* number of entries needed */
71 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
74 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
76 unsigned long offset
, addr
= (unsigned long)from
;
77 unsigned long size
, len
= 0;
83 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
87 offset
= addr
& (PAGE_SIZE
- 1);
88 size
= min(PAGE_SIZE
- offset
, n
- len
);
90 map
= kmap_atomic(page
);
91 memcpy(to
, map
+offset
, size
);
104 struct event_constraint
{
106 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
115 int nb_id
; /* NorthBridge id */
116 int refcnt
; /* reference count */
117 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
118 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
121 struct intel_percore
;
123 #define MAX_LBR_ENTRIES 16
125 struct cpu_hw_events
{
127 * Generic x86 PMC bits
129 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
130 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
131 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
137 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
138 u64 tags
[X86_PMC_IDX_MAX
];
139 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
141 unsigned int group_flag
;
144 * Intel DebugStore bits
146 struct debug_store
*ds
;
154 struct perf_branch_stack lbr_stack
;
155 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
158 * manage shared (per-core, per-cpu) registers
159 * used on Intel NHM/WSM/SNB
161 struct intel_shared_regs
*shared_regs
;
166 struct amd_nb
*amd_nb
;
169 #define __EVENT_CONSTRAINT(c, n, m, w) {\
170 { .idxmsk64 = (n) }, \
176 #define EVENT_CONSTRAINT(c, n, m) \
177 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
180 * Constraint on the Event code.
182 #define INTEL_EVENT_CONSTRAINT(c, n) \
183 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
186 * Constraint on the Event code + UMask + fixed-mask
188 * filter mask to validate fixed counter events.
189 * the following filters disqualify for fixed counters:
193 * The other filters are supported by fixed counters.
194 * The any-thread option is supported starting with v3.
196 #define FIXED_EVENT_CONSTRAINT(c, n) \
197 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
200 * Constraint on the Event code + UMask
202 #define INTEL_UEVENT_CONSTRAINT(c, n) \
203 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
205 #define EVENT_CONSTRAINT_END \
206 EVENT_CONSTRAINT(0, 0, 0)
208 #define for_each_event_constraint(e, c) \
209 for ((e) = (c); (e)->weight; (e)++)
212 * Per register state.
215 raw_spinlock_t lock
; /* per-core: protect structure */
216 u64 config
; /* extra MSR config */
217 u64 reg
; /* extra MSR number */
218 atomic_t ref
; /* reference count */
222 * Extra registers for specific events.
224 * Some events need large masks and require external MSRs.
225 * Those extra MSRs end up being shared for all events on
226 * a PMU and sometimes between PMU of sibling HT threads.
227 * In either case, the kernel needs to handle conflicting
228 * accesses to those extra, shared, regs. The data structure
229 * to manage those registers is stored in cpu_hw_event.
236 int idx
; /* per_xxx->regs[] reg index */
239 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
242 .config_mask = (m), \
243 .valid_mask = (vm), \
244 .idx = EXTRA_REG_##i \
247 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
248 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
250 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
252 union perf_capabilities
{
256 u64 pebs_arch_reg
: 1;
264 * struct x86_pmu - generic x86 pmu
268 * Generic x86 PMC bits
272 int (*handle_irq
)(struct pt_regs
*);
273 void (*disable_all
)(void);
274 void (*enable_all
)(int added
);
275 void (*enable
)(struct perf_event
*);
276 void (*disable
)(struct perf_event
*);
277 void (*hw_watchdog_set_attr
)(struct perf_event_attr
*attr
);
278 int (*hw_config
)(struct perf_event
*event
);
279 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
282 u64 (*event_map
)(int);
285 int num_counters_fixed
;
290 struct event_constraint
*
291 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
292 struct perf_event
*event
);
294 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
295 struct perf_event
*event
);
296 struct event_constraint
*event_constraints
;
297 void (*quirks
)(void);
298 int perfctr_second_write
;
300 int (*cpu_prepare
)(int cpu
);
301 void (*cpu_starting
)(int cpu
);
302 void (*cpu_dying
)(int cpu
);
303 void (*cpu_dead
)(int cpu
);
306 * Intel Arch Perfmon v2+
309 union perf_capabilities intel_cap
;
312 * Intel DebugStore bits
315 int bts_active
, pebs_active
;
316 int pebs_record_size
;
317 void (*drain_pebs
)(struct pt_regs
*regs
);
318 struct event_constraint
*pebs_constraints
;
323 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
324 int lbr_nr
; /* hardware stack size */
327 * Extra registers for events
329 struct extra_reg
*extra_regs
;
332 static struct x86_pmu x86_pmu __read_mostly
;
334 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
338 static int x86_perf_event_set_period(struct perf_event
*event
);
341 * Generalized hw caching related hw_event table, filled
342 * in on a per model basis. A value of 0 means
343 * 'not supported', -1 means 'hw_event makes no sense on
344 * this CPU', any other value means the raw hw_event
348 #define C(x) PERF_COUNT_HW_CACHE_##x
350 static u64 __read_mostly hw_cache_event_ids
351 [PERF_COUNT_HW_CACHE_MAX
]
352 [PERF_COUNT_HW_CACHE_OP_MAX
]
353 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
354 static u64 __read_mostly hw_cache_extra_regs
355 [PERF_COUNT_HW_CACHE_MAX
]
356 [PERF_COUNT_HW_CACHE_OP_MAX
]
357 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
359 void hw_nmi_watchdog_set_attr(struct perf_event_attr
*wd_attr
)
361 if (x86_pmu
.hw_watchdog_set_attr
)
362 x86_pmu
.hw_watchdog_set_attr(wd_attr
);
366 * Propagate event elapsed time into the generic event.
367 * Can only be executed on the CPU where the event is active.
368 * Returns the delta events processed.
371 x86_perf_event_update(struct perf_event
*event
)
373 struct hw_perf_event
*hwc
= &event
->hw
;
374 int shift
= 64 - x86_pmu
.cntval_bits
;
375 u64 prev_raw_count
, new_raw_count
;
379 if (idx
== X86_PMC_IDX_FIXED_BTS
)
383 * Careful: an NMI might modify the previous event value.
385 * Our tactic to handle this is to first atomically read and
386 * exchange a new raw count - then add that new-prev delta
387 * count to the generic event atomically:
390 prev_raw_count
= local64_read(&hwc
->prev_count
);
391 rdmsrl(hwc
->event_base
, new_raw_count
);
393 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
394 new_raw_count
) != prev_raw_count
)
398 * Now we have the new raw value and have updated the prev
399 * timestamp already. We can now calculate the elapsed delta
400 * (event-)time and add that to the generic event.
402 * Careful, not all hw sign-extends above the physical width
405 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
408 local64_add(delta
, &event
->count
);
409 local64_sub(delta
, &hwc
->period_left
);
411 return new_raw_count
;
414 static inline int x86_pmu_addr_offset(int index
)
418 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
419 alternative_io(ASM_NOP2
,
421 X86_FEATURE_PERFCTR_CORE
,
428 static inline unsigned int x86_pmu_config_addr(int index
)
430 return x86_pmu
.eventsel
+ x86_pmu_addr_offset(index
);
433 static inline unsigned int x86_pmu_event_addr(int index
)
435 return x86_pmu
.perfctr
+ x86_pmu_addr_offset(index
);
439 * Find and validate any extra registers to set up.
441 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
443 struct hw_perf_event_extra
*reg
;
444 struct extra_reg
*er
;
446 reg
= &event
->hw
.extra_reg
;
448 if (!x86_pmu
.extra_regs
)
451 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
452 if (er
->event
!= (config
& er
->config_mask
))
454 if (event
->attr
.config1
& ~er
->valid_mask
)
458 reg
->config
= event
->attr
.config1
;
465 static atomic_t active_events
;
466 static DEFINE_MUTEX(pmc_reserve_mutex
);
468 #ifdef CONFIG_X86_LOCAL_APIC
470 static bool reserve_pmc_hardware(void)
474 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
475 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
479 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
480 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
487 for (i
--; i
>= 0; i
--)
488 release_evntsel_nmi(x86_pmu_config_addr(i
));
490 i
= x86_pmu
.num_counters
;
493 for (i
--; i
>= 0; i
--)
494 release_perfctr_nmi(x86_pmu_event_addr(i
));
499 static void release_pmc_hardware(void)
503 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
504 release_perfctr_nmi(x86_pmu_event_addr(i
));
505 release_evntsel_nmi(x86_pmu_config_addr(i
));
511 static bool reserve_pmc_hardware(void) { return true; }
512 static void release_pmc_hardware(void) {}
516 static bool check_hw_exists(void)
518 u64 val
, val_new
= 0;
522 * Check to see if the BIOS enabled any of the counters, if so
525 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
526 reg
= x86_pmu_config_addr(i
);
527 ret
= rdmsrl_safe(reg
, &val
);
530 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
)
534 if (x86_pmu
.num_counters_fixed
) {
535 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
536 ret
= rdmsrl_safe(reg
, &val
);
539 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
540 if (val
& (0x03 << i
*4))
546 * Now write a value and read it back to see if it matches,
547 * this is needed to detect certain hardware emulators (qemu/kvm)
548 * that don't trap on the MSR access and always return 0s.
551 ret
= checking_wrmsrl(x86_pmu_event_addr(0), val
);
552 ret
|= rdmsrl_safe(x86_pmu_event_addr(0), &val_new
);
553 if (ret
|| val
!= val_new
)
560 * We still allow the PMU driver to operate:
562 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
563 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg
, val
);
568 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
573 static void reserve_ds_buffers(void);
574 static void release_ds_buffers(void);
576 static void hw_perf_event_destroy(struct perf_event
*event
)
578 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
579 release_pmc_hardware();
580 release_ds_buffers();
581 mutex_unlock(&pmc_reserve_mutex
);
585 static inline int x86_pmu_initialized(void)
587 return x86_pmu
.handle_irq
!= NULL
;
591 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
593 struct perf_event_attr
*attr
= &event
->attr
;
594 unsigned int cache_type
, cache_op
, cache_result
;
597 config
= attr
->config
;
599 cache_type
= (config
>> 0) & 0xff;
600 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
603 cache_op
= (config
>> 8) & 0xff;
604 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
607 cache_result
= (config
>> 16) & 0xff;
608 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
611 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
620 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
621 return x86_pmu_extra_regs(val
, event
);
624 static int x86_setup_perfctr(struct perf_event
*event
)
626 struct perf_event_attr
*attr
= &event
->attr
;
627 struct hw_perf_event
*hwc
= &event
->hw
;
630 if (!is_sampling_event(event
)) {
631 hwc
->sample_period
= x86_pmu
.max_period
;
632 hwc
->last_period
= hwc
->sample_period
;
633 local64_set(&hwc
->period_left
, hwc
->sample_period
);
636 * If we have a PMU initialized but no APIC
637 * interrupts, we cannot sample hardware
638 * events (user-space has to fall back and
639 * sample via a hrtimer based software event):
646 * Do not allow config1 (extended registers) to propagate,
647 * there's no sane user-space generalization yet:
649 if (attr
->type
== PERF_TYPE_RAW
)
652 if (attr
->type
== PERF_TYPE_HW_CACHE
)
653 return set_ext_hw_attr(hwc
, event
);
655 if (attr
->config
>= x86_pmu
.max_events
)
661 config
= x86_pmu
.event_map(attr
->config
);
672 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
673 !attr
->freq
&& hwc
->sample_period
== 1) {
674 /* BTS is not supported by this architecture. */
675 if (!x86_pmu
.bts_active
)
678 /* BTS is currently only allowed for user-mode. */
679 if (!attr
->exclude_kernel
)
683 hwc
->config
|= config
;
688 static int x86_pmu_hw_config(struct perf_event
*event
)
690 if (event
->attr
.precise_ip
) {
693 /* Support for constant skid */
694 if (x86_pmu
.pebs_active
) {
697 /* Support for IP fixup */
702 if (event
->attr
.precise_ip
> precise
)
708 * (keep 'enabled' bit clear for now)
710 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
713 * Count user and OS events unless requested not to
715 if (!event
->attr
.exclude_user
)
716 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
717 if (!event
->attr
.exclude_kernel
)
718 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
720 if (event
->attr
.type
== PERF_TYPE_RAW
)
721 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
723 return x86_setup_perfctr(event
);
727 * Setup the hardware configuration for a given attr_type
729 static int __x86_pmu_event_init(struct perf_event
*event
)
733 if (!x86_pmu_initialized())
737 if (!atomic_inc_not_zero(&active_events
)) {
738 mutex_lock(&pmc_reserve_mutex
);
739 if (atomic_read(&active_events
) == 0) {
740 if (!reserve_pmc_hardware())
743 reserve_ds_buffers();
746 atomic_inc(&active_events
);
747 mutex_unlock(&pmc_reserve_mutex
);
752 event
->destroy
= hw_perf_event_destroy
;
755 event
->hw
.last_cpu
= -1;
756 event
->hw
.last_tag
= ~0ULL;
759 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
761 return x86_pmu
.hw_config(event
);
764 static void x86_pmu_disable_all(void)
766 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
769 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
772 if (!test_bit(idx
, cpuc
->active_mask
))
774 rdmsrl(x86_pmu_config_addr(idx
), val
);
775 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
777 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
778 wrmsrl(x86_pmu_config_addr(idx
), val
);
782 static void x86_pmu_disable(struct pmu
*pmu
)
784 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
786 if (!x86_pmu_initialized())
796 x86_pmu
.disable_all();
799 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
802 if (hwc
->extra_reg
.reg
)
803 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
804 wrmsrl(hwc
->config_base
, hwc
->config
| enable_mask
);
807 static void x86_pmu_enable_all(int added
)
809 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
812 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
813 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
815 if (!test_bit(idx
, cpuc
->active_mask
))
818 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
822 static struct pmu pmu
;
824 static inline int is_x86_event(struct perf_event
*event
)
826 return event
->pmu
== &pmu
;
829 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
831 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
832 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
833 int i
, j
, w
, wmax
, num
= 0;
834 struct hw_perf_event
*hwc
;
836 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
838 for (i
= 0; i
< n
; i
++) {
839 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
844 * fastpath, try to reuse previous register
846 for (i
= 0; i
< n
; i
++) {
847 hwc
= &cpuc
->event_list
[i
]->hw
;
854 /* constraint still honored */
855 if (!test_bit(hwc
->idx
, c
->idxmsk
))
858 /* not already used */
859 if (test_bit(hwc
->idx
, used_mask
))
862 __set_bit(hwc
->idx
, used_mask
);
864 assign
[i
] = hwc
->idx
;
873 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
876 * weight = number of possible counters
878 * 1 = most constrained, only works on one counter
879 * wmax = least constrained, works on any counter
881 * assign events to counters starting with most
882 * constrained events.
884 wmax
= x86_pmu
.num_counters
;
887 * when fixed event counters are present,
888 * wmax is incremented by 1 to account
889 * for one more choice
891 if (x86_pmu
.num_counters_fixed
)
894 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
896 for (i
= 0; num
&& i
< n
; i
++) {
898 hwc
= &cpuc
->event_list
[i
]->hw
;
903 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
904 if (!test_bit(j
, used_mask
))
908 if (j
== X86_PMC_IDX_MAX
)
911 __set_bit(j
, used_mask
);
920 * scheduling failed or is just a simulation,
921 * free resources if necessary
923 if (!assign
|| num
) {
924 for (i
= 0; i
< n
; i
++) {
925 if (x86_pmu
.put_event_constraints
)
926 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
929 return num
? -ENOSPC
: 0;
933 * dogrp: true if must collect siblings events (group)
934 * returns total number of events and error code
936 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
938 struct perf_event
*event
;
941 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
943 /* current number of events already accepted */
946 if (is_x86_event(leader
)) {
949 cpuc
->event_list
[n
] = leader
;
955 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
956 if (!is_x86_event(event
) ||
957 event
->state
<= PERF_EVENT_STATE_OFF
)
963 cpuc
->event_list
[n
] = event
;
969 static inline void x86_assign_hw_event(struct perf_event
*event
,
970 struct cpu_hw_events
*cpuc
, int i
)
972 struct hw_perf_event
*hwc
= &event
->hw
;
974 hwc
->idx
= cpuc
->assign
[i
];
975 hwc
->last_cpu
= smp_processor_id();
976 hwc
->last_tag
= ++cpuc
->tags
[i
];
978 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
979 hwc
->config_base
= 0;
981 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
982 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
983 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- X86_PMC_IDX_FIXED
);
985 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
986 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
990 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
991 struct cpu_hw_events
*cpuc
,
994 return hwc
->idx
== cpuc
->assign
[i
] &&
995 hwc
->last_cpu
== smp_processor_id() &&
996 hwc
->last_tag
== cpuc
->tags
[i
];
999 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1000 static void x86_pmu_stop(struct perf_event
*event
, int flags
);
1002 static void x86_pmu_enable(struct pmu
*pmu
)
1004 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1005 struct perf_event
*event
;
1006 struct hw_perf_event
*hwc
;
1007 int i
, added
= cpuc
->n_added
;
1009 if (!x86_pmu_initialized())
1015 if (cpuc
->n_added
) {
1016 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1018 * apply assignment obtained either from
1019 * hw_perf_group_sched_in() or x86_pmu_enable()
1021 * step1: save events moving to new counters
1022 * step2: reprogram moved events into new counters
1024 for (i
= 0; i
< n_running
; i
++) {
1025 event
= cpuc
->event_list
[i
];
1029 * we can avoid reprogramming counter if:
1030 * - assigned same counter as last time
1031 * - running on same CPU as last time
1032 * - no other event has used the counter since
1034 if (hwc
->idx
== -1 ||
1035 match_prev_assignment(hwc
, cpuc
, i
))
1039 * Ensure we don't accidentally enable a stopped
1040 * counter simply because we rescheduled.
1042 if (hwc
->state
& PERF_HES_STOPPED
)
1043 hwc
->state
|= PERF_HES_ARCH
;
1045 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1048 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1049 event
= cpuc
->event_list
[i
];
1052 if (!match_prev_assignment(hwc
, cpuc
, i
))
1053 x86_assign_hw_event(event
, cpuc
, i
);
1054 else if (i
< n_running
)
1057 if (hwc
->state
& PERF_HES_ARCH
)
1060 x86_pmu_start(event
, PERF_EF_RELOAD
);
1063 perf_events_lapic_init();
1069 x86_pmu
.enable_all(added
);
1072 static inline void x86_pmu_disable_event(struct perf_event
*event
)
1074 struct hw_perf_event
*hwc
= &event
->hw
;
1076 wrmsrl(hwc
->config_base
, hwc
->config
);
1079 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1082 * Set the next IRQ period, based on the hwc->period_left value.
1083 * To be called with the event disabled in hw:
1086 x86_perf_event_set_period(struct perf_event
*event
)
1088 struct hw_perf_event
*hwc
= &event
->hw
;
1089 s64 left
= local64_read(&hwc
->period_left
);
1090 s64 period
= hwc
->sample_period
;
1091 int ret
= 0, idx
= hwc
->idx
;
1093 if (idx
== X86_PMC_IDX_FIXED_BTS
)
1097 * If we are way outside a reasonable range then just skip forward:
1099 if (unlikely(left
<= -period
)) {
1101 local64_set(&hwc
->period_left
, left
);
1102 hwc
->last_period
= period
;
1106 if (unlikely(left
<= 0)) {
1108 local64_set(&hwc
->period_left
, left
);
1109 hwc
->last_period
= period
;
1113 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1115 if (unlikely(left
< 2))
1118 if (left
> x86_pmu
.max_period
)
1119 left
= x86_pmu
.max_period
;
1121 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1124 * The hw event starts counting from this event offset,
1125 * mark it to be able to extra future deltas:
1127 local64_set(&hwc
->prev_count
, (u64
)-left
);
1129 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1132 * Due to erratum on certan cpu we need
1133 * a second write to be sure the register
1134 * is updated properly
1136 if (x86_pmu
.perfctr_second_write
) {
1137 wrmsrl(hwc
->event_base
,
1138 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1141 perf_event_update_userpage(event
);
1146 static void x86_pmu_enable_event(struct perf_event
*event
)
1148 if (__this_cpu_read(cpu_hw_events
.enabled
))
1149 __x86_pmu_enable_event(&event
->hw
,
1150 ARCH_PERFMON_EVENTSEL_ENABLE
);
1154 * Add a single event to the PMU.
1156 * The event is added to the group of enabled events
1157 * but only if it can be scehduled with existing events.
1159 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1161 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1162 struct hw_perf_event
*hwc
;
1163 int assign
[X86_PMC_IDX_MAX
];
1168 perf_pmu_disable(event
->pmu
);
1169 n0
= cpuc
->n_events
;
1170 ret
= n
= collect_events(cpuc
, event
, false);
1174 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1175 if (!(flags
& PERF_EF_START
))
1176 hwc
->state
|= PERF_HES_ARCH
;
1179 * If group events scheduling transaction was started,
1180 * skip the schedulability test here, it will be performed
1181 * at commit time (->commit_txn) as a whole
1183 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1186 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1190 * copy new assignment, now we know it is possible
1191 * will be used by hw_perf_enable()
1193 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1197 cpuc
->n_added
+= n
- n0
;
1198 cpuc
->n_txn
+= n
- n0
;
1202 perf_pmu_enable(event
->pmu
);
1206 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1208 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1209 int idx
= event
->hw
.idx
;
1211 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1214 if (WARN_ON_ONCE(idx
== -1))
1217 if (flags
& PERF_EF_RELOAD
) {
1218 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1219 x86_perf_event_set_period(event
);
1222 event
->hw
.state
= 0;
1224 cpuc
->events
[idx
] = event
;
1225 __set_bit(idx
, cpuc
->active_mask
);
1226 __set_bit(idx
, cpuc
->running
);
1227 x86_pmu
.enable(event
);
1228 perf_event_update_userpage(event
);
1231 void perf_event_print_debug(void)
1233 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1235 struct cpu_hw_events
*cpuc
;
1236 unsigned long flags
;
1239 if (!x86_pmu
.num_counters
)
1242 local_irq_save(flags
);
1244 cpu
= smp_processor_id();
1245 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1247 if (x86_pmu
.version
>= 2) {
1248 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1249 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1250 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1251 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1252 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1255 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1256 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1257 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1258 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1259 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1261 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1263 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1264 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1265 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1267 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1269 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1270 cpu
, idx
, pmc_ctrl
);
1271 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1272 cpu
, idx
, pmc_count
);
1273 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1274 cpu
, idx
, prev_left
);
1276 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1277 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1279 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1280 cpu
, idx
, pmc_count
);
1282 local_irq_restore(flags
);
1285 static void x86_pmu_stop(struct perf_event
*event
, int flags
)
1287 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1288 struct hw_perf_event
*hwc
= &event
->hw
;
1290 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1291 x86_pmu
.disable(event
);
1292 cpuc
->events
[hwc
->idx
] = NULL
;
1293 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1294 hwc
->state
|= PERF_HES_STOPPED
;
1297 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1299 * Drain the remaining delta count out of a event
1300 * that we are disabling:
1302 x86_perf_event_update(event
);
1303 hwc
->state
|= PERF_HES_UPTODATE
;
1307 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1309 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1313 * If we're called during a txn, we don't need to do anything.
1314 * The events never got scheduled and ->cancel_txn will truncate
1317 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1320 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1322 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1323 if (event
== cpuc
->event_list
[i
]) {
1325 if (x86_pmu
.put_event_constraints
)
1326 x86_pmu
.put_event_constraints(cpuc
, event
);
1328 while (++i
< cpuc
->n_events
)
1329 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1335 perf_event_update_userpage(event
);
1338 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1340 struct perf_sample_data data
;
1341 struct cpu_hw_events
*cpuc
;
1342 struct perf_event
*event
;
1343 int idx
, handled
= 0;
1346 perf_sample_data_init(&data
, 0);
1348 cpuc
= &__get_cpu_var(cpu_hw_events
);
1351 * Some chipsets need to unmask the LVTPC in a particular spot
1352 * inside the nmi handler. As a result, the unmasking was pushed
1353 * into all the nmi handlers.
1355 * This generic handler doesn't seem to have any issues where the
1356 * unmasking occurs so it was left at the top.
1358 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1360 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1361 if (!test_bit(idx
, cpuc
->active_mask
)) {
1363 * Though we deactivated the counter some cpus
1364 * might still deliver spurious interrupts still
1365 * in flight. Catch them:
1367 if (__test_and_clear_bit(idx
, cpuc
->running
))
1372 event
= cpuc
->events
[idx
];
1374 val
= x86_perf_event_update(event
);
1375 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1382 data
.period
= event
->hw
.last_period
;
1384 if (!x86_perf_event_set_period(event
))
1387 if (perf_event_overflow(event
, &data
, regs
))
1388 x86_pmu_stop(event
, 0);
1392 inc_irq_stat(apic_perf_irqs
);
1397 void perf_events_lapic_init(void)
1399 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1403 * Always use NMI for PMU
1405 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1408 struct pmu_nmi_state
{
1409 unsigned int marked
;
1413 static DEFINE_PER_CPU(struct pmu_nmi_state
, pmu_nmi
);
1415 static int __kprobes
1416 perf_event_nmi_handler(struct notifier_block
*self
,
1417 unsigned long cmd
, void *__args
)
1419 struct die_args
*args
= __args
;
1420 unsigned int this_nmi
;
1423 if (!atomic_read(&active_events
))
1429 case DIE_NMIUNKNOWN
:
1430 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1431 if (this_nmi
!= __this_cpu_read(pmu_nmi
.marked
))
1432 /* let the kernel handle the unknown nmi */
1435 * This one is a PMU back-to-back nmi. Two events
1436 * trigger 'simultaneously' raising two back-to-back
1437 * NMIs. If the first NMI handles both, the latter
1438 * will be empty and daze the CPU. So, we drop it to
1439 * avoid false-positive 'unknown nmi' messages.
1446 handled
= x86_pmu
.handle_irq(args
->regs
);
1450 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1451 if ((handled
> 1) ||
1452 /* the next nmi could be a back-to-back nmi */
1453 ((__this_cpu_read(pmu_nmi
.marked
) == this_nmi
) &&
1454 (__this_cpu_read(pmu_nmi
.handled
) > 1))) {
1456 * We could have two subsequent back-to-back nmis: The
1457 * first handles more than one counter, the 2nd
1458 * handles only one counter and the 3rd handles no
1461 * This is the 2nd nmi because the previous was
1462 * handling more than one counter. We will mark the
1463 * next (3rd) and then drop it if unhandled.
1465 __this_cpu_write(pmu_nmi
.marked
, this_nmi
+ 1);
1466 __this_cpu_write(pmu_nmi
.handled
, handled
);
1472 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1473 .notifier_call
= perf_event_nmi_handler
,
1475 .priority
= NMI_LOCAL_LOW_PRIOR
,
1478 static struct event_constraint unconstrained
;
1479 static struct event_constraint emptyconstraint
;
1481 static struct event_constraint
*
1482 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1484 struct event_constraint
*c
;
1486 if (x86_pmu
.event_constraints
) {
1487 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1488 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1493 return &unconstrained
;
1496 #include "perf_event_amd.c"
1497 #include "perf_event_p6.c"
1498 #include "perf_event_p4.c"
1499 #include "perf_event_intel_lbr.c"
1500 #include "perf_event_intel_ds.c"
1501 #include "perf_event_intel.c"
1503 static int __cpuinit
1504 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1506 unsigned int cpu
= (long)hcpu
;
1507 int ret
= NOTIFY_OK
;
1509 switch (action
& ~CPU_TASKS_FROZEN
) {
1510 case CPU_UP_PREPARE
:
1511 if (x86_pmu
.cpu_prepare
)
1512 ret
= x86_pmu
.cpu_prepare(cpu
);
1516 if (x86_pmu
.cpu_starting
)
1517 x86_pmu
.cpu_starting(cpu
);
1521 if (x86_pmu
.cpu_dying
)
1522 x86_pmu
.cpu_dying(cpu
);
1525 case CPU_UP_CANCELED
:
1527 if (x86_pmu
.cpu_dead
)
1528 x86_pmu
.cpu_dead(cpu
);
1538 static void __init
pmu_check_apic(void)
1544 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1545 pr_info("no hardware sampling interrupt available.\n");
1548 static int __init
init_hw_perf_events(void)
1550 struct event_constraint
*c
;
1553 pr_info("Performance Events: ");
1555 switch (boot_cpu_data
.x86_vendor
) {
1556 case X86_VENDOR_INTEL
:
1557 err
= intel_pmu_init();
1559 case X86_VENDOR_AMD
:
1560 err
= amd_pmu_init();
1566 pr_cont("no PMU driver, software events only.\n");
1572 /* sanity check that the hardware exists or is emulated */
1573 if (!check_hw_exists())
1576 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1581 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1582 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1583 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1584 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1586 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1588 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1589 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1590 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1591 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1594 x86_pmu
.intel_ctrl
|=
1595 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1597 perf_events_lapic_init();
1598 register_die_notifier(&perf_event_nmi_notifier
);
1600 unconstrained
= (struct event_constraint
)
1601 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1602 0, x86_pmu
.num_counters
);
1604 if (x86_pmu
.event_constraints
) {
1605 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1606 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1609 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1610 c
->weight
+= x86_pmu
.num_counters
;
1614 pr_info("... version: %d\n", x86_pmu
.version
);
1615 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1616 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1617 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1618 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1619 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1620 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1622 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1623 perf_cpu_notifier(x86_pmu_notifier
);
1627 early_initcall(init_hw_perf_events
);
1629 static inline void x86_pmu_read(struct perf_event
*event
)
1631 x86_perf_event_update(event
);
1635 * Start group events scheduling transaction
1636 * Set the flag to make pmu::enable() not perform the
1637 * schedulability test, it will be performed at commit time
1639 static void x86_pmu_start_txn(struct pmu
*pmu
)
1641 perf_pmu_disable(pmu
);
1642 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1643 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1647 * Stop group events scheduling transaction
1648 * Clear the flag and pmu::enable() will perform the
1649 * schedulability test.
1651 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1653 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1655 * Truncate the collected events.
1657 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1658 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1659 perf_pmu_enable(pmu
);
1663 * Commit group events scheduling transaction
1664 * Perform the group schedulability test as a whole
1665 * Return 0 if success
1667 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1669 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1670 int assign
[X86_PMC_IDX_MAX
];
1675 if (!x86_pmu_initialized())
1678 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1683 * copy new assignment, now we know it is possible
1684 * will be used by hw_perf_enable()
1686 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1688 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1689 perf_pmu_enable(pmu
);
1694 * validate that we can schedule this event
1696 static int validate_event(struct perf_event
*event
)
1698 struct cpu_hw_events
*fake_cpuc
;
1699 struct event_constraint
*c
;
1702 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1706 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1708 if (!c
|| !c
->weight
)
1711 if (x86_pmu
.put_event_constraints
)
1712 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1720 * validate a single event group
1722 * validation include:
1723 * - check events are compatible which each other
1724 * - events do not compete for the same counter
1725 * - number of events <= number of counters
1727 * validation ensures the group can be loaded onto the
1728 * PMU if it was the only group available.
1730 static int validate_group(struct perf_event
*event
)
1732 struct perf_event
*leader
= event
->group_leader
;
1733 struct cpu_hw_events
*fake_cpuc
;
1737 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1741 * the event is not yet connected with its
1742 * siblings therefore we must first collect
1743 * existing siblings, then add the new event
1744 * before we can simulate the scheduling
1747 n
= collect_events(fake_cpuc
, leader
, true);
1751 fake_cpuc
->n_events
= n
;
1752 n
= collect_events(fake_cpuc
, event
, false);
1756 fake_cpuc
->n_events
= n
;
1758 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1766 static int x86_pmu_event_init(struct perf_event
*event
)
1771 switch (event
->attr
.type
) {
1773 case PERF_TYPE_HARDWARE
:
1774 case PERF_TYPE_HW_CACHE
:
1781 err
= __x86_pmu_event_init(event
);
1784 * we temporarily connect event to its pmu
1785 * such that validate_group() can classify
1786 * it as an x86 event using is_x86_event()
1791 if (event
->group_leader
!= event
)
1792 err
= validate_group(event
);
1794 err
= validate_event(event
);
1800 event
->destroy(event
);
1806 static struct pmu pmu
= {
1807 .pmu_enable
= x86_pmu_enable
,
1808 .pmu_disable
= x86_pmu_disable
,
1810 .event_init
= x86_pmu_event_init
,
1814 .start
= x86_pmu_start
,
1815 .stop
= x86_pmu_stop
,
1816 .read
= x86_pmu_read
,
1818 .start_txn
= x86_pmu_start_txn
,
1819 .cancel_txn
= x86_pmu_cancel_txn
,
1820 .commit_txn
= x86_pmu_commit_txn
,
1827 static int backtrace_stack(void *data
, char *name
)
1832 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1834 struct perf_callchain_entry
*entry
= data
;
1836 perf_callchain_store(entry
, addr
);
1839 static const struct stacktrace_ops backtrace_ops
= {
1840 .stack
= backtrace_stack
,
1841 .address
= backtrace_address
,
1842 .walk_stack
= print_context_stack_bp
,
1846 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1848 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1849 /* TODO: We don't support guest os callchain now */
1853 perf_callchain_store(entry
, regs
->ip
);
1855 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1858 #ifdef CONFIG_COMPAT
1860 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1862 /* 32-bit process in 64-bit kernel. */
1863 struct stack_frame_ia32 frame
;
1864 const void __user
*fp
;
1866 if (!test_thread_flag(TIF_IA32
))
1869 fp
= compat_ptr(regs
->bp
);
1870 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1871 unsigned long bytes
;
1872 frame
.next_frame
= 0;
1873 frame
.return_address
= 0;
1875 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1876 if (bytes
!= sizeof(frame
))
1879 if (fp
< compat_ptr(regs
->sp
))
1882 perf_callchain_store(entry
, frame
.return_address
);
1883 fp
= compat_ptr(frame
.next_frame
);
1889 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1896 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1898 struct stack_frame frame
;
1899 const void __user
*fp
;
1901 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1902 /* TODO: We don't support guest os callchain now */
1906 fp
= (void __user
*)regs
->bp
;
1908 perf_callchain_store(entry
, regs
->ip
);
1910 if (perf_callchain_user32(regs
, entry
))
1913 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1914 unsigned long bytes
;
1915 frame
.next_frame
= NULL
;
1916 frame
.return_address
= 0;
1918 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1919 if (bytes
!= sizeof(frame
))
1922 if ((unsigned long)fp
< regs
->sp
)
1925 perf_callchain_store(entry
, frame
.return_address
);
1926 fp
= frame
.next_frame
;
1930 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1934 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1935 ip
= perf_guest_cbs
->get_guest_ip();
1937 ip
= instruction_pointer(regs
);
1942 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1946 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1947 if (perf_guest_cbs
->is_user_mode())
1948 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1950 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1952 if (user_mode(regs
))
1953 misc
|= PERF_RECORD_MISC_USER
;
1955 misc
|= PERF_RECORD_MISC_KERNEL
;
1958 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1959 misc
|= PERF_RECORD_MISC_EXACT_IP
;