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[media] s5p-fimc: Conversion to multiplanar formats
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / video / s5p-fimc / fimc-core.c
blobfe210976f30bd7f32ded3fe2a8eaacb9904b9c99
1 /*
2 * S5P camera interface (video postprocessor) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd
5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/version.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/bug.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/list.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/videobuf2-core.h>
29 #include <media/videobuf2-dma-contig.h>
30
31 #include "fimc-core.h"
32
33 static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
34
35 static struct fimc_fmt fimc_formats[] = {
36 {
37 .name = "RGB565",
38 .fourcc = V4L2_PIX_FMT_RGB565X,
39 .depth = { 16 },
40 .color = S5P_FIMC_RGB565,
41 .memplanes = 1,
42 .colplanes = 1,
43 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_BE,
44 .flags = FMT_FLAGS_M2M,
45 }, {
46 .name = "BGR666",
47 .fourcc = V4L2_PIX_FMT_BGR666,
48 .depth = { 32 },
49 .color = S5P_FIMC_RGB666,
50 .memplanes = 1,
51 .colplanes = 1,
52 .flags = FMT_FLAGS_M2M,
53 }, {
54 .name = "XRGB-8-8-8-8, 32 bpp",
55 .fourcc = V4L2_PIX_FMT_RGB32,
56 .depth = { 32 },
57 .color = S5P_FIMC_RGB888,
58 .memplanes = 1,
59 .colplanes = 1,
60 .flags = FMT_FLAGS_M2M,
61 }, {
62 .name = "YUV 4:2:2 packed, YCbYCr",
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .depth = { 16 },
65 .color = S5P_FIMC_YCBYCR422,
66 .memplanes = 1,
67 .colplanes = 1,
68 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
69 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
70 }, {
71 .name = "YUV 4:2:2 packed, CbYCrY",
72 .fourcc = V4L2_PIX_FMT_UYVY,
73 .depth = { 16 },
74 .color = S5P_FIMC_CBYCRY422,
75 .memplanes = 1,
76 .colplanes = 1,
77 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
78 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
79 }, {
80 .name = "YUV 4:2:2 packed, CrYCbY",
81 .fourcc = V4L2_PIX_FMT_VYUY,
82 .depth = { 16 },
83 .color = S5P_FIMC_CRYCBY422,
84 .memplanes = 1,
85 .colplanes = 1,
86 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
87 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
88 }, {
89 .name = "YUV 4:2:2 packed, YCrYCb",
90 .fourcc = V4L2_PIX_FMT_YVYU,
91 .depth = { 16 },
92 .color = S5P_FIMC_YCRYCB422,
93 .memplanes = 1,
94 .colplanes = 1,
95 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
96 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
97 }, {
98 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
99 .fourcc = V4L2_PIX_FMT_YUV422P,
100 .depth = { 12 },
101 .color = S5P_FIMC_YCBYCR422,
102 .memplanes = 1,
103 .colplanes = 3,
104 .flags = FMT_FLAGS_M2M,
105 }, {
106 .name = "YUV 4:2:2 planar, Y/CbCr",
107 .fourcc = V4L2_PIX_FMT_NV16,
108 .depth = { 16 },
109 .color = S5P_FIMC_YCBYCR422,
110 .memplanes = 1,
111 .colplanes = 2,
112 .flags = FMT_FLAGS_M2M,
113 }, {
114 .name = "YUV 4:2:2 planar, Y/CrCb",
115 .fourcc = V4L2_PIX_FMT_NV61,
116 .depth = { 16 },
117 .color = S5P_FIMC_YCRYCB422,
118 .memplanes = 1,
119 .colplanes = 2,
120 .flags = FMT_FLAGS_M2M,
121 }, {
122 .name = "YUV 4:2:0 planar, YCbCr",
123 .fourcc = V4L2_PIX_FMT_YUV420,
124 .depth = { 12 },
125 .color = S5P_FIMC_YCBCR420,
126 .memplanes = 1,
127 .colplanes = 3,
128 .flags = FMT_FLAGS_M2M,
129 }, {
130 .name = "YUV 4:2:0 planar, Y/CbCr",
131 .fourcc = V4L2_PIX_FMT_NV12,
132 .depth = { 12 },
133 .color = S5P_FIMC_YCBCR420,
134 .memplanes = 1,
135 .colplanes = 2,
136 .flags = FMT_FLAGS_M2M,
137 }, {
138 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
139 .fourcc = V4L2_PIX_FMT_NV12M,
140 .color = S5P_FIMC_YCBCR420,
141 .depth = { 8, 4 },
142 .memplanes = 2,
143 .colplanes = 2,
144 .flags = FMT_FLAGS_M2M,
145 }, {
146 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
147 .fourcc = V4L2_PIX_FMT_YUV420M,
148 .color = S5P_FIMC_YCBCR420,
149 .depth = { 8, 2, 2 },
150 .memplanes = 3,
151 .colplanes = 3,
152 .flags = FMT_FLAGS_M2M,
153 }, {
154 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
155 .fourcc = V4L2_PIX_FMT_NV12MT,
156 .color = S5P_FIMC_YCBCR420,
157 .depth = { 8, 4 },
158 .memplanes = 2,
159 .colplanes = 2,
160 .flags = FMT_FLAGS_M2M,
161 },
162 };
163
164 static struct v4l2_queryctrl fimc_ctrls[] = {
165 {
166 .id = V4L2_CID_HFLIP,
167 .type = V4L2_CTRL_TYPE_BOOLEAN,
168 .name = "Horizontal flip",
169 .minimum = 0,
170 .maximum = 1,
171 .default_value = 0,
172 }, {
173 .id = V4L2_CID_VFLIP,
174 .type = V4L2_CTRL_TYPE_BOOLEAN,
175 .name = "Vertical flip",
176 .minimum = 0,
177 .maximum = 1,
178 .default_value = 0,
179 }, {
180 .id = V4L2_CID_ROTATE,
181 .type = V4L2_CTRL_TYPE_INTEGER,
182 .name = "Rotation (CCW)",
183 .minimum = 0,
184 .maximum = 270,
185 .step = 90,
186 .default_value = 0,
187 },
188 };
189
190
191 static struct v4l2_queryctrl *get_ctrl(int id)
192 {
193 int i;
194
195 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
196 if (id == fimc_ctrls[i].id)
197 return &fimc_ctrls[i];
198 return NULL;
199 }
200
201 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
202 {
203 if (r->width > f->width) {
204 if (f->width > (r->width * SCALER_MAX_HRATIO))
205 return -EINVAL;
206 } else {
207 if ((f->width * SCALER_MAX_HRATIO) < r->width)
208 return -EINVAL;
209 }
210
211 if (r->height > f->height) {
212 if (f->height > (r->height * SCALER_MAX_VRATIO))
213 return -EINVAL;
214 } else {
215 if ((f->height * SCALER_MAX_VRATIO) < r->height)
216 return -EINVAL;
217 }
218
219 return 0;
220 }
221
222 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
223 {
224 u32 sh = 6;
225
226 if (src >= 64 * tar)
227 return -EINVAL;
228
229 while (sh--) {
230 u32 tmp = 1 << sh;
231 if (src >= tar * tmp) {
232 *shift = sh, *ratio = tmp;
233 return 0;
234 }
235 }
236
237 *shift = 0, *ratio = 1;
238
239 dbg("s: %d, t: %d, shift: %d, ratio: %d",
240 src, tar, *shift, *ratio);
241 return 0;
242 }
243
244 int fimc_set_scaler_info(struct fimc_ctx *ctx)
245 {
246 struct fimc_scaler *sc = &ctx->scaler;
247 struct fimc_frame *s_frame = &ctx->s_frame;
248 struct fimc_frame *d_frame = &ctx->d_frame;
249 int tx, ty, sx, sy;
250 int ret;
251
252 if (ctx->rotation == 90 || ctx->rotation == 270) {
253 ty = d_frame->width;
254 tx = d_frame->height;
255 } else {
256 tx = d_frame->width;
257 ty = d_frame->height;
258 }
259 if (tx <= 0 || ty <= 0) {
260 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
261 "invalid target size: %d x %d", tx, ty);
262 return -EINVAL;
263 }
264
265 sx = s_frame->width;
266 sy = s_frame->height;
267 if (sx <= 0 || sy <= 0) {
268 err("invalid source size: %d x %d", sx, sy);
269 return -EINVAL;
270 }
271
272 sc->real_width = sx;
273 sc->real_height = sy;
274 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
275
276 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
277 if (ret)
278 return ret;
279
280 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
281 if (ret)
282 return ret;
283
284 sc->pre_dst_width = sx / sc->pre_hratio;
285 sc->pre_dst_height = sy / sc->pre_vratio;
286
287 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
288 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
289
290 sc->scaleup_h = (tx >= sx) ? 1 : 0;
291 sc->scaleup_v = (ty >= sy) ? 1 : 0;
292
293 /* check to see if input and output size/format differ */
294 if (s_frame->fmt->color == d_frame->fmt->color
295 && s_frame->width == d_frame->width
296 && s_frame->height == d_frame->height)
297 sc->copy_mode = 1;
298 else
299 sc->copy_mode = 0;
300
301 return 0;
302 }
303
304 static void fimc_capture_handler(struct fimc_dev *fimc)
305 {
306 struct fimc_vid_cap *cap = &fimc->vid_cap;
307 struct fimc_vid_buffer *v_buf = NULL;
308
309 if (!list_empty(&cap->active_buf_q)) {
310 v_buf = active_queue_pop(cap);
311 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
312 }
313
314 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
315 wake_up(&fimc->irq_queue);
316 return;
317 }
318
319 if (!list_empty(&cap->pending_buf_q)) {
320
321 v_buf = pending_queue_pop(cap);
322 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
323 v_buf->index = cap->buf_index;
324
325 dbg("hw ptr: %d, sw ptr: %d",
326 fimc_hw_get_frame_index(fimc), cap->buf_index);
327
328 /* Move the buffer to the capture active queue */
329 active_queue_add(cap, v_buf);
330
331 dbg("next frame: %d, done frame: %d",
332 fimc_hw_get_frame_index(fimc), v_buf->index);
333
334 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
335 cap->buf_index = 0;
336
337 } else if (test_and_clear_bit(ST_CAPT_STREAM, &fimc->state) &&
338 cap->active_buf_cnt <= 1) {
339 fimc_deactivate_capture(fimc);
340 }
341
342 dbg("frame: %d, active_buf_cnt= %d",
343 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
344 }
345
346 static irqreturn_t fimc_isr(int irq, void *priv)
347 {
348 struct fimc_dev *fimc = priv;
349
350 BUG_ON(!fimc);
351 fimc_hw_clear_irq(fimc);
352
353 spin_lock(&fimc->slock);
354
355 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
356 struct vb2_buffer *src_vb, *dst_vb;
357 struct fimc_ctx *ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
358
359 if (!ctx || !ctx->m2m_ctx)
360 goto isr_unlock;
361
362 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
363 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
364 if (src_vb && dst_vb) {
365 v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
366 v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
367 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
368 }
369 goto isr_unlock;
370
371 }
372
373 if (test_bit(ST_CAPT_RUN, &fimc->state))
374 fimc_capture_handler(fimc);
375
376 if (test_and_clear_bit(ST_CAPT_PEND, &fimc->state)) {
377 set_bit(ST_CAPT_RUN, &fimc->state);
378 wake_up(&fimc->irq_queue);
379 }
380
381 isr_unlock:
382 spin_unlock(&fimc->slock);
383 return IRQ_HANDLED;
384 }
385
386 /* The color format (colplanes, memplanes) must be already configured. */
387 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
388 struct fimc_frame *frame, struct fimc_addr *paddr)
389 {
390 int ret = 0;
391 u32 pix_size;
392
393 if (vb == NULL || frame == NULL)
394 return -EINVAL;
395
396 pix_size = frame->width * frame->height;
397
398 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
399 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
400
401 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
402
403 if (frame->fmt->memplanes == 1) {
404 switch (frame->fmt->colplanes) {
405 case 1:
406 paddr->cb = 0;
407 paddr->cr = 0;
408 break;
409 case 2:
410 /* decompose Y into Y/Cb */
411 paddr->cb = (u32)(paddr->y + pix_size);
412 paddr->cr = 0;
413 break;
414 case 3:
415 paddr->cb = (u32)(paddr->y + pix_size);
416 /* decompose Y into Y/Cb/Cr */
417 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
418 paddr->cr = (u32)(paddr->cb
419 + (pix_size >> 2));
420 else /* 422 */
421 paddr->cr = (u32)(paddr->cb
422 + (pix_size >> 1));
423 break;
424 default:
425 return -EINVAL;
426 }
427 } else {
428 if (frame->fmt->memplanes >= 2)
429 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
430
431 if (frame->fmt->memplanes == 3)
432 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
433 }
434
435 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
436 paddr->y, paddr->cb, paddr->cr, ret);
437
438 return ret;
439 }
440
441 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
442 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
443 {
444 /* The one only mode supported in SoC. */
445 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
446 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
447
448 /* Set order for 1 plane input formats. */
449 switch (ctx->s_frame.fmt->color) {
450 case S5P_FIMC_YCRYCB422:
451 ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
452 break;
453 case S5P_FIMC_CBYCRY422:
454 ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
455 break;
456 case S5P_FIMC_CRYCBY422:
457 ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
458 break;
459 case S5P_FIMC_YCBYCR422:
460 default:
461 ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
462 break;
463 }
464 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
465
466 switch (ctx->d_frame.fmt->color) {
467 case S5P_FIMC_YCRYCB422:
468 ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
469 break;
470 case S5P_FIMC_CBYCRY422:
471 ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
472 break;
473 case S5P_FIMC_CRYCBY422:
474 ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
475 break;
476 case S5P_FIMC_YCBYCR422:
477 default:
478 ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
479 break;
480 }
481 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
482 }
483
484 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
485 {
486 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
487 u32 i, depth = 0;
488
489 for (i = 0; i < f->fmt->colplanes; i++)
490 depth += f->fmt->depth[i];
491
492 f->dma_offset.y_h = f->offs_h;
493 if (!variant->pix_hoff)
494 f->dma_offset.y_h *= (depth >> 3);
495
496 f->dma_offset.y_v = f->offs_v;
497
498 f->dma_offset.cb_h = f->offs_h;
499 f->dma_offset.cb_v = f->offs_v;
500
501 f->dma_offset.cr_h = f->offs_h;
502 f->dma_offset.cr_v = f->offs_v;
503
504 if (!variant->pix_hoff) {
505 if (f->fmt->colplanes == 3) {
506 f->dma_offset.cb_h >>= 1;
507 f->dma_offset.cr_h >>= 1;
508 }
509 if (f->fmt->color == S5P_FIMC_YCBCR420) {
510 f->dma_offset.cb_v >>= 1;
511 f->dma_offset.cr_v >>= 1;
512 }
513 }
514
515 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
516 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
517 }
518
519 /**
520 * fimc_prepare_config - check dimensions, operation and color mode
521 * and pre-calculate offset and the scaling coefficients.
522 *
523 * @ctx: hardware context information
524 * @flags: flags indicating which parameters to check/update
525 *
526 * Return: 0 if dimensions are valid or non zero otherwise.
527 */
528 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
529 {
530 struct fimc_frame *s_frame, *d_frame;
531 struct vb2_buffer *vb = NULL;
532 int ret = 0;
533
534 s_frame = &ctx->s_frame;
535 d_frame = &ctx->d_frame;
536
537 if (flags & FIMC_PARAMS) {
538 /* Prepare the DMA offset ratios for scaler. */
539 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
540 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
541
542 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
543 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
544 err("out of scaler range");
545 return -EINVAL;
546 }
547 fimc_set_yuv_order(ctx);
548 }
549
550 /* Input DMA mode is not allowed when the scaler is disabled. */
551 ctx->scaler.enabled = 1;
552
553 if (flags & FIMC_SRC_ADDR) {
554 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
555 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
556 if (ret)
557 return ret;
558 }
559
560 if (flags & FIMC_DST_ADDR) {
561 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
562 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
563 }
564
565 return ret;
566 }
567
568 static void fimc_dma_run(void *priv)
569 {
570 struct fimc_ctx *ctx = priv;
571 struct fimc_dev *fimc;
572 unsigned long flags;
573 u32 ret;
574
575 if (WARN(!ctx, "null hardware context\n"))
576 return;
577
578 fimc = ctx->fimc_dev;
579
580 spin_lock_irqsave(&ctx->slock, flags);
581 set_bit(ST_M2M_PEND, &fimc->state);
582
583 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
584 ret = fimc_prepare_config(ctx, ctx->state);
585 if (ret) {
586 err("Wrong parameters");
587 goto dma_unlock;
588 }
589 /* Reconfigure hardware if the context has changed. */
590 if (fimc->m2m.ctx != ctx) {
591 ctx->state |= FIMC_PARAMS;
592 fimc->m2m.ctx = ctx;
593 }
594
595 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
596
597 if (ctx->state & FIMC_PARAMS) {
598 fimc_hw_set_input_path(ctx);
599 fimc_hw_set_in_dma(ctx);
600 if (fimc_set_scaler_info(ctx)) {
601 err("Scaler setup error");
602 goto dma_unlock;
603 }
604 fimc_hw_set_scaler(ctx);
605 fimc_hw_set_target_format(ctx);
606 fimc_hw_set_rotation(ctx);
607 fimc_hw_set_effect(ctx);
608 }
609
610 fimc_hw_set_output_path(ctx);
611 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
612 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
613
614 if (ctx->state & FIMC_PARAMS)
615 fimc_hw_set_out_dma(ctx);
616
617 fimc_activate_capture(ctx);
618
619 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
620 FIMC_SRC_FMT | FIMC_DST_FMT);
621 fimc_hw_activate_input_dma(fimc, true);
622
623 dma_unlock:
624 spin_unlock_irqrestore(&ctx->slock, flags);
625 }
626
627 static void fimc_job_abort(void *priv)
628 {
629 /* Nothing done in job_abort. */
630 }
631
632 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
633 unsigned int *num_planes, unsigned long sizes[],
634 void *allocators[])
635 {
636 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
637 struct fimc_frame *f;
638 int i;
639
640 f = ctx_get_frame(ctx, vq->type);
641 if (IS_ERR(f))
642 return PTR_ERR(f);
643
644 /*
645 * Return number of non-contigous planes (plane buffers)
646 * depending on the configured color format.
647 */
648 if (f->fmt)
649 *num_planes = f->fmt->memplanes;
650
651 for (i = 0; i < f->fmt->memplanes; i++) {
652 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
653 allocators[i] = ctx->fimc_dev->alloc_ctx;
654 }
655
656 if (*num_buffers == 0)
657 *num_buffers = 1;
658
659 return 0;
660 }
661
662 static int fimc_buf_prepare(struct vb2_buffer *vb)
663 {
664 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
665 struct fimc_frame *frame;
666 int i;
667
668 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
669 if (IS_ERR(frame))
670 return PTR_ERR(frame);
671
672 for (i = 0; i < frame->fmt->memplanes; i++)
673 vb2_set_plane_payload(vb, i, frame->payload[i]);
674
675 return 0;
676 }
677
678 static void fimc_buf_queue(struct vb2_buffer *vb)
679 {
680 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
681
682 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
683
684 if (ctx->m2m_ctx)
685 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
686 }
687
688 static void fimc_lock(struct vb2_queue *vq)
689 {
690 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
691 mutex_lock(&ctx->fimc_dev->lock);
692 }
693
694 static void fimc_unlock(struct vb2_queue *vq)
695 {
696 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
697 mutex_unlock(&ctx->fimc_dev->lock);
698 }
699
700 struct vb2_ops fimc_qops = {
701 .queue_setup = fimc_queue_setup,
702 .buf_prepare = fimc_buf_prepare,
703 .buf_queue = fimc_buf_queue,
704 .wait_prepare = fimc_unlock,
705 .wait_finish = fimc_lock,
706 };
707
708 static int fimc_m2m_querycap(struct file *file, void *priv,
709 struct v4l2_capability *cap)
710 {
711 struct fimc_ctx *ctx = file->private_data;
712 struct fimc_dev *fimc = ctx->fimc_dev;
713
714 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
715 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
716 cap->bus_info[0] = 0;
717 cap->version = KERNEL_VERSION(1, 0, 0);
718 cap->capabilities = V4L2_CAP_STREAMING |
719 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
720 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
721
722 return 0;
723 }
724
725 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
726 struct v4l2_fmtdesc *f)
727 {
728 struct fimc_fmt *fmt;
729
730 if (f->index >= ARRAY_SIZE(fimc_formats))
731 return -EINVAL;
732
733 fmt = &fimc_formats[f->index];
734 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
735 f->pixelformat = fmt->fourcc;
736
737 return 0;
738 }
739
740 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
741 struct v4l2_format *f)
742 {
743 struct fimc_ctx *ctx = priv;
744 struct fimc_dev *fimc = ctx->fimc_dev;
745 struct fimc_frame *frame;
746
747 frame = ctx_get_frame(ctx, f->type);
748 if (IS_ERR(frame))
749 return PTR_ERR(frame);
750
751 if (mutex_lock_interruptible(&fimc->lock))
752 return -ERESTARTSYS;
753
754 f->fmt.pix.width = frame->width;
755 f->fmt.pix.height = frame->height;
756 f->fmt.pix.field = V4L2_FIELD_NONE;
757 f->fmt.pix.pixelformat = frame->fmt->fourcc;
758
759 mutex_unlock(&fimc->lock);
760 return 0;
761 }
762
763 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
764 {
765 struct fimc_fmt *fmt;
766 unsigned int i;
767
768 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
769 fmt = &fimc_formats[i];
770 if (fmt->fourcc == f->fmt.pix.pixelformat &&
771 (fmt->flags & mask))
772 break;
773 }
774
775 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
776 }
777
778 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
779 unsigned int mask)
780 {
781 struct fimc_fmt *fmt;
782 unsigned int i;
783
784 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
785 fmt = &fimc_formats[i];
786 if (fmt->mbus_code == f->code && (fmt->flags & mask))
787 break;
788 }
789
790 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
791 }
792
793
794 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
795 struct v4l2_format *f)
796 {
797 struct fimc_ctx *ctx = priv;
798 struct fimc_dev *fimc = ctx->fimc_dev;
799 struct samsung_fimc_variant *variant = fimc->variant;
800 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
801 struct fimc_fmt *fmt;
802 u32 max_width, mod_x, mod_y, mask;
803 int ret, i, is_output = 0;
804
805 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
806 if (ctx->state & FIMC_CTX_CAP)
807 return -EINVAL;
808 is_output = 1;
809 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
810 return -EINVAL;
811 }
812
813 if (mutex_lock_interruptible(&fimc->lock))
814 return -ERESTARTSYS;
815 dbg("w: %d, h: %d", pix->width, pix->height);
816
817 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
818 fmt = find_format(f, mask);
819 if (!fmt) {
820 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
821 pix->pixelformat);
822 goto tf_out;
823 }
824
825 if (pix->field == V4L2_FIELD_ANY)
826 pix->field = V4L2_FIELD_NONE;
827 else if (V4L2_FIELD_NONE != pix->field)
828 goto tf_out;
829
830 if (is_output) {
831 max_width = variant->pix_limit->scaler_dis_w;
832 mod_x = ffs(variant->min_inp_pixsize) - 1;
833 } else {
834 max_width = variant->pix_limit->out_rot_dis_w;
835 mod_x = ffs(variant->min_out_pixsize) - 1;
836 }
837
838 if (tiled_fmt(fmt)) {
839 mod_x = 6; /* 64 x 32 pixels tile */
840 mod_y = 5;
841 } else {
842 if (fimc->id == 1 && variant->pix_hoff)
843 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
844 else
845 mod_y = mod_x;
846 }
847
848 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
849
850 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
851 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
852
853 pix->num_planes = fmt->memplanes;
854
855 for (i = 0; i < pix->num_planes; ++i) {
856 int bpl = pix->plane_fmt[i].bytesperline;
857
858 dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
859 i, bpl, fmt->depth[i], pix->width, pix->height);
860
861 if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
862 bpl = (pix->width * fmt->depth[0]) >> 3;
863
864 if (!pix->plane_fmt[i].sizeimage)
865 pix->plane_fmt[i].sizeimage = pix->height * bpl;
866
867 pix->plane_fmt[i].bytesperline = bpl;
868
869 dbg("[%d]: bpl: %d, sizeimage: %d",
870 i, pix->plane_fmt[i].bytesperline,
871 pix->plane_fmt[i].sizeimage);
872 }
873
874 ret = 0;
875
876 tf_out:
877 mutex_unlock(&fimc->lock);
878 return ret;
879 }
880
881 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
882 struct v4l2_format *f)
883 {
884 struct fimc_ctx *ctx = priv;
885 struct fimc_dev *fimc = ctx->fimc_dev;
886 struct vb2_queue *vq;
887 struct fimc_frame *frame;
888 struct v4l2_pix_format_mplane *pix;
889 unsigned long flags;
890 int i, ret = 0;
891
892 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
893 if (ret)
894 return ret;
895
896 if (mutex_lock_interruptible(&fimc->lock))
897 return -ERESTARTSYS;
898
899 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
900
901 if (vb2_is_streaming(vq)) {
902 v4l2_err(&fimc->vid_cap.v4l2_dev, "%s: queue (%d) busy\n",
903 __func__, f->type);
904 ret = -EBUSY;
905 goto sf_out;
906 }
907
908 spin_lock_irqsave(&ctx->slock, flags);
909 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
910 frame = &ctx->s_frame;
911 ctx->state |= FIMC_SRC_FMT;
912 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
913 frame = &ctx->d_frame;
914 ctx->state |= FIMC_DST_FMT;
915 } else {
916 spin_unlock_irqrestore(&ctx->slock, flags);
917 v4l2_err(&fimc->m2m.v4l2_dev,
918 "Wrong buffer/video queue type (%d)\n", f->type);
919 ret = -EINVAL;
920 goto sf_out;
921 }
922 spin_unlock_irqrestore(&ctx->slock, flags);
923
924 pix = &f->fmt.pix_mp;
925 frame->fmt = find_format(f, FMT_FLAGS_M2M);
926 if (!frame->fmt) {
927 ret = -EINVAL;
928 goto sf_out;
929 }
930
931 for (i = 0; i < frame->fmt->colplanes; i++)
932 frame->payload[i] = pix->plane_fmt[i].bytesperline * pix->height;
933
934 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
935 frame->fmt->depth[0];
936 frame->f_height = pix->height;
937 frame->width = pix->width;
938 frame->height = pix->height;
939 frame->o_width = pix->width;
940 frame->o_height = pix->height;
941 frame->offs_h = 0;
942 frame->offs_v = 0;
943
944 spin_lock_irqsave(&ctx->slock, flags);
945 ctx->state |= FIMC_PARAMS;
946 spin_unlock_irqrestore(&ctx->slock, flags);
947
948 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
949
950 sf_out:
951 mutex_unlock(&fimc->lock);
952 return ret;
953 }
954
955 static int fimc_m2m_reqbufs(struct file *file, void *priv,
956 struct v4l2_requestbuffers *reqbufs)
957 {
958 struct fimc_ctx *ctx = priv;
959 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
960 }
961
962 static int fimc_m2m_querybuf(struct file *file, void *priv,
963 struct v4l2_buffer *buf)
964 {
965 struct fimc_ctx *ctx = priv;
966 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
967 }
968
969 static int fimc_m2m_qbuf(struct file *file, void *priv,
970 struct v4l2_buffer *buf)
971 {
972 struct fimc_ctx *ctx = priv;
973
974 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
975 }
976
977 static int fimc_m2m_dqbuf(struct file *file, void *priv,
978 struct v4l2_buffer *buf)
979 {
980 struct fimc_ctx *ctx = priv;
981 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
982 }
983
984 static int fimc_m2m_streamon(struct file *file, void *priv,
985 enum v4l2_buf_type type)
986 {
987 struct fimc_ctx *ctx = priv;
988
989 /* The source and target color format need to be set */
990 if (V4L2_TYPE_IS_OUTPUT(type)) {
991 if (~ctx->state & FIMC_SRC_FMT)
992 return -EINVAL;
993 } else if (~ctx->state & FIMC_DST_FMT) {
994 return -EINVAL;
995 }
996
997 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
998 }
999
1000 static int fimc_m2m_streamoff(struct file *file, void *priv,
1001 enum v4l2_buf_type type)
1002 {
1003 struct fimc_ctx *ctx = priv;
1004 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1005 }
1006
1007 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1008 struct v4l2_queryctrl *qc)
1009 {
1010 struct fimc_ctx *ctx = priv;
1011 struct v4l2_queryctrl *c;
1012 int ret = -EINVAL;
1013
1014 c = get_ctrl(qc->id);
1015 if (c) {
1016 *qc = *c;
1017 return 0;
1018 }
1019
1020 if (ctx->state & FIMC_CTX_CAP) {
1021 if (mutex_lock_interruptible(&ctx->fimc_dev->lock))
1022 return -ERESTARTSYS;
1023 ret = v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1024 core, queryctrl, qc);
1025 mutex_unlock(&ctx->fimc_dev->lock);
1026 }
1027 return ret;
1028 }
1029
1030 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1031 struct v4l2_control *ctrl)
1032 {
1033 struct fimc_ctx *ctx = priv;
1034 struct fimc_dev *fimc = ctx->fimc_dev;
1035 int ret = 0;
1036
1037 if (mutex_lock_interruptible(&fimc->lock))
1038 return -ERESTARTSYS;
1039
1040 switch (ctrl->id) {
1041 case V4L2_CID_HFLIP:
1042 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1043 break;
1044 case V4L2_CID_VFLIP:
1045 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1046 break;
1047 case V4L2_CID_ROTATE:
1048 ctrl->value = ctx->rotation;
1049 break;
1050 default:
1051 if (ctx->state & FIMC_CTX_CAP) {
1052 ret = v4l2_subdev_call(fimc->vid_cap.sd, core,
1053 g_ctrl, ctrl);
1054 } else {
1055 v4l2_err(&fimc->m2m.v4l2_dev,
1056 "Invalid control\n");
1057 ret = -EINVAL;
1058 }
1059 }
1060 dbg("ctrl->value= %d", ctrl->value);
1061
1062 mutex_unlock(&fimc->lock);
1063 return ret;
1064 }
1065
1066 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1067 {
1068 struct v4l2_queryctrl *c;
1069 c = get_ctrl(ctrl->id);
1070 if (!c)
1071 return -EINVAL;
1072
1073 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1074 || (c->step != 0 && ctrl->value % c->step != 0)) {
1075 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1076 "Invalid control value\n");
1077 return -ERANGE;
1078 }
1079
1080 return 0;
1081 }
1082
1083 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1084 {
1085 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1086 struct fimc_dev *fimc = ctx->fimc_dev;
1087 unsigned long flags;
1088
1089 if (ctx->rotation != 0 &&
1090 (ctrl->id == V4L2_CID_HFLIP || ctrl->id == V4L2_CID_VFLIP)) {
1091 v4l2_err(&fimc->m2m.v4l2_dev,
1092 "Simultaneous flip and rotation is not supported\n");
1093 return -EINVAL;
1094 }
1095
1096 spin_lock_irqsave(&ctx->slock, flags);
1097
1098 switch (ctrl->id) {
1099 case V4L2_CID_HFLIP:
1100 if (ctrl->value)
1101 ctx->flip |= FLIP_X_AXIS;
1102 else
1103 ctx->flip &= ~FLIP_X_AXIS;
1104 break;
1105
1106 case V4L2_CID_VFLIP:
1107 if (ctrl->value)
1108 ctx->flip |= FLIP_Y_AXIS;
1109 else
1110 ctx->flip &= ~FLIP_Y_AXIS;
1111 break;
1112
1113 case V4L2_CID_ROTATE:
1114 /* Check for the output rotator availability */
1115 if ((ctrl->value == 90 || ctrl->value == 270) &&
1116 (ctx->in_path == FIMC_DMA && !variant->has_out_rot)) {
1117 spin_unlock_irqrestore(&ctx->slock, flags);
1118 return -EINVAL;
1119 } else {
1120 ctx->rotation = ctrl->value;
1121 }
1122 break;
1123
1124 default:
1125 spin_unlock_irqrestore(&ctx->slock, flags);
1126 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1127 return -EINVAL;
1128 }
1129 ctx->state |= FIMC_PARAMS;
1130 spin_unlock_irqrestore(&ctx->slock, flags);
1131
1132 return 0;
1133 }
1134
1135 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1136 struct v4l2_control *ctrl)
1137 {
1138 struct fimc_ctx *ctx = priv;
1139 int ret = 0;
1140
1141 ret = check_ctrl_val(ctx, ctrl);
1142 if (ret)
1143 return ret;
1144
1145 ret = fimc_s_ctrl(ctx, ctrl);
1146 return 0;
1147 }
1148
1149 static int fimc_m2m_cropcap(struct file *file, void *fh,
1150 struct v4l2_cropcap *cr)
1151 {
1152 struct fimc_frame *frame;
1153 struct fimc_ctx *ctx = fh;
1154 struct fimc_dev *fimc = ctx->fimc_dev;
1155
1156 frame = ctx_get_frame(ctx, cr->type);
1157 if (IS_ERR(frame))
1158 return PTR_ERR(frame);
1159
1160 if (mutex_lock_interruptible(&fimc->lock))
1161 return -ERESTARTSYS;
1162
1163 cr->bounds.left = 0;
1164 cr->bounds.top = 0;
1165 cr->bounds.width = frame->f_width;
1166 cr->bounds.height = frame->f_height;
1167 cr->defrect = cr->bounds;
1168
1169 mutex_unlock(&fimc->lock);
1170 return 0;
1171 }
1172
1173 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1174 {
1175 struct fimc_frame *frame;
1176 struct fimc_ctx *ctx = file->private_data;
1177 struct fimc_dev *fimc = ctx->fimc_dev;
1178
1179 frame = ctx_get_frame(ctx, cr->type);
1180 if (IS_ERR(frame))
1181 return PTR_ERR(frame);
1182
1183 if (mutex_lock_interruptible(&fimc->lock))
1184 return -ERESTARTSYS;
1185
1186 cr->c.left = frame->offs_h;
1187 cr->c.top = frame->offs_v;
1188 cr->c.width = frame->width;
1189 cr->c.height = frame->height;
1190
1191 mutex_unlock(&fimc->lock);
1192 return 0;
1193 }
1194
1195 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1196 {
1197 struct fimc_dev *fimc = ctx->fimc_dev;
1198 struct fimc_frame *f;
1199 u32 min_size, halign, depth = 0;
1200 int i;
1201
1202 if (cr->c.top < 0 || cr->c.left < 0) {
1203 v4l2_err(&fimc->m2m.v4l2_dev,
1204 "doesn't support negative values for top & left\n");
1205 return -EINVAL;
1206 }
1207
1208 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1209 f = (ctx->state & FIMC_CTX_CAP) ? &ctx->s_frame : &ctx->d_frame;
1210 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1211 ctx->state & FIMC_CTX_M2M)
1212 f = &ctx->s_frame;
1213 else
1214 return -EINVAL;
1215
1216 min_size = (f == &ctx->s_frame) ?
1217 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1218
1219 if (ctx->state & FIMC_CTX_M2M) {
1220 if (fimc->id == 1 && fimc->variant->pix_hoff)
1221 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1222 else
1223 halign = ffs(min_size) - 1;
1224 /* there are more strict aligment requirements at camera interface */
1225 } else {
1226 min_size = 16;
1227 halign = 4;
1228 }
1229
1230 for (i = 0; i < f->fmt->colplanes; i++)
1231 depth += f->fmt->depth[i];
1232
1233 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1234 ffs(min_size) - 1,
1235 &cr->c.height, min_size, f->o_height,
1236 halign, 64/(ALIGN(depth, 8)));
1237
1238 /* adjust left/top if cropping rectangle is out of bounds */
1239 if (cr->c.left + cr->c.width > f->o_width)
1240 cr->c.left = f->o_width - cr->c.width;
1241 if (cr->c.top + cr->c.height > f->o_height)
1242 cr->c.top = f->o_height - cr->c.height;
1243
1244 cr->c.left = round_down(cr->c.left, min_size);
1245 cr->c.top = round_down(cr->c.top,
1246 ctx->state & FIMC_CTX_M2M ? 8 : 16);
1247
1248 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1249 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1250 f->f_width, f->f_height);
1251
1252 return 0;
1253 }
1254
1255
1256 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1257 {
1258 struct fimc_ctx *ctx = file->private_data;
1259 struct fimc_dev *fimc = ctx->fimc_dev;
1260 unsigned long flags;
1261 struct fimc_frame *f;
1262 int ret;
1263
1264 ret = fimc_try_crop(ctx, cr);
1265 if (ret)
1266 return ret;
1267
1268 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1269 &ctx->s_frame : &ctx->d_frame;
1270
1271 if (mutex_lock_interruptible(&fimc->lock))
1272 return -ERESTARTSYS;
1273
1274 spin_lock_irqsave(&ctx->slock, flags);
1275 if (~ctx->state & (FIMC_SRC_FMT | FIMC_DST_FMT)) {
1276 /* Check to see if scaling ratio is within supported range */
1277 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1278 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
1279 else
1280 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
1281 if (ret) {
1282 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
1283 ret = -EINVAL;
1284 goto scr_unlock;
1285 }
1286 }
1287 ctx->state |= FIMC_PARAMS;
1288
1289 f->offs_h = cr->c.left;
1290 f->offs_v = cr->c.top;
1291 f->width = cr->c.width;
1292 f->height = cr->c.height;
1293
1294 scr_unlock:
1295 spin_unlock_irqrestore(&ctx->slock, flags);
1296 mutex_unlock(&fimc->lock);
1297 return 0;
1298 }
1299
1300 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1301 .vidioc_querycap = fimc_m2m_querycap,
1302
1303 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1304 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1305
1306 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1307 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1308
1309 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1310 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1311
1312 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1313 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1314
1315 .vidioc_reqbufs = fimc_m2m_reqbufs,
1316 .vidioc_querybuf = fimc_m2m_querybuf,
1317
1318 .vidioc_qbuf = fimc_m2m_qbuf,
1319 .vidioc_dqbuf = fimc_m2m_dqbuf,
1320
1321 .vidioc_streamon = fimc_m2m_streamon,
1322 .vidioc_streamoff = fimc_m2m_streamoff,
1323
1324 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1325 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1326 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1327
1328 .vidioc_g_crop = fimc_m2m_g_crop,
1329 .vidioc_s_crop = fimc_m2m_s_crop,
1330 .vidioc_cropcap = fimc_m2m_cropcap
1331
1332 };
1333
1334 static int queue_init(void *priv, struct vb2_queue *src_vq,
1335 struct vb2_queue *dst_vq)
1336 {
1337 struct fimc_ctx *ctx = priv;
1338 int ret;
1339
1340 memset(src_vq, 0, sizeof(*src_vq));
1341 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1342 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1343 src_vq->drv_priv = ctx;
1344 src_vq->ops = &fimc_qops;
1345 src_vq->mem_ops = &vb2_dma_contig_memops;
1346 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1347
1348 ret = vb2_queue_init(src_vq);
1349 if (ret)
1350 return ret;
1351
1352 memset(dst_vq, 0, sizeof(*dst_vq));
1353 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1354 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1355 dst_vq->drv_priv = ctx;
1356 dst_vq->ops = &fimc_qops;
1357 dst_vq->mem_ops = &vb2_dma_contig_memops;
1358 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1359
1360 return vb2_queue_init(dst_vq);
1361 }
1362
1363 static int fimc_m2m_open(struct file *file)
1364 {
1365 struct fimc_dev *fimc = video_drvdata(file);
1366 struct fimc_ctx *ctx = NULL;
1367 int err = 0;
1368
1369 if (mutex_lock_interruptible(&fimc->lock))
1370 return -ERESTARTSYS;
1371
1372 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1373 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1374
1375 /*
1376 * Return if the corresponding video capture node
1377 * is already opened.
1378 */
1379 if (fimc->vid_cap.refcnt > 0) {
1380 err = -EBUSY;
1381 goto err_unlock;
1382 }
1383
1384 fimc->m2m.refcnt++;
1385 set_bit(ST_OUTDMA_RUN, &fimc->state);
1386
1387 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1388 if (!ctx) {
1389 err = -ENOMEM;
1390 goto err_unlock;
1391 }
1392
1393 file->private_data = ctx;
1394 ctx->fimc_dev = fimc;
1395 /* Default color format */
1396 ctx->s_frame.fmt = &fimc_formats[0];
1397 ctx->d_frame.fmt = &fimc_formats[0];
1398 /* Setup the device context for mem2mem mode. */
1399 ctx->state = FIMC_CTX_M2M;
1400 ctx->flags = 0;
1401 ctx->in_path = FIMC_DMA;
1402 ctx->out_path = FIMC_DMA;
1403 spin_lock_init(&ctx->slock);
1404
1405 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1406 if (IS_ERR(ctx->m2m_ctx)) {
1407 err = PTR_ERR(ctx->m2m_ctx);
1408 kfree(ctx);
1409 }
1410
1411 err_unlock:
1412 mutex_unlock(&fimc->lock);
1413 return err;
1414 }
1415
1416 static int fimc_m2m_release(struct file *file)
1417 {
1418 struct fimc_ctx *ctx = file->private_data;
1419 struct fimc_dev *fimc = ctx->fimc_dev;
1420
1421 mutex_lock(&fimc->lock);
1422
1423 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1424 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1425
1426 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1427 kfree(ctx);
1428 if (--fimc->m2m.refcnt <= 0)
1429 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1430
1431 mutex_unlock(&fimc->lock);
1432 return 0;
1433 }
1434
1435 static unsigned int fimc_m2m_poll(struct file *file,
1436 struct poll_table_struct *wait)
1437 {
1438 struct fimc_ctx *ctx = file->private_data;
1439
1440 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1441 }
1442
1443
1444 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1445 {
1446 struct fimc_ctx *ctx = file->private_data;
1447
1448 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1449 }
1450
1451 static const struct v4l2_file_operations fimc_m2m_fops = {
1452 .owner = THIS_MODULE,
1453 .open = fimc_m2m_open,
1454 .release = fimc_m2m_release,
1455 .poll = fimc_m2m_poll,
1456 .unlocked_ioctl = video_ioctl2,
1457 .mmap = fimc_m2m_mmap,
1458 };
1459
1460 static struct v4l2_m2m_ops m2m_ops = {
1461 .device_run = fimc_dma_run,
1462 .job_abort = fimc_job_abort,
1463 };
1464
1465 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1466 {
1467 struct video_device *vfd;
1468 struct platform_device *pdev;
1469 struct v4l2_device *v4l2_dev;
1470 int ret = 0;
1471
1472 if (!fimc)
1473 return -ENODEV;
1474
1475 pdev = fimc->pdev;
1476 v4l2_dev = &fimc->m2m.v4l2_dev;
1477
1478 /* set name if it is empty */
1479 if (!v4l2_dev->name[0])
1480 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1481 "%s.m2m", dev_name(&pdev->dev));
1482
1483 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1484 if (ret)
1485 goto err_m2m_r1;
1486
1487 vfd = video_device_alloc();
1488 if (!vfd) {
1489 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1490 goto err_m2m_r1;
1491 }
1492
1493 vfd->fops = &fimc_m2m_fops;
1494 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1495 vfd->minor = -1;
1496 vfd->release = video_device_release;
1497
1498 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1499
1500 video_set_drvdata(vfd, fimc);
1501 platform_set_drvdata(pdev, fimc);
1502
1503 fimc->m2m.vfd = vfd;
1504 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1505 if (IS_ERR(fimc->m2m.m2m_dev)) {
1506 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1507 ret = PTR_ERR(fimc->m2m.m2m_dev);
1508 goto err_m2m_r2;
1509 }
1510
1511 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1512 if (ret) {
1513 v4l2_err(v4l2_dev,
1514 "%s(): failed to register video device\n", __func__);
1515 goto err_m2m_r3;
1516 }
1517 v4l2_info(v4l2_dev,
1518 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1519
1520 return 0;
1521
1522 err_m2m_r3:
1523 v4l2_m2m_release(fimc->m2m.m2m_dev);
1524 err_m2m_r2:
1525 video_device_release(fimc->m2m.vfd);
1526 err_m2m_r1:
1527 v4l2_device_unregister(v4l2_dev);
1528
1529 return ret;
1530 }
1531
1532 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1533 {
1534 if (fimc) {
1535 v4l2_m2m_release(fimc->m2m.m2m_dev);
1536 video_unregister_device(fimc->m2m.vfd);
1537
1538 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1539 }
1540 }
1541
1542 static void fimc_clk_release(struct fimc_dev *fimc)
1543 {
1544 int i;
1545 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1546 if (fimc->clock[i]) {
1547 clk_disable(fimc->clock[i]);
1548 clk_put(fimc->clock[i]);
1549 }
1550 }
1551 }
1552
1553 static int fimc_clk_get(struct fimc_dev *fimc)
1554 {
1555 int i;
1556 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1557 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
1558 if (IS_ERR(fimc->clock[i])) {
1559 dev_err(&fimc->pdev->dev,
1560 "failed to get fimc clock: %s\n",
1561 fimc_clock_name[i]);
1562 return -ENXIO;
1563 }
1564 clk_enable(fimc->clock[i]);
1565 }
1566 return 0;
1567 }
1568
1569 static int fimc_probe(struct platform_device *pdev)
1570 {
1571 struct fimc_dev *fimc;
1572 struct resource *res;
1573 struct samsung_fimc_driverdata *drv_data;
1574 int ret = 0;
1575
1576 dev_dbg(&pdev->dev, "%s():\n", __func__);
1577
1578 drv_data = (struct samsung_fimc_driverdata *)
1579 platform_get_device_id(pdev)->driver_data;
1580
1581 if (pdev->id >= drv_data->num_entities) {
1582 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1583 pdev->id);
1584 return -EINVAL;
1585 }
1586
1587 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1588 if (!fimc)
1589 return -ENOMEM;
1590
1591 fimc->id = pdev->id;
1592 fimc->variant = drv_data->variant[fimc->id];
1593 fimc->pdev = pdev;
1594 fimc->pdata = pdev->dev.platform_data;
1595 fimc->state = ST_IDLE;
1596
1597 init_waitqueue_head(&fimc->irq_queue);
1598 spin_lock_init(&fimc->slock);
1599
1600 mutex_init(&fimc->lock);
1601
1602 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1603 if (!res) {
1604 dev_err(&pdev->dev, "failed to find the registers\n");
1605 ret = -ENOENT;
1606 goto err_info;
1607 }
1608
1609 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1610 dev_name(&pdev->dev));
1611 if (!fimc->regs_res) {
1612 dev_err(&pdev->dev, "failed to obtain register region\n");
1613 ret = -ENOENT;
1614 goto err_info;
1615 }
1616
1617 fimc->regs = ioremap(res->start, resource_size(res));
1618 if (!fimc->regs) {
1619 dev_err(&pdev->dev, "failed to map registers\n");
1620 ret = -ENXIO;
1621 goto err_req_region;
1622 }
1623
1624 ret = fimc_clk_get(fimc);
1625 if (ret)
1626 goto err_regs_unmap;
1627 clk_set_rate(fimc->clock[0], drv_data->lclk_frequency);
1628
1629 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1630 if (!res) {
1631 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1632 ret = -ENXIO;
1633 goto err_clk;
1634 }
1635 fimc->irq = res->start;
1636
1637 fimc_hw_reset(fimc);
1638
1639 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1640 if (ret) {
1641 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1642 goto err_clk;
1643 }
1644
1645 /* Initialize contiguous memory allocator */
1646 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1647 if (IS_ERR(fimc->alloc_ctx)) {
1648 ret = PTR_ERR(fimc->alloc_ctx);
1649 goto err_irq;
1650 }
1651
1652 ret = fimc_register_m2m_device(fimc);
1653 if (ret)
1654 goto err_irq;
1655
1656 /* At least one camera sensor is required to register capture node */
1657 if (fimc->pdata) {
1658 int i;
1659 for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
1660 if (fimc->pdata->isp_info[i])
1661 break;
1662
1663 if (i < FIMC_MAX_CAMIF_CLIENTS) {
1664 ret = fimc_register_capture_device(fimc);
1665 if (ret)
1666 goto err_m2m;
1667 }
1668 }
1669
1670 /*
1671 * Exclude the additional output DMA address registers by masking
1672 * them out on HW revisions that provide extended capabilites.
1673 */
1674 if (fimc->variant->out_buf_count > 4)
1675 fimc_hw_set_dma_seq(fimc, 0xF);
1676
1677 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1678 __func__, fimc->id);
1679
1680 return 0;
1681
1682 err_m2m:
1683 fimc_unregister_m2m_device(fimc);
1684 err_irq:
1685 free_irq(fimc->irq, fimc);
1686 err_clk:
1687 fimc_clk_release(fimc);
1688 err_regs_unmap:
1689 iounmap(fimc->regs);
1690 err_req_region:
1691 release_resource(fimc->regs_res);
1692 kfree(fimc->regs_res);
1693 err_info:
1694 kfree(fimc);
1695
1696 return ret;
1697 }
1698
1699 static int __devexit fimc_remove(struct platform_device *pdev)
1700 {
1701 struct fimc_dev *fimc =
1702 (struct fimc_dev *)platform_get_drvdata(pdev);
1703
1704 free_irq(fimc->irq, fimc);
1705 fimc_hw_reset(fimc);
1706
1707 fimc_unregister_m2m_device(fimc);
1708 fimc_unregister_capture_device(fimc);
1709
1710 fimc_clk_release(fimc);
1711
1712 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1713
1714 iounmap(fimc->regs);
1715 release_resource(fimc->regs_res);
1716 kfree(fimc->regs_res);
1717 kfree(fimc);
1718
1719 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1720 return 0;
1721 }
1722
1723 /* Image pixel limits, similar across several FIMC HW revisions. */
1724 static struct fimc_pix_limit s5p_pix_limit[3] = {
1725 [0] = {
1726 .scaler_en_w = 3264,
1727 .scaler_dis_w = 8192,
1728 .in_rot_en_h = 1920,
1729 .in_rot_dis_w = 8192,
1730 .out_rot_en_w = 1920,
1731 .out_rot_dis_w = 4224,
1732 },
1733 [1] = {
1734 .scaler_en_w = 4224,
1735 .scaler_dis_w = 8192,
1736 .in_rot_en_h = 1920,
1737 .in_rot_dis_w = 8192,
1738 .out_rot_en_w = 1920,
1739 .out_rot_dis_w = 4224,
1740 },
1741 [2] = {
1742 .scaler_en_w = 1920,
1743 .scaler_dis_w = 8192,
1744 .in_rot_en_h = 1280,
1745 .in_rot_dis_w = 8192,
1746 .out_rot_en_w = 1280,
1747 .out_rot_dis_w = 1920,
1748 },
1749 };
1750
1751 static struct samsung_fimc_variant fimc0_variant_s5p = {
1752 .has_inp_rot = 1,
1753 .has_out_rot = 1,
1754 .min_inp_pixsize = 16,
1755 .min_out_pixsize = 16,
1756 .hor_offs_align = 8,
1757 .out_buf_count = 4,
1758 .pix_limit = &s5p_pix_limit[0],
1759 };
1760
1761 static struct samsung_fimc_variant fimc2_variant_s5p = {
1762 .min_inp_pixsize = 16,
1763 .min_out_pixsize = 16,
1764 .hor_offs_align = 8,
1765 .out_buf_count = 4,
1766 .pix_limit = &s5p_pix_limit[1],
1767 };
1768
1769 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1770 .pix_hoff = 1,
1771 .has_inp_rot = 1,
1772 .has_out_rot = 1,
1773 .min_inp_pixsize = 16,
1774 .min_out_pixsize = 16,
1775 .hor_offs_align = 8,
1776 .out_buf_count = 4,
1777 .pix_limit = &s5p_pix_limit[1],
1778 };
1779
1780 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1781 .pix_hoff = 1,
1782 .has_inp_rot = 1,
1783 .has_out_rot = 1,
1784 .min_inp_pixsize = 16,
1785 .min_out_pixsize = 16,
1786 .hor_offs_align = 1,
1787 .out_buf_count = 4,
1788 .pix_limit = &s5p_pix_limit[2],
1789 };
1790
1791 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1792 .pix_hoff = 1,
1793 .min_inp_pixsize = 16,
1794 .min_out_pixsize = 16,
1795 .hor_offs_align = 8,
1796 .out_buf_count = 4,
1797 .pix_limit = &s5p_pix_limit[2],
1798 };
1799
1800 static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1801 .pix_hoff = 1,
1802 .has_inp_rot = 1,
1803 .has_out_rot = 1,
1804 .has_cistatus2 = 1,
1805 .min_inp_pixsize = 16,
1806 .min_out_pixsize = 16,
1807 .hor_offs_align = 1,
1808 .out_buf_count = 32,
1809 .pix_limit = &s5p_pix_limit[1],
1810 };
1811
1812 static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1813 .pix_hoff = 1,
1814 .has_cistatus2 = 1,
1815 .min_inp_pixsize = 16,
1816 .min_out_pixsize = 16,
1817 .hor_offs_align = 1,
1818 .out_buf_count = 32,
1819 .pix_limit = &s5p_pix_limit[2],
1820 };
1821
1822 /* S5PC100 */
1823 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1824 .variant = {
1825 [0] = &fimc0_variant_s5p,
1826 [1] = &fimc0_variant_s5p,
1827 [2] = &fimc2_variant_s5p,
1828 },
1829 .num_entities = 3,
1830 .lclk_frequency = 133000000UL,
1831 };
1832
1833 /* S5PV210, S5PC110 */
1834 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1835 .variant = {
1836 [0] = &fimc0_variant_s5pv210,
1837 [1] = &fimc1_variant_s5pv210,
1838 [2] = &fimc2_variant_s5pv210,
1839 },
1840 .num_entities = 3,
1841 .lclk_frequency = 166000000UL,
1842 };
1843
1844 /* S5PV310, S5PC210 */
1845 static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1846 .variant = {
1847 [0] = &fimc0_variant_s5pv310,
1848 [1] = &fimc0_variant_s5pv310,
1849 [2] = &fimc0_variant_s5pv310,
1850 [3] = &fimc2_variant_s5pv310,
1851 },
1852 .num_entities = 4,
1853 .lclk_frequency = 166000000UL,
1854 };
1855
1856 static struct platform_device_id fimc_driver_ids[] = {
1857 {
1858 .name = "s5p-fimc",
1859 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1860 }, {
1861 .name = "s5pv210-fimc",
1862 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1863 }, {
1864 .name = "s5pv310-fimc",
1865 .driver_data = (unsigned long)&fimc_drvdata_s5pv310,
1866 },
1867 {},
1868 };
1869 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1870
1871 static struct platform_driver fimc_driver = {
1872 .probe = fimc_probe,
1873 .remove = __devexit_p(fimc_remove),
1874 .id_table = fimc_driver_ids,
1875 .driver = {
1876 .name = MODULE_NAME,
1877 .owner = THIS_MODULE,
1878 }
1879 };
1880
1881 static int __init fimc_init(void)
1882 {
1883 int ret = platform_driver_register(&fimc_driver);
1884 if (ret)
1885 err("platform_driver_register failed: %d\n", ret);
1886 return ret;
1887 }
1888
1889 static void __exit fimc_exit(void)
1890 {
1891 platform_driver_unregister(&fimc_driver);
1892 }
1893
1894 module_init(fimc_init);
1895 module_exit(fimc_exit);
1896
1897 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1898 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1899 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree